arch/arm/mach-s3c2440/mach-anubis.c

   1 /* linux/arch/arm/mach-s3c2440/mach-anubis.c
   2  *
   3  * Copyright (c) 2003-2005,2008 Simtec Electronics
   4  *      http://armlinux.simtec.co.uk/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #include <linux/kernel.h>
  13 #include <linux/types.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/list.h>
  16 #include <linux/timer.h>
  17 #include <linux/init.h>
  18 #include <linux/serial_core.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/ata_platform.h>
  21 #include <linux/i2c.h>
  22 #include <linux/io.h>
  23 #include <linux/sm501.h>
  24 #include <linux/sm501-regs.h>
  25
  26 #include <asm/mach/arch.h>
  27 #include <asm/mach/map.h>
  28 #include <asm/mach/irq.h>
  29
  30 #include <mach/anubis-map.h>
  31 #include <mach/anubis-irq.h>
  32 #include <mach/anubis-cpld.h>
  33
  34 #include <mach/hardware.h>
  35 #include <asm/irq.h>
  36 #include <asm/mach-types.h>
  37
  38 #include <plat/regs-serial.h>
  39 #include <mach/regs-gpio.h>
  40 #include <mach/regs-mem.h>
  41 #include <mach/regs-lcd.h>
  42 #include <plat/nand.h>
  43
  44 #include <linux/mtd/mtd.h>
  45 #include <linux/mtd/nand.h>
  46 #include <linux/mtd/nand_ecc.h>
  47 #include <linux/mtd/partitions.h>
  48
  49 #include <net/ax88796.h>
  50
  51 #include <plat/clock.h>
  52 #include <plat/devs.h>
  53 #include <plat/cpu.h>
  54
  55 #define COPYRIGHT ", (c) 2005 Simtec Electronics"
  56
  57 static struct map_desc anubis_iodesc[] __initdata = {
  58   /* ISA IO areas */
  59
  60   {
  61         .virtual        = (u32)S3C24XX_VA_ISA_BYTE,
  62         .pfn            = __phys_to_pfn(0x0),
  63         .length         = SZ_4M,
  64         .type           = MT_DEVICE,
  65   }, {
  66         .virtual        = (u32)S3C24XX_VA_ISA_WORD,
  67         .pfn            = __phys_to_pfn(0x0),
  68         .length         = SZ_4M,
  69         .type           = MT_DEVICE,
  70   },
  71
  72   /* we could possibly compress the next set down into a set of smaller tables
  73    * pagetables, but that would mean using an L2 section, and it still means
  74    * we cannot actually feed the same register to an LDR due to 16K spacing
  75    */
  76
  77   /* CPLD control registers */
  78
  79   {
  80         .virtual        = (u32)ANUBIS_VA_CTRL1,
  81         .pfn            = __phys_to_pfn(ANUBIS_PA_CTRL1),
  82         .length         = SZ_4K,
  83         .type           = MT_DEVICE,
  84   }, {
  85         .virtual        = (u32)ANUBIS_VA_IDREG,
  86         .pfn            = __phys_to_pfn(ANUBIS_PA_IDREG),
  87         .length         = SZ_4K,
  88         .type           = MT_DEVICE,
  89   },
  90 };
  91
  92 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
  93 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
  94 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  95
  96 static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = {
  97         [0] = {
  98                 .name           = "uclk",
  99                 .divisor        = 1,
 100                 .min_baud       = 0,
 101                 .max_baud       = 0,
 102         },
 103         [1] = {
 104                 .name           = "pclk",
 105                 .divisor        = 1,
 106                 .min_baud       = 0,
 107                 .max_baud       = 0,
 108         }
 109 };
 110
 111
 112 static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
 113         [0] = {
 114                 .hwport      = 0,
 115                 .flags       = 0,
 116                 .ucon        = UCON,
 117                 .ulcon       = ULCON,
 118                 .ufcon       = UFCON,
 119                 .clocks      = anubis_serial_clocks,
 120                 .clocks_size = ARRAY_SIZE(anubis_serial_clocks),
 121         },
 122         [1] = {
 123                 .hwport      = 2,
 124                 .flags       = 0,
 125                 .ucon        = UCON,
 126                 .ulcon       = ULCON,
 127                 .ufcon       = UFCON,
 128                 .clocks      = anubis_serial_clocks,
 129                 .clocks_size = ARRAY_SIZE(anubis_serial_clocks),
 130         },
 131 };
 132
 133 /* NAND Flash on Anubis board */
 134
 135 static int external_map[]   = { 2 };
 136 static int chip0_map[]      = { 0 };
 137 static int chip1_map[]      = { 1 };
 138
 139 static struct mtd_partition anubis_default_nand_part[] = {
 140         [0] = {
 141                 .name   = "Boot Agent",
 142                 .size   = SZ_16K,
 143                 .offset = 0,
 144         },
 145         [1] = {
 146                 .name   = "/boot",
 147                 .size   = SZ_4M - SZ_16K,
 148                 .offset = SZ_16K,
 149         },
 150         [2] = {
 151                 .name   = "user1",
 152                 .offset = SZ_4M,
 153                 .size   = SZ_32M - SZ_4M,
 154         },
 155         [3] = {
 156                 .name   = "user2",
 157                 .offset = SZ_32M,
 158                 .size   = MTDPART_SIZ_FULL,
 159         }
 160 };
 161
 162 static struct mtd_partition anubis_default_nand_part_large[] = {
 163         [0] = {
 164                 .name   = "Boot Agent",
 165                 .size   = SZ_128K,
 166                 .offset = 0,
 167         },
 168         [1] = {
 169                 .name   = "/boot",
 170                 .size   = SZ_4M - SZ_128K,
 171                 .offset = SZ_128K,
 172         },
 173         [2] = {
 174                 .name   = "user1",
 175                 .offset = SZ_4M,
 176                 .size   = SZ_32M - SZ_4M,
 177         },
 178         [3] = {
 179                 .name   = "user2",
 180                 .offset = SZ_32M,
 181                 .size   = MTDPART_SIZ_FULL,
 182         }
 183 };
 184
 185 /* the Anubis has 3 selectable slots for nand-flash, the two
 186  * on-board chip areas, as well as the external slot.
 187  *
 188  * Note, there is no current hot-plug support for the External
 189  * socket.
 190 */
 191
 192 static struct s3c2410_nand_set anubis_nand_sets[] = {
 193         [1] = {
 194                 .name           = "External",
 195                 .nr_chips       = 1,
 196                 .nr_map         = external_map,
 197                 .nr_partitions  = ARRAY_SIZE(anubis_default_nand_part),
 198                 .partitions     = anubis_default_nand_part,
 199         },
 200         [0] = {
 201                 .name           = "chip0",
 202                 .nr_chips       = 1,
 203                 .nr_map         = chip0_map,
 204                 .nr_partitions  = ARRAY_SIZE(anubis_default_nand_part),
 205                 .partitions     = anubis_default_nand_part,
 206         },
 207         [2] = {
 208                 .name           = "chip1",
 209                 .nr_chips       = 1,
 210                 .nr_map         = chip1_map,
 211                 .nr_partitions  = ARRAY_SIZE(anubis_default_nand_part),
 212                 .partitions     = anubis_default_nand_part,
 213         },
 214 };
 215
 216 static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
 217 {
 218         unsigned int tmp;
 219
 220         slot = set->nr_map[slot] & 3;
 221
 222         pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
 223                  slot, set, set->nr_map);
 224
 225         tmp = __raw_readb(ANUBIS_VA_CTRL1);
 226         tmp &= ~ANUBIS_CTRL1_NANDSEL;
 227         tmp |= slot;
 228
 229         pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);
 230
 231         __raw_writeb(tmp, ANUBIS_VA_CTRL1);
 232 }
 233
 234 static struct s3c2410_platform_nand anubis_nand_info = {
 235         .tacls          = 25,
 236         .twrph0         = 55,
 237         .twrph1         = 40,
 238         .nr_sets        = ARRAY_SIZE(anubis_nand_sets),
 239         .sets           = anubis_nand_sets,
 240         .select_chip    = anubis_nand_select,
 241 };
 242
 243 /* IDE channels */
 244
 245 struct pata_platform_info anubis_ide_platdata = {
 246         .ioport_shift   = 5,
 247 };
 248
 249 static struct resource anubis_ide0_resource[] = {
 250         {
 251                 .start  = S3C2410_CS3,
 252                 .end    = S3C2410_CS3 + (8*32) - 1,
 253                 .flags  = IORESOURCE_MEM,
 254         }, {
 255                 .start  = S3C2410_CS3 + (1<<26) + (6*32),
 256                 .end    = S3C2410_CS3 + (1<<26) + (7*32) - 1,
 257                 .flags  = IORESOURCE_MEM,
 258         }, {
 259                 .start  = IRQ_IDE0,
 260                 .end    = IRQ_IDE0,
 261                 .flags  = IORESOURCE_IRQ,
 262         },
 263 };
 264
 265 static struct platform_device anubis_device_ide0 = {
 266         .name           = "pata_platform",
 267         .id             = 0,
 268         .num_resources  = ARRAY_SIZE(anubis_ide0_resource),
 269         .resource       = anubis_ide0_resource,
 270         .dev    = {
 271                 .platform_data = &anubis_ide_platdata,
 272                 .coherent_dma_mask = ~0,
 273         },
 274 };
 275
 276 static struct resource anubis_ide1_resource[] = {
 277         {
 278                 .start  = S3C2410_CS4,
 279                 .end    = S3C2410_CS4 + (8*32) - 1,
 280                 .flags  = IORESOURCE_MEM,
 281         }, {
 282                 .start  = S3C2410_CS4 + (1<<26) + (6*32),
 283                 .end    = S3C2410_CS4 + (1<<26) + (7*32) - 1,
 284                 .flags  = IORESOURCE_MEM,
 285         }, {
 286                 .start  = IRQ_IDE0,
 287                 .end    = IRQ_IDE0,
 288                 .flags  = IORESOURCE_IRQ,
 289         },
 290 };
 291
 292 static struct platform_device anubis_device_ide1 = {
 293         .name           = "pata_platform",
 294         .id             = 1,
 295         .num_resources  = ARRAY_SIZE(anubis_ide1_resource),
 296         .resource       = anubis_ide1_resource,
 297         .dev    = {
 298                 .platform_data = &anubis_ide_platdata,
 299                 .coherent_dma_mask = ~0,
 300         },
 301 };
 302
 303 /* Asix AX88796 10/100 ethernet controller */
 304
 305 static struct ax_plat_data anubis_asix_platdata = {
 306         .flags          = AXFLG_MAC_FROMDEV,
 307         .wordlength     = 2,
 308         .dcr_val        = 0x48,
 309         .rcr_val        = 0x40,
 310 };
 311
 312 static struct resource anubis_asix_resource[] = {
 313         [0] = {
 314                 .start = S3C2410_CS5,
 315                 .end   = S3C2410_CS5 + (0x20 * 0x20) -1,
 316                 .flags = IORESOURCE_MEM
 317         },
 318         [1] = {
 319                 .start = IRQ_ASIX,
 320                 .end   = IRQ_ASIX,
 321                 .flags = IORESOURCE_IRQ
 322         }
 323 };
 324
 325 static struct platform_device anubis_device_asix = {
 326         .name           = "ax88796",
 327         .id             = 0,
 328         .num_resources  = ARRAY_SIZE(anubis_asix_resource),
 329         .resource       = anubis_asix_resource,
 330         .dev            = {
 331                 .platform_data = &anubis_asix_platdata,
 332         }
 333 };
 334
 335 /* SM501 */
 336
 337 static struct resource anubis_sm501_resource[] = {
 338         [0] = {
 339                 .start  = S3C2410_CS2,
 340                 .end    = S3C2410_CS2 + SZ_8M,
 341                 .flags  = IORESOURCE_MEM,
 342         },
 343         [1] = {
 344                 .start  = S3C2410_CS2 + SZ_64M - SZ_2M,
 345                 .end    = S3C2410_CS2 + SZ_64M - 1,
 346                 .flags  = IORESOURCE_MEM,
 347         },
 348         [2] = {
 349                 .start  = IRQ_EINT0,
 350                 .end    = IRQ_EINT0,
 351                 .flags  = IORESOURCE_IRQ,
 352         },
 353 };
 354
 355 static struct sm501_initdata anubis_sm501_initdata = {
 356         .gpio_high      = {
 357                 .set    = 0x3F000000,           /* 24bit panel */
 358                 .mask   = 0x0,
 359         },
 360         .misc_timing    = {
 361                 .set    = 0x010100,             /* SDRAM timing */
 362                 .mask   = 0x1F1F00,
 363         },
 364         .misc_control   = {
 365                 .set    = SM501_MISC_PNL_24BIT,
 366                 .mask   = 0,
 367         },
 368
 369         /* set the SDRAM and bus clocks */
 370         .mclk           = 72 * MHZ,
 371         .m1xclk         = 144 * MHZ,
 372 };
 373
 374 static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = {
 375         [0] = {
 376                 .pin_scl        = 44,
 377                 .pin_sda        = 45,
 378         },
 379         [1] = {
 380                 .pin_scl        = 40,
 381                 .pin_sda        = 41,
 382         },
 383 };
 384
 385 static struct sm501_platdata anubis_sm501_platdata = {
 386         .init           = &anubis_sm501_initdata,
 387         .gpio_i2c       = anubis_sm501_gpio_i2c,
 388         .gpio_i2c_nr    = ARRAY_SIZE(anubis_sm501_gpio_i2c),
 389 };
 390
 391 static struct platform_device anubis_device_sm501 = {
 392         .name           = "sm501",
 393         .id             = 0,
 394         .num_resources  = ARRAY_SIZE(anubis_sm501_resource),
 395         .resource       = anubis_sm501_resource,
 396         .dev            = {
 397                 .platform_data = &anubis_sm501_platdata,
 398         },
 399 };
 400
 401 /* Standard Anubis devices */
 402
 403 static struct platform_device *anubis_devices[] __initdata = {
 404         &s3c_device_usb,
 405         &s3c_device_wdt,
 406         &s3c_device_adc,
 407         &s3c_device_i2c,
 408         &s3c_device_rtc,
 409         &s3c_device_nand,
 410         &anubis_device_ide0,
 411         &anubis_device_ide1,
 412         &anubis_device_asix,
 413         &anubis_device_sm501,
 414 };
 415
 416 static struct clk *anubis_clocks[] __initdata = {
 417         &s3c24xx_dclk0,
 418         &s3c24xx_dclk1,
 419         &s3c24xx_clkout0,
 420         &s3c24xx_clkout1,
 421         &s3c24xx_uclk,
 422 };
 423
 424 /* I2C devices. */
 425
 426 static struct i2c_board_info anubis_i2c_devs[] __initdata = {
 427         {
 428                 I2C_BOARD_INFO("tps65011", 0x48),
 429                 .irq    = IRQ_EINT20,
 430         }
 431 };
 432
 433 static void __init anubis_map_io(void)
 434 {
 435         /* initialise the clocks */
 436
 437         s3c24xx_dclk0.parent = &clk_upll;
 438         s3c24xx_dclk0.rate   = 12*1000*1000;
 439
 440         s3c24xx_dclk1.parent = &clk_upll;
 441         s3c24xx_dclk1.rate   = 24*1000*1000;
 442
 443         s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
 444         s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
 445
 446         s3c24xx_uclk.parent  = &s3c24xx_clkout1;
 447
 448         s3c24xx_register_clocks(anubis_clocks, ARRAY_SIZE(anubis_clocks));
 449
 450         s3c_device_nand.dev.platform_data = &anubis_nand_info;
 451
 452         s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
 453         s3c24xx_init_clocks(0);
 454         s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
 455
 456         /* check for the newer revision boards with large page nand */
 457
 458         if ((__raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK) >= 4) {
 459                 printk(KERN_INFO "ANUBIS-B detected (revision %d)\n",
 460                        __raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK);
 461                 anubis_nand_sets[0].partitions = anubis_default_nand_part_large;
 462                 anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large);
 463         } else {
 464                 /* ensure that the GPIO is setup */
 465                 s3c2410_gpio_setpin(S3C2410_GPA0, 1);
 466         }
 467 }
 468
 469 static void __init anubis_init(void)
 470 {
 471         platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
 472
 473         i2c_register_board_info(0, anubis_i2c_devs,
 474                                 ARRAY_SIZE(anubis_i2c_devs));
 475 }
 476
 477
 478 MACHINE_START(ANUBIS, "Simtec-Anubis")
 479         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
 480         .phys_io        = S3C2410_PA_UART,
 481         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
 482         .boot_params    = S3C2410_SDRAM_PA + 0x100,
 483         .map_io         = anubis_map_io,
 484         .init_machine   = anubis_init,
 485         .init_irq       = s3c24xx_init_irq,
 486         .timer          = &s3c24xx_timer,
 487 MACHINE_END