2 * linux/arch/arm/plat-omap/dma.c
4 * Copyright (C) 2003 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2 support Copyright (C) 2004-2005 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
13 * Support functions for the OMAP internal DMA channels.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/sched.h>
24 #include <linux/spinlock.h>
25 #include <linux/errno.h>
26 #include <linux/interrupt.h>
27 #include <linux/irq.h>
29 #include <asm/system.h>
30 #include <asm/hardware.h>
34 #include <asm/arch/tc.h>
39 #define debug_printk(x) printk x
41 #define debug_printk(x)
44 #define OMAP_DMA_ACTIVE 0x01
45 #define OMAP_DMA_CCR_EN (1 << 7)
46 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
48 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
50 static int enable_1510_mode
= 0;
58 void (* callback
)(int lch
, u16 ch_status
, void *data
);
63 static int dma_chan_count
;
65 static spinlock_t dma_chan_lock
;
66 static struct omap_dma_lch dma_chan
[OMAP_LOGICAL_DMA_CH_COUNT
];
68 static const u8 omap1_dma_irq
[OMAP_LOGICAL_DMA_CH_COUNT
] = {
69 INT_DMA_CH0_6
, INT_DMA_CH1_7
, INT_DMA_CH2_8
, INT_DMA_CH3
,
70 INT_DMA_CH4
, INT_DMA_CH5
, INT_1610_DMA_CH6
, INT_1610_DMA_CH7
,
71 INT_1610_DMA_CH8
, INT_1610_DMA_CH9
, INT_1610_DMA_CH10
,
72 INT_1610_DMA_CH11
, INT_1610_DMA_CH12
, INT_1610_DMA_CH13
,
73 INT_1610_DMA_CH14
, INT_1610_DMA_CH15
, INT_DMA_LCD
76 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
79 #ifdef CONFIG_ARCH_OMAP15XX
80 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
81 int omap_dma_in_1510_mode(void)
83 return enable_1510_mode
;
86 #define omap_dma_in_1510_mode() 0
89 #ifdef CONFIG_ARCH_OMAP1
90 static inline int get_gdma_dev(int req
)
92 u32 reg
= OMAP_FUNC_MUX_ARM_BASE
+ ((req
- 1) / 5) * 4;
93 int shift
= ((req
- 1) % 5) * 6;
95 return ((omap_readl(reg
) >> shift
) & 0x3f) + 1;
98 static inline void set_gdma_dev(int req
, int dev
)
100 u32 reg
= OMAP_FUNC_MUX_ARM_BASE
+ ((req
- 1) / 5) * 4;
101 int shift
= ((req
- 1) % 5) * 6;
105 l
&= ~(0x3f << shift
);
106 l
|= (dev
- 1) << shift
;
110 #define set_gdma_dev(req, dev) do {} while (0)
113 static void clear_lch_regs(int lch
)
116 u32 lch_base
= OMAP_DMA_BASE
+ lch
* 0x40;
118 for (i
= 0; i
< 0x2c; i
+= 2)
119 omap_writew(0, lch_base
+ i
);
122 void omap_set_dma_priority(int lch
, int dst_port
, int priority
)
127 if (cpu_class_is_omap1()) {
129 case OMAP_DMA_PORT_OCP_T1
: /* FFFECC00 */
130 reg
= OMAP_TC_OCPT1_PRIOR
;
132 case OMAP_DMA_PORT_OCP_T2
: /* FFFECCD0 */
133 reg
= OMAP_TC_OCPT2_PRIOR
;
135 case OMAP_DMA_PORT_EMIFF
: /* FFFECC08 */
136 reg
= OMAP_TC_EMIFF_PRIOR
;
138 case OMAP_DMA_PORT_EMIFS
: /* FFFECC04 */
139 reg
= OMAP_TC_EMIFS_PRIOR
;
147 l
|= (priority
& 0xf) << 8;
151 if (cpu_is_omap24xx()) {
153 OMAP_DMA_CCR_REG(lch
) |= (1 << 6);
155 OMAP_DMA_CCR_REG(lch
) &= ~(1 << 6);
159 void omap_set_dma_transfer_params(int lch
, int data_type
, int elem_count
,
160 int frame_count
, int sync_mode
,
161 int dma_trigger
, int src_or_dst_synch
)
163 OMAP_DMA_CSDP_REG(lch
) &= ~0x03;
164 OMAP_DMA_CSDP_REG(lch
) |= data_type
;
166 if (cpu_class_is_omap1()) {
167 OMAP_DMA_CCR_REG(lch
) &= ~(1 << 5);
168 if (sync_mode
== OMAP_DMA_SYNC_FRAME
)
169 OMAP_DMA_CCR_REG(lch
) |= 1 << 5;
171 OMAP1_DMA_CCR2_REG(lch
) &= ~(1 << 2);
172 if (sync_mode
== OMAP_DMA_SYNC_BLOCK
)
173 OMAP1_DMA_CCR2_REG(lch
) |= 1 << 2;
176 if (cpu_is_omap24xx() && dma_trigger
) {
177 u32 val
= OMAP_DMA_CCR_REG(lch
);
180 if (dma_trigger
> 63)
182 if (dma_trigger
> 31)
186 val
|= (dma_trigger
& 0x1f);
188 if (sync_mode
& OMAP_DMA_SYNC_FRAME
)
193 if (sync_mode
& OMAP_DMA_SYNC_BLOCK
)
198 if (src_or_dst_synch
)
199 val
|= 1 << 24; /* source synch */
201 val
&= ~(1 << 24); /* dest synch */
203 OMAP_DMA_CCR_REG(lch
) = val
;
206 OMAP_DMA_CEN_REG(lch
) = elem_count
;
207 OMAP_DMA_CFN_REG(lch
) = frame_count
;
210 void omap_set_dma_color_mode(int lch
, enum omap_dma_color_mode mode
, u32 color
)
214 BUG_ON(omap_dma_in_1510_mode());
216 if (cpu_is_omap24xx()) {
221 w
= OMAP1_DMA_CCR2_REG(lch
) & ~0x03;
223 case OMAP_DMA_CONSTANT_FILL
:
226 case OMAP_DMA_TRANSPARENT_COPY
:
229 case OMAP_DMA_COLOR_DIS
:
234 OMAP1_DMA_CCR2_REG(lch
) = w
;
236 w
= OMAP1_DMA_LCH_CTRL_REG(lch
) & ~0x0f;
237 /* Default is channel type 2D */
239 OMAP1_DMA_COLOR_L_REG(lch
) = (u16
)color
;
240 OMAP1_DMA_COLOR_U_REG(lch
) = (u16
)(color
>> 16);
241 w
|= 1; /* Channel type G */
243 OMAP1_DMA_LCH_CTRL_REG(lch
) = w
;
246 void omap_set_dma_write_mode(int lch
, enum omap_dma_write_mode mode
)
248 if (cpu_is_omap24xx()) {
249 OMAP_DMA_CSDP_REG(lch
) &= ~(0x3 << 16);
250 OMAP_DMA_CSDP_REG(lch
) |= (mode
<< 16);
254 /* Note that src_port is only for omap1 */
255 void omap_set_dma_src_params(int lch
, int src_port
, int src_amode
,
256 unsigned long src_start
,
257 int src_ei
, int src_fi
)
259 if (cpu_class_is_omap1()) {
260 OMAP_DMA_CSDP_REG(lch
) &= ~(0x1f << 2);
261 OMAP_DMA_CSDP_REG(lch
) |= src_port
<< 2;
264 OMAP_DMA_CCR_REG(lch
) &= ~(0x03 << 12);
265 OMAP_DMA_CCR_REG(lch
) |= src_amode
<< 12;
267 if (cpu_class_is_omap1()) {
268 OMAP1_DMA_CSSA_U_REG(lch
) = src_start
>> 16;
269 OMAP1_DMA_CSSA_L_REG(lch
) = src_start
;
272 if (cpu_is_omap24xx())
273 OMAP2_DMA_CSSA_REG(lch
) = src_start
;
275 OMAP_DMA_CSEI_REG(lch
) = src_ei
;
276 OMAP_DMA_CSFI_REG(lch
) = src_fi
;
279 void omap_set_dma_params(int lch
, struct omap_dma_channel_params
* params
)
281 omap_set_dma_transfer_params(lch
, params
->data_type
,
282 params
->elem_count
, params
->frame_count
,
283 params
->sync_mode
, params
->trigger
,
284 params
->src_or_dst_synch
);
285 omap_set_dma_src_params(lch
, params
->src_port
,
286 params
->src_amode
, params
->src_start
,
287 params
->src_ei
, params
->src_fi
);
289 omap_set_dma_dest_params(lch
, params
->dst_port
,
290 params
->dst_amode
, params
->dst_start
,
291 params
->dst_ei
, params
->dst_fi
);
294 void omap_set_dma_src_index(int lch
, int eidx
, int fidx
)
296 if (cpu_is_omap24xx()) {
300 OMAP_DMA_CSEI_REG(lch
) = eidx
;
301 OMAP_DMA_CSFI_REG(lch
) = fidx
;
304 void omap_set_dma_src_data_pack(int lch
, int enable
)
306 OMAP_DMA_CSDP_REG(lch
) &= ~(1 << 6);
308 OMAP_DMA_CSDP_REG(lch
) |= (1 << 6);
311 void omap_set_dma_src_burst_mode(int lch
, enum omap_dma_burst_mode burst_mode
)
313 unsigned int burst
= 0;
314 OMAP_DMA_CSDP_REG(lch
) &= ~(0x03 << 7);
316 switch (burst_mode
) {
317 case OMAP_DMA_DATA_BURST_DIS
:
319 case OMAP_DMA_DATA_BURST_4
:
320 if (cpu_is_omap24xx())
325 case OMAP_DMA_DATA_BURST_8
:
326 if (cpu_is_omap24xx()) {
330 /* not supported by current hardware on OMAP1
334 case OMAP_DMA_DATA_BURST_16
:
335 if (cpu_is_omap24xx()) {
339 /* OMAP1 don't support burst 16
345 OMAP_DMA_CSDP_REG(lch
) |= (burst
<< 7);
348 /* Note that dest_port is only for OMAP1 */
349 void omap_set_dma_dest_params(int lch
, int dest_port
, int dest_amode
,
350 unsigned long dest_start
,
351 int dst_ei
, int dst_fi
)
353 if (cpu_class_is_omap1()) {
354 OMAP_DMA_CSDP_REG(lch
) &= ~(0x1f << 9);
355 OMAP_DMA_CSDP_REG(lch
) |= dest_port
<< 9;
358 OMAP_DMA_CCR_REG(lch
) &= ~(0x03 << 14);
359 OMAP_DMA_CCR_REG(lch
) |= dest_amode
<< 14;
361 if (cpu_class_is_omap1()) {
362 OMAP1_DMA_CDSA_U_REG(lch
) = dest_start
>> 16;
363 OMAP1_DMA_CDSA_L_REG(lch
) = dest_start
;
366 if (cpu_is_omap24xx())
367 OMAP2_DMA_CDSA_REG(lch
) = dest_start
;
369 OMAP_DMA_CDEI_REG(lch
) = dst_ei
;
370 OMAP_DMA_CDFI_REG(lch
) = dst_fi
;
373 void omap_set_dma_dest_index(int lch
, int eidx
, int fidx
)
375 if (cpu_is_omap24xx()) {
379 OMAP_DMA_CDEI_REG(lch
) = eidx
;
380 OMAP_DMA_CDFI_REG(lch
) = fidx
;
383 void omap_set_dma_dest_data_pack(int lch
, int enable
)
385 OMAP_DMA_CSDP_REG(lch
) &= ~(1 << 13);
387 OMAP_DMA_CSDP_REG(lch
) |= 1 << 13;
390 void omap_set_dma_dest_burst_mode(int lch
, enum omap_dma_burst_mode burst_mode
)
392 unsigned int burst
= 0;
393 OMAP_DMA_CSDP_REG(lch
) &= ~(0x03 << 14);
395 switch (burst_mode
) {
396 case OMAP_DMA_DATA_BURST_DIS
:
398 case OMAP_DMA_DATA_BURST_4
:
399 if (cpu_is_omap24xx())
404 case OMAP_DMA_DATA_BURST_8
:
405 if (cpu_is_omap24xx())
410 case OMAP_DMA_DATA_BURST_16
:
411 if (cpu_is_omap24xx()) {
415 /* OMAP1 don't support burst 16
419 printk(KERN_ERR
"Invalid DMA burst mode\n");
423 OMAP_DMA_CSDP_REG(lch
) |= (burst
<< 14);
426 static inline void omap_enable_channel_irq(int lch
)
431 if (cpu_class_is_omap1())
432 status
= OMAP_DMA_CSR_REG(lch
);
433 else if (cpu_is_omap24xx())
434 OMAP_DMA_CSR_REG(lch
) = OMAP2_DMA_CSR_CLEAR_MASK
;
436 /* Enable some nice interrupts. */
437 OMAP_DMA_CICR_REG(lch
) = dma_chan
[lch
].enabled_irqs
;
439 dma_chan
[lch
].flags
|= OMAP_DMA_ACTIVE
;
442 static void omap_disable_channel_irq(int lch
)
444 if (cpu_is_omap24xx())
445 OMAP_DMA_CICR_REG(lch
) = 0;
448 void omap_enable_dma_irq(int lch
, u16 bits
)
450 dma_chan
[lch
].enabled_irqs
|= bits
;
453 void omap_disable_dma_irq(int lch
, u16 bits
)
455 dma_chan
[lch
].enabled_irqs
&= ~bits
;
458 static inline void enable_lnk(int lch
)
460 if (cpu_class_is_omap1())
461 OMAP_DMA_CLNK_CTRL_REG(lch
) &= ~(1 << 14);
463 /* Set the ENABLE_LNK bits */
464 if (dma_chan
[lch
].next_lch
!= -1)
465 OMAP_DMA_CLNK_CTRL_REG(lch
) =
466 dma_chan
[lch
].next_lch
| (1 << 15);
469 static inline void disable_lnk(int lch
)
471 /* Disable interrupts */
472 if (cpu_class_is_omap1()) {
473 OMAP_DMA_CICR_REG(lch
) = 0;
474 /* Set the STOP_LNK bit */
475 OMAP_DMA_CLNK_CTRL_REG(lch
) |= 1 << 14;
478 if (cpu_is_omap24xx()) {
479 omap_disable_channel_irq(lch
);
480 /* Clear the ENABLE_LNK bit */
481 OMAP_DMA_CLNK_CTRL_REG(lch
) &= ~(1 << 15);
484 dma_chan
[lch
].flags
&= ~OMAP_DMA_ACTIVE
;
487 static inline void omap2_enable_irq_lch(int lch
)
491 if (!cpu_is_omap24xx())
494 val
= omap_readl(OMAP_DMA4_IRQENABLE_L0
);
496 omap_writel(val
, OMAP_DMA4_IRQENABLE_L0
);
499 int omap_request_dma(int dev_id
, const char *dev_name
,
500 void (* callback
)(int lch
, u16 ch_status
, void *data
),
501 void *data
, int *dma_ch_out
)
503 int ch
, free_ch
= -1;
505 struct omap_dma_lch
*chan
;
507 spin_lock_irqsave(&dma_chan_lock
, flags
);
508 for (ch
= 0; ch
< dma_chan_count
; ch
++) {
509 if (free_ch
== -1 && dma_chan
[ch
].dev_id
== -1) {
516 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
519 chan
= dma_chan
+ free_ch
;
520 chan
->dev_id
= dev_id
;
522 if (cpu_class_is_omap1())
523 clear_lch_regs(free_ch
);
525 if (cpu_is_omap24xx())
526 omap_clear_dma(free_ch
);
528 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
530 chan
->dev_name
= dev_name
;
531 chan
->callback
= callback
;
533 chan
->enabled_irqs
= OMAP_DMA_DROP_IRQ
| OMAP_DMA_BLOCK_IRQ
;
535 if (cpu_class_is_omap1())
536 chan
->enabled_irqs
|= OMAP1_DMA_TOUT_IRQ
;
537 else if (cpu_is_omap24xx())
538 chan
->enabled_irqs
|= OMAP2_DMA_MISALIGNED_ERR_IRQ
|
539 OMAP2_DMA_TRANS_ERR_IRQ
;
541 if (cpu_is_omap16xx()) {
542 /* If the sync device is set, configure it dynamically. */
544 set_gdma_dev(free_ch
+ 1, dev_id
);
545 dev_id
= free_ch
+ 1;
547 /* Disable the 1510 compatibility mode and set the sync device
549 OMAP_DMA_CCR_REG(free_ch
) = dev_id
| (1 << 10);
550 } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
551 OMAP_DMA_CCR_REG(free_ch
) = dev_id
;
554 if (cpu_is_omap24xx()) {
555 omap2_enable_irq_lch(free_ch
);
557 omap_enable_channel_irq(free_ch
);
558 /* Clear the CSR register and IRQ status register */
559 OMAP_DMA_CSR_REG(free_ch
) = OMAP2_DMA_CSR_CLEAR_MASK
;
560 omap_writel(1 << free_ch
, OMAP_DMA4_IRQSTATUS_L0
);
563 *dma_ch_out
= free_ch
;
568 void omap_free_dma(int lch
)
572 spin_lock_irqsave(&dma_chan_lock
, flags
);
573 if (dma_chan
[lch
].dev_id
== -1) {
574 printk("omap_dma: trying to free nonallocated DMA channel %d\n",
576 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
579 dma_chan
[lch
].dev_id
= -1;
580 dma_chan
[lch
].next_lch
= -1;
581 dma_chan
[lch
].callback
= NULL
;
582 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
584 if (cpu_class_is_omap1()) {
585 /* Disable all DMA interrupts for the channel. */
586 OMAP_DMA_CICR_REG(lch
) = 0;
587 /* Make sure the DMA transfer is stopped. */
588 OMAP_DMA_CCR_REG(lch
) = 0;
591 if (cpu_is_omap24xx()) {
593 /* Disable interrupts */
594 val
= omap_readl(OMAP_DMA4_IRQENABLE_L0
);
596 omap_writel(val
, OMAP_DMA4_IRQENABLE_L0
);
598 /* Clear the CSR register and IRQ status register */
599 OMAP_DMA_CSR_REG(lch
) = OMAP2_DMA_CSR_CLEAR_MASK
;
600 omap_writel(1 << lch
, OMAP_DMA4_IRQSTATUS_L0
);
602 /* Disable all DMA interrupts for the channel. */
603 OMAP_DMA_CICR_REG(lch
) = 0;
605 /* Make sure the DMA transfer is stopped. */
606 OMAP_DMA_CCR_REG(lch
) = 0;
612 * Clears any DMA state so the DMA engine is ready to restart with new buffers
613 * through omap_start_dma(). Any buffers in flight are discarded.
615 void omap_clear_dma(int lch
)
619 local_irq_save(flags
);
621 if (cpu_class_is_omap1()) {
623 OMAP_DMA_CCR_REG(lch
) &= ~OMAP_DMA_CCR_EN
;
625 /* Clear pending interrupts */
626 status
= OMAP_DMA_CSR_REG(lch
);
629 if (cpu_is_omap24xx()) {
631 u32 lch_base
= OMAP24XX_DMA_BASE
+ lch
* 0x60 + 0x80;
632 for (i
= 0; i
< 0x44; i
+= 4)
633 omap_writel(0, lch_base
+ i
);
636 local_irq_restore(flags
);
639 void omap_start_dma(int lch
)
641 if (!omap_dma_in_1510_mode() && dma_chan
[lch
].next_lch
!= -1) {
642 int next_lch
, cur_lch
;
643 char dma_chan_link_map
[OMAP_LOGICAL_DMA_CH_COUNT
];
645 dma_chan_link_map
[lch
] = 1;
646 /* Set the link register of the first channel */
649 memset(dma_chan_link_map
, 0, sizeof(dma_chan_link_map
));
650 cur_lch
= dma_chan
[lch
].next_lch
;
652 next_lch
= dma_chan
[cur_lch
].next_lch
;
654 /* The loop case: we've been here already */
655 if (dma_chan_link_map
[cur_lch
])
657 /* Mark the current channel */
658 dma_chan_link_map
[cur_lch
] = 1;
661 omap_enable_channel_irq(cur_lch
);
664 } while (next_lch
!= -1);
665 } else if (cpu_is_omap24xx()) {
666 /* Errata: Need to write lch even if not using chaining */
667 OMAP_DMA_CLNK_CTRL_REG(lch
) = lch
;
670 omap_enable_channel_irq(lch
);
672 /* Errata: On ES2.0 BUFFERING disable must be set.
673 * This will always fail on ES1.0 */
674 if (cpu_is_omap24xx()) {
675 OMAP_DMA_CCR_REG(lch
) |= OMAP_DMA_CCR_EN
;
678 OMAP_DMA_CCR_REG(lch
) |= OMAP_DMA_CCR_EN
;
680 dma_chan
[lch
].flags
|= OMAP_DMA_ACTIVE
;
683 void omap_stop_dma(int lch
)
685 if (!omap_dma_in_1510_mode() && dma_chan
[lch
].next_lch
!= -1) {
686 int next_lch
, cur_lch
= lch
;
687 char dma_chan_link_map
[OMAP_LOGICAL_DMA_CH_COUNT
];
689 memset(dma_chan_link_map
, 0, sizeof(dma_chan_link_map
));
691 /* The loop case: we've been here already */
692 if (dma_chan_link_map
[cur_lch
])
694 /* Mark the current channel */
695 dma_chan_link_map
[cur_lch
] = 1;
697 disable_lnk(cur_lch
);
699 next_lch
= dma_chan
[cur_lch
].next_lch
;
701 } while (next_lch
!= -1);
706 /* Disable all interrupts on the channel */
707 if (cpu_class_is_omap1())
708 OMAP_DMA_CICR_REG(lch
) = 0;
710 OMAP_DMA_CCR_REG(lch
) &= ~OMAP_DMA_CCR_EN
;
711 dma_chan
[lch
].flags
&= ~OMAP_DMA_ACTIVE
;
715 * Allows changing the DMA callback function or data. This may be needed if
716 * the driver shares a single DMA channel for multiple dma triggers.
718 int omap_set_dma_callback(int lch
,
719 void (* callback
)(int lch
, u16 ch_status
, void *data
),
727 spin_lock_irqsave(&dma_chan_lock
, flags
);
728 if (dma_chan
[lch
].dev_id
== -1) {
729 printk(KERN_ERR
"DMA callback for not set for free channel\n");
730 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
733 dma_chan
[lch
].callback
= callback
;
734 dma_chan
[lch
].data
= data
;
735 spin_unlock_irqrestore(&dma_chan_lock
, flags
);
741 * Returns current physical source address for the given DMA channel.
742 * If the channel is running the caller must disable interrupts prior calling
743 * this function and process the returned value before re-enabling interrupt to
744 * prevent races with the interrupt handler. Note that in continuous mode there
745 * is a chance for CSSA_L register overflow inbetween the two reads resulting
746 * in incorrect return value.
748 dma_addr_t
omap_get_dma_src_pos(int lch
)
752 if (cpu_class_is_omap1())
753 offset
= (dma_addr_t
) (OMAP1_DMA_CSSA_L_REG(lch
) |
754 (OMAP1_DMA_CSSA_U_REG(lch
) << 16));
756 if (cpu_is_omap24xx())
757 offset
= OMAP_DMA_CSAC_REG(lch
);
763 * Returns current physical destination address for the given DMA channel.
764 * If the channel is running the caller must disable interrupts prior calling
765 * this function and process the returned value before re-enabling interrupt to
766 * prevent races with the interrupt handler. Note that in continuous mode there
767 * is a chance for CDSA_L register overflow inbetween the two reads resulting
768 * in incorrect return value.
770 dma_addr_t
omap_get_dma_dst_pos(int lch
)
774 if (cpu_class_is_omap1())
775 offset
= (dma_addr_t
) (OMAP1_DMA_CDSA_L_REG(lch
) |
776 (OMAP1_DMA_CDSA_U_REG(lch
) << 16));
778 if (cpu_is_omap24xx())
779 offset
= OMAP2_DMA_CDSA_REG(lch
);
785 * Returns current source transfer counting for the given DMA channel.
786 * Can be used to monitor the progress of a transfer inside a block.
787 * It must be called with disabled interrupts.
789 int omap_get_dma_src_addr_counter(int lch
)
791 return (dma_addr_t
) OMAP_DMA_CSAC_REG(lch
);
794 int omap_dma_running(void)
798 /* Check if LCD DMA is running */
799 if (cpu_is_omap16xx())
800 if (omap_readw(OMAP1610_DMA_LCD_CCR
) & OMAP_DMA_CCR_EN
)
803 for (lch
= 0; lch
< dma_chan_count
; lch
++)
804 if (OMAP_DMA_CCR_REG(lch
) & OMAP_DMA_CCR_EN
)
811 * lch_queue DMA will start right after lch_head one is finished.
812 * For this DMA link to start, you still need to start (see omap_start_dma)
813 * the first one. That will fire up the entire queue.
815 void omap_dma_link_lch (int lch_head
, int lch_queue
)
817 if (omap_dma_in_1510_mode()) {
818 printk(KERN_ERR
"DMA linking is not supported in 1510 mode\n");
823 if ((dma_chan
[lch_head
].dev_id
== -1) ||
824 (dma_chan
[lch_queue
].dev_id
== -1)) {
825 printk(KERN_ERR
"omap_dma: trying to link "
826 "non requested channels\n");
830 dma_chan
[lch_head
].next_lch
= lch_queue
;
834 * Once the DMA queue is stopped, we can destroy it.
836 void omap_dma_unlink_lch (int lch_head
, int lch_queue
)
838 if (omap_dma_in_1510_mode()) {
839 printk(KERN_ERR
"DMA linking is not supported in 1510 mode\n");
844 if (dma_chan
[lch_head
].next_lch
!= lch_queue
||
845 dma_chan
[lch_head
].next_lch
== -1) {
846 printk(KERN_ERR
"omap_dma: trying to unlink "
847 "non linked channels\n");
852 if ((dma_chan
[lch_head
].flags
& OMAP_DMA_ACTIVE
) ||
853 (dma_chan
[lch_head
].flags
& OMAP_DMA_ACTIVE
)) {
854 printk(KERN_ERR
"omap_dma: You need to stop the DMA channels "
855 "before unlinking\n");
859 dma_chan
[lch_head
].next_lch
= -1;
862 /*----------------------------------------------------------------------------*/
864 #ifdef CONFIG_ARCH_OMAP1
866 static int omap1_dma_handle_ch(int ch
)
870 if (enable_1510_mode
&& ch
>= 6) {
871 csr
= dma_chan
[ch
].saved_csr
;
872 dma_chan
[ch
].saved_csr
= 0;
874 csr
= OMAP_DMA_CSR_REG(ch
);
875 if (enable_1510_mode
&& ch
<= 2 && (csr
>> 7) != 0) {
876 dma_chan
[ch
+ 6].saved_csr
= csr
>> 7;
879 if ((csr
& 0x3f) == 0)
881 if (unlikely(dma_chan
[ch
].dev_id
== -1)) {
882 printk(KERN_WARNING
"Spurious interrupt from DMA channel "
883 "%d (CSR %04x)\n", ch
, csr
);
886 if (unlikely(csr
& OMAP1_DMA_TOUT_IRQ
))
887 printk(KERN_WARNING
"DMA timeout with device %d\n",
888 dma_chan
[ch
].dev_id
);
889 if (unlikely(csr
& OMAP_DMA_DROP_IRQ
))
890 printk(KERN_WARNING
"DMA synchronization event drop occurred "
891 "with device %d\n", dma_chan
[ch
].dev_id
);
892 if (likely(csr
& OMAP_DMA_BLOCK_IRQ
))
893 dma_chan
[ch
].flags
&= ~OMAP_DMA_ACTIVE
;
894 if (likely(dma_chan
[ch
].callback
!= NULL
))
895 dma_chan
[ch
].callback(ch
, csr
, dma_chan
[ch
].data
);
899 static irqreturn_t
omap1_dma_irq_handler(int irq
, void *dev_id
)
901 int ch
= ((int) dev_id
) - 1;
907 handled_now
+= omap1_dma_handle_ch(ch
);
908 if (enable_1510_mode
&& dma_chan
[ch
+ 6].saved_csr
)
909 handled_now
+= omap1_dma_handle_ch(ch
+ 6);
912 handled
+= handled_now
;
915 return handled
? IRQ_HANDLED
: IRQ_NONE
;
919 #define omap1_dma_irq_handler NULL
922 #ifdef CONFIG_ARCH_OMAP2
924 static int omap2_dma_handle_ch(int ch
)
926 u32 status
= OMAP_DMA_CSR_REG(ch
);
930 if (unlikely(dma_chan
[ch
].dev_id
== -1))
932 if (unlikely(status
& OMAP_DMA_DROP_IRQ
))
934 "DMA synchronization event drop occurred with device "
935 "%d\n", dma_chan
[ch
].dev_id
);
936 if (unlikely(status
& OMAP2_DMA_TRANS_ERR_IRQ
))
937 printk(KERN_INFO
"DMA transaction error with device %d\n",
938 dma_chan
[ch
].dev_id
);
939 if (unlikely(status
& OMAP2_DMA_SECURE_ERR_IRQ
))
940 printk(KERN_INFO
"DMA secure error with device %d\n",
941 dma_chan
[ch
].dev_id
);
942 if (unlikely(status
& OMAP2_DMA_MISALIGNED_ERR_IRQ
))
943 printk(KERN_INFO
"DMA misaligned error with device %d\n",
944 dma_chan
[ch
].dev_id
);
946 OMAP_DMA_CSR_REG(ch
) = OMAP2_DMA_CSR_CLEAR_MASK
;
947 omap_writel(1 << ch
, OMAP_DMA4_IRQSTATUS_L0
);
949 if (likely(dma_chan
[ch
].callback
!= NULL
))
950 dma_chan
[ch
].callback(ch
, status
, dma_chan
[ch
].data
);
955 /* STATUS register count is from 1-32 while our is 0-31 */
956 static irqreturn_t
omap2_dma_irq_handler(int irq
, void *dev_id
)
961 val
= omap_readl(OMAP_DMA4_IRQSTATUS_L0
);
963 for (i
= 1; i
<= OMAP_LOGICAL_DMA_CH_COUNT
; i
++) {
964 int active
= val
& (1 << (i
- 1));
966 omap2_dma_handle_ch(i
- 1);
972 static struct irqaction omap24xx_dma_irq
= {
974 .handler
= omap2_dma_irq_handler
,
975 .flags
= IRQF_DISABLED
979 static struct irqaction omap24xx_dma_irq
;
982 /*----------------------------------------------------------------------------*/
984 static struct lcd_dma_info
{
987 void (* callback
)(u16 status
, void *data
);
991 unsigned long addr
, size
;
992 int rotate
, data_type
, xres
, yres
;
1001 void omap_set_lcd_dma_b1(unsigned long addr
, u16 fb_xres
, u16 fb_yres
,
1004 lcd_dma
.addr
= addr
;
1005 lcd_dma
.data_type
= data_type
;
1006 lcd_dma
.xres
= fb_xres
;
1007 lcd_dma
.yres
= fb_yres
;
1010 void omap_set_lcd_dma_src_port(int port
)
1012 lcd_dma
.src_port
= port
;
1015 void omap_set_lcd_dma_ext_controller(int external
)
1017 lcd_dma
.ext_ctrl
= external
;
1020 void omap_set_lcd_dma_single_transfer(int single
)
1022 lcd_dma
.single_transfer
= single
;
1026 void omap_set_lcd_dma_b1_rotation(int rotate
)
1028 if (omap_dma_in_1510_mode()) {
1029 printk(KERN_ERR
"DMA rotation is not supported in 1510 mode\n");
1033 lcd_dma
.rotate
= rotate
;
1036 void omap_set_lcd_dma_b1_mirror(int mirror
)
1038 if (omap_dma_in_1510_mode()) {
1039 printk(KERN_ERR
"DMA mirror is not supported in 1510 mode\n");
1042 lcd_dma
.mirror
= mirror
;
1045 void omap_set_lcd_dma_b1_vxres(unsigned long vxres
)
1047 if (omap_dma_in_1510_mode()) {
1048 printk(KERN_ERR
"DMA virtual resulotion is not supported "
1052 lcd_dma
.vxres
= vxres
;
1055 void omap_set_lcd_dma_b1_scale(unsigned int xscale
, unsigned int yscale
)
1057 if (omap_dma_in_1510_mode()) {
1058 printk(KERN_ERR
"DMA scale is not supported in 1510 mode\n");
1061 lcd_dma
.xscale
= xscale
;
1062 lcd_dma
.yscale
= yscale
;
1065 static void set_b1_regs(void)
1067 unsigned long top
, bottom
;
1070 unsigned long en
, fn
;
1072 unsigned long vxres
;
1073 unsigned int xscale
, yscale
;
1075 switch (lcd_dma
.data_type
) {
1076 case OMAP_DMA_DATA_TYPE_S8
:
1079 case OMAP_DMA_DATA_TYPE_S16
:
1082 case OMAP_DMA_DATA_TYPE_S32
:
1090 vxres
= lcd_dma
.vxres
? lcd_dma
.vxres
: lcd_dma
.xres
;
1091 xscale
= lcd_dma
.xscale
? lcd_dma
.xscale
: 1;
1092 yscale
= lcd_dma
.yscale
? lcd_dma
.yscale
: 1;
1093 BUG_ON(vxres
< lcd_dma
.xres
);
1094 #define PIXADDR(x,y) (lcd_dma.addr + ((y) * vxres * yscale + (x) * xscale) * es)
1095 #define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
1096 switch (lcd_dma
.rotate
) {
1098 if (!lcd_dma
.mirror
) {
1099 top
= PIXADDR(0, 0);
1100 bottom
= PIXADDR(lcd_dma
.xres
- 1, lcd_dma
.yres
- 1);
1101 /* 1510 DMA requires the bottom address to be 2 more
1102 * than the actual last memory access location. */
1103 if (omap_dma_in_1510_mode() &&
1104 lcd_dma
.data_type
== OMAP_DMA_DATA_TYPE_S32
)
1106 ei
= PIXSTEP(0, 0, 1, 0);
1107 fi
= PIXSTEP(lcd_dma
.xres
- 1, 0, 0, 1);
1109 top
= PIXADDR(lcd_dma
.xres
- 1, 0);
1110 bottom
= PIXADDR(0, lcd_dma
.yres
- 1);
1111 ei
= PIXSTEP(1, 0, 0, 0);
1112 fi
= PIXSTEP(0, 0, lcd_dma
.xres
- 1, 1);
1118 if (!lcd_dma
.mirror
) {
1119 top
= PIXADDR(0, lcd_dma
.yres
- 1);
1120 bottom
= PIXADDR(lcd_dma
.xres
- 1, 0);
1121 ei
= PIXSTEP(0, 1, 0, 0);
1122 fi
= PIXSTEP(0, 0, 1, lcd_dma
.yres
- 1);
1124 top
= PIXADDR(lcd_dma
.xres
- 1, lcd_dma
.yres
- 1);
1125 bottom
= PIXADDR(0, 0);
1126 ei
= PIXSTEP(0, 1, 0, 0);
1127 fi
= PIXSTEP(1, 0, 0, lcd_dma
.yres
- 1);
1133 if (!lcd_dma
.mirror
) {
1134 top
= PIXADDR(lcd_dma
.xres
- 1, lcd_dma
.yres
- 1);
1135 bottom
= PIXADDR(0, 0);
1136 ei
= PIXSTEP(1, 0, 0, 0);
1137 fi
= PIXSTEP(0, 1, lcd_dma
.xres
- 1, 0);
1139 top
= PIXADDR(0, lcd_dma
.yres
- 1);
1140 bottom
= PIXADDR(lcd_dma
.xres
- 1, 0);
1141 ei
= PIXSTEP(0, 0, 1, 0);
1142 fi
= PIXSTEP(lcd_dma
.xres
- 1, 1, 0, 0);
1148 if (!lcd_dma
.mirror
) {
1149 top
= PIXADDR(lcd_dma
.xres
- 1, 0);
1150 bottom
= PIXADDR(0, lcd_dma
.yres
- 1);
1151 ei
= PIXSTEP(0, 0, 0, 1);
1152 fi
= PIXSTEP(1, lcd_dma
.yres
- 1, 0, 0);
1154 top
= PIXADDR(0, 0);
1155 bottom
= PIXADDR(lcd_dma
.xres
- 1, lcd_dma
.yres
- 1);
1156 ei
= PIXSTEP(0, 0, 0, 1);
1157 fi
= PIXSTEP(0, lcd_dma
.yres
- 1, 1, 0);
1164 return; /* Supress warning about uninitialized vars */
1167 if (omap_dma_in_1510_mode()) {
1168 omap_writew(top
>> 16, OMAP1510_DMA_LCD_TOP_F1_U
);
1169 omap_writew(top
, OMAP1510_DMA_LCD_TOP_F1_L
);
1170 omap_writew(bottom
>> 16, OMAP1510_DMA_LCD_BOT_F1_U
);
1171 omap_writew(bottom
, OMAP1510_DMA_LCD_BOT_F1_L
);
1177 omap_writew(top
>> 16, OMAP1610_DMA_LCD_TOP_B1_U
);
1178 omap_writew(top
, OMAP1610_DMA_LCD_TOP_B1_L
);
1179 omap_writew(bottom
>> 16, OMAP1610_DMA_LCD_BOT_B1_U
);
1180 omap_writew(bottom
, OMAP1610_DMA_LCD_BOT_B1_L
);
1182 omap_writew(en
, OMAP1610_DMA_LCD_SRC_EN_B1
);
1183 omap_writew(fn
, OMAP1610_DMA_LCD_SRC_FN_B1
);
1185 w
= omap_readw(OMAP1610_DMA_LCD_CSDP
);
1187 w
|= lcd_dma
.data_type
;
1188 omap_writew(w
, OMAP1610_DMA_LCD_CSDP
);
1190 w
= omap_readw(OMAP1610_DMA_LCD_CTRL
);
1191 /* Always set the source port as SDRAM for now*/
1193 if (lcd_dma
.callback
!= NULL
)
1194 w
|= 1 << 1; /* Block interrupt enable */
1197 omap_writew(w
, OMAP1610_DMA_LCD_CTRL
);
1199 if (!(lcd_dma
.rotate
|| lcd_dma
.mirror
||
1200 lcd_dma
.vxres
|| lcd_dma
.xscale
|| lcd_dma
.yscale
))
1203 w
= omap_readw(OMAP1610_DMA_LCD_CCR
);
1204 /* Set the double-indexed addressing mode */
1206 omap_writew(w
, OMAP1610_DMA_LCD_CCR
);
1208 omap_writew(ei
, OMAP1610_DMA_LCD_SRC_EI_B1
);
1209 omap_writew(fi
>> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U
);
1210 omap_writew(fi
, OMAP1610_DMA_LCD_SRC_FI_B1_L
);
1213 static irqreturn_t
lcd_dma_irq_handler(int irq
, void *dev_id
)
1217 w
= omap_readw(OMAP1610_DMA_LCD_CTRL
);
1218 if (unlikely(!(w
& (1 << 3)))) {
1219 printk(KERN_WARNING
"Spurious LCD DMA IRQ\n");
1224 omap_writew(w
, OMAP1610_DMA_LCD_CTRL
);
1226 if (lcd_dma
.callback
!= NULL
)
1227 lcd_dma
.callback(w
, lcd_dma
.cb_data
);
1232 int omap_request_lcd_dma(void (* callback
)(u16 status
, void *data
),
1235 spin_lock_irq(&lcd_dma
.lock
);
1236 if (lcd_dma
.reserved
) {
1237 spin_unlock_irq(&lcd_dma
.lock
);
1238 printk(KERN_ERR
"LCD DMA channel already reserved\n");
1242 lcd_dma
.reserved
= 1;
1243 spin_unlock_irq(&lcd_dma
.lock
);
1244 lcd_dma
.callback
= callback
;
1245 lcd_dma
.cb_data
= data
;
1247 lcd_dma
.single_transfer
= 0;
1253 lcd_dma
.ext_ctrl
= 0;
1254 lcd_dma
.src_port
= 0;
1259 void omap_free_lcd_dma(void)
1261 spin_lock(&lcd_dma
.lock
);
1262 if (!lcd_dma
.reserved
) {
1263 spin_unlock(&lcd_dma
.lock
);
1264 printk(KERN_ERR
"LCD DMA is not reserved\n");
1268 if (!enable_1510_mode
)
1269 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR
) & ~1,
1270 OMAP1610_DMA_LCD_CCR
);
1271 lcd_dma
.reserved
= 0;
1272 spin_unlock(&lcd_dma
.lock
);
1275 void omap_enable_lcd_dma(void)
1279 /* Set the Enable bit only if an external controller is
1280 * connected. Otherwise the OMAP internal controller will
1281 * start the transfer when it gets enabled.
1283 if (enable_1510_mode
|| !lcd_dma
.ext_ctrl
)
1286 w
= omap_readw(OMAP1610_DMA_LCD_CTRL
);
1288 omap_writew(w
, OMAP1610_DMA_LCD_CTRL
);
1292 w
= omap_readw(OMAP1610_DMA_LCD_CCR
);
1294 omap_writew(w
, OMAP1610_DMA_LCD_CCR
);
1297 void omap_setup_lcd_dma(void)
1299 BUG_ON(lcd_dma
.active
);
1300 if (!enable_1510_mode
) {
1301 /* Set some reasonable defaults */
1302 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR
);
1303 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP
);
1304 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL
);
1307 if (!enable_1510_mode
) {
1310 w
= omap_readw(OMAP1610_DMA_LCD_CCR
);
1311 /* If DMA was already active set the end_prog bit to have
1312 * the programmed register set loaded into the active
1315 w
|= 1 << 11; /* End_prog */
1316 if (!lcd_dma
.single_transfer
)
1317 w
|= (3 << 8); /* Auto_init, repeat */
1318 omap_writew(w
, OMAP1610_DMA_LCD_CCR
);
1322 void omap_stop_lcd_dma(void)
1327 if (enable_1510_mode
|| !lcd_dma
.ext_ctrl
)
1330 w
= omap_readw(OMAP1610_DMA_LCD_CCR
);
1332 omap_writew(w
, OMAP1610_DMA_LCD_CCR
);
1334 w
= omap_readw(OMAP1610_DMA_LCD_CTRL
);
1336 omap_writew(w
, OMAP1610_DMA_LCD_CTRL
);
1339 int omap_lcd_dma_ext_running(void)
1341 return lcd_dma
.ext_ctrl
&& lcd_dma
.active
;
1344 /*----------------------------------------------------------------------------*/
1346 static int __init
omap_init_dma(void)
1350 if (cpu_is_omap15xx()) {
1351 printk(KERN_INFO
"DMA support for OMAP15xx initialized\n");
1353 enable_1510_mode
= 1;
1354 } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
1355 printk(KERN_INFO
"OMAP DMA hardware version %d\n",
1356 omap_readw(OMAP_DMA_HW_ID
));
1357 printk(KERN_INFO
"DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
1358 (omap_readw(OMAP_DMA_CAPS_0_U
) << 16) |
1359 omap_readw(OMAP_DMA_CAPS_0_L
),
1360 (omap_readw(OMAP_DMA_CAPS_1_U
) << 16) |
1361 omap_readw(OMAP_DMA_CAPS_1_L
),
1362 omap_readw(OMAP_DMA_CAPS_2
), omap_readw(OMAP_DMA_CAPS_3
),
1363 omap_readw(OMAP_DMA_CAPS_4
));
1364 if (!enable_1510_mode
) {
1367 /* Disable OMAP 3.0/3.1 compatibility mode. */
1368 w
= omap_readw(OMAP_DMA_GSCR
);
1370 omap_writew(w
, OMAP_DMA_GSCR
);
1371 dma_chan_count
= 16;
1374 if (cpu_is_omap16xx()) {
1377 /* this would prevent OMAP sleep */
1378 w
= omap_readw(OMAP1610_DMA_LCD_CTRL
);
1380 omap_writew(w
, OMAP1610_DMA_LCD_CTRL
);
1382 } else if (cpu_is_omap24xx()) {
1383 u8 revision
= omap_readb(OMAP_DMA4_REVISION
);
1384 printk(KERN_INFO
"OMAP DMA hardware revision %d.%d\n",
1385 revision
>> 4, revision
& 0xf);
1386 dma_chan_count
= OMAP_LOGICAL_DMA_CH_COUNT
;
1392 memset(&lcd_dma
, 0, sizeof(lcd_dma
));
1393 spin_lock_init(&lcd_dma
.lock
);
1394 spin_lock_init(&dma_chan_lock
);
1395 memset(&dma_chan
, 0, sizeof(dma_chan
));
1397 for (ch
= 0; ch
< dma_chan_count
; ch
++) {
1399 dma_chan
[ch
].dev_id
= -1;
1400 dma_chan
[ch
].next_lch
= -1;
1402 if (ch
>= 6 && enable_1510_mode
)
1405 if (cpu_class_is_omap1()) {
1406 /* request_irq() doesn't like dev_id (ie. ch) being
1407 * zero, so we have to kludge around this. */
1408 r
= request_irq(omap1_dma_irq
[ch
],
1409 omap1_dma_irq_handler
, 0, "DMA",
1414 printk(KERN_ERR
"unable to request IRQ %d "
1415 "for DMA (error %d)\n",
1416 omap1_dma_irq
[ch
], r
);
1417 for (i
= 0; i
< ch
; i
++)
1418 free_irq(omap1_dma_irq
[i
],
1425 if (cpu_is_omap24xx())
1426 setup_irq(INT_24XX_SDMA_IRQ0
, &omap24xx_dma_irq
);
1428 /* FIXME: Update LCD DMA to work on 24xx */
1429 if (cpu_class_is_omap1()) {
1430 r
= request_irq(INT_DMA_LCD
, lcd_dma_irq_handler
, 0,
1435 printk(KERN_ERR
"unable to request IRQ for LCD DMA "
1437 for (i
= 0; i
< dma_chan_count
; i
++)
1438 free_irq(omap1_dma_irq
[i
], (void *) (i
+ 1));
1446 arch_initcall(omap_init_dma
);
1448 EXPORT_SYMBOL(omap_get_dma_src_pos
);
1449 EXPORT_SYMBOL(omap_get_dma_dst_pos
);
1450 EXPORT_SYMBOL(omap_get_dma_src_addr_counter
);
1451 EXPORT_SYMBOL(omap_clear_dma
);
1452 EXPORT_SYMBOL(omap_set_dma_priority
);
1453 EXPORT_SYMBOL(omap_request_dma
);
1454 EXPORT_SYMBOL(omap_free_dma
);
1455 EXPORT_SYMBOL(omap_start_dma
);
1456 EXPORT_SYMBOL(omap_stop_dma
);
1457 EXPORT_SYMBOL(omap_set_dma_callback
);
1458 EXPORT_SYMBOL(omap_enable_dma_irq
);
1459 EXPORT_SYMBOL(omap_disable_dma_irq
);
1461 EXPORT_SYMBOL(omap_set_dma_transfer_params
);
1462 EXPORT_SYMBOL(omap_set_dma_color_mode
);
1463 EXPORT_SYMBOL(omap_set_dma_write_mode
);
1465 EXPORT_SYMBOL(omap_set_dma_src_params
);
1466 EXPORT_SYMBOL(omap_set_dma_src_index
);
1467 EXPORT_SYMBOL(omap_set_dma_src_data_pack
);
1468 EXPORT_SYMBOL(omap_set_dma_src_burst_mode
);
1470 EXPORT_SYMBOL(omap_set_dma_dest_params
);
1471 EXPORT_SYMBOL(omap_set_dma_dest_index
);
1472 EXPORT_SYMBOL(omap_set_dma_dest_data_pack
);
1473 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode
);
1475 EXPORT_SYMBOL(omap_set_dma_params
);
1477 EXPORT_SYMBOL(omap_dma_link_lch
);
1478 EXPORT_SYMBOL(omap_dma_unlink_lch
);
1480 EXPORT_SYMBOL(omap_request_lcd_dma
);
1481 EXPORT_SYMBOL(omap_free_lcd_dma
);
1482 EXPORT_SYMBOL(omap_enable_lcd_dma
);
1483 EXPORT_SYMBOL(omap_setup_lcd_dma
);
1484 EXPORT_SYMBOL(omap_stop_lcd_dma
);
1485 EXPORT_SYMBOL(omap_lcd_dma_ext_running
);
1486 EXPORT_SYMBOL(omap_set_lcd_dma_b1
);
1487 EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer
);
1488 EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller
);
1489 EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation
);
1490 EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres
);
1491 EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale
);
1492 EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror
);