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[PATCH] add bottom_half.h
[linux-2.6/openmoko-kernel.git] / drivers / net / smc91x.h
bloba8640169fc77afede8c7f28376ccc8967b214668
1 /*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 .
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
27 .
28 . Authors
29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@cam.org>
32 .
33 ---------------------------------------------------------------------------*/
34 #ifndef _SMC91X_H_
35 #define _SMC91X_H_
36
37
38 /*
39 * Define your architecture specific bus configuration parameters here.
40 */
41
42 #if defined(CONFIG_ARCH_LUBBOCK)
43
44 /* We can only do 16-bit reads and writes in the static memory space. */
45 #define SMC_CAN_USE_8BIT 0
46 #define SMC_CAN_USE_16BIT 1
47 #define SMC_CAN_USE_32BIT 0
48 #define SMC_NOWAIT 1
49
50 /* The first two address lines aren't connected... */
51 #define SMC_IO_SHIFT 2
52
53 #define SMC_inw(a, r) readw((a) + (r))
54 #define SMC_outw(v, a, r) writew(v, (a) + (r))
55 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
56 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
57
58 #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
59
60 /* We can only do 16-bit reads and writes in the static memory space. */
61 #define SMC_CAN_USE_8BIT 0
62 #define SMC_CAN_USE_16BIT 1
63 #define SMC_CAN_USE_32BIT 0
64 #define SMC_NOWAIT 1
65
66 #define SMC_IO_SHIFT 0
67
68 #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
69 #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
70 #define SMC_insw(a, r, p, l) \
71 do { \
72 unsigned long __port = (a) + (r); \
73 u16 *__p = (u16 *)(p); \
74 int __l = (l); \
75 insw(__port, __p, __l); \
76 while (__l > 0) { \
77 *__p = swab16(*__p); \
78 __p++; \
79 __l--; \
80 } \
81 } while (0)
82 #define SMC_outsw(a, r, p, l) \
83 do { \
84 unsigned long __port = (a) + (r); \
85 u16 *__p = (u16 *)(p); \
86 int __l = (l); \
87 while (__l > 0) { \
88 /* Believe it or not, the swab isn't needed. */ \
89 outw( /* swab16 */ (*__p++), __port); \
90 __l--; \
91 } \
92 } while (0)
93 #define SMC_IRQ_FLAGS (0)
94
95 #elif defined(CONFIG_SA1100_PLEB)
96 /* We can only do 16-bit reads and writes in the static memory space. */
97 #define SMC_CAN_USE_8BIT 1
98 #define SMC_CAN_USE_16BIT 1
99 #define SMC_CAN_USE_32BIT 0
100 #define SMC_IO_SHIFT 0
101 #define SMC_NOWAIT 1
102
103 #define SMC_inb(a, r) readb((a) + (r))
104 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
105 #define SMC_inw(a, r) readw((a) + (r))
106 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
107 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
108 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
109 #define SMC_outw(v, a, r) writew(v, (a) + (r))
110 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
111
112 #define SMC_IRQ_FLAGS (0)
113
114 #elif defined(CONFIG_SA1100_ASSABET)
115
116 #include <asm/arch/neponset.h>
117
118 /* We can only do 8-bit reads and writes in the static memory space. */
119 #define SMC_CAN_USE_8BIT 1
120 #define SMC_CAN_USE_16BIT 0
121 #define SMC_CAN_USE_32BIT 0
122 #define SMC_NOWAIT 1
123
124 /* The first two address lines aren't connected... */
125 #define SMC_IO_SHIFT 2
126
127 #define SMC_inb(a, r) readb((a) + (r))
128 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
129 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
130 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
131
132 #elif defined(CONFIG_MACH_LOGICPD_PXA270)
133
134 #define SMC_CAN_USE_8BIT 0
135 #define SMC_CAN_USE_16BIT 1
136 #define SMC_CAN_USE_32BIT 0
137 #define SMC_IO_SHIFT 0
138 #define SMC_NOWAIT 1
139
140 #define SMC_inw(a, r) readw((a) + (r))
141 #define SMC_outw(v, a, r) writew(v, (a) + (r))
142 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
143 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
144
145 #elif defined(CONFIG_ARCH_INNOKOM) || \
146 defined(CONFIG_MACH_MAINSTONE) || \
147 defined(CONFIG_ARCH_PXA_IDP) || \
148 defined(CONFIG_ARCH_RAMSES)
149
150 #define SMC_CAN_USE_8BIT 1
151 #define SMC_CAN_USE_16BIT 1
152 #define SMC_CAN_USE_32BIT 1
153 #define SMC_IO_SHIFT 0
154 #define SMC_NOWAIT 1
155 #define SMC_USE_PXA_DMA 1
156
157 #define SMC_inb(a, r) readb((a) + (r))
158 #define SMC_inw(a, r) readw((a) + (r))
159 #define SMC_inl(a, r) readl((a) + (r))
160 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
161 #define SMC_outl(v, a, r) writel(v, (a) + (r))
162 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
163 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
164
165 /* We actually can't write halfwords properly if not word aligned */
166 static inline void
167 SMC_outw(u16 val, void __iomem *ioaddr, int reg)
168 {
169 if (reg & 2) {
170 unsigned int v = val << 16;
171 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
172 writel(v, ioaddr + (reg & ~2));
173 } else {
174 writew(val, ioaddr + reg);
175 }
176 }
177
178 #elif defined(CONFIG_ARCH_OMAP)
179
180 /* We can only do 16-bit reads and writes in the static memory space. */
181 #define SMC_CAN_USE_8BIT 0
182 #define SMC_CAN_USE_16BIT 1
183 #define SMC_CAN_USE_32BIT 0
184 #define SMC_IO_SHIFT 0
185 #define SMC_NOWAIT 1
186
187 #define SMC_inw(a, r) readw((a) + (r))
188 #define SMC_outw(v, a, r) writew(v, (a) + (r))
189 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
190 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
191
192 #include <asm/mach-types.h>
193 #include <asm/arch/cpu.h>
194
195 #define SMC_IRQ_FLAGS (( \
196 machine_is_omap_h2() \
197 || machine_is_omap_h3() \
198 || machine_is_omap_h4() \
199 || (machine_is_omap_innovator() && !cpu_is_omap1510()) \
200 ) ? IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING)
201
202
203 #elif defined(CONFIG_SH_SH4202_MICRODEV)
204
205 #define SMC_CAN_USE_8BIT 0
206 #define SMC_CAN_USE_16BIT 1
207 #define SMC_CAN_USE_32BIT 0
208
209 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
210 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
211 #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
212 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
213 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
214 #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
215 #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
216 #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
217 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
218 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
219
220 #define SMC_IRQ_FLAGS (0)
221
222 #elif defined(CONFIG_ISA)
223
224 #define SMC_CAN_USE_8BIT 1
225 #define SMC_CAN_USE_16BIT 1
226 #define SMC_CAN_USE_32BIT 0
227
228 #define SMC_inb(a, r) inb((a) + (r))
229 #define SMC_inw(a, r) inw((a) + (r))
230 #define SMC_outb(v, a, r) outb(v, (a) + (r))
231 #define SMC_outw(v, a, r) outw(v, (a) + (r))
232 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
233 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
234
235 #elif defined(CONFIG_M32R)
236
237 #define SMC_CAN_USE_8BIT 0
238 #define SMC_CAN_USE_16BIT 1
239 #define SMC_CAN_USE_32BIT 0
240
241 #define SMC_inb(a, r) inb((u32)a) + (r))
242 #define SMC_inw(a, r) inw(((u32)a) + (r))
243 #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
244 #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
245 #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
246 #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
247
248 #define SMC_IRQ_FLAGS (0)
249
250 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
251 #define RPC_LSB_DEFAULT RPC_LED_100_10
252
253 #elif defined(CONFIG_MACH_LPD79520) \
254 || defined(CONFIG_MACH_LPD7A400) \
255 || defined(CONFIG_MACH_LPD7A404)
256
257 /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
258 * way that the CPU handles chip selects and the way that the SMC chip
259 * expects the chip select to operate. Refer to
260 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
261 * IOBARRIER is a byte, in order that we read the least-common
262 * denominator. It would be wasteful to read 32 bits from an 8-bit
263 * accessible region.
264 *
265 * There is no explicit protection against interrupts intervening
266 * between the writew and the IOBARRIER. In SMC ISR there is a
267 * preamble that performs an IOBARRIER in the extremely unlikely event
268 * that the driver interrupts itself between a writew to the chip an
269 * the IOBARRIER that follows *and* the cache is large enough that the
270 * first off-chip access while handing the interrupt is to the SMC
271 * chip. Other devices in the same address space as the SMC chip must
272 * be aware of the potential for trouble and perform a similar
273 * IOBARRIER on entry to their ISR.
274 */
275
276 #include <asm/arch/constants.h> /* IOBARRIER_VIRT */
277
278 #define SMC_CAN_USE_8BIT 0
279 #define SMC_CAN_USE_16BIT 1
280 #define SMC_CAN_USE_32BIT 0
281 #define SMC_NOWAIT 0
282 #define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
283
284 #define SMC_inw(a,r)\
285 ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
286 #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
287
288 #define SMC_insw LPD7_SMC_insw
289 static inline void LPD7_SMC_insw (unsigned char* a, int r,
290 unsigned char* p, int l)
291 {
292 unsigned short* ps = (unsigned short*) p;
293 while (l-- > 0) {
294 *ps++ = readw (a + r);
295 LPD7X_IOBARRIER;
296 }
297 }
298
299 #define SMC_outsw LPD7_SMC_outsw
300 static inline void LPD7_SMC_outsw (unsigned char* a, int r,
301 unsigned char* p, int l)
302 {
303 unsigned short* ps = (unsigned short*) p;
304 while (l-- > 0) {
305 writew (*ps++, a + r);
306 LPD7X_IOBARRIER;
307 }
308 }
309
310 #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
311
312 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
313 #define RPC_LSB_DEFAULT RPC_LED_100_10
314
315 #elif defined(CONFIG_SOC_AU1X00)
316
317 #include <au1xxx.h>
318
319 /* We can only do 16-bit reads and writes in the static memory space. */
320 #define SMC_CAN_USE_8BIT 0
321 #define SMC_CAN_USE_16BIT 1
322 #define SMC_CAN_USE_32BIT 0
323 #define SMC_IO_SHIFT 0
324 #define SMC_NOWAIT 1
325
326 #define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
327 #define SMC_insw(a, r, p, l) \
328 do { \
329 unsigned long _a = (unsigned long)((a) + (r)); \
330 int _l = (l); \
331 u16 *_p = (u16 *)(p); \
332 while (_l-- > 0) \
333 *_p++ = au_readw(_a); \
334 } while(0)
335 #define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
336 #define SMC_outsw(a, r, p, l) \
337 do { \
338 unsigned long _a = (unsigned long)((a) + (r)); \
339 int _l = (l); \
340 const u16 *_p = (const u16 *)(p); \
341 while (_l-- > 0) \
342 au_writew(*_p++ , _a); \
343 } while(0)
344
345 #define SMC_IRQ_FLAGS (0)
346
347 #elif defined(CONFIG_ARCH_VERSATILE)
348
349 #define SMC_CAN_USE_8BIT 1
350 #define SMC_CAN_USE_16BIT 1
351 #define SMC_CAN_USE_32BIT 1
352 #define SMC_NOWAIT 1
353
354 #define SMC_inb(a, r) readb((a) + (r))
355 #define SMC_inw(a, r) readw((a) + (r))
356 #define SMC_inl(a, r) readl((a) + (r))
357 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
358 #define SMC_outw(v, a, r) writew(v, (a) + (r))
359 #define SMC_outl(v, a, r) writel(v, (a) + (r))
360 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
361 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
362
363 #define SMC_IRQ_FLAGS (0)
364
365 #elif defined(CONFIG_ARCH_VERSATILE)
366
367 #define SMC_CAN_USE_8BIT 1
368 #define SMC_CAN_USE_16BIT 1
369 #define SMC_CAN_USE_32BIT 1
370 #define SMC_NOWAIT 1
371
372 #define SMC_inb(a, r) readb((a) + (r))
373 #define SMC_inw(a, r) readw((a) + (r))
374 #define SMC_inl(a, r) readl((a) + (r))
375 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
376 #define SMC_outw(v, a, r) writew(v, (a) + (r))
377 #define SMC_outl(v, a, r) writel(v, (a) + (r))
378 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
379 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
380
381 #define SMC_IRQ_FLAGS (0)
382
383 #elif defined(CONFIG_ARCH_VERSATILE)
384
385 #define SMC_CAN_USE_8BIT 1
386 #define SMC_CAN_USE_16BIT 1
387 #define SMC_CAN_USE_32BIT 1
388 #define SMC_NOWAIT 1
389
390 #define SMC_inb(a, r) readb((a) + (r))
391 #define SMC_inw(a, r) readw((a) + (r))
392 #define SMC_inl(a, r) readl((a) + (r))
393 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
394 #define SMC_outw(v, a, r) writew(v, (a) + (r))
395 #define SMC_outl(v, a, r) writel(v, (a) + (r))
396 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
397 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
398
399 #define SMC_IRQ_FLAGS (0)
400
401 #elif defined(CONFIG_ARCH_VERSATILE)
402
403 #define SMC_CAN_USE_8BIT 1
404 #define SMC_CAN_USE_16BIT 1
405 #define SMC_CAN_USE_32BIT 1
406 #define SMC_NOWAIT 1
407
408 #define SMC_inb(a, r) readb((a) + (r))
409 #define SMC_inw(a, r) readw((a) + (r))
410 #define SMC_inl(a, r) readl((a) + (r))
411 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
412 #define SMC_outw(v, a, r) writew(v, (a) + (r))
413 #define SMC_outl(v, a, r) writel(v, (a) + (r))
414 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
415 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
416
417 #define SMC_IRQ_FLAGS (0)
418
419 #elif defined(CONFIG_ARCH_VERSATILE)
420
421 #define SMC_CAN_USE_8BIT 1
422 #define SMC_CAN_USE_16BIT 1
423 #define SMC_CAN_USE_32BIT 1
424 #define SMC_NOWAIT 1
425
426 #define SMC_inb(a, r) readb((a) + (r))
427 #define SMC_inw(a, r) readw((a) + (r))
428 #define SMC_inl(a, r) readl((a) + (r))
429 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
430 #define SMC_outw(v, a, r) writew(v, (a) + (r))
431 #define SMC_outl(v, a, r) writel(v, (a) + (r))
432 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
433 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
434
435 #define SMC_IRQ_FLAGS (0)
436
437 #else
438
439 #define SMC_CAN_USE_8BIT 1
440 #define SMC_CAN_USE_16BIT 1
441 #define SMC_CAN_USE_32BIT 1
442 #define SMC_NOWAIT 1
443
444 #define SMC_inb(a, r) readb((a) + (r))
445 #define SMC_inw(a, r) readw((a) + (r))
446 #define SMC_inl(a, r) readl((a) + (r))
447 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
448 #define SMC_outw(v, a, r) writew(v, (a) + (r))
449 #define SMC_outl(v, a, r) writel(v, (a) + (r))
450 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
451 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
452
453 #define RPC_LSA_DEFAULT RPC_LED_100_10
454 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
455
456 #endif
457
458 #ifdef SMC_USE_PXA_DMA
459 /*
460 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
461 * always happening in irq context so no need to worry about races. TX is
462 * different and probably not worth it for that reason, and not as critical
463 * as RX which can overrun memory and lose packets.
464 */
465 #include <linux/dma-mapping.h>
466 #include <asm/dma.h>
467 #include <asm/arch/pxa-regs.h>
468
469 #ifdef SMC_insl
470 #undef SMC_insl
471 #define SMC_insl(a, r, p, l) \
472 smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l)
473 static inline void
474 smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
475 u_char *buf, int len)
476 {
477 dma_addr_t dmabuf;
478
479 /* fallback if no DMA available */
480 if (dma == (unsigned char)-1) {
481 readsl(ioaddr + reg, buf, len);
482 return;
483 }
484
485 /* 64 bit alignment is required for memory to memory DMA */
486 if ((long)buf & 4) {
487 *((u32 *)buf) = SMC_inl(ioaddr, reg);
488 buf += 4;
489 len--;
490 }
491
492 len *= 4;
493 dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
494 DCSR(dma) = DCSR_NODESC;
495 DTADR(dma) = dmabuf;
496 DSADR(dma) = physaddr + reg;
497 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
498 DCMD_WIDTH4 | (DCMD_LENGTH & len));
499 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
500 while (!(DCSR(dma) & DCSR_STOPSTATE))
501 cpu_relax();
502 DCSR(dma) = 0;
503 dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
504 }
505 #endif
506
507 #ifdef SMC_insw
508 #undef SMC_insw
509 #define SMC_insw(a, r, p, l) \
510 smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l)
511 static inline void
512 smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
513 u_char *buf, int len)
514 {
515 dma_addr_t dmabuf;
516
517 /* fallback if no DMA available */
518 if (dma == (unsigned char)-1) {
519 readsw(ioaddr + reg, buf, len);
520 return;
521 }
522
523 /* 64 bit alignment is required for memory to memory DMA */
524 while ((long)buf & 6) {
525 *((u16 *)buf) = SMC_inw(ioaddr, reg);
526 buf += 2;
527 len--;
528 }
529
530 len *= 2;
531 dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
532 DCSR(dma) = DCSR_NODESC;
533 DTADR(dma) = dmabuf;
534 DSADR(dma) = physaddr + reg;
535 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
536 DCMD_WIDTH2 | (DCMD_LENGTH & len));
537 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
538 while (!(DCSR(dma) & DCSR_STOPSTATE))
539 cpu_relax();
540 DCSR(dma) = 0;
541 dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
542 }
543 #endif
544
545 static void
546 smc_pxa_dma_irq(int dma, void *dummy)
547 {
548 DCSR(dma) = 0;
549 }
550 #endif /* SMC_USE_PXA_DMA */
551
552
553 /*
554 * Everything a particular hardware setup needs should have been defined
555 * at this point. Add stubs for the undefined cases, mainly to avoid
556 * compilation warnings since they'll be optimized away, or to prevent buggy
557 * use of them.
558 */
559
560 #if ! SMC_CAN_USE_32BIT
561 #define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
562 #define SMC_outl(x, ioaddr, reg) BUG()
563 #define SMC_insl(a, r, p, l) BUG()
564 #define SMC_outsl(a, r, p, l) BUG()
565 #endif
566
567 #if !defined(SMC_insl) || !defined(SMC_outsl)
568 #define SMC_insl(a, r, p, l) BUG()
569 #define SMC_outsl(a, r, p, l) BUG()
570 #endif
571
572 #if ! SMC_CAN_USE_16BIT
573
574 /*
575 * Any 16-bit access is performed with two 8-bit accesses if the hardware
576 * can't do it directly. Most registers are 16-bit so those are mandatory.
577 */
578 #define SMC_outw(x, ioaddr, reg) \
579 do { \
580 unsigned int __val16 = (x); \
581 SMC_outb( __val16, ioaddr, reg ); \
582 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
583 } while (0)
584 #define SMC_inw(ioaddr, reg) \
585 ({ \
586 unsigned int __val16; \
587 __val16 = SMC_inb( ioaddr, reg ); \
588 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
589 __val16; \
590 })
591
592 #define SMC_insw(a, r, p, l) BUG()
593 #define SMC_outsw(a, r, p, l) BUG()
594
595 #endif
596
597 #if !defined(SMC_insw) || !defined(SMC_outsw)
598 #define SMC_insw(a, r, p, l) BUG()
599 #define SMC_outsw(a, r, p, l) BUG()
600 #endif
601
602 #if ! SMC_CAN_USE_8BIT
603 #define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
604 #define SMC_outb(x, ioaddr, reg) BUG()
605 #define SMC_insb(a, r, p, l) BUG()
606 #define SMC_outsb(a, r, p, l) BUG()
607 #endif
608
609 #if !defined(SMC_insb) || !defined(SMC_outsb)
610 #define SMC_insb(a, r, p, l) BUG()
611 #define SMC_outsb(a, r, p, l) BUG()
612 #endif
613
614 #ifndef SMC_CAN_USE_DATACS
615 #define SMC_CAN_USE_DATACS 0
616 #endif
617
618 #ifndef SMC_IO_SHIFT
619 #define SMC_IO_SHIFT 0
620 #endif
621
622 #ifndef SMC_IRQ_FLAGS
623 #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
624 #endif
625
626 #ifndef SMC_INTERRUPT_PREAMBLE
627 #define SMC_INTERRUPT_PREAMBLE
628 #endif
629
630
631 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
632 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
633 #define SMC_DATA_EXTENT (4)
634
635 /*
636 . Bank Select Register:
637 .
638 . yyyy yyyy 0000 00xx
639 . xx = bank number
640 . yyyy yyyy = 0x33, for identification purposes.
641 */
642 #define BANK_SELECT (14 << SMC_IO_SHIFT)
643
644
645 // Transmit Control Register
646 /* BANK 0 */
647 #define TCR_REG SMC_REG(0x0000, 0)
648 #define TCR_ENABLE 0x0001 // When 1 we can transmit
649 #define TCR_LOOP 0x0002 // Controls output pin LBK
650 #define TCR_FORCOL 0x0004 // When 1 will force a collision
651 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
652 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
653 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
654 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
655 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
656 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
657 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
658
659 #define TCR_CLEAR 0 /* do NOTHING */
660 /* the default settings for the TCR register : */
661 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
662
663
664 // EPH Status Register
665 /* BANK 0 */
666 #define EPH_STATUS_REG SMC_REG(0x0002, 0)
667 #define ES_TX_SUC 0x0001 // Last TX was successful
668 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
669 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
670 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
671 #define ES_16COL 0x0010 // 16 Collisions Reached
672 #define ES_SQET 0x0020 // Signal Quality Error Test
673 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
674 #define ES_TXDEFR 0x0080 // Transmit Deferred
675 #define ES_LATCOL 0x0200 // Late collision detected on last tx
676 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
677 #define ES_EXC_DEF 0x0800 // Excessive Deferral
678 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
679 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
680 #define ES_TXUNRN 0x8000 // Tx Underrun
681
682
683 // Receive Control Register
684 /* BANK 0 */
685 #define RCR_REG SMC_REG(0x0004, 0)
686 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
687 #define RCR_PRMS 0x0002 // Enable promiscuous mode
688 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
689 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
690 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
691 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
692 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
693 #define RCR_SOFTRST 0x8000 // resets the chip
694
695 /* the normal settings for the RCR register : */
696 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
697 #define RCR_CLEAR 0x0 // set it to a base state
698
699
700 // Counter Register
701 /* BANK 0 */
702 #define COUNTER_REG SMC_REG(0x0006, 0)
703
704
705 // Memory Information Register
706 /* BANK 0 */
707 #define MIR_REG SMC_REG(0x0008, 0)
708
709
710 // Receive/Phy Control Register
711 /* BANK 0 */
712 #define RPC_REG SMC_REG(0x000A, 0)
713 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
714 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
715 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
716 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
717 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
718 #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
719 #define RPC_LED_RES (0x01) // LED = Reserved
720 #define RPC_LED_10 (0x02) // LED = 10Mbps link detect
721 #define RPC_LED_FD (0x03) // LED = Full Duplex Mode
722 #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
723 #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
724 #define RPC_LED_TX (0x06) // LED = TX packet occurred
725 #define RPC_LED_RX (0x07) // LED = RX packet occurred
726
727 #ifndef RPC_LSA_DEFAULT
728 #define RPC_LSA_DEFAULT RPC_LED_100
729 #endif
730 #ifndef RPC_LSB_DEFAULT
731 #define RPC_LSB_DEFAULT RPC_LED_FD
732 #endif
733
734 #define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
735
736
737 /* Bank 0 0x0C is reserved */
738
739 // Bank Select Register
740 /* All Banks */
741 #define BSR_REG 0x000E
742
743
744 // Configuration Reg
745 /* BANK 1 */
746 #define CONFIG_REG SMC_REG(0x0000, 1)
747 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
748 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
749 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
750 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
751
752 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
753 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
754
755
756 // Base Address Register
757 /* BANK 1 */
758 #define BASE_REG SMC_REG(0x0002, 1)
759
760
761 // Individual Address Registers
762 /* BANK 1 */
763 #define ADDR0_REG SMC_REG(0x0004, 1)
764 #define ADDR1_REG SMC_REG(0x0006, 1)
765 #define ADDR2_REG SMC_REG(0x0008, 1)
766
767
768 // General Purpose Register
769 /* BANK 1 */
770 #define GP_REG SMC_REG(0x000A, 1)
771
772
773 // Control Register
774 /* BANK 1 */
775 #define CTL_REG SMC_REG(0x000C, 1)
776 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
777 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
778 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
779 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
780 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
781 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
782 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
783 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
784
785
786 // MMU Command Register
787 /* BANK 2 */
788 #define MMU_CMD_REG SMC_REG(0x0000, 2)
789 #define MC_BUSY 1 // When 1 the last release has not completed
790 #define MC_NOP (0<<5) // No Op
791 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
792 #define MC_RESET (2<<5) // Reset MMU to initial state
793 #define MC_REMOVE (3<<5) // Remove the current rx packet
794 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
795 #define MC_FREEPKT (5<<5) // Release packet in PNR register
796 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
797 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
798
799
800 // Packet Number Register
801 /* BANK 2 */
802 #define PN_REG SMC_REG(0x0002, 2)
803
804
805 // Allocation Result Register
806 /* BANK 2 */
807 #define AR_REG SMC_REG(0x0003, 2)
808 #define AR_FAILED 0x80 // Alocation Failed
809
810
811 // TX FIFO Ports Register
812 /* BANK 2 */
813 #define TXFIFO_REG SMC_REG(0x0004, 2)
814 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
815
816 // RX FIFO Ports Register
817 /* BANK 2 */
818 #define RXFIFO_REG SMC_REG(0x0005, 2)
819 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
820
821 #define FIFO_REG SMC_REG(0x0004, 2)
822
823 // Pointer Register
824 /* BANK 2 */
825 #define PTR_REG SMC_REG(0x0006, 2)
826 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
827 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
828 #define PTR_READ 0x2000 // When 1 the operation is a read
829
830
831 // Data Register
832 /* BANK 2 */
833 #define DATA_REG SMC_REG(0x0008, 2)
834
835
836 // Interrupt Status/Acknowledge Register
837 /* BANK 2 */
838 #define INT_REG SMC_REG(0x000C, 2)
839
840
841 // Interrupt Mask Register
842 /* BANK 2 */
843 #define IM_REG SMC_REG(0x000D, 2)
844 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
845 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
846 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
847 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
848 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
849 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
850 #define IM_TX_INT 0x02 // Transmit Interrupt
851 #define IM_RCV_INT 0x01 // Receive Interrupt
852
853
854 // Multicast Table Registers
855 /* BANK 3 */
856 #define MCAST_REG1 SMC_REG(0x0000, 3)
857 #define MCAST_REG2 SMC_REG(0x0002, 3)
858 #define MCAST_REG3 SMC_REG(0x0004, 3)
859 #define MCAST_REG4 SMC_REG(0x0006, 3)
860
861
862 // Management Interface Register (MII)
863 /* BANK 3 */
864 #define MII_REG SMC_REG(0x0008, 3)
865 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
866 #define MII_MDOE 0x0008 // MII Output Enable
867 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
868 #define MII_MDI 0x0002 // MII Input, pin MDI
869 #define MII_MDO 0x0001 // MII Output, pin MDO
870
871
872 // Revision Register
873 /* BANK 3 */
874 /* ( hi: chip id low: rev # ) */
875 #define REV_REG SMC_REG(0x000A, 3)
876
877
878 // Early RCV Register
879 /* BANK 3 */
880 /* this is NOT on SMC9192 */
881 #define ERCV_REG SMC_REG(0x000C, 3)
882 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
883 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
884
885
886 // External Register
887 /* BANK 7 */
888 #define EXT_REG SMC_REG(0x0000, 7)
889
890
891 #define CHIP_9192 3
892 #define CHIP_9194 4
893 #define CHIP_9195 5
894 #define CHIP_9196 6
895 #define CHIP_91100 7
896 #define CHIP_91100FD 8
897 #define CHIP_91111FD 9
898
899 static const char * chip_ids[ 16 ] = {
900 NULL, NULL, NULL,
901 /* 3 */ "SMC91C90/91C92",
902 /* 4 */ "SMC91C94",
903 /* 5 */ "SMC91C95",
904 /* 6 */ "SMC91C96",
905 /* 7 */ "SMC91C100",
906 /* 8 */ "SMC91C100FD",
907 /* 9 */ "SMC91C11xFD",
908 NULL, NULL, NULL,
909 NULL, NULL, NULL};
910
911
912 /*
913 . Receive status bits
914 */
915 #define RS_ALGNERR 0x8000
916 #define RS_BRODCAST 0x4000
917 #define RS_BADCRC 0x2000
918 #define RS_ODDFRAME 0x1000
919 #define RS_TOOLONG 0x0800
920 #define RS_TOOSHORT 0x0400
921 #define RS_MULTICAST 0x0001
922 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
923
924
925 /*
926 * PHY IDs
927 * LAN83C183 == LAN91C111 Internal PHY
928 */
929 #define PHY_LAN83C183 0x0016f840
930 #define PHY_LAN83C180 0x02821c50
931
932 /*
933 * PHY Register Addresses (LAN91C111 Internal PHY)
934 *
935 * Generic PHY registers can be found in <linux/mii.h>
936 *
937 * These phy registers are specific to our on-board phy.
938 */
939
940 // PHY Configuration Register 1
941 #define PHY_CFG1_REG 0x10
942 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
943 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
944 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
945 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
946 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
947 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
948 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
949 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
950 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
951 #define PHY_CFG1_TLVL_MASK 0x003C
952 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
953
954
955 // PHY Configuration Register 2
956 #define PHY_CFG2_REG 0x11
957 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
958 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
959 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
960 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
961
962 // PHY Status Output (and Interrupt status) Register
963 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
964 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
965 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
966 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
967 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
968 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
969 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
970 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
971 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
972 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
973 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
974
975 // PHY Interrupt/Status Mask Register
976 #define PHY_MASK_REG 0x13 // Interrupt Mask
977 // Uses the same bit definitions as PHY_INT_REG
978
979
980 /*
981 * SMC91C96 ethernet config and status registers.
982 * These are in the "attribute" space.
983 */
984 #define ECOR 0x8000
985 #define ECOR_RESET 0x80
986 #define ECOR_LEVEL_IRQ 0x40
987 #define ECOR_WR_ATTRIB 0x04
988 #define ECOR_ENABLE 0x01
989
990 #define ECSR 0x8002
991 #define ECSR_IOIS8 0x20
992 #define ECSR_PWRDWN 0x04
993 #define ECSR_INT 0x02
994
995 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
996
997
998 /*
999 * Macros to abstract register access according to the data bus
1000 * capabilities. Please use those and not the in/out primitives.
1001 * Note: the following macros do *not* select the bank -- this must
1002 * be done separately as needed in the main code. The SMC_REG() macro
1003 * only uses the bank argument for debugging purposes (when enabled).
1004 *
1005 * Note: despite inline functions being safer, everything leading to this
1006 * should preferably be macros to let BUG() display the line number in
1007 * the core source code since we're interested in the top call site
1008 * not in any inline function location.
1009 */
1010
1011 #if SMC_DEBUG > 0
1012 #define SMC_REG(reg, bank) \
1013 ({ \
1014 int __b = SMC_CURRENT_BANK(); \
1015 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
1016 printk( "%s: bank reg screwed (0x%04x)\n", \
1017 CARDNAME, __b ); \
1018 BUG(); \
1019 } \
1020 reg<<SMC_IO_SHIFT; \
1021 })
1022 #else
1023 #define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT)
1024 #endif
1025
1026 /*
1027 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
1028 * aligned to a 32 bit boundary. I tell you that does exist!
1029 * Fortunately the affected register accesses can be easily worked around
1030 * since we can write zeroes to the preceeding 16 bits without adverse
1031 * effects and use a 32-bit access.
1032 *
1033 * Enforce it on any 32-bit capable setup for now.
1034 */
1035 #define SMC_MUST_ALIGN_WRITE SMC_CAN_USE_32BIT
1036
1037 #define SMC_GET_PN() \
1038 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, PN_REG)) \
1039 : (SMC_inw(ioaddr, PN_REG) & 0xFF) )
1040
1041 #define SMC_SET_PN(x) \
1042 do { \
1043 if (SMC_MUST_ALIGN_WRITE) \
1044 SMC_outl((x)<<16, ioaddr, SMC_REG(0, 2)); \
1045 else if (SMC_CAN_USE_8BIT) \
1046 SMC_outb(x, ioaddr, PN_REG); \
1047 else \
1048 SMC_outw(x, ioaddr, PN_REG); \
1049 } while (0)
1050
1051 #define SMC_GET_AR() \
1052 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, AR_REG)) \
1053 : (SMC_inw(ioaddr, PN_REG) >> 8) )
1054
1055 #define SMC_GET_TXFIFO() \
1056 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, TXFIFO_REG)) \
1057 : (SMC_inw(ioaddr, TXFIFO_REG) & 0xFF) )
1058
1059 #define SMC_GET_RXFIFO() \
1060 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, RXFIFO_REG)) \
1061 : (SMC_inw(ioaddr, TXFIFO_REG) >> 8) )
1062
1063 #define SMC_GET_INT() \
1064 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, INT_REG)) \
1065 : (SMC_inw(ioaddr, INT_REG) & 0xFF) )
1066
1067 #define SMC_ACK_INT(x) \
1068 do { \
1069 if (SMC_CAN_USE_8BIT) \
1070 SMC_outb(x, ioaddr, INT_REG); \
1071 else { \
1072 unsigned long __flags; \
1073 int __mask; \
1074 local_irq_save(__flags); \
1075 __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \
1076 SMC_outw( __mask | (x), ioaddr, INT_REG ); \
1077 local_irq_restore(__flags); \
1078 } \
1079 } while (0)
1080
1081 #define SMC_GET_INT_MASK() \
1082 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG)) \
1083 : (SMC_inw( ioaddr, INT_REG ) >> 8) )
1084
1085 #define SMC_SET_INT_MASK(x) \
1086 do { \
1087 if (SMC_CAN_USE_8BIT) \
1088 SMC_outb(x, ioaddr, IM_REG); \
1089 else \
1090 SMC_outw((x) << 8, ioaddr, INT_REG); \
1091 } while (0)
1092
1093 #define SMC_CURRENT_BANK() SMC_inw(ioaddr, BANK_SELECT)
1094
1095 #define SMC_SELECT_BANK(x) \
1096 do { \
1097 if (SMC_MUST_ALIGN_WRITE) \
1098 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
1099 else \
1100 SMC_outw(x, ioaddr, BANK_SELECT); \
1101 } while (0)
1102
1103 #define SMC_GET_BASE() SMC_inw(ioaddr, BASE_REG)
1104
1105 #define SMC_SET_BASE(x) SMC_outw(x, ioaddr, BASE_REG)
1106
1107 #define SMC_GET_CONFIG() SMC_inw(ioaddr, CONFIG_REG)
1108
1109 #define SMC_SET_CONFIG(x) SMC_outw(x, ioaddr, CONFIG_REG)
1110
1111 #define SMC_GET_COUNTER() SMC_inw(ioaddr, COUNTER_REG)
1112
1113 #define SMC_GET_CTL() SMC_inw(ioaddr, CTL_REG)
1114
1115 #define SMC_SET_CTL(x) SMC_outw(x, ioaddr, CTL_REG)
1116
1117 #define SMC_GET_MII() SMC_inw(ioaddr, MII_REG)
1118
1119 #define SMC_SET_MII(x) SMC_outw(x, ioaddr, MII_REG)
1120
1121 #define SMC_GET_MIR() SMC_inw(ioaddr, MIR_REG)
1122
1123 #define SMC_SET_MIR(x) SMC_outw(x, ioaddr, MIR_REG)
1124
1125 #define SMC_GET_MMU_CMD() SMC_inw(ioaddr, MMU_CMD_REG)
1126
1127 #define SMC_SET_MMU_CMD(x) SMC_outw(x, ioaddr, MMU_CMD_REG)
1128
1129 #define SMC_GET_FIFO() SMC_inw(ioaddr, FIFO_REG)
1130
1131 #define SMC_GET_PTR() SMC_inw(ioaddr, PTR_REG)
1132
1133 #define SMC_SET_PTR(x) \
1134 do { \
1135 if (SMC_MUST_ALIGN_WRITE) \
1136 SMC_outl((x)<<16, ioaddr, SMC_REG(4, 2)); \
1137 else \
1138 SMC_outw(x, ioaddr, PTR_REG); \
1139 } while (0)
1140
1141 #define SMC_GET_EPH_STATUS() SMC_inw(ioaddr, EPH_STATUS_REG)
1142
1143 #define SMC_GET_RCR() SMC_inw(ioaddr, RCR_REG)
1144
1145 #define SMC_SET_RCR(x) SMC_outw(x, ioaddr, RCR_REG)
1146
1147 #define SMC_GET_REV() SMC_inw(ioaddr, REV_REG)
1148
1149 #define SMC_GET_RPC() SMC_inw(ioaddr, RPC_REG)
1150
1151 #define SMC_SET_RPC(x) \
1152 do { \
1153 if (SMC_MUST_ALIGN_WRITE) \
1154 SMC_outl((x)<<16, ioaddr, SMC_REG(8, 0)); \
1155 else \
1156 SMC_outw(x, ioaddr, RPC_REG); \
1157 } while (0)
1158
1159 #define SMC_GET_TCR() SMC_inw(ioaddr, TCR_REG)
1160
1161 #define SMC_SET_TCR(x) SMC_outw(x, ioaddr, TCR_REG)
1162
1163 #ifndef SMC_GET_MAC_ADDR
1164 #define SMC_GET_MAC_ADDR(addr) \
1165 do { \
1166 unsigned int __v; \
1167 __v = SMC_inw( ioaddr, ADDR0_REG ); \
1168 addr[0] = __v; addr[1] = __v >> 8; \
1169 __v = SMC_inw( ioaddr, ADDR1_REG ); \
1170 addr[2] = __v; addr[3] = __v >> 8; \
1171 __v = SMC_inw( ioaddr, ADDR2_REG ); \
1172 addr[4] = __v; addr[5] = __v >> 8; \
1173 } while (0)
1174 #endif
1175
1176 #define SMC_SET_MAC_ADDR(addr) \
1177 do { \
1178 SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \
1179 SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \
1180 SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \
1181 } while (0)
1182
1183 #define SMC_SET_MCAST(x) \
1184 do { \
1185 const unsigned char *mt = (x); \
1186 SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \
1187 SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \
1188 SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \
1189 SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \
1190 } while (0)
1191
1192 #define SMC_PUT_PKT_HDR(status, length) \
1193 do { \
1194 if (SMC_CAN_USE_32BIT) \
1195 SMC_outl((status) | (length)<<16, ioaddr, DATA_REG); \
1196 else { \
1197 SMC_outw(status, ioaddr, DATA_REG); \
1198 SMC_outw(length, ioaddr, DATA_REG); \
1199 } \
1200 } while (0)
1201
1202 #define SMC_GET_PKT_HDR(status, length) \
1203 do { \
1204 if (SMC_CAN_USE_32BIT) { \
1205 unsigned int __val = SMC_inl(ioaddr, DATA_REG); \
1206 (status) = __val & 0xffff; \
1207 (length) = __val >> 16; \
1208 } else { \
1209 (status) = SMC_inw(ioaddr, DATA_REG); \
1210 (length) = SMC_inw(ioaddr, DATA_REG); \
1211 } \
1212 } while (0)
1213
1214 #define SMC_PUSH_DATA(p, l) \
1215 do { \
1216 if (SMC_CAN_USE_32BIT) { \
1217 void *__ptr = (p); \
1218 int __len = (l); \
1219 void *__ioaddr = ioaddr; \
1220 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1221 __len -= 2; \
1222 SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \
1223 __ptr += 2; \
1224 } \
1225 if (SMC_CAN_USE_DATACS && lp->datacs) \
1226 __ioaddr = lp->datacs; \
1227 SMC_outsl(__ioaddr, DATA_REG, __ptr, __len>>2); \
1228 if (__len & 2) { \
1229 __ptr += (__len & ~3); \
1230 SMC_outw(*((u16 *)__ptr), ioaddr, DATA_REG); \
1231 } \
1232 } else if (SMC_CAN_USE_16BIT) \
1233 SMC_outsw(ioaddr, DATA_REG, p, (l) >> 1); \
1234 else if (SMC_CAN_USE_8BIT) \
1235 SMC_outsb(ioaddr, DATA_REG, p, l); \
1236 } while (0)
1237
1238 #define SMC_PULL_DATA(p, l) \
1239 do { \
1240 if (SMC_CAN_USE_32BIT) { \
1241 void *__ptr = (p); \
1242 int __len = (l); \
1243 void *__ioaddr = ioaddr; \
1244 if ((unsigned long)__ptr & 2) { \
1245 /* \
1246 * We want 32bit alignment here. \
1247 * Since some buses perform a full \
1248 * 32bit fetch even for 16bit data \
1249 * we can't use SMC_inw() here. \
1250 * Back both source (on-chip) and \
1251 * destination pointers of 2 bytes. \
1252 * This is possible since the call to \
1253 * SMC_GET_PKT_HDR() already advanced \
1254 * the source pointer of 4 bytes, and \
1255 * the skb_reserve(skb, 2) advanced \
1256 * the destination pointer of 2 bytes. \
1257 */ \
1258 __ptr -= 2; \
1259 __len += 2; \
1260 SMC_SET_PTR(2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1261 } \
1262 if (SMC_CAN_USE_DATACS && lp->datacs) \
1263 __ioaddr = lp->datacs; \
1264 __len += 2; \
1265 SMC_insl(__ioaddr, DATA_REG, __ptr, __len>>2); \
1266 } else if (SMC_CAN_USE_16BIT) \
1267 SMC_insw(ioaddr, DATA_REG, p, (l) >> 1); \
1268 else if (SMC_CAN_USE_8BIT) \
1269 SMC_insb(ioaddr, DATA_REG, p, l); \
1270 } while (0)
1271
1272 #endif /* _SMC91X_H_ */
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