include/asm-blackfin/mach-bf561/bfin_serial_5xx.h

   1 /*
   2  * file:        include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
   3  * based on:
   4  * author:
   5  *
   6  * created:
   7  * description:
   8  *      blackfin serial driver head file
   9  * rev:
  10  *
  11  * modified:
  12  *
  13  *
  14  * bugs:         enter bugs at http://blackfin.uclinux.org/
  15  *
  16  * this program is free software; you can redistribute it and/or modify
  17  * it under the terms of the gnu general public license as published by
  18  * the free software foundation; either version 2, or (at your option)
  19  * any later version.
  20  *
  21  * this program is distributed in the hope that it will be useful,
  22  * but without any warranty; without even the implied warranty of
  23  * merchantability or fitness for a particular purpose.  see the
  24  * gnu general public license for more details.
  25  *
  26  * you should have received a copy of the gnu general public license
  27  * along with this program; see the file copying.
  28  * if not, write to the free software foundation,
  29  * 59 temple place - suite 330, boston, ma 02111-1307, usa.
  30  */
  31
  32 #include <linux/serial.h>
  33 #include <asm/dma.h>
  34 #include <asm/portmux.h>
  35
  36 #define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
  37 #define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
  38 #define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
  39 #define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
  40 #define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
  41 #define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
  42 #define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
  43
  44 #define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
  45 #define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
  46 #define UART_PUT_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER),v)
  47 #define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
  48 #define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
  49 #define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
  50
  51 #ifdef CONFIG_BFIN_UART0_CTSRTS
  52 # define CONFIG_SERIAL_BFIN_CTSRTS
  53 # ifndef CONFIG_UART0_CTS_PIN
  54 #  define CONFIG_UART0_CTS_PIN -1
  55 # endif
  56 # ifndef CONFIG_UART0_RTS_PIN
  57 #  define CONFIG_UART0_RTS_PIN -1
  58 # endif
  59 #endif
  60
  61 struct bfin_serial_port {
  62         struct uart_port        port;
  63         unsigned int            old_status;
  64         unsigned int lsr;
  65 #ifdef CONFIG_SERIAL_BFIN_DMA
  66         int                     tx_done;
  67         int                     tx_count;
  68         struct circ_buf         rx_dma_buf;
  69         struct timer_list       rx_dma_timer;
  70         int                     rx_dma_nrows;
  71         unsigned int            tx_dma_channel;
  72         unsigned int            rx_dma_channel;
  73         struct work_struct      tx_dma_workqueue;
  74 #else
  75 # if ANOMALY_05000230
  76         unsigned int anomaly_threshold;
  77 # endif
  78 #endif
  79 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
  80         struct work_struct      cts_workqueue;
  81         int                     cts_pin;
  82         int                     rts_pin;
  83 #endif
  84 };
  85
  86 /* The hardware clears the LSR bits upon read, so we need to cache
  87  * some of the more fun bits in software so they don't get lost
  88  * when checking the LSR in other code paths (TX).
  89  */
  90 static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
  91 {
  92         unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
  93         uart->lsr |= (lsr & (BI|FE|PE|OE));
  94         return lsr | uart->lsr;
  95 }
  96
  97 static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
  98 {
  99         uart->lsr = 0;
 100         bfin_write16(uart->port.membase + OFFSET_LSR, -1);
 101 }
 102
 103 struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
 104 struct bfin_serial_res {
 105         unsigned long   uart_base_addr;
 106         int             uart_irq;
 107 #ifdef CONFIG_SERIAL_BFIN_DMA
 108         unsigned int    uart_tx_dma_channel;
 109         unsigned int    uart_rx_dma_channel;
 110 #endif
 111 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 112         int             uart_cts_pin;
 113         int             uart_rts_pin;
 114 #endif
 115 };
 116
 117 struct bfin_serial_res bfin_serial_resource[] = {
 118         {
 119         0xFFC00400,
 120         IRQ_UART_RX,
 121 #ifdef CONFIG_SERIAL_BFIN_DMA
 122         CH_UART_TX,
 123         CH_UART_RX,
 124 #endif
 125 #ifdef CONFIG_BFIN_UART0_CTSRTS
 126         CONFIG_UART0_CTS_PIN,
 127         CONFIG_UART0_RTS_PIN,
 128 #endif
 129         }
 130 };
 131
 132 #define DRIVER_NAME "bfin-uart"
 133
 134 int nr_ports = BFIN_UART_NR_PORTS;
 135 static void bfin_serial_hw_init(struct bfin_serial_port *uart)
 136 {
 137
 138 #ifdef CONFIG_SERIAL_BFIN_UART0
 139         peripheral_request(P_UART0_TX, DRIVER_NAME);
 140         peripheral_request(P_UART0_RX, DRIVER_NAME);
 141 #endif
 142
 143 #ifdef CONFIG_SERIAL_BFIN_CTSRTS
 144         if (uart->cts_pin >= 0) {
 145                 gpio_request(uart->cts_pin, DRIVER_NAME);
 146                 gpio_direction_input(uart->cts_pin);
 147         }
 148         if (uart->rts_pin >= 0) {
 149                 gpio_request(uart->rts_pin, DRIVER_NAME);
 150                 gpio_direction_input(uart->rts_pin, 0);
 151         }
 152 #endif
 153 }