include/linux/mtd/nand.h

   1 /*
   2  *  linux/include/linux/mtd/nand.h
   3  *
   4  *  Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
   5  *                     Steven J. Hill <sjhill@realitydiluted.com>
   6  *                     Thomas Gleixner <tglx@linutronix.de>
   7  *
   8  * $Id: nand.h,v 1.74 2005/09/15 13:58:50 vwool Exp $
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * Info:
  15  *      Contains standard defines and IDs for NAND flash devices
  16  *
  17  * Changelog:
  18  *      See git changelog.
  19  */
  20 #ifndef __LINUX_MTD_NAND_H
  21 #define __LINUX_MTD_NAND_H
  22
  23 #include <linux/wait.h>
  24 #include <linux/spinlock.h>
  25 #include <linux/mtd/mtd.h>
  26
  27 struct mtd_info;
  28 /* Scan and identify a NAND device */
  29 extern int nand_scan (struct mtd_info *mtd, int max_chips);
  30 /* Separate phases of nand_scan(), allowing board driver to intervene
  31  * and override command or ECC setup according to flash type */
  32 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips);
  33 extern int nand_scan_tail(struct mtd_info *mtd);
  34
  35 /* Free resources held by the NAND device */
  36 extern void nand_release (struct mtd_info *mtd);
  37
  38 /* The maximum number of NAND chips in an array */
  39 #define NAND_MAX_CHIPS          8
  40
  41 /* This constant declares the max. oobsize / page, which
  42  * is supported now. If you add a chip with bigger oobsize/page
  43  * adjust this accordingly.
  44  */
  45 #define NAND_MAX_OOBSIZE        64
  46 #define NAND_MAX_PAGESIZE       2048
  47
  48 /*
  49  * Constants for hardware specific CLE/ALE/NCE function
  50  *
  51  * These are bits which can be or'ed to set/clear multiple
  52  * bits in one go.
  53  */
  54 /* Select the chip by setting nCE to low */
  55 #define NAND_NCE                0x01
  56 /* Select the command latch by setting CLE to high */
  57 #define NAND_CLE                0x02
  58 /* Select the address latch by setting ALE to high */
  59 #define NAND_ALE                0x04
  60
  61 #define NAND_CTRL_CLE           (NAND_NCE | NAND_CLE)
  62 #define NAND_CTRL_ALE           (NAND_NCE | NAND_ALE)
  63 #define NAND_CTRL_CHANGE        0x80
  64
  65 /*
  66  * Standard NAND flash commands
  67  */
  68 #define NAND_CMD_READ0          0
  69 #define NAND_CMD_READ1          1
  70 #define NAND_CMD_RNDOUT         5
  71 #define NAND_CMD_PAGEPROG       0x10
  72 #define NAND_CMD_READOOB        0x50
  73 #define NAND_CMD_ERASE1         0x60
  74 #define NAND_CMD_STATUS         0x70
  75 #define NAND_CMD_STATUS_MULTI   0x71
  76 #define NAND_CMD_SEQIN          0x80
  77 #define NAND_CMD_RNDIN          0x85
  78 #define NAND_CMD_READID         0x90
  79 #define NAND_CMD_ERASE2         0xd0
  80 #define NAND_CMD_RESET          0xff
  81
  82 /* Extended commands for large page devices */
  83 #define NAND_CMD_READSTART      0x30
  84 #define NAND_CMD_RNDOUTSTART    0xE0
  85 #define NAND_CMD_CACHEDPROG     0x15
  86
  87 /* Extended commands for AG-AND device */
  88 /*
  89  * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
  90  *       there is no way to distinguish that from NAND_CMD_READ0
  91  *       until the remaining sequence of commands has been completed
  92  *       so add a high order bit and mask it off in the command.
  93  */
  94 #define NAND_CMD_DEPLETE1       0x100
  95 #define NAND_CMD_DEPLETE2       0x38
  96 #define NAND_CMD_STATUS_MULTI   0x71
  97 #define NAND_CMD_STATUS_ERROR   0x72
  98 /* multi-bank error status (banks 0-3) */
  99 #define NAND_CMD_STATUS_ERROR0  0x73
 100 #define NAND_CMD_STATUS_ERROR1  0x74
 101 #define NAND_CMD_STATUS_ERROR2  0x75
 102 #define NAND_CMD_STATUS_ERROR3  0x76
 103 #define NAND_CMD_STATUS_RESET   0x7f
 104 #define NAND_CMD_STATUS_CLEAR   0xff
 105
 106 #define NAND_CMD_NONE           -1
 107
 108 /* Status bits */
 109 #define NAND_STATUS_FAIL        0x01
 110 #define NAND_STATUS_FAIL_N1     0x02
 111 #define NAND_STATUS_TRUE_READY  0x20
 112 #define NAND_STATUS_READY       0x40
 113 #define NAND_STATUS_WP          0x80
 114
 115 /*
 116  * Constants for ECC_MODES
 117  */
 118 typedef enum {
 119         NAND_ECC_NONE,
 120         NAND_ECC_SOFT,
 121         NAND_ECC_HW,
 122         NAND_ECC_HW_SYNDROME,
 123 } nand_ecc_modes_t;
 124
 125 /*
 126  * Constants for Hardware ECC
 127  */
 128 /* Reset Hardware ECC for read */
 129 #define NAND_ECC_READ           0
 130 /* Reset Hardware ECC for write */
 131 #define NAND_ECC_WRITE          1
 132 /* Enable Hardware ECC before syndrom is read back from flash */
 133 #define NAND_ECC_READSYN        2
 134
 135 /* Bit mask for flags passed to do_nand_read_ecc */
 136 #define NAND_GET_DEVICE         0x80
 137
 138
 139 /* Option constants for bizarre disfunctionality and real
 140 *  features
 141 */
 142 /* Chip can not auto increment pages */
 143 #define NAND_NO_AUTOINCR        0x00000001
 144 /* Buswitdh is 16 bit */
 145 #define NAND_BUSWIDTH_16        0x00000002
 146 /* Device supports partial programming without padding */
 147 #define NAND_NO_PADDING         0x00000004
 148 /* Chip has cache program function */
 149 #define NAND_CACHEPRG           0x00000008
 150 /* Chip has copy back function */
 151 #define NAND_COPYBACK           0x00000010
 152 /* AND Chip which has 4 banks and a confusing page / block
 153  * assignment. See Renesas datasheet for further information */
 154 #define NAND_IS_AND             0x00000020
 155 /* Chip has a array of 4 pages which can be read without
 156  * additional ready /busy waits */
 157 #define NAND_4PAGE_ARRAY        0x00000040
 158 /* Chip requires that BBT is periodically rewritten to prevent
 159  * bits from adjacent blocks from 'leaking' in altering data.
 160  * This happens with the Renesas AG-AND chips, possibly others.  */
 161 #define BBT_AUTO_REFRESH        0x00000080
 162 /* Chip does not require ready check on read. True
 163  * for all large page devices, as they do not support
 164  * autoincrement.*/
 165 #define NAND_NO_READRDY         0x00000100
 166
 167 /* Options valid for Samsung large page devices */
 168 #define NAND_SAMSUNG_LP_OPTIONS \
 169         (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
 170
 171 /* Macros to identify the above */
 172 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
 173 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
 174 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
 175 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
 176
 177 /* Mask to zero out the chip options, which come from the id table */
 178 #define NAND_CHIPOPTIONS_MSK    (0x0000ffff & ~NAND_NO_AUTOINCR)
 179
 180 /* Non chip related options */
 181 /* Use a flash based bad block table. This option is passed to the
 182  * default bad block table function. */
 183 #define NAND_USE_FLASH_BBT      0x00010000
 184 /* This option skips the bbt scan during initialization. */
 185 #define NAND_SKIP_BBTSCAN       0x00020000
 186
 187 /* Options set by nand scan */
 188 /* Nand scan has allocated controller struct */
 189 #define NAND_CONTROLLER_ALLOC   0x80000000
 190
 191
 192 /*
 193  * nand_state_t - chip states
 194  * Enumeration for NAND flash chip state
 195  */
 196 typedef enum {
 197         FL_READY,
 198         FL_READING,
 199         FL_WRITING,
 200         FL_ERASING,
 201         FL_SYNCING,
 202         FL_CACHEDPRG,
 203         FL_PM_SUSPENDED,
 204 } nand_state_t;
 205
 206 /* Keep gcc happy */
 207 struct nand_chip;
 208
 209 /**
 210  * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
 211  * @lock:               protection lock
 212  * @active:             the mtd device which holds the controller currently
 213  * @wq:                 wait queue to sleep on if a NAND operation is in progress
 214  *                      used instead of the per chip wait queue when a hw controller is available
 215  */
 216 struct nand_hw_control {
 217         spinlock_t       lock;
 218         struct nand_chip *active;
 219         wait_queue_head_t wq;
 220 };
 221
 222 /**
 223  * struct nand_ecc_ctrl - Control structure for ecc
 224  * @mode:       ecc mode
 225  * @steps:      number of ecc steps per page
 226  * @size:       data bytes per ecc step
 227  * @bytes:      ecc bytes per step
 228  * @total:      total number of ecc bytes per page
 229  * @prepad:     padding information for syndrome based ecc generators
 230  * @postpad:    padding information for syndrome based ecc generators
 231  * @layout:     ECC layout control struct pointer
 232  * @hwctl:      function to control hardware ecc generator. Must only
 233  *              be provided if an hardware ECC is available
 234  * @calculate:  function for ecc calculation or readback from ecc hardware
 235  * @correct:    function for ecc correction, matching to ecc generator (sw/hw)
 236  * @read_page:  function to read a page according to the ecc generator requirements
 237  * @write_page: function to write a page according to the ecc generator requirements
 238  * @read_oob:   function to read chip OOB data
 239  * @write_oob:  function to write chip OOB data
 240  */
 241 struct nand_ecc_ctrl {
 242         nand_ecc_modes_t        mode;
 243         int                     steps;
 244         int                     size;
 245         int                     bytes;
 246         int                     total;
 247         int                     prepad;
 248         int                     postpad;
 249         struct nand_ecclayout   *layout;
 250         void                    (*hwctl)(struct mtd_info *mtd, int mode);
 251         int                     (*calculate)(struct mtd_info *mtd,
 252                                              const uint8_t *dat,
 253                                              uint8_t *ecc_code);
 254         int                     (*correct)(struct mtd_info *mtd, uint8_t *dat,
 255                                            uint8_t *read_ecc,
 256                                            uint8_t *calc_ecc);
 257         int                     (*read_page)(struct mtd_info *mtd,
 258                                              struct nand_chip *chip,
 259                                              uint8_t *buf);
 260         void                    (*write_page)(struct mtd_info *mtd,
 261                                               struct nand_chip *chip,
 262                                               const uint8_t *buf);
 263         int                     (*read_oob)(struct mtd_info *mtd,
 264                                             struct nand_chip *chip,
 265                                             int page,
 266                                             int sndcmd);
 267         int                     (*write_oob)(struct mtd_info *mtd,
 268                                              struct nand_chip *chip,
 269                                              int page);
 270 };
 271
 272 /**
 273  * struct nand_buffers - buffer structure for read/write
 274  * @ecccalc:    buffer for calculated ecc
 275  * @ecccode:    buffer for ecc read from flash
 276  * @oobwbuf:    buffer for write oob data
 277  * @databuf:    buffer for data - dynamically sized
 278  * @oobrbuf:    buffer to read oob data
 279  *
 280  * Do not change the order of buffers. databuf and oobrbuf must be in
 281  * consecutive order.
 282  */
 283 struct nand_buffers {
 284         uint8_t ecccalc[NAND_MAX_OOBSIZE];
 285         uint8_t ecccode[NAND_MAX_OOBSIZE];
 286         uint8_t oobwbuf[NAND_MAX_OOBSIZE];
 287         uint8_t databuf[NAND_MAX_PAGESIZE];
 288         uint8_t oobrbuf[NAND_MAX_OOBSIZE];
 289 };
 290
 291 /**
 292  * struct nand_chip - NAND Private Flash Chip Data
 293  * @IO_ADDR_R:          [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
 294  * @IO_ADDR_W:          [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
 295  * @read_byte:          [REPLACEABLE] read one byte from the chip
 296  * @read_word:          [REPLACEABLE] read one word from the chip
 297  * @write_buf:          [REPLACEABLE] write data from the buffer to the chip
 298  * @read_buf:           [REPLACEABLE] read data from the chip into the buffer
 299  * @verify_buf:         [REPLACEABLE] verify buffer contents against the chip data
 300  * @select_chip:        [REPLACEABLE] select chip nr
 301  * @block_bad:          [REPLACEABLE] check, if the block is bad
 302  * @block_markbad:      [REPLACEABLE] mark the block bad
 303  * @cmd_ctrl:           [BOARDSPECIFIC] hardwarespecific funtion for controlling
 304  *                      ALE/CLE/nCE. Also used to write command and address
 305  * @dev_ready:          [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
 306  *                      If set to NULL no access to ready/busy is available and the ready/busy information
 307  *                      is read from the chip status register
 308  * @cmdfunc:            [REPLACEABLE] hardwarespecific function for writing commands to the chip
 309  * @waitfunc:           [REPLACEABLE] hardwarespecific function for wait on ready
 310  * @ecc:                [BOARDSPECIFIC] ecc control ctructure
 311  * @buffers:            buffer structure for read/write
 312  * @hwcontrol:          platform-specific hardware control structure
 313  * @ops:                oob operation operands
 314  * @erase_cmd:          [INTERN] erase command write function, selectable due to AND support
 315  * @scan_bbt:           [REPLACEABLE] function to scan bad block table
 316  * @chip_delay:         [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
 317  * @wq:                 [INTERN] wait queue to sleep on if a NAND operation is in progress
 318  * @state:              [INTERN] the current state of the NAND device
 319  * @oob_poi:            poison value buffer
 320  * @page_shift:         [INTERN] number of address bits in a page (column address bits)
 321  * @phys_erase_shift:   [INTERN] number of address bits in a physical eraseblock
 322  * @bbt_erase_shift:    [INTERN] number of address bits in a bbt entry
 323  * @chip_shift:         [INTERN] number of address bits in one chip
 324  * @datbuf:             [INTERN] internal buffer for one page + oob
 325  * @oobbuf:             [INTERN] oob buffer for one eraseblock
 326  * @oobdirty:           [INTERN] indicates that oob_buf must be reinitialized
 327  * @data_poi:           [INTERN] pointer to a data buffer
 328  * @options:            [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
 329  *                      special functionality. See the defines for further explanation
 330  * @badblockpos:        [INTERN] position of the bad block marker in the oob area
 331  * @numchips:           [INTERN] number of physical chips
 332  * @chipsize:           [INTERN] the size of one chip for multichip arrays
 333  * @pagemask:           [INTERN] page number mask = number of (pages / chip) - 1
 334  * @pagebuf:            [INTERN] holds the pagenumber which is currently in data_buf
 335  * @ecclayout:          [REPLACEABLE] the default ecc placement scheme
 336  * @bbt:                [INTERN] bad block table pointer
 337  * @bbt_td:             [REPLACEABLE] bad block table descriptor for flash lookup
 338  * @bbt_md:             [REPLACEABLE] bad block table mirror descriptor
 339  * @badblock_pattern:   [REPLACEABLE] bad block scan pattern used for initial bad block scan
 340  * @controller:         [REPLACEABLE] a pointer to a hardware controller structure
 341  *                      which is shared among multiple independend devices
 342  * @priv:               [OPTIONAL] pointer to private chip date
 343  * @errstat:            [OPTIONAL] hardware specific function to perform additional error status checks
 344  *                      (determine if errors are correctable)
 345  */
 346
 347 struct nand_chip {
 348         void  __iomem   *IO_ADDR_R;
 349         void  __iomem   *IO_ADDR_W;
 350
 351         uint8_t         (*read_byte)(struct mtd_info *mtd);
 352         u16             (*read_word)(struct mtd_info *mtd);
 353         void            (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 354         void            (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
 355         int             (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 356         void            (*select_chip)(struct mtd_info *mtd, int chip);
 357         int             (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
 358         int             (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
 359         void            (*cmd_ctrl)(struct mtd_info *mtd, int dat,
 360                                     unsigned int ctrl);
 361         int             (*dev_ready)(struct mtd_info *mtd);
 362         void            (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
 363         int             (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
 364         void            (*erase_cmd)(struct mtd_info *mtd, int page);
 365         int             (*scan_bbt)(struct mtd_info *mtd);
 366         int             (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
 367
 368         int             chip_delay;
 369         unsigned int    options;
 370
 371         int             page_shift;
 372         int             phys_erase_shift;
 373         int             bbt_erase_shift;
 374         int             chip_shift;
 375         int             numchips;
 376         unsigned long   chipsize;
 377         int             pagemask;
 378         int             pagebuf;
 379         int             badblockpos;
 380
 381         nand_state_t    state;
 382
 383         uint8_t         *oob_poi;
 384         struct nand_hw_control  *controller;
 385         struct nand_ecclayout   *ecclayout;
 386
 387         struct nand_ecc_ctrl ecc;
 388         struct nand_buffers buffers;
 389         struct nand_hw_control hwcontrol;
 390
 391         struct mtd_oob_ops ops;
 392
 393         uint8_t         *bbt;
 394         struct nand_bbt_descr   *bbt_td;
 395         struct nand_bbt_descr   *bbt_md;
 396
 397         struct nand_bbt_descr   *badblock_pattern;
 398
 399         void            *priv;
 400 };
 401
 402 /*
 403  * NAND Flash Manufacturer ID Codes
 404  */
 405 #define NAND_MFR_TOSHIBA        0x98
 406 #define NAND_MFR_SAMSUNG        0xec
 407 #define NAND_MFR_FUJITSU        0x04
 408 #define NAND_MFR_NATIONAL       0x8f
 409 #define NAND_MFR_RENESAS        0x07
 410 #define NAND_MFR_STMICRO        0x20
 411 #define NAND_MFR_HYNIX          0xad
 412
 413 /**
 414  * struct nand_flash_dev - NAND Flash Device ID Structure
 415  * @name:       Identify the device type
 416  * @id:         device ID code
 417  * @pagesize:   Pagesize in bytes. Either 256 or 512 or 0
 418  *              If the pagesize is 0, then the real pagesize
 419  *              and the eraseize are determined from the
 420  *              extended id bytes in the chip
 421  * @erasesize:  Size of an erase block in the flash device.
 422  * @chipsize:   Total chipsize in Mega Bytes
 423  * @options:    Bitfield to store chip relevant options
 424  */
 425 struct nand_flash_dev {
 426         char *name;
 427         int id;
 428         unsigned long pagesize;
 429         unsigned long chipsize;
 430         unsigned long erasesize;
 431         unsigned long options;
 432 };
 433
 434 /**
 435  * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
 436  * @name:       Manufacturer name
 437  * @id:         manufacturer ID code of device.
 438 */
 439 struct nand_manufacturers {
 440         int id;
 441         char * name;
 442 };
 443
 444 extern struct nand_flash_dev nand_flash_ids[];
 445 extern struct nand_manufacturers nand_manuf_ids[];
 446
 447 /**
 448  * struct nand_bbt_descr - bad block table descriptor
 449  * @options:    options for this descriptor
 450  * @pages:      the page(s) where we find the bbt, used with option BBT_ABSPAGE
 451  *              when bbt is searched, then we store the found bbts pages here.
 452  *              Its an array and supports up to 8 chips now
 453  * @offs:       offset of the pattern in the oob area of the page
 454  * @veroffs:    offset of the bbt version counter in the oob are of the page
 455  * @version:    version read from the bbt page during scan
 456  * @len:        length of the pattern, if 0 no pattern check is performed
 457  * @maxblocks:  maximum number of blocks to search for a bbt. This number of
 458  *              blocks is reserved at the end of the device where the tables are
 459  *              written.
 460  * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
 461  *              bad) block in the stored bbt
 462  * @pattern:    pattern to identify bad block table or factory marked good /
 463  *              bad blocks, can be NULL, if len = 0
 464  *
 465  * Descriptor for the bad block table marker and the descriptor for the
 466  * pattern which identifies good and bad blocks. The assumption is made
 467  * that the pattern and the version count are always located in the oob area
 468  * of the first block.
 469  */
 470 struct nand_bbt_descr {
 471         int     options;
 472         int     pages[NAND_MAX_CHIPS];
 473         int     offs;
 474         int     veroffs;
 475         uint8_t version[NAND_MAX_CHIPS];
 476         int     len;
 477         int     maxblocks;
 478         int     reserved_block_code;
 479         uint8_t *pattern;
 480 };
 481
 482 /* Options for the bad block table descriptors */
 483
 484 /* The number of bits used per block in the bbt on the device */
 485 #define NAND_BBT_NRBITS_MSK     0x0000000F
 486 #define NAND_BBT_1BIT           0x00000001
 487 #define NAND_BBT_2BIT           0x00000002
 488 #define NAND_BBT_4BIT           0x00000004
 489 #define NAND_BBT_8BIT           0x00000008
 490 /* The bad block table is in the last good block of the device */
 491 #define NAND_BBT_LASTBLOCK      0x00000010
 492 /* The bbt is at the given page, else we must scan for the bbt */
 493 #define NAND_BBT_ABSPAGE        0x00000020
 494 /* The bbt is at the given page, else we must scan for the bbt */
 495 #define NAND_BBT_SEARCH         0x00000040
 496 /* bbt is stored per chip on multichip devices */
 497 #define NAND_BBT_PERCHIP        0x00000080
 498 /* bbt has a version counter at offset veroffs */
 499 #define NAND_BBT_VERSION        0x00000100
 500 /* Create a bbt if none axists */
 501 #define NAND_BBT_CREATE         0x00000200
 502 /* Search good / bad pattern through all pages of a block */
 503 #define NAND_BBT_SCANALLPAGES   0x00000400
 504 /* Scan block empty during good / bad block scan */
 505 #define NAND_BBT_SCANEMPTY      0x00000800
 506 /* Write bbt if neccecary */
 507 #define NAND_BBT_WRITE          0x00001000
 508 /* Read and write back block contents when writing bbt */
 509 #define NAND_BBT_SAVECONTENT    0x00002000
 510 /* Search good / bad pattern on the first and the second page */
 511 #define NAND_BBT_SCAN2NDPAGE    0x00004000
 512
 513 /* The maximum number of blocks to scan for a bbt */
 514 #define NAND_BBT_SCAN_MAXBLOCKS 4
 515
 516 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
 517 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
 518 extern int nand_default_bbt(struct mtd_info *mtd);
 519 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
 520 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 521                            int allowbbt);
 522 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
 523                         size_t * retlen, uint8_t * buf);
 524
 525 /*
 526 * Constants for oob configuration
 527 */
 528 #define NAND_SMALL_BADBLOCK_POS         5
 529 #define NAND_LARGE_BADBLOCK_POS         0
 530
 531 /**
 532  * struct platform_nand_chip - chip level device structure
 533  * @nr_chips:           max. number of chips to scan for
 534  * @chip_offset:        chip number offset
 535  * @nr_partitions:      number of partitions pointed to by partitions (or zero)
 536  * @partitions:         mtd partition list
 537  * @chip_delay:         R/B delay value in us
 538  * @options:            Option flags, e.g. 16bit buswidth
 539  * @ecclayout:          ecc layout info structure
 540  * @priv:               hardware controller specific settings
 541  */
 542 struct platform_nand_chip {
 543         int                     nr_chips;
 544         int                     chip_offset;
 545         int                     nr_partitions;
 546         struct mtd_partition    *partitions;
 547         struct nand_ecclayout   *ecclayout;
 548         int                     chip_delay;
 549         unsigned int            options;
 550         void                    *priv;
 551 };
 552
 553 /**
 554  * struct platform_nand_ctrl - controller level device structure
 555  * @hwcontrol:          platform specific hardware control structure
 556  * @dev_ready:          platform specific function to read ready/busy pin
 557  * @select_chip:        platform specific chip select function
 558  * @priv:               private data to transport driver specific settings
 559  *
 560  * All fields are optional and depend on the hardware driver requirements
 561  */
 562 struct platform_nand_ctrl {
 563         void            (*hwcontrol)(struct mtd_info *mtd, int cmd);
 564         int             (*dev_ready)(struct mtd_info *mtd);
 565         void            (*select_chip)(struct mtd_info *mtd, int chip);
 566         void            *priv;
 567 };
 568
 569 /* Some helpers to access the data structures */
 570 static inline
 571 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
 572 {
 573         struct nand_chip *chip = mtd->priv;
 574
 575         return chip->priv;
 576 }
 577
 578 #endif /* __LINUX_MTD_NAND_H */