1 #include <linux/init.h>
2 #include <linux/string.h>
3 #include <linux/delay.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <asm/semaphore.h>
8 #include <asm/processor.h>
12 #include <asm/mmu_context.h>
13 #ifdef CONFIG_X86_LOCAL_APIC
14 #include <asm/mpspec.h>
16 #include <mach_apic.h>
21 DEFINE_PER_CPU(struct desc_struct
, cpu_gdt_table
[GDT_ENTRIES
]);
22 EXPORT_PER_CPU_SYMBOL(cpu_gdt_table
);
24 DEFINE_PER_CPU(unsigned char, cpu_16bit_stack
[CPU_16BIT_STACK_SIZE
]);
25 EXPORT_PER_CPU_SYMBOL(cpu_16bit_stack
);
27 static int cachesize_override __devinitdata
= -1;
28 static int disable_x86_fxsr __devinitdata
= 0;
29 static int disable_x86_serial_nr __devinitdata
= 1;
31 struct cpu_dev
* cpu_devs
[X86_VENDOR_NUM
] = {};
33 extern int disable_pse
;
35 static void default_init(struct cpuinfo_x86
* c
)
37 /* Not much we can do here... */
38 /* Check if at least it has cpuid */
39 if (c
->cpuid_level
== -1) {
40 /* No cpuid. It must be an ancient CPU */
42 strcpy(c
->x86_model_id
, "486");
44 strcpy(c
->x86_model_id
, "386");
48 static struct cpu_dev default_cpu
= {
49 .c_init
= default_init
,
51 static struct cpu_dev
* this_cpu
= &default_cpu
;
53 static int __init
cachesize_setup(char *str
)
55 get_option (&str
, &cachesize_override
);
58 __setup("cachesize=", cachesize_setup
);
60 int __devinit
get_model_name(struct cpuinfo_x86
*c
)
65 if (cpuid_eax(0x80000000) < 0x80000004)
68 v
= (unsigned int *) c
->x86_model_id
;
69 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
70 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
71 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
72 c
->x86_model_id
[48] = 0;
74 /* Intel chips right-justify this string for some dumb reason;
75 undo that brain damage */
76 p
= q
= &c
->x86_model_id
[0];
82 while ( q
<= &c
->x86_model_id
[48] )
83 *q
++ = '\0'; /* Zero-pad the rest */
90 void __devinit
display_cacheinfo(struct cpuinfo_x86
*c
)
92 unsigned int n
, dummy
, ecx
, edx
, l2size
;
94 n
= cpuid_eax(0x80000000);
96 if (n
>= 0x80000005) {
97 cpuid(0x80000005, &dummy
, &dummy
, &ecx
, &edx
);
98 printk(KERN_INFO
"CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
99 edx
>>24, edx
&0xFF, ecx
>>24, ecx
&0xFF);
100 c
->x86_cache_size
=(ecx
>>24)+(edx
>>24);
103 if (n
< 0x80000006) /* Some chips just has a large L1. */
106 ecx
= cpuid_ecx(0x80000006);
109 /* do processor-specific cache resizing */
110 if (this_cpu
->c_size_cache
)
111 l2size
= this_cpu
->c_size_cache(c
,l2size
);
113 /* Allow user to override all this if necessary. */
114 if (cachesize_override
!= -1)
115 l2size
= cachesize_override
;
118 return; /* Again, no L2 cache is possible */
120 c
->x86_cache_size
= l2size
;
122 printk(KERN_INFO
"CPU: L2 Cache: %dK (%d bytes/line)\n",
126 /* Naming convention should be: <Name> [(<Codename>)] */
127 /* This table only is used unless init_<vendor>() below doesn't set it; */
128 /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */
130 /* Look up CPU names by table lookup. */
131 static char __devinit
*table_lookup_model(struct cpuinfo_x86
*c
)
133 struct cpu_model_info
*info
;
135 if ( c
->x86_model
>= 16 )
136 return NULL
; /* Range check */
141 info
= this_cpu
->c_models
;
143 while (info
&& info
->family
) {
144 if (info
->family
== c
->x86
)
145 return info
->model_names
[c
->x86_model
];
148 return NULL
; /* Not found */
152 static void __devinit
get_cpu_vendor(struct cpuinfo_x86
*c
, int early
)
154 char *v
= c
->x86_vendor_id
;
157 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
159 if (!strcmp(v
,cpu_devs
[i
]->c_ident
[0]) ||
160 (cpu_devs
[i
]->c_ident
[1] &&
161 !strcmp(v
,cpu_devs
[i
]->c_ident
[1]))) {
164 this_cpu
= cpu_devs
[i
];
172 static int __init
x86_fxsr_setup(char * s
)
174 disable_x86_fxsr
= 1;
177 __setup("nofxsr", x86_fxsr_setup
);
180 /* Standard macro to see if a specific flag is changeable */
181 static inline int flag_is_changeable_p(u32 flag
)
195 : "=&r" (f1
), "=&r" (f2
)
198 return ((f1
^f2
) & flag
) != 0;
202 /* Probe for the CPUID instruction */
203 static int __devinit
have_cpuid_p(void)
205 return flag_is_changeable_p(X86_EFLAGS_ID
);
208 /* Do minimum CPU detection early.
209 Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment.
210 The others are not touched to avoid unwanted side effects. */
211 static void __init
early_cpu_detect(void)
213 struct cpuinfo_x86
*c
= &boot_cpu_data
;
215 c
->x86_cache_alignment
= 32;
220 /* Get vendor name */
221 cpuid(0x00000000, &c
->cpuid_level
,
222 (int *)&c
->x86_vendor_id
[0],
223 (int *)&c
->x86_vendor_id
[8],
224 (int *)&c
->x86_vendor_id
[4]);
226 get_cpu_vendor(c
, 1);
229 if (c
->cpuid_level
>= 0x00000001) {
230 u32 junk
, tfms
, cap0
, misc
;
231 cpuid(0x00000001, &tfms
, &misc
, &junk
, &cap0
);
232 c
->x86
= (tfms
>> 8) & 15;
233 c
->x86_model
= (tfms
>> 4) & 15;
235 c
->x86
+= (tfms
>> 20) & 0xff;
236 c
->x86_model
+= ((tfms
>> 16) & 0xF) << 4;
238 c
->x86_mask
= tfms
& 15;
240 c
->x86_cache_alignment
= ((misc
>> 8) & 0xff) * 8;
243 early_intel_workaround(c
);
246 phys_proc_id
[smp_processor_id()] = (cpuid_ebx(1) >> 24) & 0xff;
250 void __devinit
generic_identify(struct cpuinfo_x86
* c
)
255 if (have_cpuid_p()) {
256 /* Get vendor name */
257 cpuid(0x00000000, &c
->cpuid_level
,
258 (int *)&c
->x86_vendor_id
[0],
259 (int *)&c
->x86_vendor_id
[8],
260 (int *)&c
->x86_vendor_id
[4]);
262 get_cpu_vendor(c
, 0);
263 /* Initialize the standard set of capabilities */
264 /* Note that the vendor-specific code below might override */
266 /* Intel-defined flags: level 0x00000001 */
267 if ( c
->cpuid_level
>= 0x00000001 ) {
268 u32 capability
, excap
;
269 cpuid(0x00000001, &tfms
, &junk
, &excap
, &capability
);
270 c
->x86_capability
[0] = capability
;
271 c
->x86_capability
[4] = excap
;
272 c
->x86
= (tfms
>> 8) & 15;
273 c
->x86_model
= (tfms
>> 4) & 15;
275 c
->x86
+= (tfms
>> 20) & 0xff;
276 c
->x86_model
+= ((tfms
>> 16) & 0xF) << 4;
278 c
->x86_mask
= tfms
& 15;
280 /* Have CPUID level 0 only - unheard of */
284 /* AMD-defined flags: level 0x80000001 */
285 xlvl
= cpuid_eax(0x80000000);
286 if ( (xlvl
& 0xffff0000) == 0x80000000 ) {
287 if ( xlvl
>= 0x80000001 ) {
288 c
->x86_capability
[1] = cpuid_edx(0x80000001);
289 c
->x86_capability
[6] = cpuid_ecx(0x80000001);
291 if ( xlvl
>= 0x80000004 )
292 get_model_name(c
); /* Default name */
297 static void __devinit
squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
299 if (cpu_has(c
, X86_FEATURE_PN
) && disable_x86_serial_nr
) {
300 /* Disable processor serial number */
302 rdmsr(MSR_IA32_BBL_CR_CTL
,lo
,hi
);
304 wrmsr(MSR_IA32_BBL_CR_CTL
,lo
,hi
);
305 printk(KERN_NOTICE
"CPU serial number disabled.\n");
306 clear_bit(X86_FEATURE_PN
, c
->x86_capability
);
308 /* Disabling the serial number may affect the cpuid level */
309 c
->cpuid_level
= cpuid_eax(0);
313 static int __init
x86_serial_nr_setup(char *s
)
315 disable_x86_serial_nr
= 0;
318 __setup("serialnumber", x86_serial_nr_setup
);
323 * This does the hard work of actually picking apart the CPU stuff...
325 void __devinit
identify_cpu(struct cpuinfo_x86
*c
)
329 c
->loops_per_jiffy
= loops_per_jiffy
;
330 c
->x86_cache_size
= -1;
331 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
332 c
->cpuid_level
= -1; /* CPUID not detected */
333 c
->x86_model
= c
->x86_mask
= 0; /* So far unknown... */
334 c
->x86_vendor_id
[0] = '\0'; /* Unset */
335 c
->x86_model_id
[0] = '\0'; /* Unset */
336 c
->x86_num_cores
= 1;
337 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
339 if (!have_cpuid_p()) {
340 /* First of all, decide if this is a 486 or higher */
341 /* It's a 486 if we can modify the AC flag */
342 if ( flag_is_changeable_p(X86_EFLAGS_AC
) )
350 printk(KERN_DEBUG
"CPU: After generic identify, caps:");
351 for (i
= 0; i
< NCAPINTS
; i
++)
352 printk(" %08lx", c
->x86_capability
[i
]);
355 if (this_cpu
->c_identify
) {
356 this_cpu
->c_identify(c
);
358 printk(KERN_DEBUG
"CPU: After vendor identify, caps:");
359 for (i
= 0; i
< NCAPINTS
; i
++)
360 printk(" %08lx", c
->x86_capability
[i
]);
365 * Vendor-specific initialization. In this section we
366 * canonicalize the feature flags, meaning if there are
367 * features a certain CPU supports which CPUID doesn't
368 * tell us, CPUID claiming incorrect flags, or other bugs,
369 * we handle them here.
371 * At the end of this section, c->x86_capability better
372 * indicate the features this CPU genuinely supports!
374 if (this_cpu
->c_init
)
377 /* Disable the PN if appropriate */
378 squash_the_stupid_serial_number(c
);
381 * The vendor-specific functions might have changed features. Now
382 * we do "generic changes."
387 clear_bit(X86_FEATURE_TSC
, c
->x86_capability
);
390 if (disable_x86_fxsr
) {
391 clear_bit(X86_FEATURE_FXSR
, c
->x86_capability
);
392 clear_bit(X86_FEATURE_XMM
, c
->x86_capability
);
396 clear_bit(X86_FEATURE_PSE
, c
->x86_capability
);
398 /* If the model name is still unset, do table lookup. */
399 if ( !c
->x86_model_id
[0] ) {
401 p
= table_lookup_model(c
);
403 strcpy(c
->x86_model_id
, p
);
406 sprintf(c
->x86_model_id
, "%02x/%02x",
407 c
->x86_vendor
, c
->x86_model
);
410 /* Now the feature flags better reflect actual CPU features! */
412 printk(KERN_DEBUG
"CPU: After all inits, caps:");
413 for (i
= 0; i
< NCAPINTS
; i
++)
414 printk(" %08lx", c
->x86_capability
[i
]);
418 * On SMP, boot_cpu_data holds the common feature set between
419 * all CPUs; so make sure that we indicate which features are
420 * common between the CPUs. The first time this routine gets
421 * executed, c == &boot_cpu_data.
423 if ( c
!= &boot_cpu_data
) {
424 /* AND the already accumulated flags with these */
425 for ( i
= 0 ; i
< NCAPINTS
; i
++ )
426 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
429 /* Init Machine Check Exception if available. */
432 if (c
== &boot_cpu_data
)
436 if (c
== &boot_cpu_data
)
443 void __devinit
detect_ht(struct cpuinfo_x86
*c
)
445 u32 eax
, ebx
, ecx
, edx
;
447 int cpu
= smp_processor_id();
449 if (!cpu_has(c
, X86_FEATURE_HT
) || cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
452 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
453 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
455 if (smp_num_siblings
== 1) {
456 printk(KERN_INFO
"CPU: Hyper-Threading is disabled\n");
457 } else if (smp_num_siblings
> 1 ) {
460 if (smp_num_siblings
> NR_CPUS
) {
461 printk(KERN_WARNING
"CPU: Unsupported number of the siblings %d", smp_num_siblings
);
462 smp_num_siblings
= 1;
465 tmp
= smp_num_siblings
;
466 while ((tmp
& 0x80000000 ) == 0) {
470 if (smp_num_siblings
& (smp_num_siblings
- 1))
472 phys_proc_id
[cpu
] = phys_pkg_id((ebx
>> 24) & 0xFF, index_msb
);
474 printk(KERN_INFO
"CPU: Physical Processor ID: %d\n",
477 smp_num_siblings
= smp_num_siblings
/ c
->x86_num_cores
;
479 tmp
= smp_num_siblings
;
481 while ((tmp
& 0x80000000) == 0) {
486 if (smp_num_siblings
& (smp_num_siblings
- 1))
489 cpu_core_id
[cpu
] = phys_pkg_id((ebx
>> 24) & 0xFF, index_msb
);
491 if (c
->x86_num_cores
> 1)
492 printk(KERN_INFO
"CPU: Processor Core ID: %d\n",
498 void __devinit
print_cpu_info(struct cpuinfo_x86
*c
)
502 if (c
->x86_vendor
< X86_VENDOR_NUM
)
503 vendor
= this_cpu
->c_vendor
;
504 else if (c
->cpuid_level
>= 0)
505 vendor
= c
->x86_vendor_id
;
507 if (vendor
&& strncmp(c
->x86_model_id
, vendor
, strlen(vendor
)))
508 printk("%s ", vendor
);
510 if (!c
->x86_model_id
[0])
511 printk("%d86", c
->x86
);
513 printk("%s", c
->x86_model_id
);
515 if (c
->x86_mask
|| c
->cpuid_level
>= 0)
516 printk(" stepping %02x\n", c
->x86_mask
);
521 cpumask_t cpu_initialized __devinitdata
= CPU_MASK_NONE
;
524 * We're emulating future behavior.
525 * In the future, the cpu-specific init functions will be called implicitly
526 * via the magic of initcalls.
527 * They will insert themselves into the cpu_devs structure.
528 * Then, when cpu_init() is called, we can just iterate over that array.
531 extern int intel_cpu_init(void);
532 extern int cyrix_init_cpu(void);
533 extern int nsc_init_cpu(void);
534 extern int amd_init_cpu(void);
535 extern int centaur_init_cpu(void);
536 extern int transmeta_init_cpu(void);
537 extern int rise_init_cpu(void);
538 extern int nexgen_init_cpu(void);
539 extern int umc_init_cpu(void);
541 void __init
early_cpu_init(void)
548 transmeta_init_cpu();
554 #ifdef CONFIG_DEBUG_PAGEALLOC
555 /* pse is not compatible with on-the-fly unmapping,
556 * disable it even if the cpus claim to support it.
558 clear_bit(X86_FEATURE_PSE
, boot_cpu_data
.x86_capability
);
563 * cpu_init() initializes state that is per-CPU. Some data is already
564 * initialized (naturally) in the bootstrap process, such as the GDT
565 * and IDT. We reload them nevertheless, this function acts as a
566 * 'CPU state barrier', nothing should get across.
568 void __devinit
cpu_init(void)
570 int cpu
= smp_processor_id();
571 struct tss_struct
* t
= &per_cpu(init_tss
, cpu
);
572 struct thread_struct
*thread
= ¤t
->thread
;
573 struct desc_struct
*gdt
= get_cpu_gdt_table(cpu
);
574 __u32 stk16_off
= (__u32
)&per_cpu(cpu_16bit_stack
, cpu
);
576 if (cpu_test_and_set(cpu
, cpu_initialized
)) {
577 printk(KERN_WARNING
"CPU#%d already initialized!\n", cpu
);
578 for (;;) local_irq_enable();
580 printk(KERN_INFO
"Initializing CPU#%d\n", cpu
);
582 if (cpu_has_vme
|| cpu_has_tsc
|| cpu_has_de
)
583 clear_in_cr4(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
584 if (tsc_disable
&& cpu_has_tsc
) {
585 printk(KERN_NOTICE
"Disabling TSC...\n");
586 /**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/
587 clear_bit(X86_FEATURE_TSC
, boot_cpu_data
.x86_capability
);
588 set_in_cr4(X86_CR4_TSD
);
592 * Initialize the per-CPU GDT with the boot GDT,
593 * and set up the GDT descriptor:
595 memcpy(gdt
, cpu_gdt_table
, GDT_SIZE
);
597 /* Set up GDT entry for 16bit stack */
598 *(__u64
*)(&gdt
[GDT_ENTRY_ESPFIX_SS
]) |=
599 ((((__u64
)stk16_off
) << 16) & 0x000000ffffff0000ULL
) |
600 ((((__u64
)stk16_off
) << 32) & 0xff00000000000000ULL
) |
601 (CPU_16BIT_STACK_SIZE
- 1);
603 cpu_gdt_descr
[cpu
].size
= GDT_SIZE
- 1;
604 cpu_gdt_descr
[cpu
].address
= (unsigned long)gdt
;
606 load_gdt(&cpu_gdt_descr
[cpu
]);
607 load_idt(&idt_descr
);
612 __asm__("pushfl ; andl $0xffffbfff,(%esp) ; popfl");
615 * Set up and load the per-CPU TSS and LDT
617 atomic_inc(&init_mm
.mm_count
);
618 current
->active_mm
= &init_mm
;
621 enter_lazy_tlb(&init_mm
, current
);
623 load_esp0(t
, thread
);
626 load_LDT(&init_mm
.context
);
628 /* Set up doublefault TSS pointer in the GDT */
629 __set_tss_desc(cpu
, GDT_ENTRY_DOUBLEFAULT_TSS
, &doublefault_tss
);
631 /* Clear %fs and %gs. */
632 asm volatile ("xorl %eax, %eax; movl %eax, %fs; movl %eax, %gs");
634 /* Clear all 6 debug registers: */
643 * Force FPU initialization:
645 current_thread_info()->status
= 0;
647 mxcsr_feature_mask_init();
650 #ifdef CONFIG_HOTPLUG_CPU
651 void __devinit
cpu_uninit(void)
653 int cpu
= raw_smp_processor_id();
654 cpu_clear(cpu
, cpu_initialized
);
657 per_cpu(cpu_tlbstate
, cpu
).state
= 0;
658 per_cpu(cpu_tlbstate
, cpu
).active_mm
= &init_mm
;