arch/arm/plat-s3c/pwm-clock.c

   1 /* linux/arch/arm/plat-s3c24xx/pwm-clock.c
   2  *
   3  * Copyright (c) 2007 Simtec Electronics
   4  * Copyright (c) 2007, 2008 Ben Dooks
   5  *      Ben Dooks <ben-linux@fluff.org>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License.
  10 */
  11
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/list.h>
  16 #include <linux/errno.h>
  17 #include <linux/clk.h>
  18 #include <linux/err.h>
  19 #include <linux/io.h>
  20
  21 #include <mach/hardware.h>
  22 #include <mach/map.h>
  23 #include <asm/irq.h>
  24
  25 #include <plat/clock.h>
  26 #include <plat/cpu.h>
  27
  28 #include <plat/regs-timer.h>
  29
  30 /* Each of the timers 0 through 5 go through the following
  31  * clock tree, with the inputs depending on the timers.
  32  *
  33  * pclk ---- [ prescaler 0 ] -+---> timer 0
  34  *                            +---> timer 1
  35  *
  36  * pclk ---- [ prescaler 1 ] -+---> timer 2
  37  *                            +---> timer 3
  38  *                            \---> timer 4
  39  *
  40  * Which are fed into the timers as so:
  41  *
  42  * prescaled 0 ---- [ div 2,4,8,16 ] ---\
  43  *                                     [mux] -> timer 0
  44  * tclk 0 ------------------------------/
  45  *
  46  * prescaled 0 ---- [ div 2,4,8,16 ] ---\
  47  *                                     [mux] -> timer 1
  48  * tclk 0 ------------------------------/
  49  *
  50  *
  51  * prescaled 1 ---- [ div 2,4,8,16 ] ---\
  52  *                                     [mux] -> timer 2
  53  * tclk 1 ------------------------------/
  54  *
  55  * prescaled 1 ---- [ div 2,4,8,16 ] ---\
  56  *                                     [mux] -> timer 3
  57  * tclk 1 ------------------------------/
  58  *
  59  * prescaled 1 ---- [ div 2,4,8, 16 ] --\
  60  *                                     [mux] -> timer 4
  61  * tclk 1 ------------------------------/
  62  *
  63  * Since the mux and the divider are tied together in the
  64  * same register space, it is impossible to set the parent
  65  * and the rate at the same time. To avoid this, we add an
  66  * intermediate 'prescaled-and-divided' clock to select
  67  * as the parent for the timer input clock called tdiv.
  68  *
  69  * prescaled clk --> pwm-tdiv ---\
  70  *                             [ mux ] --> timer X
  71  * tclk -------------------------/
  72 */
  73
  74 static unsigned long clk_pwm_scaler_getrate(struct clk *clk)
  75 {
  76         unsigned long tcfg0 = __raw_readl(S3C2410_TCFG0);
  77
  78         if (clk->id == 1) {
  79                 tcfg0 &= S3C2410_TCFG_PRESCALER1_MASK;
  80                 tcfg0 >>= S3C2410_TCFG_PRESCALER1_SHIFT;
  81         } else {
  82                 tcfg0 &= S3C2410_TCFG_PRESCALER0_MASK;
  83         }
  84
  85         return clk_get_rate(clk->parent) / (tcfg0 + 1);
  86 }
  87
  88 /* TODO - add set rate calls. */
  89
  90 static struct clk clk_timer_scaler[] = {
  91         [0]     = {
  92                 .name           = "pwm-scaler0",
  93                 .id             = -1,
  94                 .get_rate       = clk_pwm_scaler_getrate,
  95         },
  96         [1]     = {
  97                 .name           = "pwm-scaler1",
  98                 .id             = -1,
  99                 .get_rate       = clk_pwm_scaler_getrate,
 100         },
 101 };
 102
 103 static struct clk clk_timer_tclk[] = {
 104         [0]     = {
 105                 .name           = "pwm-tclk0",
 106                 .id             = -1,
 107         },
 108         [1]     = {
 109                 .name           = "pwm-tclk1",
 110                 .id             = -1,
 111         },
 112 };
 113
 114 struct pwm_tdiv_clk {
 115         struct clk      clk;
 116         unsigned int    divisor;
 117 };
 118
 119 static inline struct pwm_tdiv_clk *to_tdiv(struct clk *clk)
 120 {
 121         return container_of(clk, struct pwm_tdiv_clk, clk);
 122 }
 123
 124 static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
 125 {
 126         return 1 << (1 + tcfg1);
 127 }
 128
 129 static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk)
 130 {
 131         unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
 132         unsigned int divisor;
 133
 134         tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
 135         tcfg1 &= S3C2410_TCFG1_MUX_MASK;
 136
 137         if (tcfg1 == S3C2410_TCFG1_MUX_TCLK)
 138                 divisor = to_tdiv(clk)->divisor;
 139         else
 140                 divisor = tcfg_to_divisor(tcfg1);
 141
 142         return clk_get_rate(clk->parent) / divisor;
 143 }
 144
 145 static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk,
 146                                              unsigned long rate)
 147 {
 148         unsigned long parent_rate;
 149         unsigned long divisor;
 150
 151         parent_rate = clk_get_rate(clk->parent);
 152         divisor = parent_rate / rate;
 153
 154         if (divisor <= 2)
 155                 divisor = 2;
 156         else if (divisor <= 4)
 157                 divisor = 4;
 158         else if (divisor <= 8)
 159                 divisor = 8;
 160         else
 161                 divisor = 16;
 162
 163         return parent_rate / divisor;
 164 }
 165
 166 static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk)
 167 {
 168         unsigned long bits;
 169
 170         switch (divclk->divisor) {
 171         case 2:
 172                 bits = S3C2410_TCFG1_MUX_DIV2;
 173                 break;
 174         case 4:
 175                 bits = S3C2410_TCFG1_MUX_DIV4;
 176                 break;
 177         case 8:
 178                 bits = S3C2410_TCFG1_MUX_DIV8;
 179                 break;
 180         case 16:
 181         default:
 182                 bits = S3C2410_TCFG1_MUX_DIV16;
 183                 break;
 184         }
 185
 186         return bits;
 187 }
 188
 189 static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk)
 190 {
 191         unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
 192         unsigned long bits = clk_pwm_tdiv_bits(divclk);
 193         unsigned long flags;
 194         unsigned long shift =  S3C2410_TCFG1_SHIFT(divclk->clk.id);
 195
 196         local_irq_save(flags);
 197
 198         tcfg1 = __raw_readl(S3C2410_TCFG1);
 199         tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
 200         tcfg1 |= bits << shift;
 201         __raw_writel(tcfg1, S3C2410_TCFG1);
 202
 203         local_irq_restore(flags);
 204 }
 205
 206 static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate)
 207 {
 208         struct pwm_tdiv_clk *divclk = to_tdiv(clk);
 209         unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
 210         unsigned long parent_rate = clk_get_rate(clk->parent);
 211         unsigned long divisor;
 212
 213         tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
 214         tcfg1 &= S3C2410_TCFG1_MUX_MASK;
 215
 216         rate = clk_round_rate(clk, rate);
 217         divisor = parent_rate / rate;
 218
 219         if (divisor > 16)
 220                 return -EINVAL;
 221
 222         divclk->divisor = divisor;
 223
 224         /* Update the current MUX settings if we are currently
 225          * selected as the clock source for this clock. */
 226
 227         if (tcfg1 != S3C2410_TCFG1_MUX_TCLK)
 228                 clk_pwm_tdiv_update(divclk);
 229
 230         return 0;
 231 }
 232
 233 static struct pwm_tdiv_clk clk_timer_tdiv[] = {
 234         [0]     = {
 235                 .clk    = {
 236                         .name           = "pwm-tdiv",
 237                         .parent         = &clk_timer_scaler[0],
 238                         .get_rate       = clk_pwm_tdiv_get_rate,
 239                         .set_rate       = clk_pwm_tdiv_set_rate,
 240                         .round_rate     = clk_pwm_tdiv_round_rate,
 241                 },
 242         },
 243         [1]     = {
 244                 .clk    = {
 245                         .name           = "pwm-tdiv",
 246                         .parent         = &clk_timer_scaler[0],
 247                         .get_rate       = clk_pwm_tdiv_get_rate,
 248                         .set_rate       = clk_pwm_tdiv_set_rate,
 249                         .round_rate     = clk_pwm_tdiv_round_rate,
 250                 }
 251         },
 252         [2]     = {
 253                 .clk    = {
 254                         .name           = "pwm-tdiv",
 255                         .parent         = &clk_timer_scaler[1],
 256                         .get_rate       = clk_pwm_tdiv_get_rate,
 257                         .set_rate       = clk_pwm_tdiv_set_rate,
 258                         .round_rate     = clk_pwm_tdiv_round_rate,
 259                 },
 260         },
 261         [3]     = {
 262                 .clk    = {
 263                         .name           = "pwm-tdiv",
 264                         .parent         = &clk_timer_scaler[1],
 265                         .get_rate       = clk_pwm_tdiv_get_rate,
 266                         .set_rate       = clk_pwm_tdiv_set_rate,
 267                         .round_rate     = clk_pwm_tdiv_round_rate,
 268                 },
 269         },
 270         [4]     = {
 271                 .clk    = {
 272                         .name           = "pwm-tdiv",
 273                         .parent         = &clk_timer_scaler[1],
 274                         .get_rate       = clk_pwm_tdiv_get_rate,
 275                         .set_rate       = clk_pwm_tdiv_set_rate,
 276                         .round_rate     = clk_pwm_tdiv_round_rate,
 277                 },
 278         },
 279 };
 280
 281 static int __init clk_pwm_tdiv_register(unsigned int id)
 282 {
 283         struct pwm_tdiv_clk *divclk = &clk_timer_tdiv[id];
 284         unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
 285
 286         tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
 287         tcfg1 &= S3C2410_TCFG1_MUX_MASK;
 288
 289         divclk->clk.id = id;
 290         divclk->divisor = tcfg_to_divisor(tcfg1);
 291
 292         return s3c24xx_register_clock(&divclk->clk);
 293 }
 294
 295 static inline struct clk *s3c24xx_pwmclk_tclk(unsigned int id)
 296 {
 297         return (id >= 2) ? &clk_timer_tclk[1] : &clk_timer_tclk[0];
 298 }
 299
 300 static inline struct clk *s3c24xx_pwmclk_tdiv(unsigned int id)
 301 {
 302         return &clk_timer_tdiv[id].clk;
 303 }
 304
 305 static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent)
 306 {
 307         unsigned int id = clk->id;
 308         unsigned long tcfg1;
 309         unsigned long flags;
 310         unsigned long bits;
 311         unsigned long shift = S3C2410_TCFG1_SHIFT(id);
 312
 313         if (parent == s3c24xx_pwmclk_tclk(id))
 314                 bits = S3C2410_TCFG1_MUX_TCLK << shift;
 315         else if (parent == s3c24xx_pwmclk_tdiv(id))
 316                 bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift;
 317         else
 318                 return -EINVAL;
 319
 320         clk->parent = parent;
 321
 322         local_irq_save(flags);
 323
 324         tcfg1 = __raw_readl(S3C2410_TCFG1);
 325         tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
 326         __raw_writel(tcfg1 | bits, S3C2410_TCFG1);
 327
 328         local_irq_restore(flags);
 329
 330         return 0;
 331 }
 332
 333 static struct clk clk_tin[] = {
 334         [0]     = {
 335                 .name           = "pwm-tin",
 336                 .id             = 0,
 337                 .set_parent     = clk_pwm_tin_set_parent,
 338         },
 339         [1]     = {
 340                 .name           = "pwm-tin",
 341                 .id             = 1,
 342                 .set_parent     = clk_pwm_tin_set_parent,
 343         },
 344         [2]     = {
 345                 .name           = "pwm-tin",
 346                 .id             = 2,
 347                 .set_parent     = clk_pwm_tin_set_parent,
 348         },
 349         [3]     = {
 350                 .name           = "pwm-tin",
 351                 .id             = 3,
 352                 .set_parent     = clk_pwm_tin_set_parent,
 353         },
 354         [4]     = {
 355                 .name           = "pwm-tin",
 356                 .id             = 4,
 357                 .set_parent     = clk_pwm_tin_set_parent,
 358         },
 359 };
 360
 361 static __init int clk_pwm_tin_register(struct clk *pwm)
 362 {
 363         unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
 364         unsigned int id = pwm->id;
 365
 366         struct clk *parent;
 367         int ret;
 368
 369         ret = s3c24xx_register_clock(pwm);
 370         if (ret < 0)
 371                 return ret;
 372
 373         tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
 374         tcfg1 &= S3C2410_TCFG1_MUX_MASK;
 375
 376         if (tcfg1 == S3C2410_TCFG1_MUX_TCLK)
 377                 parent = s3c24xx_pwmclk_tclk(id);
 378         else
 379                 parent = s3c24xx_pwmclk_tdiv(id);
 380
 381         return clk_set_parent(pwm, parent);
 382 }
 383
 384 static __init int s3c24xx_pwmclk_init(void)
 385 {
 386         struct clk *clk_timers;
 387         unsigned int clk;
 388         int ret;
 389
 390         clk_timers = clk_get(NULL, "timers");
 391         if (IS_ERR(clk_timers)) {
 392                 printk(KERN_ERR "%s: no parent clock\n", __func__);
 393                 return -EINVAL;
 394         }
 395
 396         for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++) {
 397                 clk_timer_scaler[clk].parent = clk_timers;
 398                 ret = s3c24xx_register_clock(&clk_timer_scaler[clk]);
 399                 if (ret < 0) {
 400                         printk(KERN_ERR "error adding pwm scaler%d clock\n", clk);
 401                         goto err;
 402                 }
 403         }
 404
 405         for (clk = 0; clk < ARRAY_SIZE(clk_timer_tclk); clk++) {
 406                 ret = s3c24xx_register_clock(&clk_timer_tclk[clk]);
 407                 if (ret < 0) {
 408                         printk(KERN_ERR "error adding pww tclk%d\n", clk);
 409                         goto err;
 410                 }
 411         }
 412
 413         for (clk = 0; clk < ARRAY_SIZE(clk_timer_tdiv); clk++) {
 414                 ret = clk_pwm_tdiv_register(clk);
 415                 if (ret < 0) {
 416                         printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk);
 417                         goto err;
 418                 }
 419         }
 420
 421         for (clk = 0; clk < ARRAY_SIZE(clk_tin); clk++) {
 422                 ret = clk_pwm_tin_register(&clk_tin[clk]);
 423                 if (ret < 0) {
 424                         printk(KERN_ERR "error adding pwm%d tin clock\n", clk);
 425                         goto err;
 426                 }
 427         }
 428
 429         return 0;
 430
 431  err:
 432         return ret;
 433 }
 434
 435 arch_initcall(s3c24xx_pwmclk_init);