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[ARM] S3C: Update serial driver IRQ handling
[linux-2.6/openmoko-kernel.git] / drivers / pci / probe.c
blobaaaf0a1fed223364b82bd4e79d9fd29f2c178788
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h>
13 #include "pci.h"
14
15 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
16 #define CARDBUS_RESERVE_BUSNR 3
17
18 /* Ugh. Need to stop exporting this to modules. */
19 LIST_HEAD(pci_root_buses);
20 EXPORT_SYMBOL(pci_root_buses);
21
22
23 static int find_anything(struct device *dev, void *data)
24 {
25 return 1;
26 }
27
28 /*
29 * Some device drivers need know if pci is initiated.
30 * Basically, we think pci is not initiated when there
31 * is no device to be found on the pci_bus_type.
32 */
33 int no_pci_devices(void)
34 {
35 struct device *dev;
36 int no_devices;
37
38 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
39 no_devices = (dev == NULL);
40 put_device(dev);
41 return no_devices;
42 }
43 EXPORT_SYMBOL(no_pci_devices);
44
45 /*
46 * PCI Bus Class Devices
47 */
48 static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
49 int type,
50 struct device_attribute *attr,
51 char *buf)
52 {
53 int ret;
54 cpumask_t cpumask;
55
56 cpumask = pcibus_to_cpumask(to_pci_bus(dev));
57 ret = type?
58 cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask):
59 cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask);
60 buf[ret++] = '\n';
61 buf[ret] = '\0';
62 return ret;
63 }
64
65 static ssize_t inline pci_bus_show_cpumaskaffinity(struct device *dev,
66 struct device_attribute *attr,
67 char *buf)
68 {
69 return pci_bus_show_cpuaffinity(dev, 0, attr, buf);
70 }
71
72 static ssize_t inline pci_bus_show_cpulistaffinity(struct device *dev,
73 struct device_attribute *attr,
74 char *buf)
75 {
76 return pci_bus_show_cpuaffinity(dev, 1, attr, buf);
77 }
78
79 DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL);
80 DEVICE_ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL);
81
82 /*
83 * PCI Bus Class
84 */
85 static void release_pcibus_dev(struct device *dev)
86 {
87 struct pci_bus *pci_bus = to_pci_bus(dev);
88
89 if (pci_bus->bridge)
90 put_device(pci_bus->bridge);
91 kfree(pci_bus);
92 }
93
94 static struct class pcibus_class = {
95 .name = "pci_bus",
96 .dev_release = &release_pcibus_dev,
97 };
98
99 static int __init pcibus_class_init(void)
100 {
101 return class_register(&pcibus_class);
102 }
103 postcore_initcall(pcibus_class_init);
104
105 /*
106 * Translate the low bits of the PCI base
107 * to the resource type
108 */
109 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
110 {
111 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
112 return IORESOURCE_IO;
113
114 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
115 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
116
117 return IORESOURCE_MEM;
118 }
119
120 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
121 {
122 u64 size = mask & maxbase; /* Find the significant bits */
123 if (!size)
124 return 0;
125
126 /* Get the lowest of them to find the decode size, and
127 from that the extent. */
128 size = (size & ~(size-1)) - 1;
129
130 /* base == maxbase can be valid only if the BAR has
131 already been programmed with all 1s. */
132 if (base == maxbase && ((base | size) & mask) != mask)
133 return 0;
134
135 return size;
136 }
137
138 enum pci_bar_type {
139 pci_bar_unknown, /* Standard PCI BAR probe */
140 pci_bar_io, /* An io port BAR */
141 pci_bar_mem32, /* A 32-bit memory BAR */
142 pci_bar_mem64, /* A 64-bit memory BAR */
143 };
144
145 static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
146 {
147 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
148 res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
149 return pci_bar_io;
150 }
151
152 res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
153
154 if (res->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
155 return pci_bar_mem64;
156 return pci_bar_mem32;
157 }
158
159 /*
160 * If the type is not unknown, we assume that the lowest bit is 'enable'.
161 * Returns 1 if the BAR was 64-bit and 0 if it was 32-bit.
162 */
163 static int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
164 struct resource *res, unsigned int pos)
165 {
166 u32 l, sz, mask;
167
168 mask = type ? ~PCI_ROM_ADDRESS_ENABLE : ~0;
169
170 res->name = pci_name(dev);
171
172 pci_read_config_dword(dev, pos, &l);
173 pci_write_config_dword(dev, pos, mask);
174 pci_read_config_dword(dev, pos, &sz);
175 pci_write_config_dword(dev, pos, l);
176
177 /*
178 * All bits set in sz means the device isn't working properly.
179 * If the BAR isn't implemented, all bits must be 0. If it's a
180 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
181 * 1 must be clear.
182 */
183 if (!sz || sz == 0xffffffff)
184 goto fail;
185
186 /*
187 * I don't know how l can have all bits set. Copied from old code.
188 * Maybe it fixes a bug on some ancient platform.
189 */
190 if (l == 0xffffffff)
191 l = 0;
192
193 if (type == pci_bar_unknown) {
194 type = decode_bar(res, l);
195 res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
196 if (type == pci_bar_io) {
197 l &= PCI_BASE_ADDRESS_IO_MASK;
198 mask = PCI_BASE_ADDRESS_IO_MASK & 0xffff;
199 } else {
200 l &= PCI_BASE_ADDRESS_MEM_MASK;
201 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
202 }
203 } else {
204 res->flags |= (l & IORESOURCE_ROM_ENABLE);
205 l &= PCI_ROM_ADDRESS_MASK;
206 mask = (u32)PCI_ROM_ADDRESS_MASK;
207 }
208
209 if (type == pci_bar_mem64) {
210 u64 l64 = l;
211 u64 sz64 = sz;
212 u64 mask64 = mask | (u64)~0 << 32;
213
214 pci_read_config_dword(dev, pos + 4, &l);
215 pci_write_config_dword(dev, pos + 4, ~0);
216 pci_read_config_dword(dev, pos + 4, &sz);
217 pci_write_config_dword(dev, pos + 4, l);
218
219 l64 |= ((u64)l << 32);
220 sz64 |= ((u64)sz << 32);
221
222 sz64 = pci_size(l64, sz64, mask64);
223
224 if (!sz64)
225 goto fail;
226
227 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
228 dev_err(&dev->dev, "can't handle 64-bit BAR\n");
229 goto fail;
230 } else if ((sizeof(resource_size_t) < 8) && l) {
231 /* Address above 32-bit boundary; disable the BAR */
232 pci_write_config_dword(dev, pos, 0);
233 pci_write_config_dword(dev, pos + 4, 0);
234 res->start = 0;
235 res->end = sz64;
236 } else {
237 res->start = l64;
238 res->end = l64 + sz64;
239 dev_printk(KERN_DEBUG, &dev->dev,
240 "reg %x 64bit mmio: %pR\n", pos, res);
241 }
242 } else {
243 sz = pci_size(l, sz, mask);
244
245 if (!sz)
246 goto fail;
247
248 res->start = l;
249 res->end = l + sz;
250
251 dev_printk(KERN_DEBUG, &dev->dev, "reg %x %s: %pR\n", pos,
252 (res->flags & IORESOURCE_IO) ? "io port" : "32bit mmio",
253 res);
254 }
255
256 out:
257 return (type == pci_bar_mem64) ? 1 : 0;
258 fail:
259 res->flags = 0;
260 goto out;
261 }
262
263 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
264 {
265 unsigned int pos, reg;
266
267 for (pos = 0; pos < howmany; pos++) {
268 struct resource *res = &dev->resource[pos];
269 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
270 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
271 }
272
273 if (rom) {
274 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
275 dev->rom_base_reg = rom;
276 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
277 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
278 IORESOURCE_SIZEALIGN;
279 __pci_read_base(dev, pci_bar_mem32, res, rom);
280 }
281 }
282
283 void __devinit pci_read_bridge_bases(struct pci_bus *child)
284 {
285 struct pci_dev *dev = child->self;
286 u8 io_base_lo, io_limit_lo;
287 u16 mem_base_lo, mem_limit_lo;
288 unsigned long base, limit;
289 struct resource *res;
290 int i;
291
292 if (!dev) /* It's a host bus, nothing to read */
293 return;
294
295 if (dev->transparent) {
296 dev_info(&dev->dev, "transparent bridge\n");
297 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
298 child->resource[i] = child->parent->resource[i - 3];
299 }
300
301 for(i=0; i<3; i++)
302 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
303
304 res = child->resource[0];
305 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
306 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
307 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
308 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
309
310 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
311 u16 io_base_hi, io_limit_hi;
312 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
313 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
314 base |= (io_base_hi << 16);
315 limit |= (io_limit_hi << 16);
316 }
317
318 if (base <= limit) {
319 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
320 if (!res->start)
321 res->start = base;
322 if (!res->end)
323 res->end = limit + 0xfff;
324 dev_printk(KERN_DEBUG, &dev->dev, "bridge io port: %pR\n", res);
325 }
326
327 res = child->resource[1];
328 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
329 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
330 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
331 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
332 if (base <= limit) {
333 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
334 res->start = base;
335 res->end = limit + 0xfffff;
336 dev_printk(KERN_DEBUG, &dev->dev, "bridge 32bit mmio: %pR\n",
337 res);
338 }
339
340 res = child->resource[2];
341 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
342 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
343 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
344 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
345
346 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
347 u32 mem_base_hi, mem_limit_hi;
348 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
349 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
350
351 /*
352 * Some bridges set the base > limit by default, and some
353 * (broken) BIOSes do not initialize them. If we find
354 * this, just assume they are not being used.
355 */
356 if (mem_base_hi <= mem_limit_hi) {
357 #if BITS_PER_LONG == 64
358 base |= ((long) mem_base_hi) << 32;
359 limit |= ((long) mem_limit_hi) << 32;
360 #else
361 if (mem_base_hi || mem_limit_hi) {
362 dev_err(&dev->dev, "can't handle 64-bit "
363 "address space for bridge\n");
364 return;
365 }
366 #endif
367 }
368 }
369 if (base <= limit) {
370 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
371 res->start = base;
372 res->end = limit + 0xfffff;
373 dev_printk(KERN_DEBUG, &dev->dev, "bridge %sbit mmio pref: %pR\n",
374 (res->flags & PCI_PREF_RANGE_TYPE_64) ? "64" : "32",
375 res);
376 }
377 }
378
379 static struct pci_bus * pci_alloc_bus(void)
380 {
381 struct pci_bus *b;
382
383 b = kzalloc(sizeof(*b), GFP_KERNEL);
384 if (b) {
385 INIT_LIST_HEAD(&b->node);
386 INIT_LIST_HEAD(&b->children);
387 INIT_LIST_HEAD(&b->devices);
388 INIT_LIST_HEAD(&b->slots);
389 }
390 return b;
391 }
392
393 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
394 struct pci_dev *bridge, int busnr)
395 {
396 struct pci_bus *child;
397 int i;
398
399 /*
400 * Allocate a new bus, and inherit stuff from the parent..
401 */
402 child = pci_alloc_bus();
403 if (!child)
404 return NULL;
405
406 child->self = bridge;
407 child->parent = parent;
408 child->ops = parent->ops;
409 child->sysdata = parent->sysdata;
410 child->bus_flags = parent->bus_flags;
411 child->bridge = get_device(&bridge->dev);
412
413 /* initialize some portions of the bus device, but don't register it
414 * now as the parent is not properly set up yet. This device will get
415 * registered later in pci_bus_add_devices()
416 */
417 child->dev.class = &pcibus_class;
418 sprintf(child->dev.bus_id, "%04x:%02x", pci_domain_nr(child), busnr);
419
420 /*
421 * Set up the primary, secondary and subordinate
422 * bus numbers.
423 */
424 child->number = child->secondary = busnr;
425 child->primary = parent->secondary;
426 child->subordinate = 0xff;
427
428 /* Set up default resource pointers and names.. */
429 for (i = 0; i < 4; i++) {
430 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
431 child->resource[i]->name = child->name;
432 }
433 bridge->subordinate = child;
434
435 return child;
436 }
437
438 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
439 {
440 struct pci_bus *child;
441
442 child = pci_alloc_child_bus(parent, dev, busnr);
443 if (child) {
444 down_write(&pci_bus_sem);
445 list_add_tail(&child->node, &parent->children);
446 up_write(&pci_bus_sem);
447 }
448 return child;
449 }
450
451 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
452 {
453 struct pci_bus *parent = child->parent;
454
455 /* Attempts to fix that up are really dangerous unless
456 we're going to re-assign all bus numbers. */
457 if (!pcibios_assign_all_busses())
458 return;
459
460 while (parent->parent && parent->subordinate < max) {
461 parent->subordinate = max;
462 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
463 parent = parent->parent;
464 }
465 }
466
467 /*
468 * If it's a bridge, configure it and scan the bus behind it.
469 * For CardBus bridges, we don't scan behind as the devices will
470 * be handled by the bridge driver itself.
471 *
472 * We need to process bridges in two passes -- first we scan those
473 * already configured by the BIOS and after we are done with all of
474 * them, we proceed to assigning numbers to the remaining buses in
475 * order to avoid overlaps between old and new bus numbers.
476 */
477 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
478 {
479 struct pci_bus *child;
480 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
481 u32 buses, i, j = 0;
482 u16 bctl;
483
484 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
485
486 dev_dbg(&dev->dev, "scanning behind bridge, config %06x, pass %d\n",
487 buses & 0xffffff, pass);
488
489 /* Disable MasterAbortMode during probing to avoid reporting
490 of bus errors (in some architectures) */
491 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
492 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
493 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
494
495 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
496 unsigned int cmax, busnr;
497 /*
498 * Bus already configured by firmware, process it in the first
499 * pass and just note the configuration.
500 */
501 if (pass)
502 goto out;
503 busnr = (buses >> 8) & 0xFF;
504
505 /*
506 * If we already got to this bus through a different bridge,
507 * ignore it. This can happen with the i450NX chipset.
508 */
509 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
510 dev_info(&dev->dev, "bus %04x:%02x already known\n",
511 pci_domain_nr(bus), busnr);
512 goto out;
513 }
514
515 child = pci_add_new_bus(bus, dev, busnr);
516 if (!child)
517 goto out;
518 child->primary = buses & 0xFF;
519 child->subordinate = (buses >> 16) & 0xFF;
520 child->bridge_ctl = bctl;
521
522 cmax = pci_scan_child_bus(child);
523 if (cmax > max)
524 max = cmax;
525 if (child->subordinate > max)
526 max = child->subordinate;
527 } else {
528 /*
529 * We need to assign a number to this bus which we always
530 * do in the second pass.
531 */
532 if (!pass) {
533 if (pcibios_assign_all_busses())
534 /* Temporarily disable forwarding of the
535 configuration cycles on all bridges in
536 this bus segment to avoid possible
537 conflicts in the second pass between two
538 bridges programmed with overlapping
539 bus ranges. */
540 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
541 buses & ~0xffffff);
542 goto out;
543 }
544
545 /* Clear errors */
546 pci_write_config_word(dev, PCI_STATUS, 0xffff);
547
548 /* Prevent assigning a bus number that already exists.
549 * This can happen when a bridge is hot-plugged */
550 if (pci_find_bus(pci_domain_nr(bus), max+1))
551 goto out;
552 child = pci_add_new_bus(bus, dev, ++max);
553 buses = (buses & 0xff000000)
554 | ((unsigned int)(child->primary) << 0)
555 | ((unsigned int)(child->secondary) << 8)
556 | ((unsigned int)(child->subordinate) << 16);
557
558 /*
559 * yenta.c forces a secondary latency timer of 176.
560 * Copy that behaviour here.
561 */
562 if (is_cardbus) {
563 buses &= ~0xff000000;
564 buses |= CARDBUS_LATENCY_TIMER << 24;
565 }
566
567 /*
568 * We need to blast all three values with a single write.
569 */
570 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
571
572 if (!is_cardbus) {
573 child->bridge_ctl = bctl;
574 /*
575 * Adjust subordinate busnr in parent buses.
576 * We do this before scanning for children because
577 * some devices may not be detected if the bios
578 * was lazy.
579 */
580 pci_fixup_parent_subordinate_busnr(child, max);
581 /* Now we can scan all subordinate buses... */
582 max = pci_scan_child_bus(child);
583 /*
584 * now fix it up again since we have found
585 * the real value of max.
586 */
587 pci_fixup_parent_subordinate_busnr(child, max);
588 } else {
589 /*
590 * For CardBus bridges, we leave 4 bus numbers
591 * as cards with a PCI-to-PCI bridge can be
592 * inserted later.
593 */
594 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
595 struct pci_bus *parent = bus;
596 if (pci_find_bus(pci_domain_nr(bus),
597 max+i+1))
598 break;
599 while (parent->parent) {
600 if ((!pcibios_assign_all_busses()) &&
601 (parent->subordinate > max) &&
602 (parent->subordinate <= max+i)) {
603 j = 1;
604 }
605 parent = parent->parent;
606 }
607 if (j) {
608 /*
609 * Often, there are two cardbus bridges
610 * -- try to leave one valid bus number
611 * for each one.
612 */
613 i /= 2;
614 break;
615 }
616 }
617 max += i;
618 pci_fixup_parent_subordinate_busnr(child, max);
619 }
620 /*
621 * Set the subordinate bus number to its real value.
622 */
623 child->subordinate = max;
624 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
625 }
626
627 sprintf(child->name,
628 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
629 pci_domain_nr(bus), child->number);
630
631 /* Has only triggered on CardBus, fixup is in yenta_socket */
632 while (bus->parent) {
633 if ((child->subordinate > bus->subordinate) ||
634 (child->number > bus->subordinate) ||
635 (child->number < bus->number) ||
636 (child->subordinate < bus->number)) {
637 pr_debug("PCI: Bus #%02x (-#%02x) is %s "
638 "hidden behind%s bridge #%02x (-#%02x)\n",
639 child->number, child->subordinate,
640 (bus->number > child->subordinate &&
641 bus->subordinate < child->number) ?
642 "wholly" : "partially",
643 bus->self->transparent ? " transparent" : "",
644 bus->number, bus->subordinate);
645 }
646 bus = bus->parent;
647 }
648
649 out:
650 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
651
652 return max;
653 }
654
655 /*
656 * Read interrupt line and base address registers.
657 * The architecture-dependent code can tweak these, of course.
658 */
659 static void pci_read_irq(struct pci_dev *dev)
660 {
661 unsigned char irq;
662
663 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
664 dev->pin = irq;
665 if (irq)
666 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
667 dev->irq = irq;
668 }
669
670 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
671
672 /**
673 * pci_setup_device - fill in class and map information of a device
674 * @dev: the device structure to fill
675 *
676 * Initialize the device structure with information about the device's
677 * vendor,class,memory and IO-space addresses,IRQ lines etc.
678 * Called at initialisation of the PCI subsystem and by CardBus services.
679 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
680 * or CardBus).
681 */
682 static int pci_setup_device(struct pci_dev * dev)
683 {
684 u32 class;
685
686 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
687 dev->bus->number, PCI_SLOT(dev->devfn),
688 PCI_FUNC(dev->devfn));
689
690 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
691 dev->revision = class & 0xff;
692 class >>= 8; /* upper 3 bytes */
693 dev->class = class;
694 class >>= 8;
695
696 dev_dbg(&dev->dev, "found [%04x:%04x] class %06x header type %02x\n",
697 dev->vendor, dev->device, class, dev->hdr_type);
698
699 /* "Unknown power state" */
700 dev->current_state = PCI_UNKNOWN;
701
702 /* Early fixups, before probing the BARs */
703 pci_fixup_device(pci_fixup_early, dev);
704 class = dev->class >> 8;
705
706 switch (dev->hdr_type) { /* header type */
707 case PCI_HEADER_TYPE_NORMAL: /* standard header */
708 if (class == PCI_CLASS_BRIDGE_PCI)
709 goto bad;
710 pci_read_irq(dev);
711 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
712 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
713 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
714
715 /*
716 * Do the ugly legacy mode stuff here rather than broken chip
717 * quirk code. Legacy mode ATA controllers have fixed
718 * addresses. These are not always echoed in BAR0-3, and
719 * BAR0-3 in a few cases contain junk!
720 */
721 if (class == PCI_CLASS_STORAGE_IDE) {
722 u8 progif;
723 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
724 if ((progif & 1) == 0) {
725 dev->resource[0].start = 0x1F0;
726 dev->resource[0].end = 0x1F7;
727 dev->resource[0].flags = LEGACY_IO_RESOURCE;
728 dev->resource[1].start = 0x3F6;
729 dev->resource[1].end = 0x3F6;
730 dev->resource[1].flags = LEGACY_IO_RESOURCE;
731 }
732 if ((progif & 4) == 0) {
733 dev->resource[2].start = 0x170;
734 dev->resource[2].end = 0x177;
735 dev->resource[2].flags = LEGACY_IO_RESOURCE;
736 dev->resource[3].start = 0x376;
737 dev->resource[3].end = 0x376;
738 dev->resource[3].flags = LEGACY_IO_RESOURCE;
739 }
740 }
741 break;
742
743 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
744 if (class != PCI_CLASS_BRIDGE_PCI)
745 goto bad;
746 /* The PCI-to-PCI bridge spec requires that subtractive
747 decoding (i.e. transparent) bridge must have programming
748 interface code of 0x01. */
749 pci_read_irq(dev);
750 dev->transparent = ((dev->class & 0xff) == 1);
751 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
752 break;
753
754 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
755 if (class != PCI_CLASS_BRIDGE_CARDBUS)
756 goto bad;
757 pci_read_irq(dev);
758 pci_read_bases(dev, 1, 0);
759 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
760 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
761 break;
762
763 default: /* unknown header */
764 dev_err(&dev->dev, "unknown header type %02x, "
765 "ignoring device\n", dev->hdr_type);
766 return -1;
767
768 bad:
769 dev_err(&dev->dev, "ignoring class %02x (doesn't match header "
770 "type %02x)\n", class, dev->hdr_type);
771 dev->class = PCI_CLASS_NOT_DEFINED;
772 }
773
774 /* We found a fine healthy device, go go go... */
775 return 0;
776 }
777
778 static void pci_release_capabilities(struct pci_dev *dev)
779 {
780 pci_vpd_release(dev);
781 }
782
783 /**
784 * pci_release_dev - free a pci device structure when all users of it are finished.
785 * @dev: device that's been disconnected
786 *
787 * Will be called only by the device core when all users of this pci device are
788 * done.
789 */
790 static void pci_release_dev(struct device *dev)
791 {
792 struct pci_dev *pci_dev;
793
794 pci_dev = to_pci_dev(dev);
795 pci_release_capabilities(pci_dev);
796 kfree(pci_dev);
797 }
798
799 static void set_pcie_port_type(struct pci_dev *pdev)
800 {
801 int pos;
802 u16 reg16;
803
804 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
805 if (!pos)
806 return;
807 pdev->is_pcie = 1;
808 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
809 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
810 }
811
812 /**
813 * pci_cfg_space_size - get the configuration space size of the PCI device.
814 * @dev: PCI device
815 *
816 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
817 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
818 * access it. Maybe we don't have a way to generate extended config space
819 * accesses, or the device is behind a reverse Express bridge. So we try
820 * reading the dword at 0x100 which must either be 0 or a valid extended
821 * capability header.
822 */
823 int pci_cfg_space_size_ext(struct pci_dev *dev)
824 {
825 u32 status;
826 int pos = PCI_CFG_SPACE_SIZE;
827
828 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
829 goto fail;
830 if (status == 0xffffffff)
831 goto fail;
832
833 return PCI_CFG_SPACE_EXP_SIZE;
834
835 fail:
836 return PCI_CFG_SPACE_SIZE;
837 }
838
839 int pci_cfg_space_size(struct pci_dev *dev)
840 {
841 int pos;
842 u32 status;
843
844 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
845 if (!pos) {
846 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
847 if (!pos)
848 goto fail;
849
850 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
851 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
852 goto fail;
853 }
854
855 return pci_cfg_space_size_ext(dev);
856
857 fail:
858 return PCI_CFG_SPACE_SIZE;
859 }
860
861 static void pci_release_bus_bridge_dev(struct device *dev)
862 {
863 kfree(dev);
864 }
865
866 struct pci_dev *alloc_pci_dev(void)
867 {
868 struct pci_dev *dev;
869
870 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
871 if (!dev)
872 return NULL;
873
874 INIT_LIST_HEAD(&dev->bus_list);
875
876 return dev;
877 }
878 EXPORT_SYMBOL(alloc_pci_dev);
879
880 /*
881 * Read the config data for a PCI device, sanity-check it
882 * and fill in the dev structure...
883 */
884 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
885 {
886 struct pci_dev *dev;
887 struct pci_slot *slot;
888 u32 l;
889 u8 hdr_type;
890 int delay = 1;
891
892 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
893 return NULL;
894
895 /* some broken boards return 0 or ~0 if a slot is empty: */
896 if (l == 0xffffffff || l == 0x00000000 ||
897 l == 0x0000ffff || l == 0xffff0000)
898 return NULL;
899
900 /* Configuration request Retry Status */
901 while (l == 0xffff0001) {
902 msleep(delay);
903 delay *= 2;
904 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
905 return NULL;
906 /* Card hasn't responded in 60 seconds? Must be stuck. */
907 if (delay > 60 * 1000) {
908 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
909 "responding\n", pci_domain_nr(bus),
910 bus->number, PCI_SLOT(devfn),
911 PCI_FUNC(devfn));
912 return NULL;
913 }
914 }
915
916 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
917 return NULL;
918
919 dev = alloc_pci_dev();
920 if (!dev)
921 return NULL;
922
923 dev->bus = bus;
924 dev->sysdata = bus->sysdata;
925 dev->dev.parent = bus->bridge;
926 dev->dev.bus = &pci_bus_type;
927 dev->devfn = devfn;
928 dev->hdr_type = hdr_type & 0x7f;
929 dev->multifunction = !!(hdr_type & 0x80);
930 dev->vendor = l & 0xffff;
931 dev->device = (l >> 16) & 0xffff;
932 dev->cfg_size = pci_cfg_space_size(dev);
933 dev->error_state = pci_channel_io_normal;
934 set_pcie_port_type(dev);
935
936 list_for_each_entry(slot, &bus->slots, list)
937 if (PCI_SLOT(devfn) == slot->number)
938 dev->slot = slot;
939
940 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
941 set this higher, assuming the system even supports it. */
942 dev->dma_mask = 0xffffffff;
943 if (pci_setup_device(dev) < 0) {
944 kfree(dev);
945 return NULL;
946 }
947
948 return dev;
949 }
950
951 static void pci_init_capabilities(struct pci_dev *dev)
952 {
953 /* MSI/MSI-X list */
954 pci_msi_init_pci_dev(dev);
955
956 /* Power Management */
957 pci_pm_init(dev);
958
959 /* Vital Product Data */
960 pci_vpd_pci22_init(dev);
961
962 /* Alternative Routing-ID Forwarding */
963 pci_enable_ari(dev);
964 }
965
966 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
967 {
968 device_initialize(&dev->dev);
969 dev->dev.release = pci_release_dev;
970 pci_dev_get(dev);
971
972 dev->dev.dma_mask = &dev->dma_mask;
973 dev->dev.dma_parms = &dev->dma_parms;
974 dev->dev.coherent_dma_mask = 0xffffffffull;
975
976 pci_set_dma_max_seg_size(dev, 65536);
977 pci_set_dma_seg_boundary(dev, 0xffffffff);
978
979 /* Fix up broken headers */
980 pci_fixup_device(pci_fixup_header, dev);
981
982 /* Initialize various capabilities */
983 pci_init_capabilities(dev);
984
985 /*
986 * Add the device to our list of discovered devices
987 * and the bus list for fixup functions, etc.
988 */
989 down_write(&pci_bus_sem);
990 list_add_tail(&dev->bus_list, &bus->devices);
991 up_write(&pci_bus_sem);
992 }
993
994 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
995 {
996 struct pci_dev *dev;
997
998 dev = pci_scan_device(bus, devfn);
999 if (!dev)
1000 return NULL;
1001
1002 pci_device_add(dev, bus);
1003
1004 return dev;
1005 }
1006 EXPORT_SYMBOL(pci_scan_single_device);
1007
1008 /**
1009 * pci_scan_slot - scan a PCI slot on a bus for devices.
1010 * @bus: PCI bus to scan
1011 * @devfn: slot number to scan (must have zero function.)
1012 *
1013 * Scan a PCI slot on the specified PCI bus for devices, adding
1014 * discovered devices to the @bus->devices list. New devices
1015 * will not have is_added set.
1016 */
1017 int pci_scan_slot(struct pci_bus *bus, int devfn)
1018 {
1019 int func, nr = 0;
1020 int scan_all_fns;
1021
1022 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
1023
1024 for (func = 0; func < 8; func++, devfn++) {
1025 struct pci_dev *dev;
1026
1027 dev = pci_scan_single_device(bus, devfn);
1028 if (dev) {
1029 nr++;
1030
1031 /*
1032 * If this is a single function device,
1033 * don't scan past the first function.
1034 */
1035 if (!dev->multifunction) {
1036 if (func > 0) {
1037 dev->multifunction = 1;
1038 } else {
1039 break;
1040 }
1041 }
1042 } else {
1043 if (func == 0 && !scan_all_fns)
1044 break;
1045 }
1046 }
1047
1048 /* only one slot has pcie device */
1049 if (bus->self && nr)
1050 pcie_aspm_init_link_state(bus->self);
1051
1052 return nr;
1053 }
1054
1055 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1056 {
1057 unsigned int devfn, pass, max = bus->secondary;
1058 struct pci_dev *dev;
1059
1060 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1061
1062 /* Go find them, Rover! */
1063 for (devfn = 0; devfn < 0x100; devfn += 8)
1064 pci_scan_slot(bus, devfn);
1065
1066 /*
1067 * After performing arch-dependent fixup of the bus, look behind
1068 * all PCI-to-PCI bridges on this bus.
1069 */
1070 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1071 pcibios_fixup_bus(bus);
1072 for (pass=0; pass < 2; pass++)
1073 list_for_each_entry(dev, &bus->devices, bus_list) {
1074 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1075 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1076 max = pci_scan_bridge(bus, dev, max, pass);
1077 }
1078
1079 /*
1080 * We've scanned the bus and so we know all about what's on
1081 * the other side of any bridges that may be on this bus plus
1082 * any devices.
1083 *
1084 * Return how far we've got finding sub-buses.
1085 */
1086 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
1087 pci_domain_nr(bus), bus->number, max);
1088 return max;
1089 }
1090
1091 void __attribute__((weak)) set_pci_bus_resources_arch_default(struct pci_bus *b)
1092 {
1093 }
1094
1095 struct pci_bus * pci_create_bus(struct device *parent,
1096 int bus, struct pci_ops *ops, void *sysdata)
1097 {
1098 int error;
1099 struct pci_bus *b;
1100 struct device *dev;
1101
1102 b = pci_alloc_bus();
1103 if (!b)
1104 return NULL;
1105
1106 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
1107 if (!dev){
1108 kfree(b);
1109 return NULL;
1110 }
1111
1112 b->sysdata = sysdata;
1113 b->ops = ops;
1114
1115 if (pci_find_bus(pci_domain_nr(b), bus)) {
1116 /* If we already got to this bus through a different bridge, ignore it */
1117 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
1118 goto err_out;
1119 }
1120
1121 down_write(&pci_bus_sem);
1122 list_add_tail(&b->node, &pci_root_buses);
1123 up_write(&pci_bus_sem);
1124
1125 memset(dev, 0, sizeof(*dev));
1126 dev->parent = parent;
1127 dev->release = pci_release_bus_bridge_dev;
1128 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
1129 error = device_register(dev);
1130 if (error)
1131 goto dev_reg_err;
1132 b->bridge = get_device(dev);
1133
1134 if (!parent)
1135 set_dev_node(b->bridge, pcibus_to_node(b));
1136
1137 b->dev.class = &pcibus_class;
1138 b->dev.parent = b->bridge;
1139 sprintf(b->dev.bus_id, "%04x:%02x", pci_domain_nr(b), bus);
1140 error = device_register(&b->dev);
1141 if (error)
1142 goto class_dev_reg_err;
1143 error = device_create_file(&b->dev, &dev_attr_cpuaffinity);
1144 if (error)
1145 goto dev_create_file_err;
1146
1147 /* Create legacy_io and legacy_mem files for this bus */
1148 pci_create_legacy_files(b);
1149
1150 b->number = b->secondary = bus;
1151 b->resource[0] = &ioport_resource;
1152 b->resource[1] = &iomem_resource;
1153
1154 set_pci_bus_resources_arch_default(b);
1155
1156 return b;
1157
1158 dev_create_file_err:
1159 device_unregister(&b->dev);
1160 class_dev_reg_err:
1161 device_unregister(dev);
1162 dev_reg_err:
1163 down_write(&pci_bus_sem);
1164 list_del(&b->node);
1165 up_write(&pci_bus_sem);
1166 err_out:
1167 kfree(dev);
1168 kfree(b);
1169 return NULL;
1170 }
1171
1172 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1173 int bus, struct pci_ops *ops, void *sysdata)
1174 {
1175 struct pci_bus *b;
1176
1177 b = pci_create_bus(parent, bus, ops, sysdata);
1178 if (b)
1179 b->subordinate = pci_scan_child_bus(b);
1180 return b;
1181 }
1182 EXPORT_SYMBOL(pci_scan_bus_parented);
1183
1184 #ifdef CONFIG_HOTPLUG
1185 EXPORT_SYMBOL(pci_add_new_bus);
1186 EXPORT_SYMBOL(pci_scan_slot);
1187 EXPORT_SYMBOL(pci_scan_bridge);
1188 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1189 #endif
1190
1191 static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
1192 {
1193 const struct pci_dev *a = to_pci_dev(d_a);
1194 const struct pci_dev *b = to_pci_dev(d_b);
1195
1196 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1197 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1198
1199 if (a->bus->number < b->bus->number) return -1;
1200 else if (a->bus->number > b->bus->number) return 1;
1201
1202 if (a->devfn < b->devfn) return -1;
1203 else if (a->devfn > b->devfn) return 1;
1204
1205 return 0;
1206 }
1207
1208 void __init pci_sort_breadthfirst(void)
1209 {
1210 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
1211 }
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