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Merge branch 'rmk-next' into s3c64xx
[linux-2.6/openmoko-kernel.git] / drivers / mmc / host / sdhci.c
blobed2c89254df4468efd26b6f1fc1d847444ca2710
1 /*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/io.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/scatterlist.h>
21
22 #include <linux/leds.h>
23
24 #include <linux/mmc/host.h>
25
26 #include "sdhci.h"
27
28 #define DRIVER_NAME "sdhci"
29
30 #define DBG(f, x...) \
31 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
32
33 static unsigned int debug_quirks = 0;
34
35 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
36 static void sdhci_finish_data(struct sdhci_host *);
37
38 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
39 static void sdhci_finish_command(struct sdhci_host *);
40
41 static void sdhci_dumpregs(struct sdhci_host *host)
42 {
43 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
44
45 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
46 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
47 readw(host->ioaddr + SDHCI_HOST_VERSION));
48 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
49 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
50 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
51 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
52 readl(host->ioaddr + SDHCI_ARGUMENT),
53 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
54 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
55 readl(host->ioaddr + SDHCI_PRESENT_STATE),
56 readb(host->ioaddr + SDHCI_HOST_CONTROL));
57 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
58 readb(host->ioaddr + SDHCI_POWER_CONTROL),
59 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
60 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
61 readb(host->ioaddr + SDHCI_WAKE_UP_CONTROL),
62 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
63 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
64 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
65 readl(host->ioaddr + SDHCI_INT_STATUS));
66 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
67 readl(host->ioaddr + SDHCI_INT_ENABLE),
68 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
69 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
70 readw(host->ioaddr + SDHCI_ACMD12_ERR),
71 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
72 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
73 readl(host->ioaddr + SDHCI_CAPABILITIES),
74 readl(host->ioaddr + SDHCI_MAX_CURRENT));
75
76 if (host->flags & SDHCI_USE_ADMA)
77 printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
78 readl(host->ioaddr + SDHCI_ADMA_ERROR),
79 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
80
81 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
82 }
83
84 /*****************************************************************************\
85 * *
86 * Low level functions *
87 * *
88 \*****************************************************************************/
89
90 static void sdhci_reset(struct sdhci_host *host, u8 mask)
91 {
92 unsigned long timeout;
93
94 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
95 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
96 SDHCI_CARD_PRESENT))
97 return;
98 }
99
100 writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
101
102 if (mask & SDHCI_RESET_ALL)
103 host->clock = 0;
104
105 /* Wait max 100 ms */
106 timeout = 100;
107
108 /* hw clears the bit when it's done */
109 while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
110 if (timeout == 0) {
111 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
112 mmc_hostname(host->mmc), (int)mask);
113 sdhci_dumpregs(host);
114 return;
115 }
116 timeout--;
117 mdelay(1);
118 }
119 }
120
121 static void sdhci_init(struct sdhci_host *host)
122 {
123 u32 intmask;
124
125 sdhci_reset(host, SDHCI_RESET_ALL);
126
127 intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
128 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
129 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
130 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
131 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
132 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE |
133 SDHCI_INT_ADMA_ERROR;
134
135 writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
136 writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
137 }
138
139 static void sdhci_activate_led(struct sdhci_host *host)
140 {
141 u8 ctrl;
142
143 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
144 ctrl |= SDHCI_CTRL_LED;
145 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
146 }
147
148 static void sdhci_deactivate_led(struct sdhci_host *host)
149 {
150 u8 ctrl;
151
152 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
153 ctrl &= ~SDHCI_CTRL_LED;
154 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
155 }
156
157 #ifdef CONFIG_LEDS_CLASS
158 static void sdhci_led_control(struct led_classdev *led,
159 enum led_brightness brightness)
160 {
161 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
162 unsigned long flags;
163
164 spin_lock_irqsave(&host->lock, flags);
165
166 if (brightness == LED_OFF)
167 sdhci_deactivate_led(host);
168 else
169 sdhci_activate_led(host);
170
171 spin_unlock_irqrestore(&host->lock, flags);
172 }
173 #endif
174
175 /*****************************************************************************\
176 * *
177 * Core functions *
178 * *
179 \*****************************************************************************/
180
181 static void sdhci_read_block_pio(struct sdhci_host *host)
182 {
183 unsigned long flags;
184 size_t blksize, len, chunk;
185 u32 uninitialized_var(scratch);
186 u8 *buf;
187
188 DBG("PIO reading\n");
189
190 blksize = host->data->blksz;
191 chunk = 0;
192
193 local_irq_save(flags);
194
195 while (blksize) {
196 if (!sg_miter_next(&host->sg_miter))
197 BUG();
198
199 len = min(host->sg_miter.length, blksize);
200
201 blksize -= len;
202 host->sg_miter.consumed = len;
203
204 buf = host->sg_miter.addr;
205
206 while (len) {
207 if (chunk == 0) {
208 scratch = readl(host->ioaddr + SDHCI_BUFFER);
209 chunk = 4;
210 }
211
212 *buf = scratch & 0xFF;
213
214 buf++;
215 scratch >>= 8;
216 chunk--;
217 len--;
218 }
219 }
220
221 sg_miter_stop(&host->sg_miter);
222
223 local_irq_restore(flags);
224 }
225
226 static void sdhci_write_block_pio(struct sdhci_host *host)
227 {
228 unsigned long flags;
229 size_t blksize, len, chunk;
230 u32 scratch;
231 u8 *buf;
232
233 DBG("PIO writing\n");
234
235 blksize = host->data->blksz;
236 chunk = 0;
237 scratch = 0;
238
239 local_irq_save(flags);
240
241 while (blksize) {
242 if (!sg_miter_next(&host->sg_miter))
243 BUG();
244
245 len = min(host->sg_miter.length, blksize);
246
247 blksize -= len;
248 host->sg_miter.consumed = len;
249
250 buf = host->sg_miter.addr;
251
252 while (len) {
253 scratch |= (u32)*buf << (chunk * 8);
254
255 buf++;
256 chunk++;
257 len--;
258
259 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
260 writel(scratch, host->ioaddr + SDHCI_BUFFER);
261 chunk = 0;
262 scratch = 0;
263 }
264 }
265 }
266
267 sg_miter_stop(&host->sg_miter);
268
269 local_irq_restore(flags);
270 }
271
272 static void sdhci_transfer_pio(struct sdhci_host *host)
273 {
274 u32 mask;
275
276 BUG_ON(!host->data);
277
278 if (host->blocks == 0)
279 return;
280
281 if (host->data->flags & MMC_DATA_READ)
282 mask = SDHCI_DATA_AVAILABLE;
283 else
284 mask = SDHCI_SPACE_AVAILABLE;
285
286 /*
287 * Some controllers (JMicron JMB38x) mess up the buffer bits
288 * for transfers < 4 bytes. As long as it is just one block,
289 * we can ignore the bits.
290 */
291 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
292 (host->data->blocks == 1))
293 mask = ~0;
294
295 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
296 if (host->data->flags & MMC_DATA_READ)
297 sdhci_read_block_pio(host);
298 else
299 sdhci_write_block_pio(host);
300
301 host->blocks--;
302 if (host->blocks == 0)
303 break;
304 }
305
306 DBG("PIO transfer complete.\n");
307 }
308
309 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
310 {
311 local_irq_save(*flags);
312 return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
313 }
314
315 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
316 {
317 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
318 local_irq_restore(*flags);
319 }
320
321 static int sdhci_adma_table_pre(struct sdhci_host *host,
322 struct mmc_data *data)
323 {
324 int direction;
325
326 u8 *desc;
327 u8 *align;
328 dma_addr_t addr;
329 dma_addr_t align_addr;
330 int len, offset;
331
332 struct scatterlist *sg;
333 int i;
334 char *buffer;
335 unsigned long flags;
336
337 /*
338 * The spec does not specify endianness of descriptor table.
339 * We currently guess that it is LE.
340 */
341
342 if (data->flags & MMC_DATA_READ)
343 direction = DMA_FROM_DEVICE;
344 else
345 direction = DMA_TO_DEVICE;
346
347 /*
348 * The ADMA descriptor table is mapped further down as we
349 * need to fill it with data first.
350 */
351
352 host->align_addr = dma_map_single(mmc_dev(host->mmc),
353 host->align_buffer, 128 * 4, direction);
354 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
355 goto fail;
356 BUG_ON(host->align_addr & 0x3);
357
358 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
359 data->sg, data->sg_len, direction);
360 if (host->sg_count == 0)
361 goto unmap_align;
362
363 desc = host->adma_desc;
364 align = host->align_buffer;
365
366 align_addr = host->align_addr;
367
368 for_each_sg(data->sg, sg, host->sg_count, i) {
369 addr = sg_dma_address(sg);
370 len = sg_dma_len(sg);
371
372 /*
373 * The SDHCI specification states that ADMA
374 * addresses must be 32-bit aligned. If they
375 * aren't, then we use a bounce buffer for
376 * the (up to three) bytes that screw up the
377 * alignment.
378 */
379 offset = (4 - (addr & 0x3)) & 0x3;
380 if (offset) {
381 if (data->flags & MMC_DATA_WRITE) {
382 buffer = sdhci_kmap_atomic(sg, &flags);
383 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
384 memcpy(align, buffer, offset);
385 sdhci_kunmap_atomic(buffer, &flags);
386 }
387
388 desc[7] = (align_addr >> 24) & 0xff;
389 desc[6] = (align_addr >> 16) & 0xff;
390 desc[5] = (align_addr >> 8) & 0xff;
391 desc[4] = (align_addr >> 0) & 0xff;
392
393 BUG_ON(offset > 65536);
394
395 desc[3] = (offset >> 8) & 0xff;
396 desc[2] = (offset >> 0) & 0xff;
397
398 desc[1] = 0x00;
399 desc[0] = 0x21; /* tran, valid */
400
401 align += 4;
402 align_addr += 4;
403
404 desc += 8;
405
406 addr += offset;
407 len -= offset;
408 }
409
410 desc[7] = (addr >> 24) & 0xff;
411 desc[6] = (addr >> 16) & 0xff;
412 desc[5] = (addr >> 8) & 0xff;
413 desc[4] = (addr >> 0) & 0xff;
414
415 BUG_ON(len > 65536);
416
417 desc[3] = (len >> 8) & 0xff;
418 desc[2] = (len >> 0) & 0xff;
419
420 desc[1] = 0x00;
421 desc[0] = 0x21; /* tran, valid */
422
423 desc += 8;
424
425 /*
426 * If this triggers then we have a calculation bug
427 * somewhere. :/
428 */
429 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
430 }
431
432 /*
433 * Add a terminating entry.
434 */
435 desc[7] = 0;
436 desc[6] = 0;
437 desc[5] = 0;
438 desc[4] = 0;
439
440 desc[3] = 0;
441 desc[2] = 0;
442
443 desc[1] = 0x00;
444 desc[0] = 0x03; /* nop, end, valid */
445
446 /*
447 * Resync align buffer as we might have changed it.
448 */
449 if (data->flags & MMC_DATA_WRITE) {
450 dma_sync_single_for_device(mmc_dev(host->mmc),
451 host->align_addr, 128 * 4, direction);
452 }
453
454 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
455 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
456 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
457 goto unmap_entries;
458 BUG_ON(host->adma_addr & 0x3);
459
460 return 0;
461
462 unmap_entries:
463 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
464 data->sg_len, direction);
465 unmap_align:
466 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
467 128 * 4, direction);
468 fail:
469 return -EINVAL;
470 }
471
472 static void sdhci_adma_table_post(struct sdhci_host *host,
473 struct mmc_data *data)
474 {
475 int direction;
476
477 struct scatterlist *sg;
478 int i, size;
479 u8 *align;
480 char *buffer;
481 unsigned long flags;
482
483 if (data->flags & MMC_DATA_READ)
484 direction = DMA_FROM_DEVICE;
485 else
486 direction = DMA_TO_DEVICE;
487
488 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
489 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
490
491 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
492 128 * 4, direction);
493
494 if (data->flags & MMC_DATA_READ) {
495 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
496 data->sg_len, direction);
497
498 align = host->align_buffer;
499
500 for_each_sg(data->sg, sg, host->sg_count, i) {
501 if (sg_dma_address(sg) & 0x3) {
502 size = 4 - (sg_dma_address(sg) & 0x3);
503
504 buffer = sdhci_kmap_atomic(sg, &flags);
505 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
506 memcpy(buffer, align, size);
507 sdhci_kunmap_atomic(buffer, &flags);
508
509 align += 4;
510 }
511 }
512 }
513
514 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
515 data->sg_len, direction);
516 }
517
518 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
519 {
520 u8 count;
521 unsigned target_timeout, current_timeout;
522
523 /*
524 * If the host controller provides us with an incorrect timeout
525 * value, just skip the check and use 0xE. The hardware may take
526 * longer to time out, but that's much better than having a too-short
527 * timeout value.
528 */
529 if ((host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL))
530 return 0xE;
531
532 /* timeout in us */
533 target_timeout = data->timeout_ns / 1000 +
534 data->timeout_clks / host->clock;
535
536 /*
537 * Figure out needed cycles.
538 * We do this in steps in order to fit inside a 32 bit int.
539 * The first step is the minimum timeout, which will have a
540 * minimum resolution of 6 bits:
541 * (1) 2^13*1000 > 2^22,
542 * (2) host->timeout_clk < 2^16
543 * =>
544 * (1) / (2) > 2^6
545 */
546 count = 0;
547 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
548 while (current_timeout < target_timeout) {
549 count++;
550 current_timeout <<= 1;
551 if (count >= 0xF)
552 break;
553 }
554
555 if (count >= 0xF) {
556 printk(KERN_WARNING "%s: Too large timeout requested!\n",
557 mmc_hostname(host->mmc));
558 count = 0xE;
559 }
560
561 return count;
562 }
563
564 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
565 {
566 u8 count;
567 u8 ctrl;
568 int ret;
569
570 WARN_ON(host->data);
571
572 if (data == NULL)
573 return;
574
575 /* Sanity checks */
576 BUG_ON(data->blksz * data->blocks > 524288);
577 BUG_ON(data->blksz > host->mmc->max_blk_size);
578 BUG_ON(data->blocks > 65535);
579
580 host->data = data;
581 host->data_early = 0;
582
583 count = sdhci_calc_timeout(host, data);
584 writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
585
586 if (host->flags & SDHCI_USE_DMA)
587 host->flags |= SDHCI_REQ_USE_DMA;
588
589 /*
590 * FIXME: This doesn't account for merging when mapping the
591 * scatterlist.
592 */
593 if (host->flags & SDHCI_REQ_USE_DMA) {
594 int broken, i;
595 struct scatterlist *sg;
596
597 broken = 0;
598 if (host->flags & SDHCI_USE_ADMA) {
599 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
600 broken = 1;
601 } else {
602 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
603 broken = 1;
604 }
605
606 if (unlikely(broken)) {
607 for_each_sg(data->sg, sg, data->sg_len, i) {
608 if (sg->length & 0x3) {
609 DBG("Reverting to PIO because of "
610 "transfer size (%d)\n",
611 sg->length);
612 host->flags &= ~SDHCI_REQ_USE_DMA;
613 break;
614 }
615 }
616 }
617 }
618
619 /*
620 * The assumption here being that alignment is the same after
621 * translation to device address space.
622 */
623 if (host->flags & SDHCI_REQ_USE_DMA) {
624 int broken, i;
625 struct scatterlist *sg;
626
627 broken = 0;
628 if (host->flags & SDHCI_USE_ADMA) {
629 /*
630 * As we use 3 byte chunks to work around
631 * alignment problems, we need to check this
632 * quirk.
633 */
634 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
635 broken = 1;
636 } else {
637 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
638 broken = 1;
639 }
640
641 if (unlikely(broken)) {
642 for_each_sg(data->sg, sg, data->sg_len, i) {
643 if (sg->offset & 0x3) {
644 DBG("Reverting to PIO because of "
645 "bad alignment\n");
646 host->flags &= ~SDHCI_REQ_USE_DMA;
647 break;
648 }
649 }
650 }
651 }
652
653 if (host->flags & SDHCI_REQ_USE_DMA) {
654 if (host->flags & SDHCI_USE_ADMA) {
655 ret = sdhci_adma_table_pre(host, data);
656 if (ret) {
657 /*
658 * This only happens when someone fed
659 * us an invalid request.
660 */
661 WARN_ON(1);
662 host->flags &= ~SDHCI_REQ_USE_DMA;
663 } else {
664 writel(host->adma_addr,
665 host->ioaddr + SDHCI_ADMA_ADDRESS);
666 }
667 } else {
668 int sg_cnt;
669
670 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
671 data->sg, data->sg_len,
672 (data->flags & MMC_DATA_READ) ?
673 DMA_FROM_DEVICE :
674 DMA_TO_DEVICE);
675 if (sg_cnt == 0) {
676 /*
677 * This only happens when someone fed
678 * us an invalid request.
679 */
680 WARN_ON(1);
681 host->flags &= ~SDHCI_REQ_USE_DMA;
682 } else {
683 WARN_ON(sg_cnt != 1);
684 writel(sg_dma_address(data->sg),
685 host->ioaddr + SDHCI_DMA_ADDRESS);
686 }
687 }
688 }
689
690 /*
691 * Always adjust the DMA selection as some controllers
692 * (e.g. JMicron) can't do PIO properly when the selection
693 * is ADMA.
694 */
695 if (host->version >= SDHCI_SPEC_200) {
696 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
697 ctrl &= ~SDHCI_CTRL_DMA_MASK;
698 if ((host->flags & SDHCI_REQ_USE_DMA) &&
699 (host->flags & SDHCI_USE_ADMA))
700 ctrl |= SDHCI_CTRL_ADMA32;
701 else
702 ctrl |= SDHCI_CTRL_SDMA;
703 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
704 }
705
706 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
707 sg_miter_start(&host->sg_miter,
708 data->sg, data->sg_len, SG_MITER_ATOMIC);
709 host->blocks = data->blocks;
710 }
711
712 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
713 writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
714 host->ioaddr + SDHCI_BLOCK_SIZE);
715 writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
716 }
717
718 static void sdhci_set_transfer_mode(struct sdhci_host *host,
719 struct mmc_data *data)
720 {
721 u16 mode;
722
723 if (data == NULL)
724 return;
725
726 WARN_ON(!host->data);
727
728 mode = SDHCI_TRNS_BLK_CNT_EN;
729 if (data->blocks > 1)
730 mode |= SDHCI_TRNS_MULTI;
731 if (data->flags & MMC_DATA_READ)
732 mode |= SDHCI_TRNS_READ;
733 if (host->flags & SDHCI_REQ_USE_DMA)
734 mode |= SDHCI_TRNS_DMA;
735
736 writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
737 }
738
739 static void shdci_check_dma_overrun(struct sdhci_host *host, struct mmc_data *data)
740 {
741 u32 dma_pos = readl(host->ioaddr + SDHCI_DMA_ADDRESS);
742 u32 dma_start = sg_dma_address(data->sg);
743 u32 dma_end = dma_start + data->sg->length;
744
745 /* Test whether we ended up moving more data than
746 * was originally requested. */
747
748 if (dma_pos <= dma_end)
749 return;
750
751 printk(KERN_ERR "%s: dma overrun, dma %08x, req %08x..%08x\n",
752 mmc_hostname(host->mmc), dma_pos,
753 dma_start, dma_end);
754 }
755
756 static void sdhci_finish_data(struct sdhci_host *host)
757 {
758 struct mmc_data *data;
759
760 BUG_ON(!host->data);
761
762 data = host->data;
763 host->data = NULL;
764
765 if (host->flags & SDHCI_REQ_USE_DMA) {
766 if (host->flags & SDHCI_USE_ADMA)
767 sdhci_adma_table_post(host, data);
768 else {
769 shdci_check_dma_overrun(host, data);
770
771 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
772 data->sg_len, (data->flags & MMC_DATA_READ) ?
773 DMA_FROM_DEVICE : DMA_TO_DEVICE);
774 }
775 }
776
777 /*
778 * The specification states that the block count register must
779 * be updated, but it does not specify at what point in the
780 * data flow. That makes the register entirely useless to read
781 * back so we have to assume that nothing made it to the card
782 * in the event of an error.
783 */
784 if (data->error)
785 data->bytes_xfered = 0;
786 else
787 data->bytes_xfered = data->blksz * data->blocks;
788
789 if (data->stop) {
790 /*
791 * The controller needs a reset of internal state machines
792 * upon error conditions.
793 */
794 if (data->error) {
795 sdhci_reset(host, SDHCI_RESET_CMD);
796 sdhci_reset(host, SDHCI_RESET_DATA);
797 }
798
799 sdhci_send_command(host, data->stop);
800 } else
801 tasklet_schedule(&host->finish_tasklet);
802 }
803
804 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
805 {
806 int flags;
807 u32 mask;
808 unsigned long timeout;
809
810 WARN_ON(host->cmd);
811
812 /* Wait max 10 ms */
813 timeout = 10;
814
815 mask = SDHCI_CMD_INHIBIT;
816 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
817 mask |= SDHCI_DATA_INHIBIT;
818
819 /* We shouldn't wait for data inihibit for stop commands, even
820 though they might use busy signaling */
821 if (host->mrq->data && (cmd == host->mrq->data->stop))
822 mask &= ~SDHCI_DATA_INHIBIT;
823
824 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
825 if (timeout == 0) {
826 printk(KERN_ERR "%s: Controller never released "
827 "inhibit bit(s).\n", mmc_hostname(host->mmc));
828 sdhci_dumpregs(host);
829 cmd->error = -EIO;
830 tasklet_schedule(&host->finish_tasklet);
831 return;
832 }
833 timeout--;
834 mdelay(1);
835 }
836
837 mod_timer(&host->timer, jiffies + 10 * HZ);
838
839 host->cmd = cmd;
840
841 sdhci_prepare_data(host, cmd->data);
842
843 writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
844
845 sdhci_set_transfer_mode(host, cmd->data);
846
847 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
848 printk(KERN_ERR "%s: Unsupported response type!\n",
849 mmc_hostname(host->mmc));
850 cmd->error = -EINVAL;
851 tasklet_schedule(&host->finish_tasklet);
852 return;
853 }
854
855 if (!(cmd->flags & MMC_RSP_PRESENT))
856 flags = SDHCI_CMD_RESP_NONE;
857 else if (cmd->flags & MMC_RSP_136)
858 flags = SDHCI_CMD_RESP_LONG;
859 else if (cmd->flags & MMC_RSP_BUSY)
860 flags = SDHCI_CMD_RESP_SHORT_BUSY;
861 else
862 flags = SDHCI_CMD_RESP_SHORT;
863
864 if (cmd->flags & MMC_RSP_CRC)
865 flags |= SDHCI_CMD_CRC;
866 if (cmd->flags & MMC_RSP_OPCODE)
867 flags |= SDHCI_CMD_INDEX;
868 if (cmd->data)
869 flags |= SDHCI_CMD_DATA;
870
871 writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
872 host->ioaddr + SDHCI_COMMAND);
873 }
874
875 static void sdhci_finish_command(struct sdhci_host *host)
876 {
877 int i;
878
879 BUG_ON(host->cmd == NULL);
880
881 if (host->cmd->flags & MMC_RSP_PRESENT) {
882 if (host->cmd->flags & MMC_RSP_136) {
883 /* CRC is stripped so we need to do some shifting. */
884 for (i = 0;i < 4;i++) {
885 host->cmd->resp[i] = readl(host->ioaddr +
886 SDHCI_RESPONSE + (3-i)*4) << 8;
887 if (i != 3)
888 host->cmd->resp[i] |=
889 readb(host->ioaddr +
890 SDHCI_RESPONSE + (3-i)*4-1);
891 }
892 } else {
893 host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
894 }
895 }
896
897 host->cmd->error = 0;
898
899 if (host->data && host->data_early)
900 sdhci_finish_data(host);
901
902 if (!host->cmd->data)
903 tasklet_schedule(&host->finish_tasklet);
904
905 host->cmd = NULL;
906 }
907
908 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
909 {
910 if (clock == host->clock)
911 return;
912
913 host->ops->change_clock(host, clock);
914 }
915
916 void sdhci_change_clock(struct sdhci_host *host, unsigned int clock)
917 {
918 int div;
919 u16 clk;
920 unsigned long timeout;
921
922 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
923
924 if (clock == 0)
925 goto out;
926
927 for (div = 1;div < 256;div *= 2) {
928 if ((host->max_clk / div) <= clock)
929 break;
930 }
931 div >>= 1;
932
933 clk = div << SDHCI_DIVIDER_SHIFT;
934 clk |= SDHCI_CLOCK_INT_EN;
935 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
936
937 /* Wait max 10 ms */
938 timeout = 10;
939 while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
940 & SDHCI_CLOCK_INT_STABLE)) {
941 if (timeout == 0) {
942 printk(KERN_ERR "%s: Internal clock never "
943 "stabilised.\n", mmc_hostname(host->mmc));
944 sdhci_dumpregs(host);
945 return;
946 }
947 timeout--;
948 mdelay(1);
949 }
950
951 clk |= SDHCI_CLOCK_CARD_EN;
952 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
953
954 out:
955 host->clock = clock;
956 }
957
958 EXPORT_SYMBOL_GPL(sdhci_set_clock);
959
960 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
961 {
962 u8 pwr;
963
964 if (host->power == power)
965 return;
966
967 if (power == (unsigned short)-1) {
968 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
969 goto out;
970 }
971
972 /*
973 * Spec says that we should clear the power reg before setting
974 * a new value. Some controllers don't seem to like this though.
975 */
976 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
977 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
978
979 pwr = SDHCI_POWER_ON;
980
981 switch (1 << power) {
982 case MMC_VDD_165_195:
983 pwr |= SDHCI_POWER_180;
984 break;
985 case MMC_VDD_29_30:
986 case MMC_VDD_30_31:
987 pwr |= SDHCI_POWER_300;
988 break;
989 case MMC_VDD_32_33:
990 case MMC_VDD_33_34:
991 pwr |= SDHCI_POWER_330;
992 break;
993 default:
994 BUG();
995 }
996
997 /*
998 * At least the Marvell CaFe chip gets confused if we set the voltage
999 * and set turn on power at the same time, so set the voltage first.
1000 */
1001 if ((host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER))
1002 writeb(pwr & ~SDHCI_POWER_ON,
1003 host->ioaddr + SDHCI_POWER_CONTROL);
1004
1005 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
1006
1007 out:
1008 host->power = power;
1009 }
1010
1011 /*****************************************************************************\
1012 * *
1013 * MMC callbacks *
1014 * *
1015 \*****************************************************************************/
1016
1017 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1018 {
1019 struct sdhci_host *host;
1020 unsigned long flags;
1021
1022 host = mmc_priv(mmc);
1023
1024 spin_lock_irqsave(&host->lock, flags);
1025
1026 WARN_ON(host->mrq != NULL);
1027
1028 #ifndef CONFIG_LEDS_CLASS
1029 sdhci_activate_led(host);
1030 #endif
1031
1032 host->mrq = mrq;
1033
1034 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)
1035 || (host->flags & SDHCI_DEVICE_DEAD)) {
1036 host->mrq->cmd->error = -ENOMEDIUM;
1037 tasklet_schedule(&host->finish_tasklet);
1038 } else
1039 sdhci_send_command(host, mrq->cmd);
1040
1041 mmiowb();
1042 spin_unlock_irqrestore(&host->lock, flags);
1043 }
1044
1045 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1046 {
1047 struct sdhci_host *host;
1048 unsigned long flags;
1049 u8 ctrl;
1050
1051 host = mmc_priv(mmc);
1052
1053 spin_lock_irqsave(&host->lock, flags);
1054
1055 if (host->flags & SDHCI_DEVICE_DEAD)
1056 goto out;
1057
1058 /*
1059 * Reset the chip on each power off.
1060 * Should clear out any weird states.
1061 */
1062 if (ios->power_mode == MMC_POWER_OFF) {
1063 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
1064 sdhci_init(host);
1065 }
1066
1067 if (host->ops->set_ios)
1068 host->ops->set_ios(host, ios);
1069
1070 sdhci_set_clock(host, ios->clock);
1071
1072 if (ios->power_mode == MMC_POWER_OFF)
1073 sdhci_set_power(host, -1);
1074 else
1075 sdhci_set_power(host, ios->vdd);
1076
1077 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
1078
1079 if (ios->bus_width == MMC_BUS_WIDTH_4)
1080 ctrl |= SDHCI_CTRL_4BITBUS;
1081 else
1082 ctrl &= ~SDHCI_CTRL_4BITBUS;
1083
1084 if (ios->timing == MMC_TIMING_SD_HS)
1085 ctrl |= SDHCI_CTRL_HISPD;
1086 else
1087 ctrl &= ~SDHCI_CTRL_HISPD;
1088
1089 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
1090
1091 /*
1092 * Some (ENE) controllers go apeshit on some ios operation,
1093 * signalling timeout and CRC errors even on CMD0. Resetting
1094 * it on each ios seems to solve the problem.
1095 */
1096 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1097 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1098
1099 out:
1100 mmiowb();
1101 spin_unlock_irqrestore(&host->lock, flags);
1102 }
1103
1104 static int sdhci_get_ro(struct mmc_host *mmc)
1105 {
1106 struct sdhci_host *host;
1107 unsigned long flags;
1108 int present;
1109
1110 host = mmc_priv(mmc);
1111
1112 spin_lock_irqsave(&host->lock, flags);
1113
1114 if (host->flags & SDHCI_DEVICE_DEAD)
1115 present = 0;
1116 else
1117 present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
1118
1119 spin_unlock_irqrestore(&host->lock, flags);
1120
1121 return !(present & SDHCI_WRITE_PROTECT);
1122 }
1123
1124 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1125 {
1126 struct sdhci_host *host;
1127 unsigned long flags;
1128 u32 ier;
1129
1130 host = mmc_priv(mmc);
1131
1132 spin_lock_irqsave(&host->lock, flags);
1133
1134 if (host->flags & SDHCI_DEVICE_DEAD)
1135 goto out;
1136
1137 ier = readl(host->ioaddr + SDHCI_INT_ENABLE);
1138
1139 ier &= ~SDHCI_INT_CARD_INT;
1140 if (enable)
1141 ier |= SDHCI_INT_CARD_INT;
1142
1143 writel(ier, host->ioaddr + SDHCI_INT_ENABLE);
1144 writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
1145
1146 out:
1147 mmiowb();
1148
1149 spin_unlock_irqrestore(&host->lock, flags);
1150 }
1151
1152 static const struct mmc_host_ops sdhci_ops = {
1153 .request = sdhci_request,
1154 .set_ios = sdhci_set_ios,
1155 .get_ro = sdhci_get_ro,
1156 .enable_sdio_irq = sdhci_enable_sdio_irq,
1157 };
1158
1159 /*****************************************************************************\
1160 * *
1161 * Tasklets *
1162 * *
1163 \*****************************************************************************/
1164
1165 static void sdhci_tasklet_card(unsigned long param)
1166 {
1167 struct sdhci_host *host;
1168 unsigned long flags;
1169
1170 host = (struct sdhci_host*)param;
1171
1172 spin_lock_irqsave(&host->lock, flags);
1173
1174 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1175 if (host->mrq) {
1176 printk(KERN_ERR "%s: Card removed during transfer!\n",
1177 mmc_hostname(host->mmc));
1178 printk(KERN_ERR "%s: Resetting controller.\n",
1179 mmc_hostname(host->mmc));
1180
1181 sdhci_reset(host, SDHCI_RESET_CMD);
1182 sdhci_reset(host, SDHCI_RESET_DATA);
1183
1184 host->mrq->cmd->error = -ENOMEDIUM;
1185 tasklet_schedule(&host->finish_tasklet);
1186 }
1187 }
1188
1189 spin_unlock_irqrestore(&host->lock, flags);
1190
1191 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1192 }
1193
1194 static void sdhci_tasklet_finish(unsigned long param)
1195 {
1196 struct sdhci_host *host;
1197 unsigned long flags;
1198 struct mmc_request *mrq;
1199
1200 host = (struct sdhci_host*)param;
1201
1202 spin_lock_irqsave(&host->lock, flags);
1203
1204 del_timer(&host->timer);
1205
1206 mrq = host->mrq;
1207
1208 /*
1209 * The controller needs a reset of internal state machines
1210 * upon error conditions.
1211 */
1212 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1213 (mrq->cmd->error ||
1214 (mrq->data && (mrq->data->error ||
1215 (mrq->data->stop && mrq->data->stop->error))) ||
1216 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
1217
1218 /* Some controllers need this kick or reset won't work here */
1219 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
1220 unsigned int clock;
1221
1222 /* This is to force an update */
1223 clock = host->clock;
1224 host->clock = 0;
1225 sdhci_set_clock(host, clock);
1226 }
1227
1228 /* Spec says we should do both at the same time, but Ricoh
1229 controllers do not like that. */
1230 sdhci_reset(host, SDHCI_RESET_CMD);
1231 sdhci_reset(host, SDHCI_RESET_DATA);
1232 }
1233
1234 host->mrq = NULL;
1235 host->cmd = NULL;
1236 host->data = NULL;
1237
1238 #ifndef CONFIG_LEDS_CLASS
1239 sdhci_deactivate_led(host);
1240 #endif
1241
1242 mmiowb();
1243 spin_unlock_irqrestore(&host->lock, flags);
1244
1245 mmc_request_done(host->mmc, mrq);
1246 }
1247
1248 static void sdhci_timeout_timer(unsigned long data)
1249 {
1250 struct sdhci_host *host;
1251 unsigned long flags;
1252
1253 host = (struct sdhci_host*)data;
1254
1255 spin_lock_irqsave(&host->lock, flags);
1256
1257 if (host->mrq) {
1258 printk(KERN_ERR "%s: Timeout waiting for hardware "
1259 "interrupt.\n", mmc_hostname(host->mmc));
1260 sdhci_dumpregs(host);
1261
1262 if (host->data) {
1263 host->data->error = -ETIMEDOUT;
1264 sdhci_finish_data(host);
1265 } else {
1266 if (host->cmd)
1267 host->cmd->error = -ETIMEDOUT;
1268 else
1269 host->mrq->cmd->error = -ETIMEDOUT;
1270
1271 tasklet_schedule(&host->finish_tasklet);
1272 }
1273 }
1274
1275 mmiowb();
1276 spin_unlock_irqrestore(&host->lock, flags);
1277 }
1278
1279 /*****************************************************************************\
1280 * *
1281 * Interrupt handling *
1282 * *
1283 \*****************************************************************************/
1284
1285 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1286 {
1287 BUG_ON(intmask == 0);
1288
1289 if (!host->cmd) {
1290 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1291 "though no command operation was in progress.\n",
1292 mmc_hostname(host->mmc), (unsigned)intmask);
1293 sdhci_dumpregs(host);
1294 return;
1295 }
1296
1297 if (intmask & SDHCI_INT_TIMEOUT)
1298 host->cmd->error = -ETIMEDOUT;
1299 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1300 SDHCI_INT_INDEX))
1301 host->cmd->error = -EILSEQ;
1302
1303 if (host->cmd->error) {
1304 tasklet_schedule(&host->finish_tasklet);
1305 return;
1306 }
1307
1308 /*
1309 * The host can send and interrupt when the busy state has
1310 * ended, allowing us to wait without wasting CPU cycles.
1311 * Unfortunately this is overloaded on the "data complete"
1312 * interrupt, so we need to take some care when handling
1313 * it.
1314 *
1315 * Note: The 1.0 specification is a bit ambiguous about this
1316 * feature so there might be some problems with older
1317 * controllers.
1318 */
1319 if (host->cmd->flags & MMC_RSP_BUSY) {
1320 u32 present;
1321
1322 if (host->cmd->data)
1323 DBG("Cannot wait for busy signal when also "
1324 "doing a data transfer");
1325 else if (!(host->quirks & SDHCI_QUIRK_NO_TCIRQ_ON_NOT_BUSY))
1326 return;
1327
1328 /* The Samsung SDHCI does not seem to provide an INT_DATA_END
1329 * when the system goes non-busy, so check the state of the
1330 * transfer by reading SDHCI_PRESENT_STATE to see if the
1331 * controller is ready
1332 */
1333
1334 present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
1335 DBG("busy? present %08x, intstat %08x\n", present, intmask);
1336
1337 /* fall through and take the SDHCI_INT_RESPONSE */
1338 }
1339
1340 if (intmask & SDHCI_INT_RESPONSE)
1341 sdhci_finish_command(host);
1342 }
1343
1344 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1345 {
1346 BUG_ON(intmask == 0);
1347
1348 if (!host->data) {
1349 /*
1350 * The "data complete" interrupt is also used to
1351 * indicate that a busy state has ended. See comment
1352 * above in sdhci_cmd_irq().
1353 */
1354 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
1355 if (intmask & SDHCI_INT_DATA_END) {
1356 sdhci_finish_command(host);
1357 return;
1358 }
1359 }
1360
1361 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1362 "though no data operation was in progress.\n",
1363 mmc_hostname(host->mmc), (unsigned)intmask);
1364 sdhci_dumpregs(host);
1365
1366 return;
1367 }
1368
1369 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1370 host->data->error = -ETIMEDOUT;
1371 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1372 host->data->error = -EILSEQ;
1373 else if (intmask & SDHCI_INT_ADMA_ERROR)
1374 host->data->error = -EIO;
1375
1376 if (host->data->error)
1377 sdhci_finish_data(host);
1378 else {
1379 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1380 sdhci_transfer_pio(host);
1381
1382 /*
1383 * We currently don't do anything fancy with DMA
1384 * boundaries, but as we can't disable the feature
1385 * we need to at least restart the transfer.
1386 */
1387 if (intmask & SDHCI_INT_DMA_END)
1388 writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS),
1389 host->ioaddr + SDHCI_DMA_ADDRESS);
1390
1391 if (intmask & SDHCI_INT_DATA_END) {
1392 if (host->cmd) {
1393 /*
1394 * Data managed to finish before the
1395 * command completed. Make sure we do
1396 * things in the proper order.
1397 */
1398 host->data_early = 1;
1399 } else {
1400 sdhci_finish_data(host);
1401 }
1402 }
1403 }
1404 }
1405
1406 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1407 {
1408 irqreturn_t result;
1409 struct sdhci_host* host = dev_id;
1410 u32 intmask;
1411 int cardint = 0;
1412
1413 spin_lock(&host->lock);
1414
1415 intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
1416
1417 if (!intmask || intmask == 0xffffffff) {
1418 result = IRQ_NONE;
1419 goto out;
1420 }
1421
1422 DBG("*** %s got interrupt: 0x%08x\n",
1423 mmc_hostname(host->mmc), intmask);
1424
1425 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1426 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1427 host->ioaddr + SDHCI_INT_STATUS);
1428 tasklet_schedule(&host->card_tasklet);
1429 }
1430
1431 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1432
1433 if (intmask & SDHCI_INT_CMD_MASK) {
1434 writel(intmask & SDHCI_INT_CMD_MASK,
1435 host->ioaddr + SDHCI_INT_STATUS);
1436 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1437 }
1438
1439 if (intmask & SDHCI_INT_DATA_MASK) {
1440 writel(intmask & SDHCI_INT_DATA_MASK,
1441 host->ioaddr + SDHCI_INT_STATUS);
1442 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1443 }
1444
1445 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1446
1447 intmask &= ~SDHCI_INT_ERROR;
1448
1449 if (intmask & SDHCI_INT_BUS_POWER) {
1450 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1451 mmc_hostname(host->mmc));
1452 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
1453 }
1454
1455 intmask &= ~SDHCI_INT_BUS_POWER;
1456
1457 if (intmask & SDHCI_INT_CARD_INT)
1458 cardint = 1;
1459
1460 intmask &= ~SDHCI_INT_CARD_INT;
1461
1462 if (intmask) {
1463 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1464 mmc_hostname(host->mmc), intmask);
1465 sdhci_dumpregs(host);
1466
1467 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
1468 }
1469
1470 result = IRQ_HANDLED;
1471
1472 mmiowb();
1473 out:
1474 spin_unlock(&host->lock);
1475
1476 /*
1477 * We have to delay this as it calls back into the driver.
1478 */
1479 if (cardint)
1480 mmc_signal_sdio_irq(host->mmc);
1481
1482 return result;
1483 }
1484
1485 /*****************************************************************************\
1486 * *
1487 * Suspend/resume *
1488 * *
1489 \*****************************************************************************/
1490
1491 #ifdef CONFIG_PM
1492
1493 int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state)
1494 {
1495 int ret;
1496
1497 ret = mmc_suspend_host(host->mmc, state);
1498 if (ret)
1499 return ret;
1500
1501 free_irq(host->irq, host);
1502
1503 return 0;
1504 }
1505
1506 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
1507
1508 int sdhci_resume_host(struct sdhci_host *host)
1509 {
1510 int ret;
1511
1512 if (host->flags & SDHCI_USE_DMA) {
1513 if (host->ops->enable_dma)
1514 host->ops->enable_dma(host);
1515 }
1516
1517 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1518 mmc_hostname(host->mmc), host);
1519 if (ret)
1520 return ret;
1521
1522 sdhci_init(host);
1523 mmiowb();
1524
1525 ret = mmc_resume_host(host->mmc);
1526 if (ret)
1527 return ret;
1528
1529 return 0;
1530 }
1531
1532 EXPORT_SYMBOL_GPL(sdhci_resume_host);
1533
1534 #endif /* CONFIG_PM */
1535
1536 /*****************************************************************************\
1537 * *
1538 * Device allocation/registration *
1539 * *
1540 \*****************************************************************************/
1541
1542 struct sdhci_host *sdhci_alloc_host(struct device *dev,
1543 size_t priv_size)
1544 {
1545 struct mmc_host *mmc;
1546 struct sdhci_host *host;
1547
1548 WARN_ON(dev == NULL);
1549
1550 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
1551 if (!mmc)
1552 return ERR_PTR(-ENOMEM);
1553
1554 host = mmc_priv(mmc);
1555 host->mmc = mmc;
1556
1557 return host;
1558 }
1559
1560 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
1561
1562 int sdhci_add_host(struct sdhci_host *host)
1563 {
1564 struct mmc_host *mmc;
1565 unsigned int caps;
1566 int ret;
1567
1568 WARN_ON(host == NULL);
1569 if (host == NULL)
1570 return -EINVAL;
1571
1572 mmc = host->mmc;
1573
1574 if (debug_quirks)
1575 host->quirks = debug_quirks;
1576
1577 sdhci_reset(host, SDHCI_RESET_ALL);
1578
1579 host->version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1580 host->version = (host->version & SDHCI_SPEC_VER_MASK)
1581 >> SDHCI_SPEC_VER_SHIFT;
1582 if (host->version > SDHCI_SPEC_200) {
1583 printk(KERN_ERR "%s: Unknown controller version (%d). "
1584 "You may experience problems.\n", mmc_hostname(mmc),
1585 host->version);
1586 }
1587
1588 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1589
1590 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
1591 host->flags |= SDHCI_USE_DMA;
1592 else if (!(caps & SDHCI_CAN_DO_DMA))
1593 DBG("Controller doesn't have DMA capability\n");
1594 else
1595 host->flags |= SDHCI_USE_DMA;
1596
1597 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1598 (host->flags & SDHCI_USE_DMA)) {
1599 DBG("Disabling DMA as it is marked broken\n");
1600 host->flags &= ~SDHCI_USE_DMA;
1601 }
1602
1603 if (host->flags & SDHCI_USE_DMA) {
1604 if ((host->version >= SDHCI_SPEC_200) &&
1605 (caps & SDHCI_CAN_DO_ADMA2))
1606 host->flags |= SDHCI_USE_ADMA;
1607 }
1608
1609 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
1610 (host->flags & SDHCI_USE_ADMA)) {
1611 DBG("Disabling ADMA as it is marked broken\n");
1612 host->flags &= ~SDHCI_USE_ADMA;
1613 }
1614
1615 if (host->flags & SDHCI_USE_DMA) {
1616 if (host->ops->enable_dma) {
1617 if (host->ops->enable_dma(host)) {
1618 printk(KERN_WARNING "%s: No suitable DMA "
1619 "available. Falling back to PIO.\n",
1620 mmc_hostname(mmc));
1621 host->flags &= ~(SDHCI_USE_DMA | SDHCI_USE_ADMA);
1622 }
1623 }
1624 }
1625
1626 if (host->flags & SDHCI_USE_ADMA) {
1627 /*
1628 * We need to allocate descriptors for all sg entries
1629 * (128) and potentially one alignment transfer for
1630 * each of those entries.
1631 */
1632 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
1633 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
1634 if (!host->adma_desc || !host->align_buffer) {
1635 kfree(host->adma_desc);
1636 kfree(host->align_buffer);
1637 printk(KERN_WARNING "%s: Unable to allocate ADMA "
1638 "buffers. Falling back to standard DMA.\n",
1639 mmc_hostname(mmc));
1640 host->flags &= ~SDHCI_USE_ADMA;
1641 }
1642 }
1643
1644 /*
1645 * If we use DMA, then it's up to the caller to set the DMA
1646 * mask, but PIO does not need the hw shim so we set a new
1647 * mask here in that case.
1648 */
1649 if (!(host->flags & SDHCI_USE_DMA)) {
1650 host->dma_mask = DMA_BIT_MASK(64);
1651 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
1652 }
1653
1654 if (host->ops->get_max_clock)
1655 host->max_clk = host->ops->get_max_clock(host);
1656 else {
1657 host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1658 host->max_clk *= 1000000;
1659 }
1660 if (host->max_clk == 0) {
1661 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1662 "frequency.\n", mmc_hostname(mmc));
1663 return -ENODEV;
1664 }
1665
1666 if (host->ops->get_timeout_clock)
1667 host->timeout_clk = host->ops->get_timeout_clock(host);
1668 else
1669 host->timeout_clk =
1670 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1671 if (host->timeout_clk == 0) {
1672 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1673 "frequency.\n", mmc_hostname(mmc));
1674 return -ENODEV;
1675 }
1676 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1677 host->timeout_clk *= 1000;
1678
1679 /*
1680 * Set host parameters.
1681 */
1682 mmc->ops = &sdhci_ops;
1683 mmc->f_min = host->max_clk / 256;
1684 mmc->f_max = host->max_clk;
1685 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1686
1687 if ((caps & SDHCI_CAN_DO_HISPD) ||
1688 (host->quirks & SDHCI_QUIRK_FORCE_HIGHSPEED))
1689 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1690
1691 mmc->ocr_avail = 0;
1692 if (caps & SDHCI_CAN_VDD_330)
1693 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1694 if (caps & SDHCI_CAN_VDD_300)
1695 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1696 if (caps & SDHCI_CAN_VDD_180)
1697 mmc->ocr_avail |= MMC_VDD_165_195;
1698
1699 if (mmc->ocr_avail == 0) {
1700 printk(KERN_ERR "%s: Hardware doesn't report any "
1701 "support voltages.\n", mmc_hostname(mmc));
1702 return -ENODEV;
1703 }
1704
1705 spin_lock_init(&host->lock);
1706
1707 /*
1708 * Maximum number of segments. Depends on if the hardware
1709 * can do scatter/gather or not.
1710 */
1711 if (host->flags & SDHCI_USE_ADMA)
1712 mmc->max_hw_segs = 128;
1713 else if (host->flags & SDHCI_USE_DMA)
1714 mmc->max_hw_segs = 1;
1715 else /* PIO */
1716 mmc->max_hw_segs = 128;
1717 mmc->max_phys_segs = 128;
1718
1719 /*
1720 * Maximum number of sectors in one transfer. Limited by DMA boundary
1721 * size (512KiB).
1722 */
1723 mmc->max_req_size = 524288;
1724
1725 /*
1726 * Maximum segment size. Could be one segment with the maximum number
1727 * of bytes. When doing hardware scatter/gather, each entry cannot
1728 * be larger than 64 KiB though.
1729 */
1730 if (host->flags & SDHCI_USE_ADMA)
1731 mmc->max_seg_size = 65536;
1732 else
1733 mmc->max_seg_size = mmc->max_req_size;
1734
1735 /*
1736 * Maximum block size. This varies from controller to controller and
1737 * is specified in the capabilities register.
1738 */
1739 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1740 if (mmc->max_blk_size >= 3) {
1741 printk(KERN_WARNING "%s: Invalid maximum block size, "
1742 "assuming 512 bytes\n", mmc_hostname(mmc));
1743 mmc->max_blk_size = 512;
1744 } else
1745 mmc->max_blk_size = 512 << mmc->max_blk_size;
1746
1747 /*
1748 * Maximum block count.
1749 */
1750 mmc->max_blk_count = 65535;
1751
1752 /*
1753 * Init tasklets.
1754 */
1755 tasklet_init(&host->card_tasklet,
1756 sdhci_tasklet_card, (unsigned long)host);
1757 tasklet_init(&host->finish_tasklet,
1758 sdhci_tasklet_finish, (unsigned long)host);
1759
1760 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1761
1762 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1763 mmc_hostname(mmc), host);
1764 if (ret)
1765 goto untasklet;
1766
1767 sdhci_init(host);
1768
1769 #ifdef CONFIG_MMC_DEBUG
1770 sdhci_dumpregs(host);
1771 #endif
1772
1773 #ifdef CONFIG_LEDS_CLASS
1774 host->led.name = mmc_hostname(mmc);
1775 host->led.brightness = LED_OFF;
1776 host->led.default_trigger = mmc_hostname(mmc);
1777 host->led.brightness_set = sdhci_led_control;
1778
1779 ret = led_classdev_register(mmc_dev(mmc), &host->led);
1780 if (ret)
1781 goto reset;
1782 #endif
1783
1784 mmiowb();
1785
1786 mmc_add_host(mmc);
1787
1788 printk(KERN_INFO "%s: SDHCI controller on %s [%s] using %s%s\n",
1789 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
1790 (host->flags & SDHCI_USE_ADMA)?"A":"",
1791 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1792
1793 return 0;
1794
1795 #ifdef CONFIG_LEDS_CLASS
1796 reset:
1797 sdhci_reset(host, SDHCI_RESET_ALL);
1798 free_irq(host->irq, host);
1799 #endif
1800 untasklet:
1801 tasklet_kill(&host->card_tasklet);
1802 tasklet_kill(&host->finish_tasklet);
1803
1804 return ret;
1805 }
1806
1807 EXPORT_SYMBOL_GPL(sdhci_add_host);
1808
1809 void sdhci_remove_host(struct sdhci_host *host, int dead)
1810 {
1811 unsigned long flags;
1812
1813 if (dead) {
1814 spin_lock_irqsave(&host->lock, flags);
1815
1816 host->flags |= SDHCI_DEVICE_DEAD;
1817
1818 if (host->mrq) {
1819 printk(KERN_ERR "%s: Controller removed during "
1820 " transfer!\n", mmc_hostname(host->mmc));
1821
1822 host->mrq->cmd->error = -ENOMEDIUM;
1823 tasklet_schedule(&host->finish_tasklet);
1824 }
1825
1826 spin_unlock_irqrestore(&host->lock, flags);
1827 }
1828
1829 mmc_remove_host(host->mmc);
1830
1831 #ifdef CONFIG_LEDS_CLASS
1832 led_classdev_unregister(&host->led);
1833 #endif
1834
1835 if (!dead)
1836 sdhci_reset(host, SDHCI_RESET_ALL);
1837
1838 free_irq(host->irq, host);
1839
1840 del_timer_sync(&host->timer);
1841
1842 tasklet_kill(&host->card_tasklet);
1843 tasklet_kill(&host->finish_tasklet);
1844
1845 kfree(host->adma_desc);
1846 kfree(host->align_buffer);
1847
1848 host->adma_desc = NULL;
1849 host->align_buffer = NULL;
1850 }
1851
1852 EXPORT_SYMBOL_GPL(sdhci_remove_host);
1853
1854 void sdhci_free_host(struct sdhci_host *host)
1855 {
1856 mmc_free_host(host->mmc);
1857 }
1858
1859 EXPORT_SYMBOL_GPL(sdhci_free_host);
1860
1861 /*****************************************************************************\
1862 * *
1863 * Driver init/exit *
1864 * *
1865 \*****************************************************************************/
1866
1867 static int __init sdhci_drv_init(void)
1868 {
1869 printk(KERN_INFO DRIVER_NAME
1870 ": Secure Digital Host Controller Interface driver\n");
1871 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1872
1873 return 0;
1874 }
1875
1876 static void __exit sdhci_drv_exit(void)
1877 {
1878 }
1879
1880 module_init(sdhci_drv_init);
1881 module_exit(sdhci_drv_exit);
1882
1883 module_param(debug_quirks, uint, 0444);
1884
1885 MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1886 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
1887 MODULE_LICENSE("GPL");
1888
1889 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
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