include/asm-arm/arch-omap/dma.h

   1 /*
   2  *  linux/include/asm-arm/arch-omap/dma.h
   3  *
   4  *  Copyright (C) 2003 Nokia Corporation
   5  *  Author: Juha Yrjölä <juha.yrjola@nokia.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20  */
  21 #ifndef __ASM_ARCH_DMA_H
  22 #define __ASM_ARCH_DMA_H
  23
  24 /* Hardware registers for omap1 */
  25 #define OMAP_DMA_BASE                   (0xfffed800)
  26 #define OMAP_DMA_GCR                    (OMAP_DMA_BASE + 0x400)
  27 #define OMAP_DMA_GSCR                   (OMAP_DMA_BASE + 0x404)
  28 #define OMAP_DMA_GRST                   (OMAP_DMA_BASE + 0x408)
  29 #define OMAP_DMA_HW_ID                  (OMAP_DMA_BASE + 0x442)
  30 #define OMAP_DMA_PCH2_ID                (OMAP_DMA_BASE + 0x444)
  31 #define OMAP_DMA_PCH0_ID                (OMAP_DMA_BASE + 0x446)
  32 #define OMAP_DMA_PCH1_ID                (OMAP_DMA_BASE + 0x448)
  33 #define OMAP_DMA_PCHG_ID                (OMAP_DMA_BASE + 0x44a)
  34 #define OMAP_DMA_PCHD_ID                (OMAP_DMA_BASE + 0x44c)
  35 #define OMAP_DMA_CAPS_0_U               (OMAP_DMA_BASE + 0x44e)
  36 #define OMAP_DMA_CAPS_0_L               (OMAP_DMA_BASE + 0x450)
  37 #define OMAP_DMA_CAPS_1_U               (OMAP_DMA_BASE + 0x452)
  38 #define OMAP_DMA_CAPS_1_L               (OMAP_DMA_BASE + 0x454)
  39 #define OMAP_DMA_CAPS_2                 (OMAP_DMA_BASE + 0x456)
  40 #define OMAP_DMA_CAPS_3                 (OMAP_DMA_BASE + 0x458)
  41 #define OMAP_DMA_CAPS_4                 (OMAP_DMA_BASE + 0x45a)
  42 #define OMAP_DMA_PCH2_SR                (OMAP_DMA_BASE + 0x460)
  43 #define OMAP_DMA_PCH0_SR                (OMAP_DMA_BASE + 0x480)
  44 #define OMAP_DMA_PCH1_SR                (OMAP_DMA_BASE + 0x482)
  45 #define OMAP_DMA_PCHD_SR                (OMAP_DMA_BASE + 0x4c0)
  46
  47 /* Hardware registers for omap2 */
  48 #if defined(CONFIG_ARCH_OMAP3)
  49 #define OMAP_DMA4_BASE                  (L4_34XX_BASE + 0x56000)
  50 #else   /* CONFIG_ARCH_OMAP2 */
  51 #define OMAP_DMA4_BASE                  (L4_24XX_BASE + 0x56000)
  52 #endif
  53
  54 #define OMAP_DMA4_REVISION              (OMAP_DMA4_BASE + 0x00)
  55 #define OMAP_DMA4_GCR_REG               (OMAP_DMA4_BASE + 0x78)
  56 #define OMAP_DMA4_IRQSTATUS_L0          (OMAP_DMA4_BASE + 0x08)
  57 #define OMAP_DMA4_IRQSTATUS_L1          (OMAP_DMA4_BASE + 0x0c)
  58 #define OMAP_DMA4_IRQSTATUS_L2          (OMAP_DMA4_BASE + 0x10)
  59 #define OMAP_DMA4_IRQSTATUS_L3          (OMAP_DMA4_BASE + 0x14)
  60 #define OMAP_DMA4_IRQENABLE_L0          (OMAP_DMA4_BASE + 0x18)
  61 #define OMAP_DMA4_IRQENABLE_L1          (OMAP_DMA4_BASE + 0x1c)
  62 #define OMAP_DMA4_IRQENABLE_L2          (OMAP_DMA4_BASE + 0x20)
  63 #define OMAP_DMA4_IRQENABLE_L3          (OMAP_DMA4_BASE + 0x24)
  64 #define OMAP_DMA4_SYSSTATUS             (OMAP_DMA4_BASE + 0x28)
  65 #define OMAP_DMA4_OCP_SYSCONFIG         (OMAP_DMA4_BASE + 0x2c)
  66 #define OMAP_DMA4_CAPS_0                (OMAP_DMA4_BASE + 0x64)
  67 #define OMAP_DMA4_CAPS_2                (OMAP_DMA4_BASE + 0x6c)
  68 #define OMAP_DMA4_CAPS_3                (OMAP_DMA4_BASE + 0x70)
  69 #define OMAP_DMA4_CAPS_4                (OMAP_DMA4_BASE + 0x74)
  70
  71 #ifdef CONFIG_ARCH_OMAP1
  72
  73 #define OMAP_LOGICAL_DMA_CH_COUNT       17
  74
  75 /* Common channel specific registers for omap1 */
  76 #define OMAP_DMA_CSDP_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x00)
  77 #define OMAP_DMA_CCR_REG(n)             __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x02)
  78 #define OMAP_DMA_CICR_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x04)
  79 #define OMAP_DMA_CSR_REG(n)             __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x06)
  80 #define OMAP_DMA_CEN_REG(n)             __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x10)
  81 #define OMAP_DMA_CFN_REG(n)             __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x12)
  82 #define OMAP_DMA_CSFI_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x14)
  83 #define OMAP_DMA_CSEI_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x16)
  84 #define OMAP_DMA_CSAC_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x18)
  85 #define OMAP_DMA_CDAC_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1a)
  86 #define OMAP_DMA_CDEI_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1c)
  87 #define OMAP_DMA_CDFI_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1e)
  88 #define OMAP_DMA_CLNK_CTRL_REG(n)       __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x28)
  89
  90 #else
  91
  92 #define OMAP_LOGICAL_DMA_CH_COUNT       32      /* REVISIT: Is this 32 + 2? */
  93
  94 /* Common channel specific registers for omap2 */
  95 #define OMAP_DMA_CCR_REG(n)             __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x80)
  96 #define OMAP_DMA_CLNK_CTRL_REG(n)       __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x84)
  97 #define OMAP_DMA_CICR_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x88)
  98 #define OMAP_DMA_CSR_REG(n)             __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x8c)
  99 #define OMAP_DMA_CSDP_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x90)
 100 #define OMAP_DMA_CEN_REG(n)             __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x94)
 101 #define OMAP_DMA_CFN_REG(n)             __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x98)
 102 #define OMAP_DMA_CSEI_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa4)
 103 #define OMAP_DMA_CSFI_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa8)
 104 #define OMAP_DMA_CDEI_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xac)
 105 #define OMAP_DMA_CDFI_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb0)
 106 #define OMAP_DMA_CSAC_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb4)
 107 #define OMAP_DMA_CDAC_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb8)
 108
 109 #endif
 110
 111 /* Channel specific registers only on omap1 */
 112 #define OMAP1_DMA_CSSA_L_REG(n)         __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x08)
 113 #define OMAP1_DMA_CSSA_U_REG(n)         __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0a)
 114 #define OMAP1_DMA_CDSA_L_REG(n)         __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0c)
 115 #define OMAP1_DMA_CDSA_U_REG(n)         __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0e)
 116 #define OMAP1_DMA_COLOR_L_REG(n)        __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x20)
 117 #define OMAP1_DMA_CCR2_REG(n)           __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x24)
 118 #define OMAP1_DMA_COLOR_U_REG(n)        __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x22)
 119 #define OMAP1_DMA_LCH_CTRL_REG(n)       __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
 120
 121 /* Channel specific registers only on omap2 */
 122 #define OMAP2_DMA_CSSA_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x9c)
 123 #define OMAP2_DMA_CDSA_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa0)
 124 #define OMAP2_DMA_CCEN_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xbc)
 125 #define OMAP2_DMA_CCFN_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc0)
 126 #define OMAP2_DMA_COLOR_REG(n)          __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc4)
 127
 128 /*----------------------------------------------------------------------------*/
 129
 130 /* DMA channels for omap1 */
 131 #define OMAP_DMA_NO_DEVICE              0
 132 #define OMAP_DMA_MCSI1_TX               1
 133 #define OMAP_DMA_MCSI1_RX               2
 134 #define OMAP_DMA_I2C_RX                 3
 135 #define OMAP_DMA_I2C_TX                 4
 136 #define OMAP_DMA_EXT_NDMA_REQ           5
 137 #define OMAP_DMA_EXT_NDMA_REQ2          6
 138 #define OMAP_DMA_UWIRE_TX               7
 139 #define OMAP_DMA_MCBSP1_TX              8
 140 #define OMAP_DMA_MCBSP1_RX              9
 141 #define OMAP_DMA_MCBSP3_TX              10
 142 #define OMAP_DMA_MCBSP3_RX              11
 143 #define OMAP_DMA_UART1_TX               12
 144 #define OMAP_DMA_UART1_RX               13
 145 #define OMAP_DMA_UART2_TX               14
 146 #define OMAP_DMA_UART2_RX               15
 147 #define OMAP_DMA_MCBSP2_TX              16
 148 #define OMAP_DMA_MCBSP2_RX              17
 149 #define OMAP_DMA_UART3_TX               18
 150 #define OMAP_DMA_UART3_RX               19
 151 #define OMAP_DMA_CAMERA_IF_RX           20
 152 #define OMAP_DMA_MMC_TX                 21
 153 #define OMAP_DMA_MMC_RX                 22
 154 #define OMAP_DMA_NAND                   23
 155 #define OMAP_DMA_IRQ_LCD_LINE           24
 156 #define OMAP_DMA_MEMORY_STICK           25
 157 #define OMAP_DMA_USB_W2FC_RX0           26
 158 #define OMAP_DMA_USB_W2FC_RX1           27
 159 #define OMAP_DMA_USB_W2FC_RX2           28
 160 #define OMAP_DMA_USB_W2FC_TX0           29
 161 #define OMAP_DMA_USB_W2FC_TX1           30
 162 #define OMAP_DMA_USB_W2FC_TX2           31
 163
 164 /* These are only for 1610 */
 165 #define OMAP_DMA_CRYPTO_DES_IN          32
 166 #define OMAP_DMA_SPI_TX                 33
 167 #define OMAP_DMA_SPI_RX                 34
 168 #define OMAP_DMA_CRYPTO_HASH            35
 169 #define OMAP_DMA_CCP_ATTN               36
 170 #define OMAP_DMA_CCP_FIFO_NOT_EMPTY     37
 171 #define OMAP_DMA_CMT_APE_TX_CHAN_0      38
 172 #define OMAP_DMA_CMT_APE_RV_CHAN_0      39
 173 #define OMAP_DMA_CMT_APE_TX_CHAN_1      40
 174 #define OMAP_DMA_CMT_APE_RV_CHAN_1      41
 175 #define OMAP_DMA_CMT_APE_TX_CHAN_2      42
 176 #define OMAP_DMA_CMT_APE_RV_CHAN_2      43
 177 #define OMAP_DMA_CMT_APE_TX_CHAN_3      44
 178 #define OMAP_DMA_CMT_APE_RV_CHAN_3      45
 179 #define OMAP_DMA_CMT_APE_TX_CHAN_4      46
 180 #define OMAP_DMA_CMT_APE_RV_CHAN_4      47
 181 #define OMAP_DMA_CMT_APE_TX_CHAN_5      48
 182 #define OMAP_DMA_CMT_APE_RV_CHAN_5      49
 183 #define OMAP_DMA_CMT_APE_TX_CHAN_6      50
 184 #define OMAP_DMA_CMT_APE_RV_CHAN_6      51
 185 #define OMAP_DMA_CMT_APE_TX_CHAN_7      52
 186 #define OMAP_DMA_CMT_APE_RV_CHAN_7      53
 187 #define OMAP_DMA_MMC2_TX                54
 188 #define OMAP_DMA_MMC2_RX                55
 189 #define OMAP_DMA_CRYPTO_DES_OUT         56
 190
 191 /* DMA channels for 24xx */
 192 #define OMAP24XX_DMA_NO_DEVICE          0
 193 #define OMAP24XX_DMA_XTI_DMA            1       /* S_DMA_0 */
 194 #define OMAP24XX_DMA_EXT_DMAREQ0        2       /* S_DMA_1 */
 195 #define OMAP24XX_DMA_EXT_DMAREQ1        3       /* S_DMA_2 */
 196 #define OMAP24XX_DMA_GPMC               4       /* S_DMA_3 */
 197 #define OMAP24XX_DMA_GFX                5       /* S_DMA_4 */
 198 #define OMAP24XX_DMA_DSS                6       /* S_DMA_5 */
 199 #define OMAP24XX_DMA_VLYNQ_TX           7       /* S_DMA_6 */
 200 #define OMAP24XX_DMA_CWT                8       /* S_DMA_7 */
 201 #define OMAP24XX_DMA_AES_TX             9       /* S_DMA_8 */
 202 #define OMAP24XX_DMA_AES_RX             10      /* S_DMA_9 */
 203 #define OMAP24XX_DMA_DES_TX             11      /* S_DMA_10 */
 204 #define OMAP24XX_DMA_DES_RX             12      /* S_DMA_11 */
 205 #define OMAP24XX_DMA_SHA1MD5_RX         13      /* S_DMA_12 */
 206 #define OMAP24XX_DMA_EXT_DMAREQ2        14      /* S_DMA_13 */
 207 #define OMAP24XX_DMA_EXT_DMAREQ3        15      /* S_DMA_14 */
 208 #define OMAP24XX_DMA_EXT_DMAREQ4        16      /* S_DMA_15 */
 209 #define OMAP24XX_DMA_EAC_AC_RD          17      /* S_DMA_16 */
 210 #define OMAP24XX_DMA_EAC_AC_WR          18      /* S_DMA_17 */
 211 #define OMAP24XX_DMA_EAC_MD_UL_RD       19      /* S_DMA_18 */
 212 #define OMAP24XX_DMA_EAC_MD_UL_WR       20      /* S_DMA_19 */
 213 #define OMAP24XX_DMA_EAC_MD_DL_RD       21      /* S_DMA_20 */
 214 #define OMAP24XX_DMA_EAC_MD_DL_WR       22      /* S_DMA_21 */
 215 #define OMAP24XX_DMA_EAC_BT_UL_RD       23      /* S_DMA_22 */
 216 #define OMAP24XX_DMA_EAC_BT_UL_WR       24      /* S_DMA_23 */
 217 #define OMAP24XX_DMA_EAC_BT_DL_RD       25      /* S_DMA_24 */
 218 #define OMAP24XX_DMA_EAC_BT_DL_WR       26      /* S_DMA_25 */
 219 #define OMAP24XX_DMA_I2C1_TX            27      /* S_DMA_26 */
 220 #define OMAP24XX_DMA_I2C1_RX            28      /* S_DMA_27 */
 221 #define OMAP24XX_DMA_I2C2_TX            29      /* S_DMA_28 */
 222 #define OMAP24XX_DMA_I2C2_RX            30      /* S_DMA_29 */
 223 #define OMAP24XX_DMA_MCBSP1_TX          31      /* SDMA_30 */
 224 #define OMAP24XX_DMA_MCBSP1_RX          32      /* SDMA_31 */
 225 #define OMAP24XX_DMA_MCBSP2_TX          33      /* SDMA_32 */
 226 #define OMAP24XX_DMA_MCBSP2_RX          34      /* SDMA_33 */
 227 #define OMAP24XX_DMA_SPI1_TX0           35      /* SDMA_34 */
 228 #define OMAP24XX_DMA_SPI1_RX0           36      /* SDMA_35 */
 229 #define OMAP24XX_DMA_SPI1_TX1           37      /* SDMA_36 */
 230 #define OMAP24XX_DMA_SPI1_RX1           38      /* SDMA_37 */
 231 #define OMAP24XX_DMA_SPI1_TX2           39      /* SDMA_38 */
 232 #define OMAP24XX_DMA_SPI1_RX2           40      /* SDMA_39 */
 233 #define OMAP24XX_DMA_SPI1_TX3           41      /* SDMA_40 */
 234 #define OMAP24XX_DMA_SPI1_RX3           42      /* SDMA_41 */
 235 #define OMAP24XX_DMA_SPI2_TX0           43      /* SDMA_42 */
 236 #define OMAP24XX_DMA_SPI2_RX0           44      /* SDMA_43 */
 237 #define OMAP24XX_DMA_SPI2_TX1           45      /* SDMA_44 */
 238 #define OMAP24XX_DMA_SPI2_RX1           46      /* SDMA_45 */
 239
 240 #define OMAP24XX_DMA_UART1_TX           49      /* SDMA_48 */
 241 #define OMAP24XX_DMA_UART1_RX           50      /* SDMA_49 */
 242 #define OMAP24XX_DMA_UART2_TX           51      /* SDMA_50 */
 243 #define OMAP24XX_DMA_UART2_RX           52      /* SDMA_51 */
 244 #define OMAP24XX_DMA_UART3_TX           53      /* SDMA_52 */
 245 #define OMAP24XX_DMA_UART3_RX           54      /* SDMA_53 */
 246 #define OMAP24XX_DMA_USB_W2FC_TX0       55      /* SDMA_54 */
 247 #define OMAP24XX_DMA_USB_W2FC_RX0       56      /* SDMA_55 */
 248 #define OMAP24XX_DMA_USB_W2FC_TX1       57      /* SDMA_56 */
 249 #define OMAP24XX_DMA_USB_W2FC_RX1       58      /* SDMA_57 */
 250 #define OMAP24XX_DMA_USB_W2FC_TX2       59      /* SDMA_58 */
 251 #define OMAP24XX_DMA_USB_W2FC_RX2       60      /* SDMA_59 */
 252 #define OMAP24XX_DMA_MMC1_TX            61      /* SDMA_60 */
 253 #define OMAP24XX_DMA_MMC1_RX            62      /* SDMA_61 */
 254 #define OMAP24XX_DMA_MS                 63      /* SDMA_62 */
 255 #define OMAP24XX_DMA_EXT_DMAREQ5        64      /* S_DMA_63 */
 256
 257 /*----------------------------------------------------------------------------*/
 258
 259 /* Hardware registers for LCD DMA */
 260 #define OMAP1510_DMA_LCD_BASE           (0xfffedb00)
 261 #define OMAP1510_DMA_LCD_CTRL           (OMAP1510_DMA_LCD_BASE + 0x00)
 262 #define OMAP1510_DMA_LCD_TOP_F1_L       (OMAP1510_DMA_LCD_BASE + 0x02)
 263 #define OMAP1510_DMA_LCD_TOP_F1_U       (OMAP1510_DMA_LCD_BASE + 0x04)
 264 #define OMAP1510_DMA_LCD_BOT_F1_L       (OMAP1510_DMA_LCD_BASE + 0x06)
 265 #define OMAP1510_DMA_LCD_BOT_F1_U       (OMAP1510_DMA_LCD_BASE + 0x08)
 266
 267 #define OMAP1610_DMA_LCD_BASE           (0xfffee300)
 268 #define OMAP1610_DMA_LCD_CSDP           (OMAP1610_DMA_LCD_BASE + 0xc0)
 269 #define OMAP1610_DMA_LCD_CCR            (OMAP1610_DMA_LCD_BASE + 0xc2)
 270 #define OMAP1610_DMA_LCD_CTRL           (OMAP1610_DMA_LCD_BASE + 0xc4)
 271 #define OMAP1610_DMA_LCD_TOP_B1_L       (OMAP1610_DMA_LCD_BASE + 0xc8)
 272 #define OMAP1610_DMA_LCD_TOP_B1_U       (OMAP1610_DMA_LCD_BASE + 0xca)
 273 #define OMAP1610_DMA_LCD_BOT_B1_L       (OMAP1610_DMA_LCD_BASE + 0xcc)
 274 #define OMAP1610_DMA_LCD_BOT_B1_U       (OMAP1610_DMA_LCD_BASE + 0xce)
 275 #define OMAP1610_DMA_LCD_TOP_B2_L       (OMAP1610_DMA_LCD_BASE + 0xd0)
 276 #define OMAP1610_DMA_LCD_TOP_B2_U       (OMAP1610_DMA_LCD_BASE + 0xd2)
 277 #define OMAP1610_DMA_LCD_BOT_B2_L       (OMAP1610_DMA_LCD_BASE + 0xd4)
 278 #define OMAP1610_DMA_LCD_BOT_B2_U       (OMAP1610_DMA_LCD_BASE + 0xd6)
 279 #define OMAP1610_DMA_LCD_SRC_EI_B1      (OMAP1610_DMA_LCD_BASE + 0xd8)
 280 #define OMAP1610_DMA_LCD_SRC_FI_B1_L    (OMAP1610_DMA_LCD_BASE + 0xda)
 281 #define OMAP1610_DMA_LCD_SRC_EN_B1      (OMAP1610_DMA_LCD_BASE + 0xe0)
 282 #define OMAP1610_DMA_LCD_SRC_FN_B1      (OMAP1610_DMA_LCD_BASE + 0xe4)
 283 #define OMAP1610_DMA_LCD_LCH_CTRL       (OMAP1610_DMA_LCD_BASE + 0xea)
 284 #define OMAP1610_DMA_LCD_SRC_FI_B1_U    (OMAP1610_DMA_LCD_BASE + 0xf4)
 285
 286 #define OMAP1_DMA_TOUT_IRQ              (1 << 0)
 287 #define OMAP_DMA_DROP_IRQ               (1 << 1)
 288 #define OMAP_DMA_HALF_IRQ               (1 << 2)
 289 #define OMAP_DMA_FRAME_IRQ              (1 << 3)
 290 #define OMAP_DMA_LAST_IRQ               (1 << 4)
 291 #define OMAP_DMA_BLOCK_IRQ              (1 << 5)
 292 #define OMAP1_DMA_SYNC_IRQ              (1 << 6)
 293 #define OMAP2_DMA_PKT_IRQ               (1 << 7)
 294 #define OMAP2_DMA_TRANS_ERR_IRQ         (1 << 8)
 295 #define OMAP2_DMA_SECURE_ERR_IRQ        (1 << 9)
 296 #define OMAP2_DMA_SUPERVISOR_ERR_IRQ    (1 << 10)
 297 #define OMAP2_DMA_MISALIGNED_ERR_IRQ    (1 << 11)
 298
 299 #define OMAP_DMA_DATA_TYPE_S8           0x00
 300 #define OMAP_DMA_DATA_TYPE_S16          0x01
 301 #define OMAP_DMA_DATA_TYPE_S32          0x02
 302
 303 #define OMAP_DMA_SYNC_ELEMENT           0x00
 304 #define OMAP_DMA_SYNC_FRAME             0x01
 305 #define OMAP_DMA_SYNC_BLOCK             0x02
 306 #define OMAP_DMA_SYNC_PACKET            0x03
 307
 308 #define OMAP_DMA_SRC_SYNC               0x01
 309 #define OMAP_DMA_DST_SYNC               0x00
 310
 311 #define OMAP_DMA_PORT_EMIFF             0x00
 312 #define OMAP_DMA_PORT_EMIFS             0x01
 313 #define OMAP_DMA_PORT_OCP_T1            0x02
 314 #define OMAP_DMA_PORT_TIPB              0x03
 315 #define OMAP_DMA_PORT_OCP_T2            0x04
 316 #define OMAP_DMA_PORT_MPUI              0x05
 317
 318 #define OMAP_DMA_AMODE_CONSTANT         0x00
 319 #define OMAP_DMA_AMODE_POST_INC         0x01
 320 #define OMAP_DMA_AMODE_SINGLE_IDX       0x02
 321 #define OMAP_DMA_AMODE_DOUBLE_IDX       0x03
 322
 323 #define DMA_DEFAULT_FIFO_DEPTH          0x10
 324 #define DMA_DEFAULT_ARB_RATE            0x01
 325 /* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
 326 #define DMA_THREAD_RESERVE_NORM         (0x00 << 12) /* Def */
 327 #define DMA_THREAD_RESERVE_ONET         (0x01 << 12)
 328 #define DMA_THREAD_RESERVE_TWOT         (0x02 << 12)
 329 #define DMA_THREAD_RESERVE_THREET       (0x03 << 12)
 330 #define DMA_THREAD_FIFO_NONE            (0x00 << 14) /* Def */
 331 #define DMA_THREAD_FIFO_75              (0x01 << 14)
 332 #define DMA_THREAD_FIFO_25              (0x02 << 14)
 333 #define DMA_THREAD_FIFO_50              (0x03 << 14)
 334
 335 /* Chaining modes*/
 336 #ifndef CONFIG_ARCH_OMAP1
 337 #define OMAP_DMA_STATIC_CHAIN           0x1
 338 #define OMAP_DMA_DYNAMIC_CHAIN          0x2
 339 #define OMAP_DMA_CHAIN_ACTIVE           0x1
 340 #define OMAP_DMA_CHAIN_INACTIVE         0x0
 341 #endif
 342
 343 #define DMA_CH_PRIO_HIGH                0x1
 344 #define DMA_CH_PRIO_LOW                 0x0 /* Def */
 345
 346 /* LCD DMA block numbers */
 347 enum {
 348         OMAP_LCD_DMA_B1_TOP,
 349         OMAP_LCD_DMA_B1_BOTTOM,
 350         OMAP_LCD_DMA_B2_TOP,
 351         OMAP_LCD_DMA_B2_BOTTOM
 352 };
 353
 354 enum omap_dma_burst_mode {
 355         OMAP_DMA_DATA_BURST_DIS = 0,
 356         OMAP_DMA_DATA_BURST_4,
 357         OMAP_DMA_DATA_BURST_8,
 358         OMAP_DMA_DATA_BURST_16,
 359 };
 360
 361 enum omap_dma_color_mode {
 362         OMAP_DMA_COLOR_DIS = 0,
 363         OMAP_DMA_CONSTANT_FILL,
 364         OMAP_DMA_TRANSPARENT_COPY
 365 };
 366
 367 enum omap_dma_write_mode {
 368         OMAP_DMA_WRITE_NON_POSTED = 0,
 369         OMAP_DMA_WRITE_POSTED,
 370         OMAP_DMA_WRITE_LAST_NON_POSTED
 371 };
 372
 373 struct omap_dma_channel_params {
 374         int data_type;          /* data type 8,16,32 */
 375         int elem_count;         /* number of elements in a frame */
 376         int frame_count;        /* number of frames in a element */
 377
 378         int src_port;           /* Only on OMAP1 REVISIT: Is this needed? */
 379         int src_amode;          /* constant , post increment, indexed , double indexed */
 380         unsigned long src_start;        /* source address : physical */
 381         int src_ei;             /* source element index */
 382         int src_fi;             /* source frame index */
 383
 384         int dst_port;           /* Only on OMAP1 REVISIT: Is this needed? */
 385         int dst_amode;          /* constant , post increment, indexed , double indexed */
 386         unsigned long dst_start;        /* source address : physical */
 387         int dst_ei;             /* source element index */
 388         int dst_fi;             /* source frame index */
 389
 390         int trigger;            /* trigger attached if the channel is synchronized */
 391         int sync_mode;          /* sycn on element, frame , block or packet */
 392         int src_or_dst_synch;   /* source synch(1) or destination synch(0) */
 393
 394         int ie;                 /* interrupt enabled */
 395
 396         unsigned char read_prio;/* read priority */
 397         unsigned char write_prio;/* write priority */
 398
 399 #ifndef CONFIG_ARCH_OMAP1
 400         enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
 401 #endif
 402 };
 403
 404
 405 extern void omap_set_dma_priority(int lch, int dst_port, int priority);
 406 extern int omap_request_dma(int dev_id, const char *dev_name,
 407                             void (* callback)(int lch, u16 ch_status, void *data),
 408                             void *data, int *dma_ch);
 409 extern void omap_enable_dma_irq(int ch, u16 irq_bits);
 410 extern void omap_disable_dma_irq(int ch, u16 irq_bits);
 411 extern void omap_free_dma(int ch);
 412 extern void omap_start_dma(int lch);
 413 extern void omap_stop_dma(int lch);
 414 extern void omap_set_dma_transfer_params(int lch, int data_type,
 415                                          int elem_count, int frame_count,
 416                                          int sync_mode,
 417                                          int dma_trigger, int src_or_dst_synch);
 418 extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
 419                                     u32 color);
 420 extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
 421
 422 extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
 423                                     unsigned long src_start,
 424                                     int src_ei, int src_fi);
 425 extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
 426 extern void omap_set_dma_src_data_pack(int lch, int enable);
 427 extern void omap_set_dma_src_burst_mode(int lch,
 428                                         enum omap_dma_burst_mode burst_mode);
 429
 430 extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
 431                                      unsigned long dest_start,
 432                                      int dst_ei, int dst_fi);
 433 extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
 434 extern void omap_set_dma_dest_data_pack(int lch, int enable);
 435 extern void omap_set_dma_dest_burst_mode(int lch,
 436                                          enum omap_dma_burst_mode burst_mode);
 437
 438 extern void omap_set_dma_params(int lch,
 439                                 struct omap_dma_channel_params * params);
 440
 441 extern void omap_dma_link_lch (int lch_head, int lch_queue);
 442 extern void omap_dma_unlink_lch (int lch_head, int lch_queue);
 443
 444 extern int omap_set_dma_callback(int lch,
 445                         void (* callback)(int lch, u16 ch_status, void *data),
 446                         void *data);
 447 extern dma_addr_t omap_get_dma_src_pos(int lch);
 448 extern dma_addr_t omap_get_dma_dst_pos(int lch);
 449 extern int omap_get_dma_src_addr_counter(int lch);
 450 extern void omap_clear_dma(int lch);
 451 extern int omap_dma_running(void);
 452 extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
 453                                        int tparams);
 454 extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
 455                                  unsigned char write_prio);
 456
 457 /* Chaining APIs */
 458 #ifndef CONFIG_ARCH_OMAP1
 459 extern int omap_request_dma_chain(int dev_id, const char *dev_name,
 460                                   void (*callback) (int chain_id, u16 ch_status,
 461                                                     void *data),
 462                                   int *chain_id, int no_of_chans,
 463                                   int chain_mode,
 464                                   struct omap_dma_channel_params params);
 465 extern int omap_free_dma_chain(int chain_id);
 466 extern int omap_dma_chain_a_transfer(int chain_id, int src_start,
 467                                      int dest_start, int elem_count,
 468                                      int frame_count, void *callbk_data);
 469 extern int omap_start_dma_chain_transfers(int chain_id);
 470 extern int omap_stop_dma_chain_transfers(int chain_id);
 471 extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi);
 472 extern int omap_get_dma_chain_dst_pos(int chain_id);
 473 extern int omap_get_dma_chain_src_pos(int chain_id);
 474
 475 extern int omap_modify_dma_chain_params(int chain_id,
 476                                         struct omap_dma_channel_params params);
 477 extern int omap_dma_chain_status(int chain_id);
 478 #endif
 479
 480 /* LCD DMA functions */
 481 extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
 482                                 void *data);
 483 extern void omap_free_lcd_dma(void);
 484 extern void omap_setup_lcd_dma(void);
 485 extern void omap_enable_lcd_dma(void);
 486 extern void omap_stop_lcd_dma(void);
 487 extern void omap_set_lcd_dma_ext_controller(int external);
 488 extern void omap_set_lcd_dma_single_transfer(int single);
 489 extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
 490                                 int data_type);
 491 extern void omap_set_lcd_dma_b1_rotation(int rotate);
 492 extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres);
 493 extern void omap_set_lcd_dma_b1_mirror(int mirror);
 494 extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale);
 495
 496 #endif /* __ASM_ARCH_DMA_H */