2 * linux/arch/arm/mach-omap1/pm.c
4 * OMAP Power Management Routines
6 * Original code for the SA11x0:
7 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
9 * Modified for the PXA250 by Nicolas Pitre:
10 * Copyright (c) 2002 Monta Vista Software, Inc.
12 * Modified for the OMAP1510 by David Singleton:
13 * Copyright (c) 2002 Monta Vista Software, Inc.
15 * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the
19 * Free Software Foundation; either version 2 of the License, or (at your
20 * option) any later version.
22 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 * You should have received a copy of the GNU General Public License along
34 * with this program; if not, write to the Free Software Foundation, Inc.,
35 * 675 Mass Ave, Cambridge, MA 02139, USA.
38 #include <linux/suspend.h>
39 #include <linux/sched.h>
40 #include <linux/proc_fs.h>
41 #include <linux/interrupt.h>
42 #include <linux/sysfs.h>
43 #include <linux/module.h>
47 #include <asm/atomic.h>
48 #include <asm/mach/time.h>
49 #include <asm/mach/irq.h>
50 #include <asm/mach-types.h>
52 #include <asm/arch/cpu.h>
53 #include <asm/arch/irqs.h>
54 #include <asm/arch/clock.h>
55 #include <asm/arch/sram.h>
56 #include <asm/arch/tc.h>
57 #include <asm/arch/pm.h>
58 #include <asm/arch/mux.h>
59 #include <asm/arch/dma.h>
60 #include <asm/arch/dsp_common.h>
61 #include <asm/arch/dmtimer.h>
63 static unsigned int arm_sleep_save
[ARM_SLEEP_SAVE_SIZE
];
64 static unsigned short dsp_sleep_save
[DSP_SLEEP_SAVE_SIZE
];
65 static unsigned short ulpd_sleep_save
[ULPD_SLEEP_SAVE_SIZE
];
66 static unsigned int mpui730_sleep_save
[MPUI730_SLEEP_SAVE_SIZE
];
67 static unsigned int mpui1510_sleep_save
[MPUI1510_SLEEP_SAVE_SIZE
];
68 static unsigned int mpui1610_sleep_save
[MPUI1610_SLEEP_SAVE_SIZE
];
70 #ifdef CONFIG_OMAP_32K_TIMER
72 static unsigned short enable_dyn_sleep
= 1;
74 static ssize_t
idle_show(struct kobject
*kobj
, struct kobj_attribute
*attr
,
77 return sprintf(buf
, "%hu\n", enable_dyn_sleep
);
80 static ssize_t
idle_store(struct kobject
*kobj
, struct kobj_attribute
*attr
,
81 const char * buf
, size_t n
)
84 if (sscanf(buf
, "%hu", &value
) != 1 ||
85 (value
!= 0 && value
!= 1)) {
86 printk(KERN_ERR
"idle_sleep_store: Invalid value\n");
89 enable_dyn_sleep
= value
;
93 static struct kobj_attribute sleep_while_idle_attr
=
94 __ATTR(sleep_while_idle
, 0644, idle_show
, idle_store
);
98 static void (*omap_sram_idle
)(void) = NULL
;
99 static void (*omap_sram_suspend
)(unsigned long r0
, unsigned long r1
) = NULL
;
102 * Let's power down on idle, but only if we are really
103 * idle, because once we start down the path of
104 * going idle we continue to do idle even if we get
105 * a clock tick interrupt . .
107 void omap_pm_idle(void)
109 extern __u32 arm_idlect1_mask
;
110 __u32 use_idlect1
= arm_idlect1_mask
;
115 if (need_resched()) {
122 * Since an interrupt may set up a timer, we don't want to
123 * reprogram the hardware timer with interrupts enabled.
124 * Re-enable interrupts only after returning from idle.
126 timer_dyn_reprogram();
128 #ifdef CONFIG_OMAP_MPU_TIMER
129 #warning Enable 32kHz OS timer in order to allow sleep states in idle
130 use_idlect1
= use_idlect1
& ~(1 << 9);
133 while (enable_dyn_sleep
) {
135 #ifdef CONFIG_CBUS_TAHVO_USB
136 extern int vbus_active
;
137 /* Clock requirements? */
147 #ifdef CONFIG_OMAP_DM_TIMER
148 use_idlect1
= omap_dm_timer_modify_idlect_mask(use_idlect1
);
151 if (omap_dma_running())
152 use_idlect1
&= ~(1 << 6);
154 /* We should be able to remove the do_sleep variable and multiple
155 * tests above as soon as drivers, timer and DMA code have been fixed.
156 * Even the sleep block count should become obsolete. */
157 if ((use_idlect1
!= ~0) || !do_sleep
) {
159 __u32 saved_idlect1
= omap_readl(ARM_IDLECT1
);
160 if (cpu_is_omap15xx())
161 use_idlect1
&= OMAP1510_BIG_SLEEP_REQUEST
;
163 use_idlect1
&= OMAP1610_IDLECT1_SLEEP_VAL
;
164 omap_writel(use_idlect1
, ARM_IDLECT1
);
165 __asm__
volatile ("mcr p15, 0, r0, c7, c0, 4");
166 omap_writel(saved_idlect1
, ARM_IDLECT1
);
172 omap_sram_suspend(omap_readl(ARM_IDLECT1
),
173 omap_readl(ARM_IDLECT2
));
180 * Configuration of the wakeup event is board specific. For the
181 * moment we put it into this helper function. Later it may move
182 * to board specific files.
184 static void omap_pm_wakeup_setup(void)
187 u32 level2_wake
= OMAP_IRQ_BIT(INT_UART2
);
190 * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
191 * and the L2 wakeup interrupts: keypad and UART2. Note that the
192 * drivers must still separately call omap_set_gpio_wakeup() to
193 * wake up to a GPIO interrupt.
195 if (cpu_is_omap730())
196 level1_wake
= OMAP_IRQ_BIT(INT_730_GPIO_BANK1
) |
197 OMAP_IRQ_BIT(INT_730_IH2_IRQ
);
198 else if (cpu_is_omap15xx())
199 level1_wake
= OMAP_IRQ_BIT(INT_GPIO_BANK1
) |
200 OMAP_IRQ_BIT(INT_1510_IH2_IRQ
);
201 else if (cpu_is_omap16xx())
202 level1_wake
= OMAP_IRQ_BIT(INT_GPIO_BANK1
) |
203 OMAP_IRQ_BIT(INT_1610_IH2_IRQ
);
205 omap_writel(~level1_wake
, OMAP_IH1_MIR
);
207 if (cpu_is_omap730()) {
208 omap_writel(~level2_wake
, OMAP_IH2_0_MIR
);
209 omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ
) |
210 OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD
)),
212 } else if (cpu_is_omap15xx()) {
213 level2_wake
|= OMAP_IRQ_BIT(INT_KEYBOARD
);
214 omap_writel(~level2_wake
, OMAP_IH2_MIR
);
215 } else if (cpu_is_omap16xx()) {
216 level2_wake
|= OMAP_IRQ_BIT(INT_KEYBOARD
);
217 omap_writel(~level2_wake
, OMAP_IH2_0_MIR
);
219 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
220 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ
),
222 omap_writel(~0x0, OMAP_IH2_2_MIR
);
223 omap_writel(~0x0, OMAP_IH2_3_MIR
);
226 /* New IRQ agreement, recalculate in cascade order */
227 omap_writel(1, OMAP_IH2_CONTROL
);
228 omap_writel(1, OMAP_IH1_CONTROL
);
231 #define EN_DSPCK 13 /* ARM_CKCTL */
232 #define EN_APICK 6 /* ARM_IDLECT2 */
233 #define DSP_EN 1 /* ARM_RSTCT1 */
235 void omap_pm_suspend(void)
237 unsigned long arg0
= 0, arg1
= 0;
239 printk("PM: OMAP%x is trying to enter deep sleep...\n", system_rev
);
241 omap_serial_wake_trigger(1);
243 if (!cpu_is_omap15xx())
244 omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG
);
247 * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
254 * Step 2: save registers
256 * The omap is a strange/beautiful device. The caches, memory
257 * and register state are preserved across power saves.
258 * We have to save and restore very little register state to
261 * Save interrupt, MPUI, ARM and UPLD control registers.
264 if (cpu_is_omap730()) {
265 MPUI730_SAVE(OMAP_IH1_MIR
);
266 MPUI730_SAVE(OMAP_IH2_0_MIR
);
267 MPUI730_SAVE(OMAP_IH2_1_MIR
);
268 MPUI730_SAVE(MPUI_CTRL
);
269 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG
);
270 MPUI730_SAVE(MPUI_DSP_API_CONFIG
);
271 MPUI730_SAVE(EMIFS_CONFIG
);
272 MPUI730_SAVE(EMIFF_SDRAM_CONFIG
);
274 } else if (cpu_is_omap15xx()) {
275 MPUI1510_SAVE(OMAP_IH1_MIR
);
276 MPUI1510_SAVE(OMAP_IH2_MIR
);
277 MPUI1510_SAVE(MPUI_CTRL
);
278 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG
);
279 MPUI1510_SAVE(MPUI_DSP_API_CONFIG
);
280 MPUI1510_SAVE(EMIFS_CONFIG
);
281 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG
);
282 } else if (cpu_is_omap16xx()) {
283 MPUI1610_SAVE(OMAP_IH1_MIR
);
284 MPUI1610_SAVE(OMAP_IH2_0_MIR
);
285 MPUI1610_SAVE(OMAP_IH2_1_MIR
);
286 MPUI1610_SAVE(OMAP_IH2_2_MIR
);
287 MPUI1610_SAVE(OMAP_IH2_3_MIR
);
288 MPUI1610_SAVE(MPUI_CTRL
);
289 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG
);
290 MPUI1610_SAVE(MPUI_DSP_API_CONFIG
);
291 MPUI1610_SAVE(EMIFS_CONFIG
);
292 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG
);
296 ARM_SAVE(ARM_IDLECT1
);
297 ARM_SAVE(ARM_IDLECT2
);
298 if (!(cpu_is_omap15xx()))
299 ARM_SAVE(ARM_IDLECT3
);
300 ARM_SAVE(ARM_EWUPCT
);
301 ARM_SAVE(ARM_RSTCT1
);
302 ARM_SAVE(ARM_RSTCT2
);
304 ULPD_SAVE(ULPD_CLOCK_CTRL
);
305 ULPD_SAVE(ULPD_STATUS_REQ
);
307 /* (Step 3 removed - we now allow deep sleep by default) */
310 * Step 4: OMAP DSP Shutdown
314 omap_writew(omap_readw(ARM_RSTCT1
) & ~(1 << DSP_EN
), ARM_RSTCT1
);
316 /* shut down dsp_ck */
317 if (!cpu_is_omap730())
318 omap_writew(omap_readw(ARM_CKCTL
) & ~(1 << EN_DSPCK
), ARM_CKCTL
);
320 /* temporarily enabling api_ck to access DSP registers */
321 omap_writew(omap_readw(ARM_IDLECT2
) | 1 << EN_APICK
, ARM_IDLECT2
);
323 /* save DSP registers */
324 DSP_SAVE(DSP_IDLECT2
);
326 /* Stop all DSP domain clocks */
327 __raw_writew(0, DSP_IDLECT2
);
330 * Step 5: Wakeup Event Setup
333 omap_pm_wakeup_setup();
336 * Step 6: ARM and Traffic controller shutdown
339 /* disable ARM watchdog */
340 omap_writel(0x00F5, OMAP_WDT_TIMER_MODE
);
341 omap_writel(0x00A0, OMAP_WDT_TIMER_MODE
);
344 * Step 6b: ARM and Traffic controller shutdown
346 * Step 6 continues here. Prepare jump to power management
347 * assembly code in internal SRAM.
349 * Since the omap_cpu_suspend routine has been copied to
350 * SRAM, we'll do an indirect procedure call to it and pass the
351 * contents of arm_idlect1 and arm_idlect2 so it can restore
352 * them when it wakes up and it will return.
355 arg0
= arm_sleep_save
[ARM_SLEEP_SAVE_ARM_IDLECT1
];
356 arg1
= arm_sleep_save
[ARM_SLEEP_SAVE_ARM_IDLECT2
];
359 * Step 6c: ARM and Traffic controller shutdown
361 * Jump to assembly code. The processor will stay there
364 omap_sram_suspend(arg0
, arg1
);
367 * If we are here, processor is woken up!
374 /* again temporarily enabling api_ck to access DSP registers */
375 omap_writew(omap_readw(ARM_IDLECT2
) | 1 << EN_APICK
, ARM_IDLECT2
);
377 /* Restore DSP domain clocks */
378 DSP_RESTORE(DSP_IDLECT2
);
381 * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
384 if (!(cpu_is_omap15xx()))
385 ARM_RESTORE(ARM_IDLECT3
);
386 ARM_RESTORE(ARM_CKCTL
);
387 ARM_RESTORE(ARM_EWUPCT
);
388 ARM_RESTORE(ARM_RSTCT1
);
389 ARM_RESTORE(ARM_RSTCT2
);
390 ARM_RESTORE(ARM_SYSST
);
391 ULPD_RESTORE(ULPD_CLOCK_CTRL
);
392 ULPD_RESTORE(ULPD_STATUS_REQ
);
394 if (cpu_is_omap730()) {
395 MPUI730_RESTORE(EMIFS_CONFIG
);
396 MPUI730_RESTORE(EMIFF_SDRAM_CONFIG
);
397 MPUI730_RESTORE(OMAP_IH1_MIR
);
398 MPUI730_RESTORE(OMAP_IH2_0_MIR
);
399 MPUI730_RESTORE(OMAP_IH2_1_MIR
);
400 } else if (cpu_is_omap15xx()) {
401 MPUI1510_RESTORE(MPUI_CTRL
);
402 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG
);
403 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG
);
404 MPUI1510_RESTORE(EMIFS_CONFIG
);
405 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG
);
406 MPUI1510_RESTORE(OMAP_IH1_MIR
);
407 MPUI1510_RESTORE(OMAP_IH2_MIR
);
408 } else if (cpu_is_omap16xx()) {
409 MPUI1610_RESTORE(MPUI_CTRL
);
410 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG
);
411 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG
);
412 MPUI1610_RESTORE(EMIFS_CONFIG
);
413 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG
);
415 MPUI1610_RESTORE(OMAP_IH1_MIR
);
416 MPUI1610_RESTORE(OMAP_IH2_0_MIR
);
417 MPUI1610_RESTORE(OMAP_IH2_1_MIR
);
418 MPUI1610_RESTORE(OMAP_IH2_2_MIR
);
419 MPUI1610_RESTORE(OMAP_IH2_3_MIR
);
422 if (!cpu_is_omap15xx())
423 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG
);
426 * Re-enable interrupts
432 omap_serial_wake_trigger(0);
434 printk("PM: OMAP%x is re-starting from deep sleep...\n", system_rev
);
437 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
438 static int g_read_completed
;
441 * Read system PM registers for debugging
443 static int omap_pm_read_proc(
445 char **my_first_byte
,
451 int my_buffer_offset
= 0;
452 char * const my_base
= page_buffer
;
455 ARM_SAVE(ARM_IDLECT1
);
456 ARM_SAVE(ARM_IDLECT2
);
457 if (!(cpu_is_omap15xx()))
458 ARM_SAVE(ARM_IDLECT3
);
459 ARM_SAVE(ARM_EWUPCT
);
460 ARM_SAVE(ARM_RSTCT1
);
461 ARM_SAVE(ARM_RSTCT2
);
464 ULPD_SAVE(ULPD_IT_STATUS
);
465 ULPD_SAVE(ULPD_CLOCK_CTRL
);
466 ULPD_SAVE(ULPD_SOFT_REQ
);
467 ULPD_SAVE(ULPD_STATUS_REQ
);
468 ULPD_SAVE(ULPD_DPLL_CTRL
);
469 ULPD_SAVE(ULPD_POWER_CTRL
);
471 if (cpu_is_omap730()) {
472 MPUI730_SAVE(MPUI_CTRL
);
473 MPUI730_SAVE(MPUI_DSP_STATUS
);
474 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG
);
475 MPUI730_SAVE(MPUI_DSP_API_CONFIG
);
476 MPUI730_SAVE(EMIFF_SDRAM_CONFIG
);
477 MPUI730_SAVE(EMIFS_CONFIG
);
478 } else if (cpu_is_omap15xx()) {
479 MPUI1510_SAVE(MPUI_CTRL
);
480 MPUI1510_SAVE(MPUI_DSP_STATUS
);
481 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG
);
482 MPUI1510_SAVE(MPUI_DSP_API_CONFIG
);
483 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG
);
484 MPUI1510_SAVE(EMIFS_CONFIG
);
485 } else if (cpu_is_omap16xx()) {
486 MPUI1610_SAVE(MPUI_CTRL
);
487 MPUI1610_SAVE(MPUI_DSP_STATUS
);
488 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG
);
489 MPUI1610_SAVE(MPUI_DSP_API_CONFIG
);
490 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG
);
491 MPUI1610_SAVE(EMIFS_CONFIG
);
494 if (virtual_start
== 0) {
495 g_read_completed
= 0;
497 my_buffer_offset
+= sprintf(my_base
+ my_buffer_offset
,
498 "ARM_CKCTL_REG: 0x%-8x \n"
499 "ARM_IDLECT1_REG: 0x%-8x \n"
500 "ARM_IDLECT2_REG: 0x%-8x \n"
501 "ARM_IDLECT3_REG: 0x%-8x \n"
502 "ARM_EWUPCT_REG: 0x%-8x \n"
503 "ARM_RSTCT1_REG: 0x%-8x \n"
504 "ARM_RSTCT2_REG: 0x%-8x \n"
505 "ARM_SYSST_REG: 0x%-8x \n"
506 "ULPD_IT_STATUS_REG: 0x%-4x \n"
507 "ULPD_CLOCK_CTRL_REG: 0x%-4x \n"
508 "ULPD_SOFT_REQ_REG: 0x%-4x \n"
509 "ULPD_DPLL_CTRL_REG: 0x%-4x \n"
510 "ULPD_STATUS_REQ_REG: 0x%-4x \n"
511 "ULPD_POWER_CTRL_REG: 0x%-4x \n",
513 ARM_SHOW(ARM_IDLECT1
),
514 ARM_SHOW(ARM_IDLECT2
),
515 ARM_SHOW(ARM_IDLECT3
),
516 ARM_SHOW(ARM_EWUPCT
),
517 ARM_SHOW(ARM_RSTCT1
),
518 ARM_SHOW(ARM_RSTCT2
),
520 ULPD_SHOW(ULPD_IT_STATUS
),
521 ULPD_SHOW(ULPD_CLOCK_CTRL
),
522 ULPD_SHOW(ULPD_SOFT_REQ
),
523 ULPD_SHOW(ULPD_DPLL_CTRL
),
524 ULPD_SHOW(ULPD_STATUS_REQ
),
525 ULPD_SHOW(ULPD_POWER_CTRL
));
527 if (cpu_is_omap730()) {
528 my_buffer_offset
+= sprintf(my_base
+ my_buffer_offset
,
529 "MPUI730_CTRL_REG 0x%-8x \n"
530 "MPUI730_DSP_STATUS_REG: 0x%-8x \n"
531 "MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
532 "MPUI730_DSP_API_CONFIG_REG: 0x%-8x \n"
533 "MPUI730_SDRAM_CONFIG_REG: 0x%-8x \n"
534 "MPUI730_EMIFS_CONFIG_REG: 0x%-8x \n",
535 MPUI730_SHOW(MPUI_CTRL
),
536 MPUI730_SHOW(MPUI_DSP_STATUS
),
537 MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG
),
538 MPUI730_SHOW(MPUI_DSP_API_CONFIG
),
539 MPUI730_SHOW(EMIFF_SDRAM_CONFIG
),
540 MPUI730_SHOW(EMIFS_CONFIG
));
541 } else if (cpu_is_omap15xx()) {
542 my_buffer_offset
+= sprintf(my_base
+ my_buffer_offset
,
543 "MPUI1510_CTRL_REG 0x%-8x \n"
544 "MPUI1510_DSP_STATUS_REG: 0x%-8x \n"
545 "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
546 "MPUI1510_DSP_API_CONFIG_REG: 0x%-8x \n"
547 "MPUI1510_SDRAM_CONFIG_REG: 0x%-8x \n"
548 "MPUI1510_EMIFS_CONFIG_REG: 0x%-8x \n",
549 MPUI1510_SHOW(MPUI_CTRL
),
550 MPUI1510_SHOW(MPUI_DSP_STATUS
),
551 MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG
),
552 MPUI1510_SHOW(MPUI_DSP_API_CONFIG
),
553 MPUI1510_SHOW(EMIFF_SDRAM_CONFIG
),
554 MPUI1510_SHOW(EMIFS_CONFIG
));
555 } else if (cpu_is_omap16xx()) {
556 my_buffer_offset
+= sprintf(my_base
+ my_buffer_offset
,
557 "MPUI1610_CTRL_REG 0x%-8x \n"
558 "MPUI1610_DSP_STATUS_REG: 0x%-8x \n"
559 "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
560 "MPUI1610_DSP_API_CONFIG_REG: 0x%-8x \n"
561 "MPUI1610_SDRAM_CONFIG_REG: 0x%-8x \n"
562 "MPUI1610_EMIFS_CONFIG_REG: 0x%-8x \n",
563 MPUI1610_SHOW(MPUI_CTRL
),
564 MPUI1610_SHOW(MPUI_DSP_STATUS
),
565 MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG
),
566 MPUI1610_SHOW(MPUI_DSP_API_CONFIG
),
567 MPUI1610_SHOW(EMIFF_SDRAM_CONFIG
),
568 MPUI1610_SHOW(EMIFS_CONFIG
));
572 } else if (g_read_completed
>= 1) {
578 *my_first_byte
= page_buffer
;
579 return my_buffer_offset
;
582 static void omap_pm_init_proc(void)
584 struct proc_dir_entry
*entry
;
586 entry
= create_proc_read_entry("driver/omap_pm",
587 S_IWUSR
| S_IRUGO
, NULL
,
588 omap_pm_read_proc
, NULL
);
591 #endif /* DEBUG && CONFIG_PROC_FS */
593 static void (*saved_idle
)(void) = NULL
;
596 * omap_pm_prepare - Do preliminary suspend work.
599 static int omap_pm_prepare(void)
601 /* We cannot sleep in idle until we have resumed */
602 saved_idle
= pm_idle
;
610 * omap_pm_enter - Actually enter a sleep state.
611 * @state: State we're entering.
615 static int omap_pm_enter(suspend_state_t state
)
619 case PM_SUSPEND_STANDBY
:
632 * omap_pm_finish - Finish up suspend sequence.
634 * This is called after we wake back up (or if entering the sleep state
638 static void omap_pm_finish(void)
640 pm_idle
= saved_idle
;
644 static irqreturn_t
omap_wakeup_interrupt(int irq
, void *dev
)
649 static struct irqaction omap_wakeup_irq
= {
650 .name
= "peripheral wakeup",
651 .flags
= IRQF_DISABLED
,
652 .handler
= omap_wakeup_interrupt
657 static struct platform_suspend_ops omap_pm_ops
={
658 .prepare
= omap_pm_prepare
,
659 .enter
= omap_pm_enter
,
660 .finish
= omap_pm_finish
,
661 .valid
= suspend_valid_only_mem
,
664 static int __init
omap_pm_init(void)
667 #ifdef CONFIG_OMAP_32K_TIMER
671 printk("Power Management for TI OMAP.\n");
674 * We copy the assembler sleep/wakeup routines to SRAM.
675 * These routines need to be in SRAM as that's the only
676 * memory the MPU can see when it wakes up.
678 if (cpu_is_omap730()) {
679 omap_sram_idle
= omap_sram_push(omap730_idle_loop_suspend
,
680 omap730_idle_loop_suspend_sz
);
681 omap_sram_suspend
= omap_sram_push(omap730_cpu_suspend
,
682 omap730_cpu_suspend_sz
);
683 } else if (cpu_is_omap15xx()) {
684 omap_sram_idle
= omap_sram_push(omap1510_idle_loop_suspend
,
685 omap1510_idle_loop_suspend_sz
);
686 omap_sram_suspend
= omap_sram_push(omap1510_cpu_suspend
,
687 omap1510_cpu_suspend_sz
);
688 } else if (cpu_is_omap16xx()) {
689 omap_sram_idle
= omap_sram_push(omap1610_idle_loop_suspend
,
690 omap1610_idle_loop_suspend_sz
);
691 omap_sram_suspend
= omap_sram_push(omap1610_cpu_suspend
,
692 omap1610_cpu_suspend_sz
);
695 if (omap_sram_idle
== NULL
|| omap_sram_suspend
== NULL
) {
696 printk(KERN_ERR
"PM not initialized: Missing SRAM support\n");
700 pm_idle
= omap_pm_idle
;
702 if (cpu_is_omap730())
703 setup_irq(INT_730_WAKE_UP_REQ
, &omap_wakeup_irq
);
704 else if (cpu_is_omap16xx())
705 setup_irq(INT_1610_WAKE_UP_REQ
, &omap_wakeup_irq
);
707 /* Program new power ramp-up time
708 * (0 for most boards since we don't lower voltage when in deep sleep)
710 omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL
, ULPD_SETUP_ANALOG_CELL_3
);
712 /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
713 omap_writew(ULPD_POWER_CTRL_REG_VAL
, ULPD_POWER_CTRL
);
715 /* Configure IDLECT3 */
716 if (cpu_is_omap730())
717 omap_writel(OMAP730_IDLECT3_VAL
, OMAP730_IDLECT3
);
718 else if (cpu_is_omap16xx())
719 omap_writel(OMAP1610_IDLECT3_VAL
, OMAP1610_IDLECT3
);
721 suspend_set_ops(&omap_pm_ops
);
723 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
727 #ifdef CONFIG_OMAP_32K_TIMER
728 error
= sysfs_create_file(power_kobj
, &sleep_while_idle_attr
);
730 printk(KERN_ERR
"sysfs_create_file failed: %d\n", error
);
733 if (cpu_is_omap16xx()) {
734 /* configure LOW_PWR pin */
735 omap_cfg_reg(T20_1610_LOW_PWR
);
740 __initcall(omap_pm_init
);