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Add linux-next specific files for 20110831
[linux-2.6/next.git] / drivers / block / cciss.c
blob6da7edea700a274815fb4367598478197a853f4e
1 /*
2 * Disk Array driver for HP Smart Array controllers.
3 * (C) Copyright 2000, 2007 Hewlett-Packard Development Company, L.P.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
17 * 02111-1307, USA.
18 *
19 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
20 *
21 */
22
23 #include <linux/module.h>
24 #include <linux/interrupt.h>
25 #include <linux/types.h>
26 #include <linux/pci.h>
27 #include <linux/kernel.h>
28 #include <linux/slab.h>
29 #include <linux/delay.h>
30 #include <linux/major.h>
31 #include <linux/fs.h>
32 #include <linux/bio.h>
33 #include <linux/blkpg.h>
34 #include <linux/timer.h>
35 #include <linux/proc_fs.h>
36 #include <linux/seq_file.h>
37 #include <linux/init.h>
38 #include <linux/jiffies.h>
39 #include <linux/hdreg.h>
40 #include <linux/spinlock.h>
41 #include <linux/compat.h>
42 #include <linux/mutex.h>
43 #include <asm/uaccess.h>
44 #include <asm/io.h>
45
46 #include <linux/dma-mapping.h>
47 #include <linux/blkdev.h>
48 #include <linux/genhd.h>
49 #include <linux/completion.h>
50 #include <scsi/scsi.h>
51 #include <scsi/sg.h>
52 #include <scsi/scsi_ioctl.h>
53 #include <linux/cdrom.h>
54 #include <linux/scatterlist.h>
55 #include <linux/kthread.h>
56
57 #define CCISS_DRIVER_VERSION(maj,min,submin) ((maj<<16)|(min<<8)|(submin))
58 #define DRIVER_NAME "HP CISS Driver (v 3.6.26)"
59 #define DRIVER_VERSION CCISS_DRIVER_VERSION(3, 6, 26)
60
61 /* Embedded module documentation macros - see modules.h */
62 MODULE_AUTHOR("Hewlett-Packard Company");
63 MODULE_DESCRIPTION("Driver for HP Smart Array Controllers");
64 MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
65 MODULE_VERSION("3.6.26");
66 MODULE_LICENSE("GPL");
67 static int cciss_tape_cmds = 6;
68 module_param(cciss_tape_cmds, int, 0644);
69 MODULE_PARM_DESC(cciss_tape_cmds,
70 "number of commands to allocate for tape devices (default: 6)");
71 static int cciss_simple_mode;
72 module_param(cciss_simple_mode, int, S_IRUGO|S_IWUSR);
73 MODULE_PARM_DESC(cciss_simple_mode,
74 "Use 'simple mode' rather than 'performant mode'");
75
76 static DEFINE_MUTEX(cciss_mutex);
77 static struct proc_dir_entry *proc_cciss;
78
79 #include "cciss_cmd.h"
80 #include "cciss.h"
81 #include <linux/cciss_ioctl.h>
82
83 /* define the PCI info for the cards we can control */
84 static const struct pci_device_id cciss_pci_device_id[] = {
85 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISS, 0x0E11, 0x4070},
86 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSB, 0x0E11, 0x4080},
87 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSB, 0x0E11, 0x4082},
88 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSB, 0x0E11, 0x4083},
89 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSC, 0x0E11, 0x4091},
90 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSC, 0x0E11, 0x409A},
91 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSC, 0x0E11, 0x409B},
92 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSC, 0x0E11, 0x409C},
93 {PCI_VENDOR_ID_COMPAQ, PCI_DEVICE_ID_COMPAQ_CISSC, 0x0E11, 0x409D},
94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSA, 0x103C, 0x3225},
95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSC, 0x103C, 0x3223},
96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSC, 0x103C, 0x3234},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSC, 0x103C, 0x3235},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSD, 0x103C, 0x3211},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSD, 0x103C, 0x3212},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSD, 0x103C, 0x3213},
101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSD, 0x103C, 0x3214},
102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSD, 0x103C, 0x3215},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSC, 0x103C, 0x3237},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSC, 0x103C, 0x323D},
105 {0,}
106 };
107
108 MODULE_DEVICE_TABLE(pci, cciss_pci_device_id);
109
110 /* board_id = Subsystem Device ID & Vendor ID
111 * product = Marketing Name for the board
112 * access = Address of the struct of function pointers
113 */
114 static struct board_type products[] = {
115 {0x40700E11, "Smart Array 5300", &SA5_access},
116 {0x40800E11, "Smart Array 5i", &SA5B_access},
117 {0x40820E11, "Smart Array 532", &SA5B_access},
118 {0x40830E11, "Smart Array 5312", &SA5B_access},
119 {0x409A0E11, "Smart Array 641", &SA5_access},
120 {0x409B0E11, "Smart Array 642", &SA5_access},
121 {0x409C0E11, "Smart Array 6400", &SA5_access},
122 {0x409D0E11, "Smart Array 6400 EM", &SA5_access},
123 {0x40910E11, "Smart Array 6i", &SA5_access},
124 {0x3225103C, "Smart Array P600", &SA5_access},
125 {0x3223103C, "Smart Array P800", &SA5_access},
126 {0x3234103C, "Smart Array P400", &SA5_access},
127 {0x3235103C, "Smart Array P400i", &SA5_access},
128 {0x3211103C, "Smart Array E200i", &SA5_access},
129 {0x3212103C, "Smart Array E200", &SA5_access},
130 {0x3213103C, "Smart Array E200i", &SA5_access},
131 {0x3214103C, "Smart Array E200i", &SA5_access},
132 {0x3215103C, "Smart Array E200i", &SA5_access},
133 {0x3237103C, "Smart Array E500", &SA5_access},
134 {0x3223103C, "Smart Array P800", &SA5_access},
135 {0x3234103C, "Smart Array P400", &SA5_access},
136 {0x323D103C, "Smart Array P700m", &SA5_access},
137 };
138
139 /* How long to wait (in milliseconds) for board to go into simple mode */
140 #define MAX_CONFIG_WAIT 30000
141 #define MAX_IOCTL_CONFIG_WAIT 1000
142
143 /*define how many times we will try a command because of bus resets */
144 #define MAX_CMD_RETRIES 3
145
146 #define MAX_CTLR 32
147
148 /* Originally cciss driver only supports 8 major numbers */
149 #define MAX_CTLR_ORIG 8
150
151 static ctlr_info_t *hba[MAX_CTLR];
152
153 static struct task_struct *cciss_scan_thread;
154 static DEFINE_MUTEX(scan_mutex);
155 static LIST_HEAD(scan_q);
156
157 static void do_cciss_request(struct request_queue *q);
158 static irqreturn_t do_cciss_intx(int irq, void *dev_id);
159 static irqreturn_t do_cciss_msix_intr(int irq, void *dev_id);
160 static int cciss_open(struct block_device *bdev, fmode_t mode);
161 static int cciss_unlocked_open(struct block_device *bdev, fmode_t mode);
162 static int cciss_release(struct gendisk *disk, fmode_t mode);
163 static int do_ioctl(struct block_device *bdev, fmode_t mode,
164 unsigned int cmd, unsigned long arg);
165 static int cciss_ioctl(struct block_device *bdev, fmode_t mode,
166 unsigned int cmd, unsigned long arg);
167 static int cciss_getgeo(struct block_device *bdev, struct hd_geometry *geo);
168
169 static int cciss_revalidate(struct gendisk *disk);
170 static int rebuild_lun_table(ctlr_info_t *h, int first_time, int via_ioctl);
171 static int deregister_disk(ctlr_info_t *h, int drv_index,
172 int clear_all, int via_ioctl);
173
174 static void cciss_read_capacity(ctlr_info_t *h, int logvol,
175 sector_t *total_size, unsigned int *block_size);
176 static void cciss_read_capacity_16(ctlr_info_t *h, int logvol,
177 sector_t *total_size, unsigned int *block_size);
178 static void cciss_geometry_inquiry(ctlr_info_t *h, int logvol,
179 sector_t total_size,
180 unsigned int block_size, InquiryData_struct *inq_buff,
181 drive_info_struct *drv);
182 static void __devinit cciss_interrupt_mode(ctlr_info_t *);
183 static int __devinit cciss_enter_simple_mode(struct ctlr_info *h);
184 static void start_io(ctlr_info_t *h);
185 static int sendcmd_withirq(ctlr_info_t *h, __u8 cmd, void *buff, size_t size,
186 __u8 page_code, unsigned char scsi3addr[],
187 int cmd_type);
188 static int sendcmd_withirq_core(ctlr_info_t *h, CommandList_struct *c,
189 int attempt_retry);
190 static int process_sendcmd_error(ctlr_info_t *h, CommandList_struct *c);
191
192 static int add_to_scan_list(struct ctlr_info *h);
193 static int scan_thread(void *data);
194 static int check_for_unit_attention(ctlr_info_t *h, CommandList_struct *c);
195 static void cciss_hba_release(struct device *dev);
196 static void cciss_device_release(struct device *dev);
197 static void cciss_free_gendisk(ctlr_info_t *h, int drv_index);
198 static void cciss_free_drive_info(ctlr_info_t *h, int drv_index);
199 static inline u32 next_command(ctlr_info_t *h);
200 static int __devinit cciss_find_cfg_addrs(struct pci_dev *pdev,
201 void __iomem *vaddr, u32 *cfg_base_addr, u64 *cfg_base_addr_index,
202 u64 *cfg_offset);
203 static int __devinit cciss_pci_find_memory_BAR(struct pci_dev *pdev,
204 unsigned long *memory_bar);
205 static inline u32 cciss_tag_discard_error_bits(ctlr_info_t *h, u32 tag);
206 static __devinit int write_driver_ver_to_cfgtable(
207 CfgTable_struct __iomem *cfgtable);
208
209 /* performant mode helper functions */
210 static void calc_bucket_map(int *bucket, int num_buckets, int nsgs,
211 int *bucket_map);
212 static void cciss_put_controller_into_performant_mode(ctlr_info_t *h);
213
214 #ifdef CONFIG_PROC_FS
215 static void cciss_procinit(ctlr_info_t *h);
216 #else
217 static void cciss_procinit(ctlr_info_t *h)
218 {
219 }
220 #endif /* CONFIG_PROC_FS */
221
222 #ifdef CONFIG_COMPAT
223 static int cciss_compat_ioctl(struct block_device *, fmode_t,
224 unsigned, unsigned long);
225 #endif
226
227 static const struct block_device_operations cciss_fops = {
228 .owner = THIS_MODULE,
229 .open = cciss_unlocked_open,
230 .release = cciss_release,
231 .ioctl = do_ioctl,
232 .getgeo = cciss_getgeo,
233 #ifdef CONFIG_COMPAT
234 .compat_ioctl = cciss_compat_ioctl,
235 #endif
236 .revalidate_disk = cciss_revalidate,
237 };
238
239 /* set_performant_mode: Modify the tag for cciss performant
240 * set bit 0 for pull model, bits 3-1 for block fetch
241 * register number
242 */
243 static void set_performant_mode(ctlr_info_t *h, CommandList_struct *c)
244 {
245 if (likely(h->transMethod & CFGTBL_Trans_Performant))
246 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
247 }
248
249 /*
250 * Enqueuing and dequeuing functions for cmdlists.
251 */
252 static inline void addQ(struct list_head *list, CommandList_struct *c)
253 {
254 list_add_tail(&c->list, list);
255 }
256
257 static inline void removeQ(CommandList_struct *c)
258 {
259 /*
260 * After kexec/dump some commands might still
261 * be in flight, which the firmware will try
262 * to complete. Resetting the firmware doesn't work
263 * with old fw revisions, so we have to mark
264 * them off as 'stale' to prevent the driver from
265 * falling over.
266 */
267 if (WARN_ON(list_empty(&c->list))) {
268 c->cmd_type = CMD_MSG_STALE;
269 return;
270 }
271
272 list_del_init(&c->list);
273 }
274
275 static void enqueue_cmd_and_start_io(ctlr_info_t *h,
276 CommandList_struct *c)
277 {
278 unsigned long flags;
279 set_performant_mode(h, c);
280 spin_lock_irqsave(&h->lock, flags);
281 addQ(&h->reqQ, c);
282 h->Qdepth++;
283 if (h->Qdepth > h->maxQsinceinit)
284 h->maxQsinceinit = h->Qdepth;
285 start_io(h);
286 spin_unlock_irqrestore(&h->lock, flags);
287 }
288
289 static void cciss_free_sg_chain_blocks(SGDescriptor_struct **cmd_sg_list,
290 int nr_cmds)
291 {
292 int i;
293
294 if (!cmd_sg_list)
295 return;
296 for (i = 0; i < nr_cmds; i++) {
297 kfree(cmd_sg_list[i]);
298 cmd_sg_list[i] = NULL;
299 }
300 kfree(cmd_sg_list);
301 }
302
303 static SGDescriptor_struct **cciss_allocate_sg_chain_blocks(
304 ctlr_info_t *h, int chainsize, int nr_cmds)
305 {
306 int j;
307 SGDescriptor_struct **cmd_sg_list;
308
309 if (chainsize <= 0)
310 return NULL;
311
312 cmd_sg_list = kmalloc(sizeof(*cmd_sg_list) * nr_cmds, GFP_KERNEL);
313 if (!cmd_sg_list)
314 return NULL;
315
316 /* Build up chain blocks for each command */
317 for (j = 0; j < nr_cmds; j++) {
318 /* Need a block of chainsized s/g elements. */
319 cmd_sg_list[j] = kmalloc((chainsize *
320 sizeof(*cmd_sg_list[j])), GFP_KERNEL);
321 if (!cmd_sg_list[j]) {
322 dev_err(&h->pdev->dev, "Cannot get memory "
323 "for s/g chains.\n");
324 goto clean;
325 }
326 }
327 return cmd_sg_list;
328 clean:
329 cciss_free_sg_chain_blocks(cmd_sg_list, nr_cmds);
330 return NULL;
331 }
332
333 static void cciss_unmap_sg_chain_block(ctlr_info_t *h, CommandList_struct *c)
334 {
335 SGDescriptor_struct *chain_sg;
336 u64bit temp64;
337
338 if (c->Header.SGTotal <= h->max_cmd_sgentries)
339 return;
340
341 chain_sg = &c->SG[h->max_cmd_sgentries - 1];
342 temp64.val32.lower = chain_sg->Addr.lower;
343 temp64.val32.upper = chain_sg->Addr.upper;
344 pci_unmap_single(h->pdev, temp64.val, chain_sg->Len, PCI_DMA_TODEVICE);
345 }
346
347 static void cciss_map_sg_chain_block(ctlr_info_t *h, CommandList_struct *c,
348 SGDescriptor_struct *chain_block, int len)
349 {
350 SGDescriptor_struct *chain_sg;
351 u64bit temp64;
352
353 chain_sg = &c->SG[h->max_cmd_sgentries - 1];
354 chain_sg->Ext = CCISS_SG_CHAIN;
355 chain_sg->Len = len;
356 temp64.val = pci_map_single(h->pdev, chain_block, len,
357 PCI_DMA_TODEVICE);
358 chain_sg->Addr.lower = temp64.val32.lower;
359 chain_sg->Addr.upper = temp64.val32.upper;
360 }
361
362 #include "cciss_scsi.c" /* For SCSI tape support */
363
364 static const char *raid_label[] = { "0", "4", "1(1+0)", "5", "5+1", "ADG",
365 "UNKNOWN"
366 };
367 #define RAID_UNKNOWN (ARRAY_SIZE(raid_label)-1)
368
369 #ifdef CONFIG_PROC_FS
370
371 /*
372 * Report information about this controller.
373 */
374 #define ENG_GIG 1000000000
375 #define ENG_GIG_FACTOR (ENG_GIG/512)
376 #define ENGAGE_SCSI "engage scsi"
377
378 static void cciss_seq_show_header(struct seq_file *seq)
379 {
380 ctlr_info_t *h = seq->private;
381
382 seq_printf(seq, "%s: HP %s Controller\n"
383 "Board ID: 0x%08lx\n"
384 "Firmware Version: %c%c%c%c\n"
385 "IRQ: %d\n"
386 "Logical drives: %d\n"
387 "Current Q depth: %d\n"
388 "Current # commands on controller: %d\n"
389 "Max Q depth since init: %d\n"
390 "Max # commands on controller since init: %d\n"
391 "Max SG entries since init: %d\n",
392 h->devname,
393 h->product_name,
394 (unsigned long)h->board_id,
395 h->firm_ver[0], h->firm_ver[1], h->firm_ver[2],
396 h->firm_ver[3], (unsigned int)h->intr[h->intr_mode],
397 h->num_luns,
398 h->Qdepth, h->commands_outstanding,
399 h->maxQsinceinit, h->max_outstanding, h->maxSG);
400
401 #ifdef CONFIG_CISS_SCSI_TAPE
402 cciss_seq_tape_report(seq, h);
403 #endif /* CONFIG_CISS_SCSI_TAPE */
404 }
405
406 static void *cciss_seq_start(struct seq_file *seq, loff_t *pos)
407 {
408 ctlr_info_t *h = seq->private;
409 unsigned long flags;
410
411 /* prevent displaying bogus info during configuration
412 * or deconfiguration of a logical volume
413 */
414 spin_lock_irqsave(&h->lock, flags);
415 if (h->busy_configuring) {
416 spin_unlock_irqrestore(&h->lock, flags);
417 return ERR_PTR(-EBUSY);
418 }
419 h->busy_configuring = 1;
420 spin_unlock_irqrestore(&h->lock, flags);
421
422 if (*pos == 0)
423 cciss_seq_show_header(seq);
424
425 return pos;
426 }
427
428 static int cciss_seq_show(struct seq_file *seq, void *v)
429 {
430 sector_t vol_sz, vol_sz_frac;
431 ctlr_info_t *h = seq->private;
432 unsigned ctlr = h->ctlr;
433 loff_t *pos = v;
434 drive_info_struct *drv = h->drv[*pos];
435
436 if (*pos > h->highest_lun)
437 return 0;
438
439 if (drv == NULL) /* it's possible for h->drv[] to have holes. */
440 return 0;
441
442 if (drv->heads == 0)
443 return 0;
444
445 vol_sz = drv->nr_blocks;
446 vol_sz_frac = sector_div(vol_sz, ENG_GIG_FACTOR);
447 vol_sz_frac *= 100;
448 sector_div(vol_sz_frac, ENG_GIG_FACTOR);
449
450 if (drv->raid_level < 0 || drv->raid_level > RAID_UNKNOWN)
451 drv->raid_level = RAID_UNKNOWN;
452 seq_printf(seq, "cciss/c%dd%d:"
453 "\t%4u.%02uGB\tRAID %s\n",
454 ctlr, (int) *pos, (int)vol_sz, (int)vol_sz_frac,
455 raid_label[drv->raid_level]);
456 return 0;
457 }
458
459 static void *cciss_seq_next(struct seq_file *seq, void *v, loff_t *pos)
460 {
461 ctlr_info_t *h = seq->private;
462
463 if (*pos > h->highest_lun)
464 return NULL;
465 *pos += 1;
466
467 return pos;
468 }
469
470 static void cciss_seq_stop(struct seq_file *seq, void *v)
471 {
472 ctlr_info_t *h = seq->private;
473
474 /* Only reset h->busy_configuring if we succeeded in setting
475 * it during cciss_seq_start. */
476 if (v == ERR_PTR(-EBUSY))
477 return;
478
479 h->busy_configuring = 0;
480 }
481
482 static const struct seq_operations cciss_seq_ops = {
483 .start = cciss_seq_start,
484 .show = cciss_seq_show,
485 .next = cciss_seq_next,
486 .stop = cciss_seq_stop,
487 };
488
489 static int cciss_seq_open(struct inode *inode, struct file *file)
490 {
491 int ret = seq_open(file, &cciss_seq_ops);
492 struct seq_file *seq = file->private_data;
493
494 if (!ret)
495 seq->private = PDE(inode)->data;
496
497 return ret;
498 }
499
500 static ssize_t
501 cciss_proc_write(struct file *file, const char __user *buf,
502 size_t length, loff_t *ppos)
503 {
504 int err;
505 char *buffer;
506
507 #ifndef CONFIG_CISS_SCSI_TAPE
508 return -EINVAL;
509 #endif
510
511 if (!buf || length > PAGE_SIZE - 1)
512 return -EINVAL;
513
514 buffer = (char *)__get_free_page(GFP_KERNEL);
515 if (!buffer)
516 return -ENOMEM;
517
518 err = -EFAULT;
519 if (copy_from_user(buffer, buf, length))
520 goto out;
521 buffer[length] = '\0';
522
523 #ifdef CONFIG_CISS_SCSI_TAPE
524 if (strncmp(ENGAGE_SCSI, buffer, sizeof ENGAGE_SCSI - 1) == 0) {
525 struct seq_file *seq = file->private_data;
526 ctlr_info_t *h = seq->private;
527
528 err = cciss_engage_scsi(h);
529 if (err == 0)
530 err = length;
531 } else
532 #endif /* CONFIG_CISS_SCSI_TAPE */
533 err = -EINVAL;
534 /* might be nice to have "disengage" too, but it's not
535 safely possible. (only 1 module use count, lock issues.) */
536
537 out:
538 free_page((unsigned long)buffer);
539 return err;
540 }
541
542 static const struct file_operations cciss_proc_fops = {
543 .owner = THIS_MODULE,
544 .open = cciss_seq_open,
545 .read = seq_read,
546 .llseek = seq_lseek,
547 .release = seq_release,
548 .write = cciss_proc_write,
549 };
550
551 static void __devinit cciss_procinit(ctlr_info_t *h)
552 {
553 struct proc_dir_entry *pde;
554
555 if (proc_cciss == NULL)
556 proc_cciss = proc_mkdir("driver/cciss", NULL);
557 if (!proc_cciss)
558 return;
559 pde = proc_create_data(h->devname, S_IWUSR | S_IRUSR | S_IRGRP |
560 S_IROTH, proc_cciss,
561 &cciss_proc_fops, h);
562 }
563 #endif /* CONFIG_PROC_FS */
564
565 #define MAX_PRODUCT_NAME_LEN 19
566
567 #define to_hba(n) container_of(n, struct ctlr_info, dev)
568 #define to_drv(n) container_of(n, drive_info_struct, dev)
569
570 /* List of controllers which cannot be hard reset on kexec with reset_devices */
571 static u32 unresettable_controller[] = {
572 0x324a103C, /* Smart Array P712m */
573 0x324b103C, /* SmartArray P711m */
574 0x3223103C, /* Smart Array P800 */
575 0x3234103C, /* Smart Array P400 */
576 0x3235103C, /* Smart Array P400i */
577 0x3211103C, /* Smart Array E200i */
578 0x3212103C, /* Smart Array E200 */
579 0x3213103C, /* Smart Array E200i */
580 0x3214103C, /* Smart Array E200i */
581 0x3215103C, /* Smart Array E200i */
582 0x3237103C, /* Smart Array E500 */
583 0x323D103C, /* Smart Array P700m */
584 0x409C0E11, /* Smart Array 6400 */
585 0x409D0E11, /* Smart Array 6400 EM */
586 };
587
588 /* List of controllers which cannot even be soft reset */
589 static u32 soft_unresettable_controller[] = {
590 0x409C0E11, /* Smart Array 6400 */
591 0x409D0E11, /* Smart Array 6400 EM */
592 };
593
594 static int ctlr_is_hard_resettable(u32 board_id)
595 {
596 int i;
597
598 for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++)
599 if (unresettable_controller[i] == board_id)
600 return 0;
601 return 1;
602 }
603
604 static int ctlr_is_soft_resettable(u32 board_id)
605 {
606 int i;
607
608 for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++)
609 if (soft_unresettable_controller[i] == board_id)
610 return 0;
611 return 1;
612 }
613
614 static int ctlr_is_resettable(u32 board_id)
615 {
616 return ctlr_is_hard_resettable(board_id) ||
617 ctlr_is_soft_resettable(board_id);
618 }
619
620 static ssize_t host_show_resettable(struct device *dev,
621 struct device_attribute *attr,
622 char *buf)
623 {
624 struct ctlr_info *h = to_hba(dev);
625
626 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
627 }
628 static DEVICE_ATTR(resettable, S_IRUGO, host_show_resettable, NULL);
629
630 static ssize_t host_store_rescan(struct device *dev,
631 struct device_attribute *attr,
632 const char *buf, size_t count)
633 {
634 struct ctlr_info *h = to_hba(dev);
635
636 add_to_scan_list(h);
637 wake_up_process(cciss_scan_thread);
638 wait_for_completion_interruptible(&h->scan_wait);
639
640 return count;
641 }
642 static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
643
644 static ssize_t host_show_transport_mode(struct device *dev,
645 struct device_attribute *attr,
646 char *buf)
647 {
648 struct ctlr_info *h = to_hba(dev);
649
650 return snprintf(buf, 20, "%s\n",
651 h->transMethod & CFGTBL_Trans_Performant ?
652 "performant" : "simple");
653 }
654 static DEVICE_ATTR(transport_mode, S_IRUGO, host_show_transport_mode, NULL);
655
656 static ssize_t dev_show_unique_id(struct device *dev,
657 struct device_attribute *attr,
658 char *buf)
659 {
660 drive_info_struct *drv = to_drv(dev);
661 struct ctlr_info *h = to_hba(drv->dev.parent);
662 __u8 sn[16];
663 unsigned long flags;
664 int ret = 0;
665
666 spin_lock_irqsave(&h->lock, flags);
667 if (h->busy_configuring)
668 ret = -EBUSY;
669 else
670 memcpy(sn, drv->serial_no, sizeof(sn));
671 spin_unlock_irqrestore(&h->lock, flags);
672
673 if (ret)
674 return ret;
675 else
676 return snprintf(buf, 16 * 2 + 2,
677 "%02X%02X%02X%02X%02X%02X%02X%02X"
678 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
679 sn[0], sn[1], sn[2], sn[3],
680 sn[4], sn[5], sn[6], sn[7],
681 sn[8], sn[9], sn[10], sn[11],
682 sn[12], sn[13], sn[14], sn[15]);
683 }
684 static DEVICE_ATTR(unique_id, S_IRUGO, dev_show_unique_id, NULL);
685
686 static ssize_t dev_show_vendor(struct device *dev,
687 struct device_attribute *attr,
688 char *buf)
689 {
690 drive_info_struct *drv = to_drv(dev);
691 struct ctlr_info *h = to_hba(drv->dev.parent);
692 char vendor[VENDOR_LEN + 1];
693 unsigned long flags;
694 int ret = 0;
695
696 spin_lock_irqsave(&h->lock, flags);
697 if (h->busy_configuring)
698 ret = -EBUSY;
699 else
700 memcpy(vendor, drv->vendor, VENDOR_LEN + 1);
701 spin_unlock_irqrestore(&h->lock, flags);
702
703 if (ret)
704 return ret;
705 else
706 return snprintf(buf, sizeof(vendor) + 1, "%s\n", drv->vendor);
707 }
708 static DEVICE_ATTR(vendor, S_IRUGO, dev_show_vendor, NULL);
709
710 static ssize_t dev_show_model(struct device *dev,
711 struct device_attribute *attr,
712 char *buf)
713 {
714 drive_info_struct *drv = to_drv(dev);
715 struct ctlr_info *h = to_hba(drv->dev.parent);
716 char model[MODEL_LEN + 1];
717 unsigned long flags;
718 int ret = 0;
719
720 spin_lock_irqsave(&h->lock, flags);
721 if (h->busy_configuring)
722 ret = -EBUSY;
723 else
724 memcpy(model, drv->model, MODEL_LEN + 1);
725 spin_unlock_irqrestore(&h->lock, flags);
726
727 if (ret)
728 return ret;
729 else
730 return snprintf(buf, sizeof(model) + 1, "%s\n", drv->model);
731 }
732 static DEVICE_ATTR(model, S_IRUGO, dev_show_model, NULL);
733
734 static ssize_t dev_show_rev(struct device *dev,
735 struct device_attribute *attr,
736 char *buf)
737 {
738 drive_info_struct *drv = to_drv(dev);
739 struct ctlr_info *h = to_hba(drv->dev.parent);
740 char rev[REV_LEN + 1];
741 unsigned long flags;
742 int ret = 0;
743
744 spin_lock_irqsave(&h->lock, flags);
745 if (h->busy_configuring)
746 ret = -EBUSY;
747 else
748 memcpy(rev, drv->rev, REV_LEN + 1);
749 spin_unlock_irqrestore(&h->lock, flags);
750
751 if (ret)
752 return ret;
753 else
754 return snprintf(buf, sizeof(rev) + 1, "%s\n", drv->rev);
755 }
756 static DEVICE_ATTR(rev, S_IRUGO, dev_show_rev, NULL);
757
758 static ssize_t cciss_show_lunid(struct device *dev,
759 struct device_attribute *attr, char *buf)
760 {
761 drive_info_struct *drv = to_drv(dev);
762 struct ctlr_info *h = to_hba(drv->dev.parent);
763 unsigned long flags;
764 unsigned char lunid[8];
765
766 spin_lock_irqsave(&h->lock, flags);
767 if (h->busy_configuring) {
768 spin_unlock_irqrestore(&h->lock, flags);
769 return -EBUSY;
770 }
771 if (!drv->heads) {
772 spin_unlock_irqrestore(&h->lock, flags);
773 return -ENOTTY;
774 }
775 memcpy(lunid, drv->LunID, sizeof(lunid));
776 spin_unlock_irqrestore(&h->lock, flags);
777 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
778 lunid[0], lunid[1], lunid[2], lunid[3],
779 lunid[4], lunid[5], lunid[6], lunid[7]);
780 }
781 static DEVICE_ATTR(lunid, S_IRUGO, cciss_show_lunid, NULL);
782
783 static ssize_t cciss_show_raid_level(struct device *dev,
784 struct device_attribute *attr, char *buf)
785 {
786 drive_info_struct *drv = to_drv(dev);
787 struct ctlr_info *h = to_hba(drv->dev.parent);
788 int raid;
789 unsigned long flags;
790
791 spin_lock_irqsave(&h->lock, flags);
792 if (h->busy_configuring) {
793 spin_unlock_irqrestore(&h->lock, flags);
794 return -EBUSY;
795 }
796 raid = drv->raid_level;
797 spin_unlock_irqrestore(&h->lock, flags);
798 if (raid < 0 || raid > RAID_UNKNOWN)
799 raid = RAID_UNKNOWN;
800
801 return snprintf(buf, strlen(raid_label[raid]) + 7, "RAID %s\n",
802 raid_label[raid]);
803 }
804 static DEVICE_ATTR(raid_level, S_IRUGO, cciss_show_raid_level, NULL);
805
806 static ssize_t cciss_show_usage_count(struct device *dev,
807 struct device_attribute *attr, char *buf)
808 {
809 drive_info_struct *drv = to_drv(dev);
810 struct ctlr_info *h = to_hba(drv->dev.parent);
811 unsigned long flags;
812 int count;
813
814 spin_lock_irqsave(&h->lock, flags);
815 if (h->busy_configuring) {
816 spin_unlock_irqrestore(&h->lock, flags);
817 return -EBUSY;
818 }
819 count = drv->usage_count;
820 spin_unlock_irqrestore(&h->lock, flags);
821 return snprintf(buf, 20, "%d\n", count);
822 }
823 static DEVICE_ATTR(usage_count, S_IRUGO, cciss_show_usage_count, NULL);
824
825 static struct attribute *cciss_host_attrs[] = {
826 &dev_attr_rescan.attr,
827 &dev_attr_resettable.attr,
828 &dev_attr_transport_mode.attr,
829 NULL
830 };
831
832 static struct attribute_group cciss_host_attr_group = {
833 .attrs = cciss_host_attrs,
834 };
835
836 static const struct attribute_group *cciss_host_attr_groups[] = {
837 &cciss_host_attr_group,
838 NULL
839 };
840
841 static struct device_type cciss_host_type = {
842 .name = "cciss_host",
843 .groups = cciss_host_attr_groups,
844 .release = cciss_hba_release,
845 };
846
847 static struct attribute *cciss_dev_attrs[] = {
848 &dev_attr_unique_id.attr,
849 &dev_attr_model.attr,
850 &dev_attr_vendor.attr,
851 &dev_attr_rev.attr,
852 &dev_attr_lunid.attr,
853 &dev_attr_raid_level.attr,
854 &dev_attr_usage_count.attr,
855 NULL
856 };
857
858 static struct attribute_group cciss_dev_attr_group = {
859 .attrs = cciss_dev_attrs,
860 };
861
862 static const struct attribute_group *cciss_dev_attr_groups[] = {
863 &cciss_dev_attr_group,
864 NULL
865 };
866
867 static struct device_type cciss_dev_type = {
868 .name = "cciss_device",
869 .groups = cciss_dev_attr_groups,
870 .release = cciss_device_release,
871 };
872
873 static struct bus_type cciss_bus_type = {
874 .name = "cciss",
875 };
876
877 /*
878 * cciss_hba_release is called when the reference count
879 * of h->dev goes to zero.
880 */
881 static void cciss_hba_release(struct device *dev)
882 {
883 /*
884 * nothing to do, but need this to avoid a warning
885 * about not having a release handler from lib/kref.c.
886 */
887 }
888
889 /*
890 * Initialize sysfs entry for each controller. This sets up and registers
891 * the 'cciss#' directory for each individual controller under
892 * /sys/bus/pci/devices/<dev>/.
893 */
894 static int cciss_create_hba_sysfs_entry(struct ctlr_info *h)
895 {
896 device_initialize(&h->dev);
897 h->dev.type = &cciss_host_type;
898 h->dev.bus = &cciss_bus_type;
899 dev_set_name(&h->dev, "%s", h->devname);
900 h->dev.parent = &h->pdev->dev;
901
902 return device_add(&h->dev);
903 }
904
905 /*
906 * Remove sysfs entries for an hba.
907 */
908 static void cciss_destroy_hba_sysfs_entry(struct ctlr_info *h)
909 {
910 device_del(&h->dev);
911 put_device(&h->dev); /* final put. */
912 }
913
914 /* cciss_device_release is called when the reference count
915 * of h->drv[x]dev goes to zero.
916 */
917 static void cciss_device_release(struct device *dev)
918 {
919 drive_info_struct *drv = to_drv(dev);
920 kfree(drv);
921 }
922
923 /*
924 * Initialize sysfs for each logical drive. This sets up and registers
925 * the 'c#d#' directory for each individual logical drive under
926 * /sys/bus/pci/devices/<dev/ccis#/. We also create a link from
927 * /sys/block/cciss!c#d# to this entry.
928 */
929 static long cciss_create_ld_sysfs_entry(struct ctlr_info *h,
930 int drv_index)
931 {
932 struct device *dev;
933
934 if (h->drv[drv_index]->device_initialized)
935 return 0;
936
937 dev = &h->drv[drv_index]->dev;
938 device_initialize(dev);
939 dev->type = &cciss_dev_type;
940 dev->bus = &cciss_bus_type;
941 dev_set_name(dev, "c%dd%d", h->ctlr, drv_index);
942 dev->parent = &h->dev;
943 h->drv[drv_index]->device_initialized = 1;
944 return device_add(dev);
945 }
946
947 /*
948 * Remove sysfs entries for a logical drive.
949 */
950 static void cciss_destroy_ld_sysfs_entry(struct ctlr_info *h, int drv_index,
951 int ctlr_exiting)
952 {
953 struct device *dev = &h->drv[drv_index]->dev;
954
955 /* special case for c*d0, we only destroy it on controller exit */
956 if (drv_index == 0 && !ctlr_exiting)
957 return;
958
959 device_del(dev);
960 put_device(dev); /* the "final" put. */
961 h->drv[drv_index] = NULL;
962 }
963
964 /*
965 * For operations that cannot sleep, a command block is allocated at init,
966 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
967 * which ones are free or in use.
968 */
969 static CommandList_struct *cmd_alloc(ctlr_info_t *h)
970 {
971 CommandList_struct *c;
972 int i;
973 u64bit temp64;
974 dma_addr_t cmd_dma_handle, err_dma_handle;
975
976 do {
977 i = find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds);
978 if (i == h->nr_cmds)
979 return NULL;
980 } while (test_and_set_bit(i & (BITS_PER_LONG - 1),
981 h->cmd_pool_bits + (i / BITS_PER_LONG)) != 0);
982 c = h->cmd_pool + i;
983 memset(c, 0, sizeof(CommandList_struct));
984 cmd_dma_handle = h->cmd_pool_dhandle + i * sizeof(CommandList_struct);
985 c->err_info = h->errinfo_pool + i;
986 memset(c->err_info, 0, sizeof(ErrorInfo_struct));
987 err_dma_handle = h->errinfo_pool_dhandle
988 + i * sizeof(ErrorInfo_struct);
989 h->nr_allocs++;
990
991 c->cmdindex = i;
992
993 INIT_LIST_HEAD(&c->list);
994 c->busaddr = (__u32) cmd_dma_handle;
995 temp64.val = (__u64) err_dma_handle;
996 c->ErrDesc.Addr.lower = temp64.val32.lower;
997 c->ErrDesc.Addr.upper = temp64.val32.upper;
998 c->ErrDesc.Len = sizeof(ErrorInfo_struct);
999
1000 c->ctlr = h->ctlr;
1001 return c;
1002 }
1003
1004 /* allocate a command using pci_alloc_consistent, used for ioctls,
1005 * etc., not for the main i/o path.
1006 */
1007 static CommandList_struct *cmd_special_alloc(ctlr_info_t *h)
1008 {
1009 CommandList_struct *c;
1010 u64bit temp64;
1011 dma_addr_t cmd_dma_handle, err_dma_handle;
1012
1013 c = (CommandList_struct *) pci_alloc_consistent(h->pdev,
1014 sizeof(CommandList_struct), &cmd_dma_handle);
1015 if (c == NULL)
1016 return NULL;
1017 memset(c, 0, sizeof(CommandList_struct));
1018
1019 c->cmdindex = -1;
1020
1021 c->err_info = (ErrorInfo_struct *)
1022 pci_alloc_consistent(h->pdev, sizeof(ErrorInfo_struct),
1023 &err_dma_handle);
1024
1025 if (c->err_info == NULL) {
1026 pci_free_consistent(h->pdev,
1027 sizeof(CommandList_struct), c, cmd_dma_handle);
1028 return NULL;
1029 }
1030 memset(c->err_info, 0, sizeof(ErrorInfo_struct));
1031
1032 INIT_LIST_HEAD(&c->list);
1033 c->busaddr = (__u32) cmd_dma_handle;
1034 temp64.val = (__u64) err_dma_handle;
1035 c->ErrDesc.Addr.lower = temp64.val32.lower;
1036 c->ErrDesc.Addr.upper = temp64.val32.upper;
1037 c->ErrDesc.Len = sizeof(ErrorInfo_struct);
1038
1039 c->ctlr = h->ctlr;
1040 return c;
1041 }
1042
1043 static void cmd_free(ctlr_info_t *h, CommandList_struct *c)
1044 {
1045 int i;
1046
1047 i = c - h->cmd_pool;
1048 clear_bit(i & (BITS_PER_LONG - 1),
1049 h->cmd_pool_bits + (i / BITS_PER_LONG));
1050 h->nr_frees++;
1051 }
1052
1053 static void cmd_special_free(ctlr_info_t *h, CommandList_struct *c)
1054 {
1055 u64bit temp64;
1056
1057 temp64.val32.lower = c->ErrDesc.Addr.lower;
1058 temp64.val32.upper = c->ErrDesc.Addr.upper;
1059 pci_free_consistent(h->pdev, sizeof(ErrorInfo_struct),
1060 c->err_info, (dma_addr_t) temp64.val);
1061 pci_free_consistent(h->pdev, sizeof(CommandList_struct), c,
1062 (dma_addr_t) cciss_tag_discard_error_bits(h, (u32) c->busaddr));
1063 }
1064
1065 static inline ctlr_info_t *get_host(struct gendisk *disk)
1066 {
1067 return disk->queue->queuedata;
1068 }
1069
1070 static inline drive_info_struct *get_drv(struct gendisk *disk)
1071 {
1072 return disk->private_data;
1073 }
1074
1075 /*
1076 * Open. Make sure the device is really there.
1077 */
1078 static int cciss_open(struct block_device *bdev, fmode_t mode)
1079 {
1080 ctlr_info_t *h = get_host(bdev->bd_disk);
1081 drive_info_struct *drv = get_drv(bdev->bd_disk);
1082
1083 dev_dbg(&h->pdev->dev, "cciss_open %s\n", bdev->bd_disk->disk_name);
1084 if (drv->busy_configuring)
1085 return -EBUSY;
1086 /*
1087 * Root is allowed to open raw volume zero even if it's not configured
1088 * so array config can still work. Root is also allowed to open any
1089 * volume that has a LUN ID, so it can issue IOCTL to reread the
1090 * disk information. I don't think I really like this
1091 * but I'm already using way to many device nodes to claim another one
1092 * for "raw controller".
1093 */
1094 if (drv->heads == 0) {
1095 if (MINOR(bdev->bd_dev) != 0) { /* not node 0? */
1096 /* if not node 0 make sure it is a partition = 0 */
1097 if (MINOR(bdev->bd_dev) & 0x0f) {
1098 return -ENXIO;
1099 /* if it is, make sure we have a LUN ID */
1100 } else if (memcmp(drv->LunID, CTLR_LUNID,
1101 sizeof(drv->LunID))) {
1102 return -ENXIO;
1103 }
1104 }
1105 if (!capable(CAP_SYS_ADMIN))
1106 return -EPERM;
1107 }
1108 drv->usage_count++;
1109 h->usage_count++;
1110 return 0;
1111 }
1112
1113 static int cciss_unlocked_open(struct block_device *bdev, fmode_t mode)
1114 {
1115 int ret;
1116
1117 mutex_lock(&cciss_mutex);
1118 ret = cciss_open(bdev, mode);
1119 mutex_unlock(&cciss_mutex);
1120
1121 return ret;
1122 }
1123
1124 /*
1125 * Close. Sync first.
1126 */
1127 static int cciss_release(struct gendisk *disk, fmode_t mode)
1128 {
1129 ctlr_info_t *h;
1130 drive_info_struct *drv;
1131
1132 mutex_lock(&cciss_mutex);
1133 h = get_host(disk);
1134 drv = get_drv(disk);
1135 dev_dbg(&h->pdev->dev, "cciss_release %s\n", disk->disk_name);
1136 drv->usage_count--;
1137 h->usage_count--;
1138 mutex_unlock(&cciss_mutex);
1139 return 0;
1140 }
1141
1142 static int do_ioctl(struct block_device *bdev, fmode_t mode,
1143 unsigned cmd, unsigned long arg)
1144 {
1145 int ret;
1146 mutex_lock(&cciss_mutex);
1147 ret = cciss_ioctl(bdev, mode, cmd, arg);
1148 mutex_unlock(&cciss_mutex);
1149 return ret;
1150 }
1151
1152 #ifdef CONFIG_COMPAT
1153
1154 static int cciss_ioctl32_passthru(struct block_device *bdev, fmode_t mode,
1155 unsigned cmd, unsigned long arg);
1156 static int cciss_ioctl32_big_passthru(struct block_device *bdev, fmode_t mode,
1157 unsigned cmd, unsigned long arg);
1158
1159 static int cciss_compat_ioctl(struct block_device *bdev, fmode_t mode,
1160 unsigned cmd, unsigned long arg)
1161 {
1162 switch (cmd) {
1163 case CCISS_GETPCIINFO:
1164 case CCISS_GETINTINFO:
1165 case CCISS_SETINTINFO:
1166 case CCISS_GETNODENAME:
1167 case CCISS_SETNODENAME:
1168 case CCISS_GETHEARTBEAT:
1169 case CCISS_GETBUSTYPES:
1170 case CCISS_GETFIRMVER:
1171 case CCISS_GETDRIVVER:
1172 case CCISS_REVALIDVOLS:
1173 case CCISS_DEREGDISK:
1174 case CCISS_REGNEWDISK:
1175 case CCISS_REGNEWD:
1176 case CCISS_RESCANDISK:
1177 case CCISS_GETLUNINFO:
1178 return do_ioctl(bdev, mode, cmd, arg);
1179
1180 case CCISS_PASSTHRU32:
1181 return cciss_ioctl32_passthru(bdev, mode, cmd, arg);
1182 case CCISS_BIG_PASSTHRU32:
1183 return cciss_ioctl32_big_passthru(bdev, mode, cmd, arg);
1184
1185 default:
1186 return -ENOIOCTLCMD;
1187 }
1188 }
1189
1190 static int cciss_ioctl32_passthru(struct block_device *bdev, fmode_t mode,
1191 unsigned cmd, unsigned long arg)
1192 {
1193 IOCTL32_Command_struct __user *arg32 =
1194 (IOCTL32_Command_struct __user *) arg;
1195 IOCTL_Command_struct arg64;
1196 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
1197 int err;
1198 u32 cp;
1199
1200 err = 0;
1201 err |=
1202 copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
1203 sizeof(arg64.LUN_info));
1204 err |=
1205 copy_from_user(&arg64.Request, &arg32->Request,
1206 sizeof(arg64.Request));
1207 err |=
1208 copy_from_user(&arg64.error_info, &arg32->error_info,
1209 sizeof(arg64.error_info));
1210 err |= get_user(arg64.buf_size, &arg32->buf_size);
1211 err |= get_user(cp, &arg32->buf);
1212 arg64.buf = compat_ptr(cp);
1213 err |= copy_to_user(p, &arg64, sizeof(arg64));
1214
1215 if (err)
1216 return -EFAULT;
1217
1218 err = do_ioctl(bdev, mode, CCISS_PASSTHRU, (unsigned long)p);
1219 if (err)
1220 return err;
1221 err |=
1222 copy_in_user(&arg32->error_info, &p->error_info,
1223 sizeof(arg32->error_info));
1224 if (err)
1225 return -EFAULT;
1226 return err;
1227 }
1228
1229 static int cciss_ioctl32_big_passthru(struct block_device *bdev, fmode_t mode,
1230 unsigned cmd, unsigned long arg)
1231 {
1232 BIG_IOCTL32_Command_struct __user *arg32 =
1233 (BIG_IOCTL32_Command_struct __user *) arg;
1234 BIG_IOCTL_Command_struct arg64;
1235 BIG_IOCTL_Command_struct __user *p =
1236 compat_alloc_user_space(sizeof(arg64));
1237 int err;
1238 u32 cp;
1239
1240 memset(&arg64, 0, sizeof(arg64));
1241 err = 0;
1242 err |=
1243 copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
1244 sizeof(arg64.LUN_info));
1245 err |=
1246 copy_from_user(&arg64.Request, &arg32->Request,
1247 sizeof(arg64.Request));
1248 err |=
1249 copy_from_user(&arg64.error_info, &arg32->error_info,
1250 sizeof(arg64.error_info));
1251 err |= get_user(arg64.buf_size, &arg32->buf_size);
1252 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
1253 err |= get_user(cp, &arg32->buf);
1254 arg64.buf = compat_ptr(cp);
1255 err |= copy_to_user(p, &arg64, sizeof(arg64));
1256
1257 if (err)
1258 return -EFAULT;
1259
1260 err = do_ioctl(bdev, mode, CCISS_BIG_PASSTHRU, (unsigned long)p);
1261 if (err)
1262 return err;
1263 err |=
1264 copy_in_user(&arg32->error_info, &p->error_info,
1265 sizeof(arg32->error_info));
1266 if (err)
1267 return -EFAULT;
1268 return err;
1269 }
1270 #endif
1271
1272 static int cciss_getgeo(struct block_device *bdev, struct hd_geometry *geo)
1273 {
1274 drive_info_struct *drv = get_drv(bdev->bd_disk);
1275
1276 if (!drv->cylinders)
1277 return -ENXIO;
1278
1279 geo->heads = drv->heads;
1280 geo->sectors = drv->sectors;
1281 geo->cylinders = drv->cylinders;
1282 return 0;
1283 }
1284
1285 static void check_ioctl_unit_attention(ctlr_info_t *h, CommandList_struct *c)
1286 {
1287 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
1288 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
1289 (void)check_for_unit_attention(h, c);
1290 }
1291
1292 static int cciss_getpciinfo(ctlr_info_t *h, void __user *argp)
1293 {
1294 cciss_pci_info_struct pciinfo;
1295
1296 if (!argp)
1297 return -EINVAL;
1298 pciinfo.domain = pci_domain_nr(h->pdev->bus);
1299 pciinfo.bus = h->pdev->bus->number;
1300 pciinfo.dev_fn = h->pdev->devfn;
1301 pciinfo.board_id = h->board_id;
1302 if (copy_to_user(argp, &pciinfo, sizeof(cciss_pci_info_struct)))
1303 return -EFAULT;
1304 return 0;
1305 }
1306
1307 static int cciss_getintinfo(ctlr_info_t *h, void __user *argp)
1308 {
1309 cciss_coalint_struct intinfo;
1310
1311 if (!argp)
1312 return -EINVAL;
1313 intinfo.delay = readl(&h->cfgtable->HostWrite.CoalIntDelay);
1314 intinfo.count = readl(&h->cfgtable->HostWrite.CoalIntCount);
1315 if (copy_to_user
1316 (argp, &intinfo, sizeof(cciss_coalint_struct)))
1317 return -EFAULT;
1318 return 0;
1319 }
1320
1321 static int cciss_setintinfo(ctlr_info_t *h, void __user *argp)
1322 {
1323 cciss_coalint_struct intinfo;
1324 unsigned long flags;
1325 int i;
1326
1327 if (!argp)
1328 return -EINVAL;
1329 if (!capable(CAP_SYS_ADMIN))
1330 return -EPERM;
1331 if (copy_from_user(&intinfo, argp, sizeof(intinfo)))
1332 return -EFAULT;
1333 if ((intinfo.delay == 0) && (intinfo.count == 0))
1334 return -EINVAL;
1335 spin_lock_irqsave(&h->lock, flags);
1336 /* Update the field, and then ring the doorbell */
1337 writel(intinfo.delay, &(h->cfgtable->HostWrite.CoalIntDelay));
1338 writel(intinfo.count, &(h->cfgtable->HostWrite.CoalIntCount));
1339 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
1340
1341 for (i = 0; i < MAX_IOCTL_CONFIG_WAIT; i++) {
1342 if (!(readl(h->vaddr + SA5_DOORBELL) & CFGTBL_ChangeReq))
1343 break;
1344 udelay(1000); /* delay and try again */
1345 }
1346 spin_unlock_irqrestore(&h->lock, flags);
1347 if (i >= MAX_IOCTL_CONFIG_WAIT)
1348 return -EAGAIN;
1349 return 0;
1350 }
1351
1352 static int cciss_getnodename(ctlr_info_t *h, void __user *argp)
1353 {
1354 NodeName_type NodeName;
1355 int i;
1356
1357 if (!argp)
1358 return -EINVAL;
1359 for (i = 0; i < 16; i++)
1360 NodeName[i] = readb(&h->cfgtable->ServerName[i]);
1361 if (copy_to_user(argp, NodeName, sizeof(NodeName_type)))
1362 return -EFAULT;
1363 return 0;
1364 }
1365
1366 static int cciss_setnodename(ctlr_info_t *h, void __user *argp)
1367 {
1368 NodeName_type NodeName;
1369 unsigned long flags;
1370 int i;
1371
1372 if (!argp)
1373 return -EINVAL;
1374 if (!capable(CAP_SYS_ADMIN))
1375 return -EPERM;
1376 if (copy_from_user(NodeName, argp, sizeof(NodeName_type)))
1377 return -EFAULT;
1378 spin_lock_irqsave(&h->lock, flags);
1379 /* Update the field, and then ring the doorbell */
1380 for (i = 0; i < 16; i++)
1381 writeb(NodeName[i], &h->cfgtable->ServerName[i]);
1382 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
1383 for (i = 0; i < MAX_IOCTL_CONFIG_WAIT; i++) {
1384 if (!(readl(h->vaddr + SA5_DOORBELL) & CFGTBL_ChangeReq))
1385 break;
1386 udelay(1000); /* delay and try again */
1387 }
1388 spin_unlock_irqrestore(&h->lock, flags);
1389 if (i >= MAX_IOCTL_CONFIG_WAIT)
1390 return -EAGAIN;
1391 return 0;
1392 }
1393
1394 static int cciss_getheartbeat(ctlr_info_t *h, void __user *argp)
1395 {
1396 Heartbeat_type heartbeat;
1397
1398 if (!argp)
1399 return -EINVAL;
1400 heartbeat = readl(&h->cfgtable->HeartBeat);
1401 if (copy_to_user(argp, &heartbeat, sizeof(Heartbeat_type)))
1402 return -EFAULT;
1403 return 0;
1404 }
1405
1406 static int cciss_getbustypes(ctlr_info_t *h, void __user *argp)
1407 {
1408 BusTypes_type BusTypes;
1409
1410 if (!argp)
1411 return -EINVAL;
1412 BusTypes = readl(&h->cfgtable->BusTypes);
1413 if (copy_to_user(argp, &BusTypes, sizeof(BusTypes_type)))
1414 return -EFAULT;
1415 return 0;
1416 }
1417
1418 static int cciss_getfirmver(ctlr_info_t *h, void __user *argp)
1419 {
1420 FirmwareVer_type firmware;
1421
1422 if (!argp)
1423 return -EINVAL;
1424 memcpy(firmware, h->firm_ver, 4);
1425
1426 if (copy_to_user
1427 (argp, firmware, sizeof(FirmwareVer_type)))
1428 return -EFAULT;
1429 return 0;
1430 }
1431
1432 static int cciss_getdrivver(ctlr_info_t *h, void __user *argp)
1433 {
1434 DriverVer_type DriverVer = DRIVER_VERSION;
1435
1436 if (!argp)
1437 return -EINVAL;
1438 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
1439 return -EFAULT;
1440 return 0;
1441 }
1442
1443 static int cciss_getluninfo(ctlr_info_t *h,
1444 struct gendisk *disk, void __user *argp)
1445 {
1446 LogvolInfo_struct luninfo;
1447 drive_info_struct *drv = get_drv(disk);
1448
1449 if (!argp)
1450 return -EINVAL;
1451 memcpy(&luninfo.LunID, drv->LunID, sizeof(luninfo.LunID));
1452 luninfo.num_opens = drv->usage_count;
1453 luninfo.num_parts = 0;
1454 if (copy_to_user(argp, &luninfo, sizeof(LogvolInfo_struct)))
1455 return -EFAULT;
1456 return 0;
1457 }
1458
1459 static int cciss_passthru(ctlr_info_t *h, void __user *argp)
1460 {
1461 IOCTL_Command_struct iocommand;
1462 CommandList_struct *c;
1463 char *buff = NULL;
1464 u64bit temp64;
1465 DECLARE_COMPLETION_ONSTACK(wait);
1466
1467 if (!argp)
1468 return -EINVAL;
1469
1470 if (!capable(CAP_SYS_RAWIO))
1471 return -EPERM;
1472
1473 if (copy_from_user
1474 (&iocommand, argp, sizeof(IOCTL_Command_struct)))
1475 return -EFAULT;
1476 if ((iocommand.buf_size < 1) &&
1477 (iocommand.Request.Type.Direction != XFER_NONE)) {
1478 return -EINVAL;
1479 }
1480 if (iocommand.buf_size > 0) {
1481 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
1482 if (buff == NULL)
1483 return -EFAULT;
1484 }
1485 if (iocommand.Request.Type.Direction == XFER_WRITE) {
1486 /* Copy the data into the buffer we created */
1487 if (copy_from_user(buff, iocommand.buf, iocommand.buf_size)) {
1488 kfree(buff);
1489 return -EFAULT;
1490 }
1491 } else {
1492 memset(buff, 0, iocommand.buf_size);
1493 }
1494 c = cmd_special_alloc(h);
1495 if (!c) {
1496 kfree(buff);
1497 return -ENOMEM;
1498 }
1499 /* Fill in the command type */
1500 c->cmd_type = CMD_IOCTL_PEND;
1501 /* Fill in Command Header */
1502 c->Header.ReplyQueue = 0; /* unused in simple mode */
1503 if (iocommand.buf_size > 0) { /* buffer to fill */
1504 c->Header.SGList = 1;
1505 c->Header.SGTotal = 1;
1506 } else { /* no buffers to fill */
1507 c->Header.SGList = 0;
1508 c->Header.SGTotal = 0;
1509 }
1510 c->Header.LUN = iocommand.LUN_info;
1511 /* use the kernel address the cmd block for tag */
1512 c->Header.Tag.lower = c->busaddr;
1513
1514 /* Fill in Request block */
1515 c->Request = iocommand.Request;
1516
1517 /* Fill in the scatter gather information */
1518 if (iocommand.buf_size > 0) {
1519 temp64.val = pci_map_single(h->pdev, buff,
1520 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
1521 c->SG[0].Addr.lower = temp64.val32.lower;
1522 c->SG[0].Addr.upper = temp64.val32.upper;
1523 c->SG[0].Len = iocommand.buf_size;
1524 c->SG[0].Ext = 0; /* we are not chaining */
1525 }
1526 c->waiting = &wait;
1527
1528 enqueue_cmd_and_start_io(h, c);
1529 wait_for_completion(&wait);
1530
1531 /* unlock the buffers from DMA */
1532 temp64.val32.lower = c->SG[0].Addr.lower;
1533 temp64.val32.upper = c->SG[0].Addr.upper;
1534 pci_unmap_single(h->pdev, (dma_addr_t) temp64.val, iocommand.buf_size,
1535 PCI_DMA_BIDIRECTIONAL);
1536 check_ioctl_unit_attention(h, c);
1537
1538 /* Copy the error information out */
1539 iocommand.error_info = *(c->err_info);
1540 if (copy_to_user(argp, &iocommand, sizeof(IOCTL_Command_struct))) {
1541 kfree(buff);
1542 cmd_special_free(h, c);
1543 return -EFAULT;
1544 }
1545
1546 if (iocommand.Request.Type.Direction == XFER_READ) {
1547 /* Copy the data out of the buffer we created */
1548 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
1549 kfree(buff);
1550 cmd_special_free(h, c);
1551 return -EFAULT;
1552 }
1553 }
1554 kfree(buff);
1555 cmd_special_free(h, c);
1556 return 0;
1557 }
1558
1559 static int cciss_bigpassthru(ctlr_info_t *h, void __user *argp)
1560 {
1561 BIG_IOCTL_Command_struct *ioc;
1562 CommandList_struct *c;
1563 unsigned char **buff = NULL;
1564 int *buff_size = NULL;
1565 u64bit temp64;
1566 BYTE sg_used = 0;
1567 int status = 0;
1568 int i;
1569 DECLARE_COMPLETION_ONSTACK(wait);
1570 __u32 left;
1571 __u32 sz;
1572 BYTE __user *data_ptr;
1573
1574 if (!argp)
1575 return -EINVAL;
1576 if (!capable(CAP_SYS_RAWIO))
1577 return -EPERM;
1578 ioc = kmalloc(sizeof(*ioc), GFP_KERNEL);
1579 if (!ioc) {
1580 status = -ENOMEM;
1581 goto cleanup1;
1582 }
1583 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
1584 status = -EFAULT;
1585 goto cleanup1;
1586 }
1587 if ((ioc->buf_size < 1) &&
1588 (ioc->Request.Type.Direction != XFER_NONE)) {
1589 status = -EINVAL;
1590 goto cleanup1;
1591 }
1592 /* Check kmalloc limits using all SGs */
1593 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
1594 status = -EINVAL;
1595 goto cleanup1;
1596 }
1597 if (ioc->buf_size > ioc->malloc_size * MAXSGENTRIES) {
1598 status = -EINVAL;
1599 goto cleanup1;
1600 }
1601 buff = kzalloc(MAXSGENTRIES * sizeof(char *), GFP_KERNEL);
1602 if (!buff) {
1603 status = -ENOMEM;
1604 goto cleanup1;
1605 }
1606 buff_size = kmalloc(MAXSGENTRIES * sizeof(int), GFP_KERNEL);
1607 if (!buff_size) {
1608 status = -ENOMEM;
1609 goto cleanup1;
1610 }
1611 left = ioc->buf_size;
1612 data_ptr = ioc->buf;
1613 while (left) {
1614 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
1615 buff_size[sg_used] = sz;
1616 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
1617 if (buff[sg_used] == NULL) {
1618 status = -ENOMEM;
1619 goto cleanup1;
1620 }
1621 if (ioc->Request.Type.Direction == XFER_WRITE) {
1622 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
1623 status = -EFAULT;
1624 goto cleanup1;
1625 }
1626 } else {
1627 memset(buff[sg_used], 0, sz);
1628 }
1629 left -= sz;
1630 data_ptr += sz;
1631 sg_used++;
1632 }
1633 c = cmd_special_alloc(h);
1634 if (!c) {
1635 status = -ENOMEM;
1636 goto cleanup1;
1637 }
1638 c->cmd_type = CMD_IOCTL_PEND;
1639 c->Header.ReplyQueue = 0;
1640 c->Header.SGList = sg_used;
1641 c->Header.SGTotal = sg_used;
1642 c->Header.LUN = ioc->LUN_info;
1643 c->Header.Tag.lower = c->busaddr;
1644
1645 c->Request = ioc->Request;
1646 for (i = 0; i < sg_used; i++) {
1647 temp64.val = pci_map_single(h->pdev, buff[i], buff_size[i],
1648 PCI_DMA_BIDIRECTIONAL);
1649 c->SG[i].Addr.lower = temp64.val32.lower;
1650 c->SG[i].Addr.upper = temp64.val32.upper;
1651 c->SG[i].Len = buff_size[i];
1652 c->SG[i].Ext = 0; /* we are not chaining */
1653 }
1654 c->waiting = &wait;
1655 enqueue_cmd_and_start_io(h, c);
1656 wait_for_completion(&wait);
1657 /* unlock the buffers from DMA */
1658 for (i = 0; i < sg_used; i++) {
1659 temp64.val32.lower = c->SG[i].Addr.lower;
1660 temp64.val32.upper = c->SG[i].Addr.upper;
1661 pci_unmap_single(h->pdev,
1662 (dma_addr_t) temp64.val, buff_size[i],
1663 PCI_DMA_BIDIRECTIONAL);
1664 }
1665 check_ioctl_unit_attention(h, c);
1666 /* Copy the error information out */
1667 ioc->error_info = *(c->err_info);
1668 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
1669 cmd_special_free(h, c);
1670 status = -EFAULT;
1671 goto cleanup1;
1672 }
1673 if (ioc->Request.Type.Direction == XFER_READ) {
1674 /* Copy the data out of the buffer we created */
1675 BYTE __user *ptr = ioc->buf;
1676 for (i = 0; i < sg_used; i++) {
1677 if (copy_to_user(ptr, buff[i], buff_size[i])) {
1678 cmd_special_free(h, c);
1679 status = -EFAULT;
1680 goto cleanup1;
1681 }
1682 ptr += buff_size[i];
1683 }
1684 }
1685 cmd_special_free(h, c);
1686 status = 0;
1687 cleanup1:
1688 if (buff) {
1689 for (i = 0; i < sg_used; i++)
1690 kfree(buff[i]);
1691 kfree(buff);
1692 }
1693 kfree(buff_size);
1694 kfree(ioc);
1695 return status;
1696 }
1697
1698 static int cciss_ioctl(struct block_device *bdev, fmode_t mode,
1699 unsigned int cmd, unsigned long arg)
1700 {
1701 struct gendisk *disk = bdev->bd_disk;
1702 ctlr_info_t *h = get_host(disk);
1703 void __user *argp = (void __user *)arg;
1704
1705 dev_dbg(&h->pdev->dev, "cciss_ioctl: Called with cmd=%x %lx\n",
1706 cmd, arg);
1707 switch (cmd) {
1708 case CCISS_GETPCIINFO:
1709 return cciss_getpciinfo(h, argp);
1710 case CCISS_GETINTINFO:
1711 return cciss_getintinfo(h, argp);
1712 case CCISS_SETINTINFO:
1713 return cciss_setintinfo(h, argp);
1714 case CCISS_GETNODENAME:
1715 return cciss_getnodename(h, argp);
1716 case CCISS_SETNODENAME:
1717 return cciss_setnodename(h, argp);
1718 case CCISS_GETHEARTBEAT:
1719 return cciss_getheartbeat(h, argp);
1720 case CCISS_GETBUSTYPES:
1721 return cciss_getbustypes(h, argp);
1722 case CCISS_GETFIRMVER:
1723 return cciss_getfirmver(h, argp);
1724 case CCISS_GETDRIVVER:
1725 return cciss_getdrivver(h, argp);
1726 case CCISS_DEREGDISK:
1727 case CCISS_REGNEWD:
1728 case CCISS_REVALIDVOLS:
1729 return rebuild_lun_table(h, 0, 1);
1730 case CCISS_GETLUNINFO:
1731 return cciss_getluninfo(h, disk, argp);
1732 case CCISS_PASSTHRU:
1733 return cciss_passthru(h, argp);
1734 case CCISS_BIG_PASSTHRU:
1735 return cciss_bigpassthru(h, argp);
1736
1737 /* scsi_cmd_ioctl handles these, below, though some are not */
1738 /* very meaningful for cciss. SG_IO is the main one people want. */
1739
1740 case SG_GET_VERSION_NUM:
1741 case SG_SET_TIMEOUT:
1742 case SG_GET_TIMEOUT:
1743 case SG_GET_RESERVED_SIZE:
1744 case SG_SET_RESERVED_SIZE:
1745 case SG_EMULATED_HOST:
1746 case SG_IO:
1747 case SCSI_IOCTL_SEND_COMMAND:
1748 return scsi_cmd_ioctl(disk->queue, disk, mode, cmd, argp);
1749
1750 /* scsi_cmd_ioctl would normally handle these, below, but */
1751 /* they aren't a good fit for cciss, as CD-ROMs are */
1752 /* not supported, and we don't have any bus/target/lun */
1753 /* which we present to the kernel. */
1754
1755 case CDROM_SEND_PACKET:
1756 case CDROMCLOSETRAY:
1757 case CDROMEJECT:
1758 case SCSI_IOCTL_GET_IDLUN:
1759 case SCSI_IOCTL_GET_BUS_NUMBER:
1760 default:
1761 return -ENOTTY;
1762 }
1763 }
1764
1765 static void cciss_check_queues(ctlr_info_t *h)
1766 {
1767 int start_queue = h->next_to_run;
1768 int i;
1769
1770 /* check to see if we have maxed out the number of commands that can
1771 * be placed on the queue. If so then exit. We do this check here
1772 * in case the interrupt we serviced was from an ioctl and did not
1773 * free any new commands.
1774 */
1775 if ((find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds)) == h->nr_cmds)
1776 return;
1777
1778 /* We have room on the queue for more commands. Now we need to queue
1779 * them up. We will also keep track of the next queue to run so
1780 * that every queue gets a chance to be started first.
1781 */
1782 for (i = 0; i < h->highest_lun + 1; i++) {
1783 int curr_queue = (start_queue + i) % (h->highest_lun + 1);
1784 /* make sure the disk has been added and the drive is real
1785 * because this can be called from the middle of init_one.
1786 */
1787 if (!h->drv[curr_queue])
1788 continue;
1789 if (!(h->drv[curr_queue]->queue) ||
1790 !(h->drv[curr_queue]->heads))
1791 continue;
1792 blk_start_queue(h->gendisk[curr_queue]->queue);
1793
1794 /* check to see if we have maxed out the number of commands
1795 * that can be placed on the queue.
1796 */
1797 if ((find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds)) == h->nr_cmds) {
1798 if (curr_queue == start_queue) {
1799 h->next_to_run =
1800 (start_queue + 1) % (h->highest_lun + 1);
1801 break;
1802 } else {
1803 h->next_to_run = curr_queue;
1804 break;
1805 }
1806 }
1807 }
1808 }
1809
1810 static void cciss_softirq_done(struct request *rq)
1811 {
1812 CommandList_struct *c = rq->completion_data;
1813 ctlr_info_t *h = hba[c->ctlr];
1814 SGDescriptor_struct *curr_sg = c->SG;
1815 u64bit temp64;
1816 unsigned long flags;
1817 int i, ddir;
1818 int sg_index = 0;
1819
1820 if (c->Request.Type.Direction == XFER_READ)
1821 ddir = PCI_DMA_FROMDEVICE;
1822 else
1823 ddir = PCI_DMA_TODEVICE;
1824
1825 /* command did not need to be retried */
1826 /* unmap the DMA mapping for all the scatter gather elements */
1827 for (i = 0; i < c->Header.SGList; i++) {
1828 if (curr_sg[sg_index].Ext == CCISS_SG_CHAIN) {
1829 cciss_unmap_sg_chain_block(h, c);
1830 /* Point to the next block */
1831 curr_sg = h->cmd_sg_list[c->cmdindex];
1832 sg_index = 0;
1833 }
1834 temp64.val32.lower = curr_sg[sg_index].Addr.lower;
1835 temp64.val32.upper = curr_sg[sg_index].Addr.upper;
1836 pci_unmap_page(h->pdev, temp64.val, curr_sg[sg_index].Len,
1837 ddir);
1838 ++sg_index;
1839 }
1840
1841 dev_dbg(&h->pdev->dev, "Done with %p\n", rq);
1842
1843 /* set the residual count for pc requests */
1844 if (rq->cmd_type == REQ_TYPE_BLOCK_PC)
1845 rq->resid_len = c->err_info->ResidualCnt;
1846
1847 blk_end_request_all(rq, (rq->errors == 0) ? 0 : -EIO);
1848
1849 spin_lock_irqsave(&h->lock, flags);
1850 cmd_free(h, c);
1851 cciss_check_queues(h);
1852 spin_unlock_irqrestore(&h->lock, flags);
1853 }
1854
1855 static inline void log_unit_to_scsi3addr(ctlr_info_t *h,
1856 unsigned char scsi3addr[], uint32_t log_unit)
1857 {
1858 memcpy(scsi3addr, h->drv[log_unit]->LunID,
1859 sizeof(h->drv[log_unit]->LunID));
1860 }
1861
1862 /* This function gets the SCSI vendor, model, and revision of a logical drive
1863 * via the inquiry page 0. Model, vendor, and rev are set to empty strings if
1864 * they cannot be read.
1865 */
1866 static void cciss_get_device_descr(ctlr_info_t *h, int logvol,
1867 char *vendor, char *model, char *rev)
1868 {
1869 int rc;
1870 InquiryData_struct *inq_buf;
1871 unsigned char scsi3addr[8];
1872
1873 *vendor = '\0';
1874 *model = '\0';
1875 *rev = '\0';
1876
1877 inq_buf = kzalloc(sizeof(InquiryData_struct), GFP_KERNEL);
1878 if (!inq_buf)
1879 return;
1880
1881 log_unit_to_scsi3addr(h, scsi3addr, logvol);
1882 rc = sendcmd_withirq(h, CISS_INQUIRY, inq_buf, sizeof(*inq_buf), 0,
1883 scsi3addr, TYPE_CMD);
1884 if (rc == IO_OK) {
1885 memcpy(vendor, &inq_buf->data_byte[8], VENDOR_LEN);
1886 vendor[VENDOR_LEN] = '\0';
1887 memcpy(model, &inq_buf->data_byte[16], MODEL_LEN);
1888 model[MODEL_LEN] = '\0';
1889 memcpy(rev, &inq_buf->data_byte[32], REV_LEN);
1890 rev[REV_LEN] = '\0';
1891 }
1892
1893 kfree(inq_buf);
1894 return;
1895 }
1896
1897 /* This function gets the serial number of a logical drive via
1898 * inquiry page 0x83. Serial no. is 16 bytes. If the serial
1899 * number cannot be had, for whatever reason, 16 bytes of 0xff
1900 * are returned instead.
1901 */
1902 static void cciss_get_serial_no(ctlr_info_t *h, int logvol,
1903 unsigned char *serial_no, int buflen)
1904 {
1905 #define PAGE_83_INQ_BYTES 64
1906 int rc;
1907 unsigned char *buf;
1908 unsigned char scsi3addr[8];
1909
1910 if (buflen > 16)
1911 buflen = 16;
1912 memset(serial_no, 0xff, buflen);
1913 buf = kzalloc(PAGE_83_INQ_BYTES, GFP_KERNEL);
1914 if (!buf)
1915 return;
1916 memset(serial_no, 0, buflen);
1917 log_unit_to_scsi3addr(h, scsi3addr, logvol);
1918 rc = sendcmd_withirq(h, CISS_INQUIRY, buf,
1919 PAGE_83_INQ_BYTES, 0x83, scsi3addr, TYPE_CMD);
1920 if (rc == IO_OK)
1921 memcpy(serial_no, &buf[8], buflen);
1922 kfree(buf);
1923 return;
1924 }
1925
1926 /*
1927 * cciss_add_disk sets up the block device queue for a logical drive
1928 */
1929 static int cciss_add_disk(ctlr_info_t *h, struct gendisk *disk,
1930 int drv_index)
1931 {
1932 disk->queue = blk_init_queue(do_cciss_request, &h->lock);
1933 if (!disk->queue)
1934 goto init_queue_failure;
1935 sprintf(disk->disk_name, "cciss/c%dd%d", h->ctlr, drv_index);
1936 disk->major = h->major;
1937 disk->first_minor = drv_index << NWD_SHIFT;
1938 disk->fops = &cciss_fops;
1939 if (cciss_create_ld_sysfs_entry(h, drv_index))
1940 goto cleanup_queue;
1941 disk->private_data = h->drv[drv_index];
1942 disk->driverfs_dev = &h->drv[drv_index]->dev;
1943
1944 /* Set up queue information */
1945 blk_queue_bounce_limit(disk->queue, h->pdev->dma_mask);
1946
1947 /* This is a hardware imposed limit. */
1948 blk_queue_max_segments(disk->queue, h->maxsgentries);
1949
1950 blk_queue_max_hw_sectors(disk->queue, h->cciss_max_sectors);
1951
1952 blk_queue_softirq_done(disk->queue, cciss_softirq_done);
1953
1954 disk->queue->queuedata = h;
1955
1956 blk_queue_logical_block_size(disk->queue,
1957 h->drv[drv_index]->block_size);
1958
1959 /* Make sure all queue data is written out before */
1960 /* setting h->drv[drv_index]->queue, as setting this */
1961 /* allows the interrupt handler to start the queue */
1962 wmb();
1963 h->drv[drv_index]->queue = disk->queue;
1964 add_disk(disk);
1965 return 0;
1966
1967 cleanup_queue:
1968 blk_cleanup_queue(disk->queue);
1969 disk->queue = NULL;
1970 init_queue_failure:
1971 return -1;
1972 }
1973
1974 /* This function will check the usage_count of the drive to be updated/added.
1975 * If the usage_count is zero and it is a heretofore unknown drive, or,
1976 * the drive's capacity, geometry, or serial number has changed,
1977 * then the drive information will be updated and the disk will be
1978 * re-registered with the kernel. If these conditions don't hold,
1979 * then it will be left alone for the next reboot. The exception to this
1980 * is disk 0 which will always be left registered with the kernel since it
1981 * is also the controller node. Any changes to disk 0 will show up on
1982 * the next reboot.
1983 */
1984 static void cciss_update_drive_info(ctlr_info_t *h, int drv_index,
1985 int first_time, int via_ioctl)
1986 {
1987 struct gendisk *disk;
1988 InquiryData_struct *inq_buff = NULL;
1989 unsigned int block_size;
1990 sector_t total_size;
1991 unsigned long flags = 0;
1992 int ret = 0;
1993 drive_info_struct *drvinfo;
1994
1995 /* Get information about the disk and modify the driver structure */
1996 inq_buff = kmalloc(sizeof(InquiryData_struct), GFP_KERNEL);
1997 drvinfo = kzalloc(sizeof(*drvinfo), GFP_KERNEL);
1998 if (inq_buff == NULL || drvinfo == NULL)
1999 goto mem_msg;
2000
2001 /* testing to see if 16-byte CDBs are already being used */
2002 if (h->cciss_read == CCISS_READ_16) {
2003 cciss_read_capacity_16(h, drv_index,
2004 &total_size, &block_size);
2005
2006 } else {
2007 cciss_read_capacity(h, drv_index, &total_size, &block_size);
2008 /* if read_capacity returns all F's this volume is >2TB */
2009 /* in size so we switch to 16-byte CDB's for all */
2010 /* read/write ops */
2011 if (total_size == 0xFFFFFFFFULL) {
2012 cciss_read_capacity_16(h, drv_index,
2013 &total_size, &block_size);
2014 h->cciss_read = CCISS_READ_16;
2015 h->cciss_write = CCISS_WRITE_16;
2016 } else {
2017 h->cciss_read = CCISS_READ_10;
2018 h->cciss_write = CCISS_WRITE_10;
2019 }
2020 }
2021
2022 cciss_geometry_inquiry(h, drv_index, total_size, block_size,
2023 inq_buff, drvinfo);
2024 drvinfo->block_size = block_size;
2025 drvinfo->nr_blocks = total_size + 1;
2026
2027 cciss_get_device_descr(h, drv_index, drvinfo->vendor,
2028 drvinfo->model, drvinfo->rev);
2029 cciss_get_serial_no(h, drv_index, drvinfo->serial_no,
2030 sizeof(drvinfo->serial_no));
2031 /* Save the lunid in case we deregister the disk, below. */
2032 memcpy(drvinfo->LunID, h->drv[drv_index]->LunID,
2033 sizeof(drvinfo->LunID));
2034
2035 /* Is it the same disk we already know, and nothing's changed? */
2036 if (h->drv[drv_index]->raid_level != -1 &&
2037 ((memcmp(drvinfo->serial_no,
2038 h->drv[drv_index]->serial_no, 16) == 0) &&
2039 drvinfo->block_size == h->drv[drv_index]->block_size &&
2040 drvinfo->nr_blocks == h->drv[drv_index]->nr_blocks &&
2041 drvinfo->heads == h->drv[drv_index]->heads &&
2042 drvinfo->sectors == h->drv[drv_index]->sectors &&
2043 drvinfo->cylinders == h->drv[drv_index]->cylinders))
2044 /* The disk is unchanged, nothing to update */
2045 goto freeret;
2046
2047 /* If we get here it's not the same disk, or something's changed,
2048 * so we need to * deregister it, and re-register it, if it's not
2049 * in use.
2050 * If the disk already exists then deregister it before proceeding
2051 * (unless it's the first disk (for the controller node).
2052 */
2053 if (h->drv[drv_index]->raid_level != -1 && drv_index != 0) {
2054 dev_warn(&h->pdev->dev, "disk %d has changed.\n", drv_index);
2055 spin_lock_irqsave(&h->lock, flags);
2056 h->drv[drv_index]->busy_configuring = 1;
2057 spin_unlock_irqrestore(&h->lock, flags);
2058
2059 /* deregister_disk sets h->drv[drv_index]->queue = NULL
2060 * which keeps the interrupt handler from starting
2061 * the queue.
2062 */
2063 ret = deregister_disk(h, drv_index, 0, via_ioctl);
2064 }
2065
2066 /* If the disk is in use return */
2067 if (ret)
2068 goto freeret;
2069
2070 /* Save the new information from cciss_geometry_inquiry
2071 * and serial number inquiry. If the disk was deregistered
2072 * above, then h->drv[drv_index] will be NULL.
2073 */
2074 if (h->drv[drv_index] == NULL) {
2075 drvinfo->device_initialized = 0;
2076 h->drv[drv_index] = drvinfo;
2077 drvinfo = NULL; /* so it won't be freed below. */
2078 } else {
2079 /* special case for cxd0 */
2080 h->drv[drv_index]->block_size = drvinfo->block_size;
2081 h->drv[drv_index]->nr_blocks = drvinfo->nr_blocks;
2082 h->drv[drv_index]->heads = drvinfo->heads;
2083 h->drv[drv_index]->sectors = drvinfo->sectors;
2084 h->drv[drv_index]->cylinders = drvinfo->cylinders;
2085 h->drv[drv_index]->raid_level = drvinfo->raid_level;
2086 memcpy(h->drv[drv_index]->serial_no, drvinfo->serial_no, 16);
2087 memcpy(h->drv[drv_index]->vendor, drvinfo->vendor,
2088 VENDOR_LEN + 1);
2089 memcpy(h->drv[drv_index]->model, drvinfo->model, MODEL_LEN + 1);
2090 memcpy(h->drv[drv_index]->rev, drvinfo->rev, REV_LEN + 1);
2091 }
2092
2093 ++h->num_luns;
2094 disk = h->gendisk[drv_index];
2095 set_capacity(disk, h->drv[drv_index]->nr_blocks);
2096
2097 /* If it's not disk 0 (drv_index != 0)
2098 * or if it was disk 0, but there was previously
2099 * no actual corresponding configured logical drive
2100 * (raid_leve == -1) then we want to update the
2101 * logical drive's information.
2102 */
2103 if (drv_index || first_time) {
2104 if (cciss_add_disk(h, disk, drv_index) != 0) {
2105 cciss_free_gendisk(h, drv_index);
2106 cciss_free_drive_info(h, drv_index);
2107 dev_warn(&h->pdev->dev, "could not update disk %d\n",
2108 drv_index);
2109 --h->num_luns;
2110 }
2111 }
2112
2113 freeret:
2114 kfree(inq_buff);
2115 kfree(drvinfo);
2116 return;
2117 mem_msg:
2118 dev_err(&h->pdev->dev, "out of memory\n");
2119 goto freeret;
2120 }
2121
2122 /* This function will find the first index of the controllers drive array
2123 * that has a null drv pointer and allocate the drive info struct and
2124 * will return that index This is where new drives will be added.
2125 * If the index to be returned is greater than the highest_lun index for
2126 * the controller then highest_lun is set * to this new index.
2127 * If there are no available indexes or if tha allocation fails, then -1
2128 * is returned. * "controller_node" is used to know if this is a real
2129 * logical drive, or just the controller node, which determines if this
2130 * counts towards highest_lun.
2131 */
2132 static int cciss_alloc_drive_info(ctlr_info_t *h, int controller_node)
2133 {
2134 int i;
2135 drive_info_struct *drv;
2136
2137 /* Search for an empty slot for our drive info */
2138 for (i = 0; i < CISS_MAX_LUN; i++) {
2139
2140 /* if not cxd0 case, and it's occupied, skip it. */
2141 if (h->drv[i] && i != 0)
2142 continue;
2143 /*
2144 * If it's cxd0 case, and drv is alloc'ed already, and a
2145 * disk is configured there, skip it.
2146 */
2147 if (i == 0 && h->drv[i] && h->drv[i]->raid_level != -1)
2148 continue;
2149
2150 /*
2151 * We've found an empty slot. Update highest_lun
2152 * provided this isn't just the fake cxd0 controller node.
2153 */
2154 if (i > h->highest_lun && !controller_node)
2155 h->highest_lun = i;
2156
2157 /* If adding a real disk at cxd0, and it's already alloc'ed */
2158 if (i == 0 && h->drv[i] != NULL)
2159 return i;
2160
2161 /*
2162 * Found an empty slot, not already alloc'ed. Allocate it.
2163 * Mark it with raid_level == -1, so we know it's new later on.
2164 */
2165 drv = kzalloc(sizeof(*drv), GFP_KERNEL);
2166 if (!drv)
2167 return -1;
2168 drv->raid_level = -1; /* so we know it's new */
2169 h->drv[i] = drv;
2170 return i;
2171 }
2172 return -1;
2173 }
2174
2175 static void cciss_free_drive_info(ctlr_info_t *h, int drv_index)
2176 {
2177 kfree(h->drv[drv_index]);
2178 h->drv[drv_index] = NULL;
2179 }
2180
2181 static void cciss_free_gendisk(ctlr_info_t *h, int drv_index)
2182 {
2183 put_disk(h->gendisk[drv_index]);
2184 h->gendisk[drv_index] = NULL;
2185 }
2186
2187 /* cciss_add_gendisk finds a free hba[]->drv structure
2188 * and allocates a gendisk if needed, and sets the lunid
2189 * in the drvinfo structure. It returns the index into
2190 * the ->drv[] array, or -1 if none are free.
2191 * is_controller_node indicates whether highest_lun should
2192 * count this disk, or if it's only being added to provide
2193 * a means to talk to the controller in case no logical
2194 * drives have yet been configured.
2195 */
2196 static int cciss_add_gendisk(ctlr_info_t *h, unsigned char lunid[],
2197 int controller_node)
2198 {
2199 int drv_index;
2200
2201 drv_index = cciss_alloc_drive_info(h, controller_node);
2202 if (drv_index == -1)
2203 return -1;
2204
2205 /*Check if the gendisk needs to be allocated */
2206 if (!h->gendisk[drv_index]) {
2207 h->gendisk[drv_index] =
2208 alloc_disk(1 << NWD_SHIFT);
2209 if (!h->gendisk[drv_index]) {
2210 dev_err(&h->pdev->dev,
2211 "could not allocate a new disk %d\n",
2212 drv_index);
2213 goto err_free_drive_info;
2214 }
2215 }
2216 memcpy(h->drv[drv_index]->LunID, lunid,
2217 sizeof(h->drv[drv_index]->LunID));
2218 if (cciss_create_ld_sysfs_entry(h, drv_index))
2219 goto err_free_disk;
2220 /* Don't need to mark this busy because nobody */
2221 /* else knows about this disk yet to contend */
2222 /* for access to it. */
2223 h->drv[drv_index]->busy_configuring = 0;
2224 wmb();
2225 return drv_index;
2226
2227 err_free_disk:
2228 cciss_free_gendisk(h, drv_index);
2229 err_free_drive_info:
2230 cciss_free_drive_info(h, drv_index);
2231 return -1;
2232 }
2233
2234 /* This is for the special case of a controller which
2235 * has no logical drives. In this case, we still need
2236 * to register a disk so the controller can be accessed
2237 * by the Array Config Utility.
2238 */
2239 static void cciss_add_controller_node(ctlr_info_t *h)
2240 {
2241 struct gendisk *disk;
2242 int drv_index;
2243
2244 if (h->gendisk[0] != NULL) /* already did this? Then bail. */
2245 return;
2246
2247 drv_index = cciss_add_gendisk(h, CTLR_LUNID, 1);
2248 if (drv_index == -1)
2249 goto error;
2250 h->drv[drv_index]->block_size = 512;
2251 h->drv[drv_index]->nr_blocks = 0;
2252 h->drv[drv_index]->heads = 0;
2253 h->drv[drv_index]->sectors = 0;
2254 h->drv[drv_index]->cylinders = 0;
2255 h->drv[drv_index]->raid_level = -1;
2256 memset(h->drv[drv_index]->serial_no, 0, 16);
2257 disk = h->gendisk[drv_index];
2258 if (cciss_add_disk(h, disk, drv_index) == 0)
2259 return;
2260 cciss_free_gendisk(h, drv_index);
2261 cciss_free_drive_info(h, drv_index);
2262 error:
2263 dev_warn(&h->pdev->dev, "could not add disk 0.\n");
2264 return;
2265 }
2266
2267 /* This function will add and remove logical drives from the Logical
2268 * drive array of the controller and maintain persistency of ordering
2269 * so that mount points are preserved until the next reboot. This allows
2270 * for the removal of logical drives in the middle of the drive array
2271 * without a re-ordering of those drives.
2272 * INPUT
2273 * h = The controller to perform the operations on
2274 */
2275 static int rebuild_lun_table(ctlr_info_t *h, int first_time,
2276 int via_ioctl)
2277 {
2278 int num_luns;
2279 ReportLunData_struct *ld_buff = NULL;
2280 int return_code;
2281 int listlength = 0;
2282 int i;
2283 int drv_found;
2284 int drv_index = 0;
2285 unsigned char lunid[8] = CTLR_LUNID;
2286 unsigned long flags;
2287
2288 if (!capable(CAP_SYS_RAWIO))
2289 return -EPERM;
2290
2291 /* Set busy_configuring flag for this operation */
2292 spin_lock_irqsave(&h->lock, flags);
2293 if (h->busy_configuring) {
2294 spin_unlock_irqrestore(&h->lock, flags);
2295 return -EBUSY;
2296 }
2297 h->busy_configuring = 1;
2298 spin_unlock_irqrestore(&h->lock, flags);
2299
2300 ld_buff = kzalloc(sizeof(ReportLunData_struct), GFP_KERNEL);
2301 if (ld_buff == NULL)
2302 goto mem_msg;
2303
2304 return_code = sendcmd_withirq(h, CISS_REPORT_LOG, ld_buff,
2305 sizeof(ReportLunData_struct),
2306 0, CTLR_LUNID, TYPE_CMD);
2307
2308 if (return_code == IO_OK)
2309 listlength = be32_to_cpu(*(__be32 *) ld_buff->LUNListLength);
2310 else { /* reading number of logical volumes failed */
2311 dev_warn(&h->pdev->dev,
2312 "report logical volume command failed\n");
2313 listlength = 0;
2314 goto freeret;
2315 }
2316
2317 num_luns = listlength / 8; /* 8 bytes per entry */
2318 if (num_luns > CISS_MAX_LUN) {
2319 num_luns = CISS_MAX_LUN;
2320 dev_warn(&h->pdev->dev, "more luns configured"
2321 " on controller than can be handled by"
2322 " this driver.\n");
2323 }
2324
2325 if (num_luns == 0)
2326 cciss_add_controller_node(h);
2327
2328 /* Compare controller drive array to driver's drive array
2329 * to see if any drives are missing on the controller due
2330 * to action of Array Config Utility (user deletes drive)
2331 * and deregister logical drives which have disappeared.
2332 */
2333 for (i = 0; i <= h->highest_lun; i++) {
2334 int j;
2335 drv_found = 0;
2336
2337 /* skip holes in the array from already deleted drives */
2338 if (h->drv[i] == NULL)
2339 continue;
2340
2341 for (j = 0; j < num_luns; j++) {
2342 memcpy(lunid, &ld_buff->LUN[j][0], sizeof(lunid));
2343 if (memcmp(h->drv[i]->LunID, lunid,
2344 sizeof(lunid)) == 0) {
2345 drv_found = 1;
2346 break;
2347 }
2348 }
2349 if (!drv_found) {
2350 /* Deregister it from the OS, it's gone. */
2351 spin_lock_irqsave(&h->lock, flags);
2352 h->drv[i]->busy_configuring = 1;
2353 spin_unlock_irqrestore(&h->lock, flags);
2354 return_code = deregister_disk(h, i, 1, via_ioctl);
2355 if (h->drv[i] != NULL)
2356 h->drv[i]->busy_configuring = 0;
2357 }
2358 }
2359
2360 /* Compare controller drive array to driver's drive array.
2361 * Check for updates in the drive information and any new drives
2362 * on the controller due to ACU adding logical drives, or changing
2363 * a logical drive's size, etc. Reregister any new/changed drives
2364 */
2365 for (i = 0; i < num_luns; i++) {
2366 int j;
2367
2368 drv_found = 0;
2369
2370 memcpy(lunid, &ld_buff->LUN[i][0], sizeof(lunid));
2371 /* Find if the LUN is already in the drive array
2372 * of the driver. If so then update its info
2373 * if not in use. If it does not exist then find
2374 * the first free index and add it.
2375 */
2376 for (j = 0; j <= h->highest_lun; j++) {
2377 if (h->drv[j] != NULL &&
2378 memcmp(h->drv[j]->LunID, lunid,
2379 sizeof(h->drv[j]->LunID)) == 0) {
2380 drv_index = j;
2381 drv_found = 1;
2382 break;
2383 }
2384 }
2385
2386 /* check if the drive was found already in the array */
2387 if (!drv_found) {
2388 drv_index = cciss_add_gendisk(h, lunid, 0);
2389 if (drv_index == -1)
2390 goto freeret;
2391 }
2392 cciss_update_drive_info(h, drv_index, first_time, via_ioctl);
2393 } /* end for */
2394
2395 freeret:
2396 kfree(ld_buff);
2397 h->busy_configuring = 0;
2398 /* We return -1 here to tell the ACU that we have registered/updated
2399 * all of the drives that we can and to keep it from calling us
2400 * additional times.
2401 */
2402 return -1;
2403 mem_msg:
2404 dev_err(&h->pdev->dev, "out of memory\n");
2405 h->busy_configuring = 0;
2406 goto freeret;
2407 }
2408
2409 static void cciss_clear_drive_info(drive_info_struct *drive_info)
2410 {
2411 /* zero out the disk size info */
2412 drive_info->nr_blocks = 0;
2413 drive_info->block_size = 0;
2414 drive_info->heads = 0;
2415 drive_info->sectors = 0;
2416 drive_info->cylinders = 0;
2417 drive_info->raid_level = -1;
2418 memset(drive_info->serial_no, 0, sizeof(drive_info->serial_no));
2419 memset(drive_info->model, 0, sizeof(drive_info->model));
2420 memset(drive_info->rev, 0, sizeof(drive_info->rev));
2421 memset(drive_info->vendor, 0, sizeof(drive_info->vendor));
2422 /*
2423 * don't clear the LUNID though, we need to remember which
2424 * one this one is.
2425 */
2426 }
2427
2428 /* This function will deregister the disk and it's queue from the
2429 * kernel. It must be called with the controller lock held and the
2430 * drv structures busy_configuring flag set. It's parameters are:
2431 *
2432 * disk = This is the disk to be deregistered
2433 * drv = This is the drive_info_struct associated with the disk to be
2434 * deregistered. It contains information about the disk used
2435 * by the driver.
2436 * clear_all = This flag determines whether or not the disk information
2437 * is going to be completely cleared out and the highest_lun
2438 * reset. Sometimes we want to clear out information about
2439 * the disk in preparation for re-adding it. In this case
2440 * the highest_lun should be left unchanged and the LunID
2441 * should not be cleared.
2442 * via_ioctl
2443 * This indicates whether we've reached this path via ioctl.
2444 * This affects the maximum usage count allowed for c0d0 to be messed with.
2445 * If this path is reached via ioctl(), then the max_usage_count will
2446 * be 1, as the process calling ioctl() has got to have the device open.
2447 * If we get here via sysfs, then the max usage count will be zero.
2448 */
2449 static int deregister_disk(ctlr_info_t *h, int drv_index,
2450 int clear_all, int via_ioctl)
2451 {
2452 int i;
2453 struct gendisk *disk;
2454 drive_info_struct *drv;
2455 int recalculate_highest_lun;
2456
2457 if (!capable(CAP_SYS_RAWIO))
2458 return -EPERM;
2459
2460 drv = h->drv[drv_index];
2461 disk = h->gendisk[drv_index];
2462
2463 /* make sure logical volume is NOT is use */
2464 if (clear_all || (h->gendisk[0] == disk)) {
2465 if (drv->usage_count > via_ioctl)
2466 return -EBUSY;
2467 } else if (drv->usage_count > 0)
2468 return -EBUSY;
2469
2470 recalculate_highest_lun = (drv == h->drv[h->highest_lun]);
2471
2472 /* invalidate the devices and deregister the disk. If it is disk
2473 * zero do not deregister it but just zero out it's values. This
2474 * allows us to delete disk zero but keep the controller registered.
2475 */
2476 if (h->gendisk[0] != disk) {
2477 struct request_queue *q = disk->queue;
2478 if (disk->flags & GENHD_FL_UP) {
2479 cciss_destroy_ld_sysfs_entry(h, drv_index, 0);
2480 del_gendisk(disk);
2481 }
2482 if (q)
2483 blk_cleanup_queue(q);
2484 /* If clear_all is set then we are deleting the logical
2485 * drive, not just refreshing its info. For drives
2486 * other than disk 0 we will call put_disk. We do not
2487 * do this for disk 0 as we need it to be able to
2488 * configure the controller.
2489 */
2490 if (clear_all){
2491 /* This isn't pretty, but we need to find the
2492 * disk in our array and NULL our the pointer.
2493 * This is so that we will call alloc_disk if
2494 * this index is used again later.
2495 */
2496 for (i=0; i < CISS_MAX_LUN; i++){
2497 if (h->gendisk[i] == disk) {
2498 h->gendisk[i] = NULL;
2499 break;
2500 }
2501 }
2502 put_disk(disk);
2503 }
2504 } else {
2505 set_capacity(disk, 0);
2506 cciss_clear_drive_info(drv);
2507 }
2508
2509 --h->num_luns;
2510
2511 /* if it was the last disk, find the new hightest lun */
2512 if (clear_all && recalculate_highest_lun) {
2513 int newhighest = -1;
2514 for (i = 0; i <= h->highest_lun; i++) {
2515 /* if the disk has size > 0, it is available */
2516 if (h->drv[i] && h->drv[i]->heads)
2517 newhighest = i;
2518 }
2519 h->highest_lun = newhighest;
2520 }
2521 return 0;
2522 }
2523
2524 static int fill_cmd(ctlr_info_t *h, CommandList_struct *c, __u8 cmd, void *buff,
2525 size_t size, __u8 page_code, unsigned char *scsi3addr,
2526 int cmd_type)
2527 {
2528 u64bit buff_dma_handle;
2529 int status = IO_OK;
2530
2531 c->cmd_type = CMD_IOCTL_PEND;
2532 c->Header.ReplyQueue = 0;
2533 if (buff != NULL) {
2534 c->Header.SGList = 1;
2535 c->Header.SGTotal = 1;
2536 } else {
2537 c->Header.SGList = 0;
2538 c->Header.SGTotal = 0;
2539 }
2540 c->Header.Tag.lower = c->busaddr;
2541 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
2542
2543 c->Request.Type.Type = cmd_type;
2544 if (cmd_type == TYPE_CMD) {
2545 switch (cmd) {
2546 case CISS_INQUIRY:
2547 /* are we trying to read a vital product page */
2548 if (page_code != 0) {
2549 c->Request.CDB[1] = 0x01;
2550 c->Request.CDB[2] = page_code;
2551 }
2552 c->Request.CDBLen = 6;
2553 c->Request.Type.Attribute = ATTR_SIMPLE;
2554 c->Request.Type.Direction = XFER_READ;
2555 c->Request.Timeout = 0;
2556 c->Request.CDB[0] = CISS_INQUIRY;
2557 c->Request.CDB[4] = size & 0xFF;
2558 break;
2559 case CISS_REPORT_LOG:
2560 case CISS_REPORT_PHYS:
2561 /* Talking to controller so It's a physical command
2562 mode = 00 target = 0. Nothing to write.
2563 */
2564 c->Request.CDBLen = 12;
2565 c->Request.Type.Attribute = ATTR_SIMPLE;
2566 c->Request.Type.Direction = XFER_READ;
2567 c->Request.Timeout = 0;
2568 c->Request.CDB[0] = cmd;
2569 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
2570 c->Request.CDB[7] = (size >> 16) & 0xFF;
2571 c->Request.CDB[8] = (size >> 8) & 0xFF;
2572 c->Request.CDB[9] = size & 0xFF;
2573 break;
2574
2575 case CCISS_READ_CAPACITY:
2576 c->Request.CDBLen = 10;
2577 c->Request.Type.Attribute = ATTR_SIMPLE;
2578 c->Request.Type.Direction = XFER_READ;
2579 c->Request.Timeout = 0;
2580 c->Request.CDB[0] = cmd;
2581 break;
2582 case CCISS_READ_CAPACITY_16:
2583 c->Request.CDBLen = 16;
2584 c->Request.Type.Attribute = ATTR_SIMPLE;
2585 c->Request.Type.Direction = XFER_READ;
2586 c->Request.Timeout = 0;
2587 c->Request.CDB[0] = cmd;
2588 c->Request.CDB[1] = 0x10;
2589 c->Request.CDB[10] = (size >> 24) & 0xFF;
2590 c->Request.CDB[11] = (size >> 16) & 0xFF;
2591 c->Request.CDB[12] = (size >> 8) & 0xFF;
2592 c->Request.CDB[13] = size & 0xFF;
2593 c->Request.Timeout = 0;
2594 c->Request.CDB[0] = cmd;
2595 break;
2596 case CCISS_CACHE_FLUSH:
2597 c->Request.CDBLen = 12;
2598 c->Request.Type.Attribute = ATTR_SIMPLE;
2599 c->Request.Type.Direction = XFER_WRITE;
2600 c->Request.Timeout = 0;
2601 c->Request.CDB[0] = BMIC_WRITE;
2602 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
2603 break;
2604 case TEST_UNIT_READY:
2605 c->Request.CDBLen = 6;
2606 c->Request.Type.Attribute = ATTR_SIMPLE;
2607 c->Request.Type.Direction = XFER_NONE;
2608 c->Request.Timeout = 0;
2609 break;
2610 default:
2611 dev_warn(&h->pdev->dev, "Unknown Command 0x%c\n", cmd);
2612 return IO_ERROR;
2613 }
2614 } else if (cmd_type == TYPE_MSG) {
2615 switch (cmd) {
2616 case CCISS_ABORT_MSG:
2617 c->Request.CDBLen = 12;
2618 c->Request.Type.Attribute = ATTR_SIMPLE;
2619 c->Request.Type.Direction = XFER_WRITE;
2620 c->Request.Timeout = 0;
2621 c->Request.CDB[0] = cmd; /* abort */
2622 c->Request.CDB[1] = 0; /* abort a command */
2623 /* buff contains the tag of the command to abort */
2624 memcpy(&c->Request.CDB[4], buff, 8);
2625 break;
2626 case CCISS_RESET_MSG:
2627 c->Request.CDBLen = 16;
2628 c->Request.Type.Attribute = ATTR_SIMPLE;
2629 c->Request.Type.Direction = XFER_NONE;
2630 c->Request.Timeout = 0;
2631 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
2632 c->Request.CDB[0] = cmd; /* reset */
2633 c->Request.CDB[1] = CCISS_RESET_TYPE_TARGET;
2634 break;
2635 case CCISS_NOOP_MSG:
2636 c->Request.CDBLen = 1;
2637 c->Request.Type.Attribute = ATTR_SIMPLE;
2638 c->Request.Type.Direction = XFER_WRITE;
2639 c->Request.Timeout = 0;
2640 c->Request.CDB[0] = cmd;
2641 break;
2642 default:
2643 dev_warn(&h->pdev->dev,
2644 "unknown message type %d\n", cmd);
2645 return IO_ERROR;
2646 }
2647 } else {
2648 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
2649 return IO_ERROR;
2650 }
2651 /* Fill in the scatter gather information */
2652 if (size > 0) {
2653 buff_dma_handle.val = (__u64) pci_map_single(h->pdev,
2654 buff, size,
2655 PCI_DMA_BIDIRECTIONAL);
2656 c->SG[0].Addr.lower = buff_dma_handle.val32.lower;
2657 c->SG[0].Addr.upper = buff_dma_handle.val32.upper;
2658 c->SG[0].Len = size;
2659 c->SG[0].Ext = 0; /* we are not chaining */
2660 }
2661 return status;
2662 }
2663
2664 static int __devinit cciss_send_reset(ctlr_info_t *h, unsigned char *scsi3addr,
2665 u8 reset_type)
2666 {
2667 CommandList_struct *c;
2668 int return_status;
2669
2670 c = cmd_alloc(h);
2671 if (!c)
2672 return -ENOMEM;
2673 return_status = fill_cmd(h, c, CCISS_RESET_MSG, NULL, 0, 0,
2674 CTLR_LUNID, TYPE_MSG);
2675 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
2676 if (return_status != IO_OK) {
2677 cmd_special_free(h, c);
2678 return return_status;
2679 }
2680 c->waiting = NULL;
2681 enqueue_cmd_and_start_io(h, c);
2682 /* Don't wait for completion, the reset won't complete. Don't free
2683 * the command either. This is the last command we will send before
2684 * re-initializing everything, so it doesn't matter and won't leak.
2685 */
2686 return 0;
2687 }
2688
2689 static int check_target_status(ctlr_info_t *h, CommandList_struct *c)
2690 {
2691 switch (c->err_info->ScsiStatus) {
2692 case SAM_STAT_GOOD:
2693 return IO_OK;
2694 case SAM_STAT_CHECK_CONDITION:
2695 switch (0xf & c->err_info->SenseInfo[2]) {
2696 case 0: return IO_OK; /* no sense */
2697 case 1: return IO_OK; /* recovered error */
2698 default:
2699 if (check_for_unit_attention(h, c))
2700 return IO_NEEDS_RETRY;
2701 dev_warn(&h->pdev->dev, "cmd 0x%02x "
2702 "check condition, sense key = 0x%02x\n",
2703 c->Request.CDB[0], c->err_info->SenseInfo[2]);
2704 }
2705 break;
2706 default:
2707 dev_warn(&h->pdev->dev, "cmd 0x%02x"
2708 "scsi status = 0x%02x\n",
2709 c->Request.CDB[0], c->err_info->ScsiStatus);
2710 break;
2711 }
2712 return IO_ERROR;
2713 }
2714
2715 static int process_sendcmd_error(ctlr_info_t *h, CommandList_struct *c)
2716 {
2717 int return_status = IO_OK;
2718
2719 if (c->err_info->CommandStatus == CMD_SUCCESS)
2720 return IO_OK;
2721
2722 switch (c->err_info->CommandStatus) {
2723 case CMD_TARGET_STATUS:
2724 return_status = check_target_status(h, c);
2725 break;
2726 case CMD_DATA_UNDERRUN:
2727 case CMD_DATA_OVERRUN:
2728 /* expected for inquiry and report lun commands */
2729 break;
2730 case CMD_INVALID:
2731 dev_warn(&h->pdev->dev, "cmd 0x%02x is "
2732 "reported invalid\n", c->Request.CDB[0]);
2733 return_status = IO_ERROR;
2734 break;
2735 case CMD_PROTOCOL_ERR:
2736 dev_warn(&h->pdev->dev, "cmd 0x%02x has "
2737 "protocol error\n", c->Request.CDB[0]);
2738 return_status = IO_ERROR;
2739 break;
2740 case CMD_HARDWARE_ERR:
2741 dev_warn(&h->pdev->dev, "cmd 0x%02x had "
2742 " hardware error\n", c->Request.CDB[0]);
2743 return_status = IO_ERROR;
2744 break;
2745 case CMD_CONNECTION_LOST:
2746 dev_warn(&h->pdev->dev, "cmd 0x%02x had "
2747 "connection lost\n", c->Request.CDB[0]);
2748 return_status = IO_ERROR;
2749 break;
2750 case CMD_ABORTED:
2751 dev_warn(&h->pdev->dev, "cmd 0x%02x was "
2752 "aborted\n", c->Request.CDB[0]);
2753 return_status = IO_ERROR;
2754 break;
2755 case CMD_ABORT_FAILED:
2756 dev_warn(&h->pdev->dev, "cmd 0x%02x reports "
2757 "abort failed\n", c->Request.CDB[0]);
2758 return_status = IO_ERROR;
2759 break;
2760 case CMD_UNSOLICITED_ABORT:
2761 dev_warn(&h->pdev->dev, "unsolicited abort 0x%02x\n",
2762 c->Request.CDB[0]);
2763 return_status = IO_NEEDS_RETRY;
2764 break;
2765 case CMD_UNABORTABLE:
2766 dev_warn(&h->pdev->dev, "cmd unabortable\n");
2767 return_status = IO_ERROR;
2768 break;
2769 default:
2770 dev_warn(&h->pdev->dev, "cmd 0x%02x returned "
2771 "unknown status %x\n", c->Request.CDB[0],
2772 c->err_info->CommandStatus);
2773 return_status = IO_ERROR;
2774 }
2775 return return_status;
2776 }
2777
2778 static int sendcmd_withirq_core(ctlr_info_t *h, CommandList_struct *c,
2779 int attempt_retry)
2780 {
2781 DECLARE_COMPLETION_ONSTACK(wait);
2782 u64bit buff_dma_handle;
2783 int return_status = IO_OK;
2784
2785 resend_cmd2:
2786 c->waiting = &wait;
2787 enqueue_cmd_and_start_io(h, c);
2788
2789 wait_for_completion(&wait);
2790
2791 if (c->err_info->CommandStatus == 0 || !attempt_retry)
2792 goto command_done;
2793
2794 return_status = process_sendcmd_error(h, c);
2795
2796 if (return_status == IO_NEEDS_RETRY &&
2797 c->retry_count < MAX_CMD_RETRIES) {
2798 dev_warn(&h->pdev->dev, "retrying 0x%02x\n",
2799 c->Request.CDB[0]);
2800 c->retry_count++;
2801 /* erase the old error information */
2802 memset(c->err_info, 0, sizeof(ErrorInfo_struct));
2803 return_status = IO_OK;
2804 INIT_COMPLETION(wait);
2805 goto resend_cmd2;
2806 }
2807
2808 command_done:
2809 /* unlock the buffers from DMA */
2810 buff_dma_handle.val32.lower = c->SG[0].Addr.lower;
2811 buff_dma_handle.val32.upper = c->SG[0].Addr.upper;
2812 pci_unmap_single(h->pdev, (dma_addr_t) buff_dma_handle.val,
2813 c->SG[0].Len, PCI_DMA_BIDIRECTIONAL);
2814 return return_status;
2815 }
2816
2817 static int sendcmd_withirq(ctlr_info_t *h, __u8 cmd, void *buff, size_t size,
2818 __u8 page_code, unsigned char scsi3addr[],
2819 int cmd_type)
2820 {
2821 CommandList_struct *c;
2822 int return_status;
2823
2824 c = cmd_special_alloc(h);
2825 if (!c)
2826 return -ENOMEM;
2827 return_status = fill_cmd(h, c, cmd, buff, size, page_code,
2828 scsi3addr, cmd_type);
2829 if (return_status == IO_OK)
2830 return_status = sendcmd_withirq_core(h, c, 1);
2831
2832 cmd_special_free(h, c);
2833 return return_status;
2834 }
2835
2836 static void cciss_geometry_inquiry(ctlr_info_t *h, int logvol,
2837 sector_t total_size,
2838 unsigned int block_size,
2839 InquiryData_struct *inq_buff,
2840 drive_info_struct *drv)
2841 {
2842 int return_code;
2843 unsigned long t;
2844 unsigned char scsi3addr[8];
2845
2846 memset(inq_buff, 0, sizeof(InquiryData_struct));
2847 log_unit_to_scsi3addr(h, scsi3addr, logvol);
2848 return_code = sendcmd_withirq(h, CISS_INQUIRY, inq_buff,
2849 sizeof(*inq_buff), 0xC1, scsi3addr, TYPE_CMD);
2850 if (return_code == IO_OK) {
2851 if (inq_buff->data_byte[8] == 0xFF) {
2852 dev_warn(&h->pdev->dev,
2853 "reading geometry failed, volume "
2854 "does not support reading geometry\n");
2855 drv->heads = 255;
2856 drv->sectors = 32; /* Sectors per track */
2857 drv->cylinders = total_size + 1;
2858 drv->raid_level = RAID_UNKNOWN;
2859 } else {
2860 drv->heads = inq_buff->data_byte[6];
2861 drv->sectors = inq_buff->data_byte[7];
2862 drv->cylinders = (inq_buff->data_byte[4] & 0xff) << 8;
2863 drv->cylinders += inq_buff->data_byte[5];
2864 drv->raid_level = inq_buff->data_byte[8];
2865 }
2866 drv->block_size = block_size;
2867 drv->nr_blocks = total_size + 1;
2868 t = drv->heads * drv->sectors;
2869 if (t > 1) {
2870 sector_t real_size = total_size + 1;
2871 unsigned long rem = sector_div(real_size, t);
2872 if (rem)
2873 real_size++;
2874 drv->cylinders = real_size;
2875 }
2876 } else { /* Get geometry failed */
2877 dev_warn(&h->pdev->dev, "reading geometry failed\n");
2878 }
2879 }
2880
2881 static void
2882 cciss_read_capacity(ctlr_info_t *h, int logvol, sector_t *total_size,
2883 unsigned int *block_size)
2884 {
2885 ReadCapdata_struct *buf;
2886 int return_code;
2887 unsigned char scsi3addr[8];
2888
2889 buf = kzalloc(sizeof(ReadCapdata_struct), GFP_KERNEL);
2890 if (!buf) {
2891 dev_warn(&h->pdev->dev, "out of memory\n");
2892 return;
2893 }
2894
2895 log_unit_to_scsi3addr(h, scsi3addr, logvol);
2896 return_code = sendcmd_withirq(h, CCISS_READ_CAPACITY, buf,
2897 sizeof(ReadCapdata_struct), 0, scsi3addr, TYPE_CMD);
2898 if (return_code == IO_OK) {
2899 *total_size = be32_to_cpu(*(__be32 *) buf->total_size);
2900 *block_size = be32_to_cpu(*(__be32 *) buf->block_size);
2901 } else { /* read capacity command failed */
2902 dev_warn(&h->pdev->dev, "read capacity failed\n");
2903 *total_size = 0;
2904 *block_size = BLOCK_SIZE;
2905 }
2906 kfree(buf);
2907 }
2908
2909 static void cciss_read_capacity_16(ctlr_info_t *h, int logvol,
2910 sector_t *total_size, unsigned int *block_size)
2911 {
2912 ReadCapdata_struct_16 *buf;
2913 int return_code;
2914 unsigned char scsi3addr[8];
2915
2916 buf = kzalloc(sizeof(ReadCapdata_struct_16), GFP_KERNEL);
2917 if (!buf) {
2918 dev_warn(&h->pdev->dev, "out of memory\n");
2919 return;
2920 }
2921
2922 log_unit_to_scsi3addr(h, scsi3addr, logvol);
2923 return_code = sendcmd_withirq(h, CCISS_READ_CAPACITY_16,
2924 buf, sizeof(ReadCapdata_struct_16),
2925 0, scsi3addr, TYPE_CMD);
2926 if (return_code == IO_OK) {
2927 *total_size = be64_to_cpu(*(__be64 *) buf->total_size);
2928 *block_size = be32_to_cpu(*(__be32 *) buf->block_size);
2929 } else { /* read capacity command failed */
2930 dev_warn(&h->pdev->dev, "read capacity failed\n");
2931 *total_size = 0;
2932 *block_size = BLOCK_SIZE;
2933 }
2934 dev_info(&h->pdev->dev, " blocks= %llu block_size= %d\n",
2935 (unsigned long long)*total_size+1, *block_size);
2936 kfree(buf);
2937 }
2938
2939 static int cciss_revalidate(struct gendisk *disk)
2940 {
2941 ctlr_info_t *h = get_host(disk);
2942 drive_info_struct *drv = get_drv(disk);
2943 int logvol;
2944 int FOUND = 0;
2945 unsigned int block_size;
2946 sector_t total_size;
2947 InquiryData_struct *inq_buff = NULL;
2948
2949 for (logvol = 0; logvol <= h->highest_lun; logvol++) {
2950 if (!h->drv[logvol])
2951 continue;
2952 if (memcmp(h->drv[logvol]->LunID, drv->LunID,
2953 sizeof(drv->LunID)) == 0) {
2954 FOUND = 1;
2955 break;
2956 }
2957 }
2958
2959 if (!FOUND)
2960 return 1;
2961
2962 inq_buff = kmalloc(sizeof(InquiryData_struct), GFP_KERNEL);
2963 if (inq_buff == NULL) {
2964 dev_warn(&h->pdev->dev, "out of memory\n");
2965 return 1;
2966 }
2967 if (h->cciss_read == CCISS_READ_10) {
2968 cciss_read_capacity(h, logvol,
2969 &total_size, &block_size);
2970 } else {
2971 cciss_read_capacity_16(h, logvol,
2972 &total_size, &block_size);
2973 }
2974 cciss_geometry_inquiry(h, logvol, total_size, block_size,
2975 inq_buff, drv);
2976
2977 blk_queue_logical_block_size(drv->queue, drv->block_size);
2978 set_capacity(disk, drv->nr_blocks);
2979
2980 kfree(inq_buff);
2981 return 0;
2982 }
2983
2984 /*
2985 * Map (physical) PCI mem into (virtual) kernel space
2986 */
2987 static void __iomem *remap_pci_mem(ulong base, ulong size)
2988 {
2989 ulong page_base = ((ulong) base) & PAGE_MASK;
2990 ulong page_offs = ((ulong) base) - page_base;
2991 void __iomem *page_remapped = ioremap(page_base, page_offs + size);
2992
2993 return page_remapped ? (page_remapped + page_offs) : NULL;
2994 }
2995
2996 /*
2997 * Takes jobs of the Q and sends them to the hardware, then puts it on
2998 * the Q to wait for completion.
2999 */
3000 static void start_io(ctlr_info_t *h)
3001 {
3002 CommandList_struct *c;
3003
3004 while (!list_empty(&h->reqQ)) {
3005 c = list_entry(h->reqQ.next, CommandList_struct, list);
3006 /* can't do anything if fifo is full */
3007 if ((h->access.fifo_full(h))) {
3008 dev_warn(&h->pdev->dev, "fifo full\n");
3009 break;
3010 }
3011
3012 /* Get the first entry from the Request Q */
3013 removeQ(c);
3014 h->Qdepth--;
3015
3016 /* Tell the controller execute command */
3017 h->access.submit_command(h, c);
3018
3019 /* Put job onto the completed Q */
3020 addQ(&h->cmpQ, c);
3021 }
3022 }
3023
3024 /* Assumes that h->lock is held. */
3025 /* Zeros out the error record and then resends the command back */
3026 /* to the controller */
3027 static inline void resend_cciss_cmd(ctlr_info_t *h, CommandList_struct *c)
3028 {
3029 /* erase the old error information */
3030 memset(c->err_info, 0, sizeof(ErrorInfo_struct));
3031
3032 /* add it to software queue and then send it to the controller */
3033 addQ(&h->reqQ, c);
3034 h->Qdepth++;
3035 if (h->Qdepth > h->maxQsinceinit)
3036 h->maxQsinceinit = h->Qdepth;
3037
3038 start_io(h);
3039 }
3040
3041 static inline unsigned int make_status_bytes(unsigned int scsi_status_byte,
3042 unsigned int msg_byte, unsigned int host_byte,
3043 unsigned int driver_byte)
3044 {
3045 /* inverse of macros in scsi.h */
3046 return (scsi_status_byte & 0xff) |
3047 ((msg_byte & 0xff) << 8) |
3048 ((host_byte & 0xff) << 16) |
3049 ((driver_byte & 0xff) << 24);
3050 }
3051
3052 static inline int evaluate_target_status(ctlr_info_t *h,
3053 CommandList_struct *cmd, int *retry_cmd)
3054 {
3055 unsigned char sense_key;
3056 unsigned char status_byte, msg_byte, host_byte, driver_byte;
3057 int error_value;
3058
3059 *retry_cmd = 0;
3060 /* If we get in here, it means we got "target status", that is, scsi status */
3061 status_byte = cmd->err_info->ScsiStatus;
3062 driver_byte = DRIVER_OK;
3063 msg_byte = cmd->err_info->CommandStatus; /* correct? seems too device specific */
3064
3065 if (cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC)
3066 host_byte = DID_PASSTHROUGH;
3067 else
3068 host_byte = DID_OK;
3069
3070 error_value = make_status_bytes(status_byte, msg_byte,
3071 host_byte, driver_byte);
3072
3073 if (cmd->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION) {
3074 if (cmd->rq->cmd_type != REQ_TYPE_BLOCK_PC)
3075 dev_warn(&h->pdev->dev, "cmd %p "
3076 "has SCSI Status 0x%x\n",
3077 cmd, cmd->err_info->ScsiStatus);
3078 return error_value;
3079 }
3080
3081 /* check the sense key */
3082 sense_key = 0xf & cmd->err_info->SenseInfo[2];
3083 /* no status or recovered error */
3084 if (((sense_key == 0x0) || (sense_key == 0x1)) &&
3085 (cmd->rq->cmd_type != REQ_TYPE_BLOCK_PC))
3086 error_value = 0;
3087
3088 if (check_for_unit_attention(h, cmd)) {
3089 *retry_cmd = !(cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC);
3090 return 0;
3091 }
3092
3093 /* Not SG_IO or similar? */
3094 if (cmd->rq->cmd_type != REQ_TYPE_BLOCK_PC) {
3095 if (error_value != 0)
3096 dev_warn(&h->pdev->dev, "cmd %p has CHECK CONDITION"
3097 " sense key = 0x%x\n", cmd, sense_key);
3098 return error_value;
3099 }
3100
3101 /* SG_IO or similar, copy sense data back */
3102 if (cmd->rq->sense) {
3103 if (cmd->rq->sense_len > cmd->err_info->SenseLen)
3104 cmd->rq->sense_len = cmd->err_info->SenseLen;
3105 memcpy(cmd->rq->sense, cmd->err_info->SenseInfo,
3106 cmd->rq->sense_len);
3107 } else
3108 cmd->rq->sense_len = 0;
3109
3110 return error_value;
3111 }
3112
3113 /* checks the status of the job and calls complete buffers to mark all
3114 * buffers for the completed job. Note that this function does not need
3115 * to hold the hba/queue lock.
3116 */
3117 static inline void complete_command(ctlr_info_t *h, CommandList_struct *cmd,
3118 int timeout)
3119 {
3120 int retry_cmd = 0;
3121 struct request *rq = cmd->rq;
3122
3123 rq->errors = 0;
3124
3125 if (timeout)
3126 rq->errors = make_status_bytes(0, 0, 0, DRIVER_TIMEOUT);
3127
3128 if (cmd->err_info->CommandStatus == 0) /* no error has occurred */
3129 goto after_error_processing;
3130
3131 switch (cmd->err_info->CommandStatus) {
3132 case CMD_TARGET_STATUS:
3133 rq->errors = evaluate_target_status(h, cmd, &retry_cmd);
3134 break;
3135 case CMD_DATA_UNDERRUN:
3136 if (cmd->rq->cmd_type == REQ_TYPE_FS) {
3137 dev_warn(&h->pdev->dev, "cmd %p has"
3138 " completed with data underrun "
3139 "reported\n", cmd);
3140 cmd->rq->resid_len = cmd->err_info->ResidualCnt;
3141 }
3142 break;
3143 case CMD_DATA_OVERRUN:
3144 if (cmd->rq->cmd_type == REQ_TYPE_FS)
3145 dev_warn(&h->pdev->dev, "cciss: cmd %p has"
3146 " completed with data overrun "
3147 "reported\n", cmd);
3148 break;
3149 case CMD_INVALID:
3150 dev_warn(&h->pdev->dev, "cciss: cmd %p is "
3151 "reported invalid\n", cmd);
3152 rq->errors = make_status_bytes(SAM_STAT_GOOD,
3153 cmd->err_info->CommandStatus, DRIVER_OK,
3154 (cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC) ?
3155 DID_PASSTHROUGH : DID_ERROR);
3156 break;
3157 case CMD_PROTOCOL_ERR:
3158 dev_warn(&h->pdev->dev, "cciss: cmd %p has "
3159 "protocol error\n", cmd);
3160 rq->errors = make_status_bytes(SAM_STAT_GOOD,
3161 cmd->err_info->CommandStatus, DRIVER_OK,
3162 (cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC) ?
3163 DID_PASSTHROUGH : DID_ERROR);
3164 break;
3165 case CMD_HARDWARE_ERR:
3166 dev_warn(&h->pdev->dev, "cciss: cmd %p had "
3167 " hardware error\n", cmd);
3168 rq->errors = make_status_bytes(SAM_STAT_GOOD,
3169 cmd->err_info->CommandStatus, DRIVER_OK,
3170 (cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC) ?
3171 DID_PASSTHROUGH : DID_ERROR);
3172 break;
3173 case CMD_CONNECTION_LOST:
3174 dev_warn(&h->pdev->dev, "cciss: cmd %p had "
3175 "connection lost\n", cmd);
3176 rq->errors = make_status_bytes(SAM_STAT_GOOD,
3177 cmd->err_info->CommandStatus, DRIVER_OK,
3178 (cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC) ?
3179 DID_PASSTHROUGH : DID_ERROR);
3180 break;
3181 case CMD_ABORTED:
3182 dev_warn(&h->pdev->dev, "cciss: cmd %p was "
3183 "aborted\n", cmd);
3184 rq->errors = make_status_bytes(SAM_STAT_GOOD,
3185 cmd->err_info->CommandStatus, DRIVER_OK,
3186 (cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC) ?
3187 DID_PASSTHROUGH : DID_ABORT);
3188 break;
3189 case CMD_ABORT_FAILED:
3190 dev_warn(&h->pdev->dev, "cciss: cmd %p reports "
3191 "abort failed\n", cmd);
3192 rq->errors = make_status_bytes(SAM_STAT_GOOD,
3193 cmd->err_info->CommandStatus, DRIVER_OK,
3194 (cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC) ?
3195 DID_PASSTHROUGH : DID_ERROR);
3196 break;
3197 case CMD_UNSOLICITED_ABORT:
3198 dev_warn(&h->pdev->dev, "cciss%d: unsolicited "
3199 "abort %p\n", h->ctlr, cmd);
3200 if (cmd->retry_count < MAX_CMD_RETRIES) {
3201 retry_cmd = 1;
3202 dev_warn(&h->pdev->dev, "retrying %p\n", cmd);
3203 cmd->retry_count++;
3204 } else
3205 dev_warn(&h->pdev->dev,
3206 "%p retried too many times\n", cmd);
3207 rq->errors = make_status_bytes(SAM_STAT_GOOD,
3208 cmd->err_info->CommandStatus, DRIVER_OK,
3209 (cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC) ?
3210 DID_PASSTHROUGH : DID_ABORT);
3211 break;
3212 case CMD_TIMEOUT:
3213 dev_warn(&h->pdev->dev, "cmd %p timedout\n", cmd);
3214 rq->errors = make_status_bytes(SAM_STAT_GOOD,
3215 cmd->err_info->CommandStatus, DRIVER_OK,
3216 (cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC) ?
3217 DID_PASSTHROUGH : DID_ERROR);
3218 break;
3219 case CMD_UNABORTABLE:
3220 dev_warn(&h->pdev->dev, "cmd %p unabortable\n", cmd);
3221 rq->errors = make_status_bytes(SAM_STAT_GOOD,
3222 cmd->err_info->CommandStatus, DRIVER_OK,
3223 cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC ?
3224 DID_PASSTHROUGH : DID_ERROR);
3225 break;
3226 default:
3227 dev_warn(&h->pdev->dev, "cmd %p returned "
3228 "unknown status %x\n", cmd,
3229 cmd->err_info->CommandStatus);
3230 rq->errors = make_status_bytes(SAM_STAT_GOOD,
3231 cmd->err_info->CommandStatus, DRIVER_OK,
3232 (cmd->rq->cmd_type == REQ_TYPE_BLOCK_PC) ?
3233 DID_PASSTHROUGH : DID_ERROR);
3234 }
3235
3236 after_error_processing:
3237
3238 /* We need to return this command */
3239 if (retry_cmd) {
3240 resend_cciss_cmd(h, cmd);
3241 return;
3242 }
3243 cmd->rq->completion_data = cmd;
3244 blk_complete_request(cmd->rq);
3245 }
3246
3247 static inline u32 cciss_tag_contains_index(u32 tag)
3248 {
3249 #define DIRECT_LOOKUP_BIT 0x10
3250 return tag & DIRECT_LOOKUP_BIT;
3251 }
3252
3253 static inline u32 cciss_tag_to_index(u32 tag)
3254 {
3255 #define DIRECT_LOOKUP_SHIFT 5
3256 return tag >> DIRECT_LOOKUP_SHIFT;
3257 }
3258
3259 static inline u32 cciss_tag_discard_error_bits(ctlr_info_t *h, u32 tag)
3260 {
3261 #define CCISS_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
3262 #define CCISS_SIMPLE_ERROR_BITS 0x03
3263 if (likely(h->transMethod & CFGTBL_Trans_Performant))
3264 return tag & ~CCISS_PERF_ERROR_BITS;
3265 return tag & ~CCISS_SIMPLE_ERROR_BITS;
3266 }
3267
3268 static inline void cciss_mark_tag_indexed(u32 *tag)
3269 {
3270 *tag |= DIRECT_LOOKUP_BIT;
3271 }
3272
3273 static inline void cciss_set_tag_index(u32 *tag, u32 index)
3274 {
3275 *tag |= (index << DIRECT_LOOKUP_SHIFT);
3276 }
3277
3278 /*
3279 * Get a request and submit it to the controller.
3280 */
3281 static void do_cciss_request(struct request_queue *q)
3282 {
3283 ctlr_info_t *h = q->queuedata;
3284 CommandList_struct *c;
3285 sector_t start_blk;
3286 int seg;
3287 struct request *creq;
3288 u64bit temp64;
3289 struct scatterlist *tmp_sg;
3290 SGDescriptor_struct *curr_sg;
3291 drive_info_struct *drv;
3292 int i, dir;
3293 int sg_index = 0;
3294 int chained = 0;
3295
3296 queue:
3297 creq = blk_peek_request(q);
3298 if (!creq)
3299 goto startio;
3300
3301 BUG_ON(creq->nr_phys_segments > h->maxsgentries);
3302
3303 c = cmd_alloc(h);
3304 if (!c)
3305 goto full;
3306
3307 blk_start_request(creq);
3308
3309 tmp_sg = h->scatter_list[c->cmdindex];
3310 spin_unlock_irq(q->queue_lock);
3311
3312 c->cmd_type = CMD_RWREQ;
3313 c->rq = creq;
3314
3315 /* fill in the request */
3316 drv = creq->rq_disk->private_data;
3317 c->Header.ReplyQueue = 0; /* unused in simple mode */
3318 /* got command from pool, so use the command block index instead */
3319 /* for direct lookups. */
3320 /* The first 2 bits are reserved for controller error reporting. */
3321 cciss_set_tag_index(&c->Header.Tag.lower, c->cmdindex);
3322 cciss_mark_tag_indexed(&c->Header.Tag.lower);
3323 memcpy(&c->Header.LUN, drv->LunID, sizeof(drv->LunID));
3324 c->Request.CDBLen = 10; /* 12 byte commands not in FW yet; */
3325 c->Request.Type.Type = TYPE_CMD; /* It is a command. */
3326 c->Request.Type.Attribute = ATTR_SIMPLE;
3327 c->Request.Type.Direction =
3328 (rq_data_dir(creq) == READ) ? XFER_READ : XFER_WRITE;
3329 c->Request.Timeout = 0; /* Don't time out */
3330 c->Request.CDB[0] =
3331 (rq_data_dir(creq) == READ) ? h->cciss_read : h->cciss_write;
3332 start_blk = blk_rq_pos(creq);
3333 dev_dbg(&h->pdev->dev, "sector =%d nr_sectors=%d\n",
3334 (int)blk_rq_pos(creq), (int)blk_rq_sectors(creq));
3335 sg_init_table(tmp_sg, h->maxsgentries);
3336 seg = blk_rq_map_sg(q, creq, tmp_sg);
3337
3338 /* get the DMA records for the setup */
3339 if (c->Request.Type.Direction == XFER_READ)
3340 dir = PCI_DMA_FROMDEVICE;
3341 else
3342 dir = PCI_DMA_TODEVICE;
3343
3344 curr_sg = c->SG;
3345 sg_index = 0;
3346 chained = 0;
3347
3348 for (i = 0; i < seg; i++) {
3349 if (((sg_index+1) == (h->max_cmd_sgentries)) &&
3350 !chained && ((seg - i) > 1)) {
3351 /* Point to next chain block. */
3352 curr_sg = h->cmd_sg_list[c->cmdindex];
3353 sg_index = 0;
3354 chained = 1;
3355 }
3356 curr_sg[sg_index].Len = tmp_sg[i].length;
3357 temp64.val = (__u64) pci_map_page(h->pdev, sg_page(&tmp_sg[i]),
3358 tmp_sg[i].offset,
3359 tmp_sg[i].length, dir);
3360 curr_sg[sg_index].Addr.lower = temp64.val32.lower;
3361 curr_sg[sg_index].Addr.upper = temp64.val32.upper;
3362 curr_sg[sg_index].Ext = 0; /* we are not chaining */
3363 ++sg_index;
3364 }
3365 if (chained)
3366 cciss_map_sg_chain_block(h, c, h->cmd_sg_list[c->cmdindex],
3367 (seg - (h->max_cmd_sgentries - 1)) *
3368 sizeof(SGDescriptor_struct));
3369
3370 /* track how many SG entries we are using */
3371 if (seg > h->maxSG)
3372 h->maxSG = seg;
3373
3374 dev_dbg(&h->pdev->dev, "Submitting %u sectors in %d segments "
3375 "chained[%d]\n",
3376 blk_rq_sectors(creq), seg, chained);
3377
3378 c->Header.SGTotal = seg + chained;
3379 if (seg <= h->max_cmd_sgentries)
3380 c->Header.SGList = c->Header.SGTotal;
3381 else
3382 c->Header.SGList = h->max_cmd_sgentries;
3383 set_performant_mode(h, c);
3384
3385 if (likely(creq->cmd_type == REQ_TYPE_FS)) {
3386 if(h->cciss_read == CCISS_READ_10) {
3387 c->Request.CDB[1] = 0;
3388 c->Request.CDB[2] = (start_blk >> 24) & 0xff; /* MSB */
3389 c->Request.CDB[3] = (start_blk >> 16) & 0xff;
3390 c->Request.CDB[4] = (start_blk >> 8) & 0xff;
3391 c->Request.CDB[5] = start_blk & 0xff;
3392 c->Request.CDB[6] = 0; /* (sect >> 24) & 0xff; MSB */
3393 c->Request.CDB[7] = (blk_rq_sectors(creq) >> 8) & 0xff;
3394 c->Request.CDB[8] = blk_rq_sectors(creq) & 0xff;
3395 c->Request.CDB[9] = c->Request.CDB[11] = c->Request.CDB[12] = 0;
3396 } else {
3397 u32 upper32 = upper_32_bits(start_blk);
3398
3399 c->Request.CDBLen = 16;
3400 c->Request.CDB[1]= 0;
3401 c->Request.CDB[2]= (upper32 >> 24) & 0xff; /* MSB */
3402 c->Request.CDB[3]= (upper32 >> 16) & 0xff;
3403 c->Request.CDB[4]= (upper32 >> 8) & 0xff;
3404 c->Request.CDB[5]= upper32 & 0xff;
3405 c->Request.CDB[6]= (start_blk >> 24) & 0xff;
3406 c->Request.CDB[7]= (start_blk >> 16) & 0xff;
3407 c->Request.CDB[8]= (start_blk >> 8) & 0xff;
3408 c->Request.CDB[9]= start_blk & 0xff;
3409 c->Request.CDB[10]= (blk_rq_sectors(creq) >> 24) & 0xff;
3410 c->Request.CDB[11]= (blk_rq_sectors(creq) >> 16) & 0xff;
3411 c->Request.CDB[12]= (blk_rq_sectors(creq) >> 8) & 0xff;
3412 c->Request.CDB[13]= blk_rq_sectors(creq) & 0xff;
3413 c->Request.CDB[14] = c->Request.CDB[15] = 0;
3414 }
3415 } else if (creq->cmd_type == REQ_TYPE_BLOCK_PC) {
3416 c->Request.CDBLen = creq->cmd_len;
3417 memcpy(c->Request.CDB, creq->cmd, BLK_MAX_CDB);
3418 } else {
3419 dev_warn(&h->pdev->dev, "bad request type %d\n",
3420 creq->cmd_type);
3421 BUG();
3422 }
3423
3424 spin_lock_irq(q->queue_lock);
3425
3426 addQ(&h->reqQ, c);
3427 h->Qdepth++;
3428 if (h->Qdepth > h->maxQsinceinit)
3429 h->maxQsinceinit = h->Qdepth;
3430
3431 goto queue;
3432 full:
3433 blk_stop_queue(q);
3434 startio:
3435 /* We will already have the driver lock here so not need
3436 * to lock it.
3437 */
3438 start_io(h);
3439 }
3440
3441 static inline unsigned long get_next_completion(ctlr_info_t *h)
3442 {
3443 return h->access.command_completed(h);
3444 }
3445
3446 static inline int interrupt_pending(ctlr_info_t *h)
3447 {
3448 return h->access.intr_pending(h);
3449 }
3450
3451 static inline long interrupt_not_for_us(ctlr_info_t *h)
3452 {
3453 return ((h->access.intr_pending(h) == 0) ||
3454 (h->interrupts_enabled == 0));
3455 }
3456
3457 static inline int bad_tag(ctlr_info_t *h, u32 tag_index,
3458 u32 raw_tag)
3459 {
3460 if (unlikely(tag_index >= h->nr_cmds)) {
3461 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
3462 return 1;
3463 }
3464 return 0;
3465 }
3466
3467 static inline void finish_cmd(ctlr_info_t *h, CommandList_struct *c,
3468 u32 raw_tag)
3469 {
3470 removeQ(c);
3471 if (likely(c->cmd_type == CMD_RWREQ))
3472 complete_command(h, c, 0);
3473 else if (c->cmd_type == CMD_IOCTL_PEND)
3474 complete(c->waiting);
3475 #ifdef CONFIG_CISS_SCSI_TAPE
3476 else if (c->cmd_type == CMD_SCSI)
3477 complete_scsi_command(c, 0, raw_tag);
3478 #endif
3479 }
3480
3481 static inline u32 next_command(ctlr_info_t *h)
3482 {
3483 u32 a;
3484
3485 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
3486 return h->access.command_completed(h);
3487
3488 if ((*(h->reply_pool_head) & 1) == (h->reply_pool_wraparound)) {
3489 a = *(h->reply_pool_head); /* Next cmd in ring buffer */
3490 (h->reply_pool_head)++;
3491 h->commands_outstanding--;
3492 } else {
3493 a = FIFO_EMPTY;
3494 }
3495 /* Check for wraparound */
3496 if (h->reply_pool_head == (h->reply_pool + h->max_commands)) {
3497 h->reply_pool_head = h->reply_pool;
3498 h->reply_pool_wraparound ^= 1;
3499 }
3500 return a;
3501 }
3502
3503 /* process completion of an indexed ("direct lookup") command */
3504 static inline u32 process_indexed_cmd(ctlr_info_t *h, u32 raw_tag)
3505 {
3506 u32 tag_index;
3507 CommandList_struct *c;
3508
3509 tag_index = cciss_tag_to_index(raw_tag);
3510 if (bad_tag(h, tag_index, raw_tag))
3511 return next_command(h);
3512 c = h->cmd_pool + tag_index;
3513 finish_cmd(h, c, raw_tag);
3514 return next_command(h);
3515 }
3516
3517 /* process completion of a non-indexed command */
3518 static inline u32 process_nonindexed_cmd(ctlr_info_t *h, u32 raw_tag)
3519 {
3520 CommandList_struct *c = NULL;
3521 __u32 busaddr_masked, tag_masked;
3522
3523 tag_masked = cciss_tag_discard_error_bits(h, raw_tag);
3524 list_for_each_entry(c, &h->cmpQ, list) {
3525 busaddr_masked = cciss_tag_discard_error_bits(h, c->busaddr);
3526 if (busaddr_masked == tag_masked) {
3527 finish_cmd(h, c, raw_tag);
3528 return next_command(h);
3529 }
3530 }
3531 bad_tag(h, h->nr_cmds + 1, raw_tag);
3532 return next_command(h);
3533 }
3534
3535 /* Some controllers, like p400, will give us one interrupt
3536 * after a soft reset, even if we turned interrupts off.
3537 * Only need to check for this in the cciss_xxx_discard_completions
3538 * functions.
3539 */
3540 static int ignore_bogus_interrupt(ctlr_info_t *h)
3541 {
3542 if (likely(!reset_devices))
3543 return 0;
3544
3545 if (likely(h->interrupts_enabled))
3546 return 0;
3547
3548 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
3549 "(known firmware bug.) Ignoring.\n");
3550
3551 return 1;
3552 }
3553
3554 static irqreturn_t cciss_intx_discard_completions(int irq, void *dev_id)
3555 {
3556 ctlr_info_t *h = dev_id;
3557 unsigned long flags;
3558 u32 raw_tag;
3559
3560 if (ignore_bogus_interrupt(h))
3561 return IRQ_NONE;
3562
3563 if (interrupt_not_for_us(h))
3564 return IRQ_NONE;
3565 spin_lock_irqsave(&h->lock, flags);
3566 while (interrupt_pending(h)) {
3567 raw_tag = get_next_completion(h);
3568 while (raw_tag != FIFO_EMPTY)
3569 raw_tag = next_command(h);
3570 }
3571 spin_unlock_irqrestore(&h->lock, flags);
3572 return IRQ_HANDLED;
3573 }
3574
3575 static irqreturn_t cciss_msix_discard_completions(int irq, void *dev_id)
3576 {
3577 ctlr_info_t *h = dev_id;
3578 unsigned long flags;
3579 u32 raw_tag;
3580
3581 if (ignore_bogus_interrupt(h))
3582 return IRQ_NONE;
3583
3584 spin_lock_irqsave(&h->lock, flags);
3585 raw_tag = get_next_completion(h);
3586 while (raw_tag != FIFO_EMPTY)
3587 raw_tag = next_command(h);
3588 spin_unlock_irqrestore(&h->lock, flags);
3589 return IRQ_HANDLED;
3590 }
3591
3592 static irqreturn_t do_cciss_intx(int irq, void *dev_id)
3593 {
3594 ctlr_info_t *h = dev_id;
3595 unsigned long flags;
3596 u32 raw_tag;
3597
3598 if (interrupt_not_for_us(h))
3599 return IRQ_NONE;
3600 spin_lock_irqsave(&h->lock, flags);
3601 while (interrupt_pending(h)) {
3602 raw_tag = get_next_completion(h);
3603 while (raw_tag != FIFO_EMPTY) {
3604 if (cciss_tag_contains_index(raw_tag))
3605 raw_tag = process_indexed_cmd(h, raw_tag);
3606 else
3607 raw_tag = process_nonindexed_cmd(h, raw_tag);
3608 }
3609 }
3610 spin_unlock_irqrestore(&h->lock, flags);
3611 return IRQ_HANDLED;
3612 }
3613
3614 /* Add a second interrupt handler for MSI/MSI-X mode. In this mode we never
3615 * check the interrupt pending register because it is not set.
3616 */
3617 static irqreturn_t do_cciss_msix_intr(int irq, void *dev_id)
3618 {
3619 ctlr_info_t *h = dev_id;
3620 unsigned long flags;
3621 u32 raw_tag;
3622
3623 spin_lock_irqsave(&h->lock, flags);
3624 raw_tag = get_next_completion(h);
3625 while (raw_tag != FIFO_EMPTY) {
3626 if (cciss_tag_contains_index(raw_tag))
3627 raw_tag = process_indexed_cmd(h, raw_tag);
3628 else
3629 raw_tag = process_nonindexed_cmd(h, raw_tag);
3630 }
3631 spin_unlock_irqrestore(&h->lock, flags);
3632 return IRQ_HANDLED;
3633 }
3634
3635 /**
3636 * add_to_scan_list() - add controller to rescan queue
3637 * @h: Pointer to the controller.
3638 *
3639 * Adds the controller to the rescan queue if not already on the queue.
3640 *
3641 * returns 1 if added to the queue, 0 if skipped (could be on the
3642 * queue already, or the controller could be initializing or shutting
3643 * down).
3644 **/
3645 static int add_to_scan_list(struct ctlr_info *h)
3646 {
3647 struct ctlr_info *test_h;
3648 int found = 0;
3649 int ret = 0;
3650
3651 if (h->busy_initializing)
3652 return 0;
3653
3654 if (!mutex_trylock(&h->busy_shutting_down))
3655 return 0;
3656
3657 mutex_lock(&scan_mutex);
3658 list_for_each_entry(test_h, &scan_q, scan_list) {
3659 if (test_h == h) {
3660 found = 1;
3661 break;
3662 }
3663 }
3664 if (!found && !h->busy_scanning) {
3665 INIT_COMPLETION(h->scan_wait);
3666 list_add_tail(&h->scan_list, &scan_q);
3667 ret = 1;
3668 }
3669 mutex_unlock(&scan_mutex);
3670 mutex_unlock(&h->busy_shutting_down);
3671
3672 return ret;
3673 }
3674
3675 /**
3676 * remove_from_scan_list() - remove controller from rescan queue
3677 * @h: Pointer to the controller.
3678 *
3679 * Removes the controller from the rescan queue if present. Blocks if
3680 * the controller is currently conducting a rescan. The controller
3681 * can be in one of three states:
3682 * 1. Doesn't need a scan
3683 * 2. On the scan list, but not scanning yet (we remove it)
3684 * 3. Busy scanning (and not on the list). In this case we want to wait for
3685 * the scan to complete to make sure the scanning thread for this
3686 * controller is completely idle.
3687 **/
3688 static void remove_from_scan_list(struct ctlr_info *h)
3689 {
3690 struct ctlr_info *test_h, *tmp_h;
3691
3692 mutex_lock(&scan_mutex);
3693 list_for_each_entry_safe(test_h, tmp_h, &scan_q, scan_list) {
3694 if (test_h == h) { /* state 2. */
3695 list_del(&h->scan_list);
3696 complete_all(&h->scan_wait);
3697 mutex_unlock(&scan_mutex);
3698 return;
3699 }
3700 }
3701 if (h->busy_scanning) { /* state 3. */
3702 mutex_unlock(&scan_mutex);
3703 wait_for_completion(&h->scan_wait);
3704 } else { /* state 1, nothing to do. */
3705 mutex_unlock(&scan_mutex);
3706 }
3707 }
3708
3709 /**
3710 * scan_thread() - kernel thread used to rescan controllers
3711 * @data: Ignored.
3712 *
3713 * A kernel thread used scan for drive topology changes on
3714 * controllers. The thread processes only one controller at a time
3715 * using a queue. Controllers are added to the queue using
3716 * add_to_scan_list() and removed from the queue either after done
3717 * processing or using remove_from_scan_list().
3718 *
3719 * returns 0.
3720 **/
3721 static int scan_thread(void *data)
3722 {
3723 struct ctlr_info *h;
3724
3725 while (1) {
3726 set_current_state(TASK_INTERRUPTIBLE);
3727 schedule();
3728 if (kthread_should_stop())
3729 break;
3730
3731 while (1) {
3732 mutex_lock(&scan_mutex);
3733 if (list_empty(&scan_q)) {
3734 mutex_unlock(&scan_mutex);
3735 break;
3736 }
3737
3738 h = list_entry(scan_q.next,
3739 struct ctlr_info,
3740 scan_list);
3741 list_del(&h->scan_list);
3742 h->busy_scanning = 1;
3743 mutex_unlock(&scan_mutex);
3744
3745 rebuild_lun_table(h, 0, 0);
3746 complete_all(&h->scan_wait);
3747 mutex_lock(&scan_mutex);
3748 h->busy_scanning = 0;
3749 mutex_unlock(&scan_mutex);
3750 }
3751 }
3752
3753 return 0;
3754 }
3755
3756 static int check_for_unit_attention(ctlr_info_t *h, CommandList_struct *c)
3757 {
3758 if (c->err_info->SenseInfo[2] != UNIT_ATTENTION)
3759 return 0;
3760
3761 switch (c->err_info->SenseInfo[12]) {
3762 case STATE_CHANGED:
3763 dev_warn(&h->pdev->dev, "a state change "
3764 "detected, command retried\n");
3765 return 1;
3766 break;
3767 case LUN_FAILED:
3768 dev_warn(&h->pdev->dev, "LUN failure "
3769 "detected, action required\n");
3770 return 1;
3771 break;
3772 case REPORT_LUNS_CHANGED:
3773 dev_warn(&h->pdev->dev, "report LUN data changed\n");
3774 /*
3775 * Here, we could call add_to_scan_list and wake up the scan thread,
3776 * except that it's quite likely that we will get more than one
3777 * REPORT_LUNS_CHANGED condition in quick succession, which means
3778 * that those which occur after the first one will likely happen
3779 * *during* the scan_thread's rescan. And the rescan code is not
3780 * robust enough to restart in the middle, undoing what it has already
3781 * done, and it's not clear that it's even possible to do this, since
3782 * part of what it does is notify the block layer, which starts
3783 * doing it's own i/o to read partition tables and so on, and the
3784 * driver doesn't have visibility to know what might need undoing.
3785 * In any event, if possible, it is horribly complicated to get right
3786 * so we just don't do it for now.
3787 *
3788 * Note: this REPORT_LUNS_CHANGED condition only occurs on the MSA2012.
3789 */
3790 return 1;
3791 break;
3792 case POWER_OR_RESET:
3793 dev_warn(&h->pdev->dev,
3794 "a power on or device reset detected\n");
3795 return 1;
3796 break;
3797 case UNIT_ATTENTION_CLEARED:
3798 dev_warn(&h->pdev->dev,
3799 "unit attention cleared by another initiator\n");
3800 return 1;
3801 break;
3802 default:
3803 dev_warn(&h->pdev->dev, "unknown unit attention detected\n");
3804 return 1;
3805 }
3806 }
3807
3808 /*
3809 * We cannot read the structure directly, for portability we must use
3810 * the io functions.
3811 * This is for debug only.
3812 */
3813 static void print_cfg_table(ctlr_info_t *h)
3814 {
3815 int i;
3816 char temp_name[17];
3817 CfgTable_struct *tb = h->cfgtable;
3818
3819 dev_dbg(&h->pdev->dev, "Controller Configuration information\n");
3820 dev_dbg(&h->pdev->dev, "------------------------------------\n");
3821 for (i = 0; i < 4; i++)
3822 temp_name[i] = readb(&(tb->Signature[i]));
3823 temp_name[4] = '\0';
3824 dev_dbg(&h->pdev->dev, " Signature = %s\n", temp_name);
3825 dev_dbg(&h->pdev->dev, " Spec Number = %d\n",
3826 readl(&(tb->SpecValence)));
3827 dev_dbg(&h->pdev->dev, " Transport methods supported = 0x%x\n",
3828 readl(&(tb->TransportSupport)));
3829 dev_dbg(&h->pdev->dev, " Transport methods active = 0x%x\n",
3830 readl(&(tb->TransportActive)));
3831 dev_dbg(&h->pdev->dev, " Requested transport Method = 0x%x\n",
3832 readl(&(tb->HostWrite.TransportRequest)));
3833 dev_dbg(&h->pdev->dev, " Coalesce Interrupt Delay = 0x%x\n",
3834 readl(&(tb->HostWrite.CoalIntDelay)));
3835 dev_dbg(&h->pdev->dev, " Coalesce Interrupt Count = 0x%x\n",
3836 readl(&(tb->HostWrite.CoalIntCount)));
3837 dev_dbg(&h->pdev->dev, " Max outstanding commands = 0x%d\n",
3838 readl(&(tb->CmdsOutMax)));
3839 dev_dbg(&h->pdev->dev, " Bus Types = 0x%x\n",
3840 readl(&(tb->BusTypes)));
3841 for (i = 0; i < 16; i++)
3842 temp_name[i] = readb(&(tb->ServerName[i]));
3843 temp_name[16] = '\0';
3844 dev_dbg(&h->pdev->dev, " Server Name = %s\n", temp_name);
3845 dev_dbg(&h->pdev->dev, " Heartbeat Counter = 0x%x\n\n\n",
3846 readl(&(tb->HeartBeat)));
3847 }
3848
3849 static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
3850 {
3851 int i, offset, mem_type, bar_type;
3852 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
3853 return 0;
3854 offset = 0;
3855 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
3856 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
3857 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
3858 offset += 4;
3859 else {
3860 mem_type = pci_resource_flags(pdev, i) &
3861 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
3862 switch (mem_type) {
3863 case PCI_BASE_ADDRESS_MEM_TYPE_32:
3864 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
3865 offset += 4; /* 32 bit */
3866 break;
3867 case PCI_BASE_ADDRESS_MEM_TYPE_64:
3868 offset += 8;
3869 break;
3870 default: /* reserved in PCI 2.2 */
3871 dev_warn(&pdev->dev,
3872 "Base address is invalid\n");
3873 return -1;
3874 break;
3875 }
3876 }
3877 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
3878 return i + 1;
3879 }
3880 return -1;
3881 }
3882
3883 /* Fill in bucket_map[], given nsgs (the max number of
3884 * scatter gather elements supported) and bucket[],
3885 * which is an array of 8 integers. The bucket[] array
3886 * contains 8 different DMA transfer sizes (in 16
3887 * byte increments) which the controller uses to fetch
3888 * commands. This function fills in bucket_map[], which
3889 * maps a given number of scatter gather elements to one of
3890 * the 8 DMA transfer sizes. The point of it is to allow the
3891 * controller to only do as much DMA as needed to fetch the
3892 * command, with the DMA transfer size encoded in the lower
3893 * bits of the command address.
3894 */
3895 static void calc_bucket_map(int bucket[], int num_buckets,
3896 int nsgs, int *bucket_map)
3897 {
3898 int i, j, b, size;
3899
3900 /* even a command with 0 SGs requires 4 blocks */
3901 #define MINIMUM_TRANSFER_BLOCKS 4
3902 #define NUM_BUCKETS 8
3903 /* Note, bucket_map must have nsgs+1 entries. */
3904 for (i = 0; i <= nsgs; i++) {
3905 /* Compute size of a command with i SG entries */
3906 size = i + MINIMUM_TRANSFER_BLOCKS;
3907 b = num_buckets; /* Assume the biggest bucket */
3908 /* Find the bucket that is just big enough */
3909 for (j = 0; j < 8; j++) {
3910 if (bucket[j] >= size) {
3911 b = j;
3912 break;
3913 }
3914 }
3915 /* for a command with i SG entries, use bucket b. */
3916 bucket_map[i] = b;
3917 }
3918 }
3919
3920 static void __devinit cciss_wait_for_mode_change_ack(ctlr_info_t *h)
3921 {
3922 int i;
3923
3924 /* under certain very rare conditions, this can take awhile.
3925 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
3926 * as we enter this code.) */
3927 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
3928 if (!(readl(h->vaddr + SA5_DOORBELL) & CFGTBL_ChangeReq))
3929 break;
3930 usleep_range(10000, 20000);
3931 }
3932 }
3933
3934 static __devinit void cciss_enter_performant_mode(ctlr_info_t *h,
3935 u32 use_short_tags)
3936 {
3937 /* This is a bit complicated. There are 8 registers on
3938 * the controller which we write to to tell it 8 different
3939 * sizes of commands which there may be. It's a way of
3940 * reducing the DMA done to fetch each command. Encoded into
3941 * each command's tag are 3 bits which communicate to the controller
3942 * which of the eight sizes that command fits within. The size of
3943 * each command depends on how many scatter gather entries there are.
3944 * Each SG entry requires 16 bytes. The eight registers are programmed
3945 * with the number of 16-byte blocks a command of that size requires.
3946 * The smallest command possible requires 5 such 16 byte blocks.
3947 * the largest command possible requires MAXSGENTRIES + 4 16-byte
3948 * blocks. Note, this only extends to the SG entries contained
3949 * within the command block, and does not extend to chained blocks
3950 * of SG elements. bft[] contains the eight values we write to
3951 * the registers. They are not evenly distributed, but have more
3952 * sizes for small commands, and fewer sizes for larger commands.
3953 */
3954 __u32 trans_offset;
3955 int bft[8] = { 5, 6, 8, 10, 12, 20, 28, MAXSGENTRIES + 4};
3956 /*
3957 * 5 = 1 s/g entry or 4k
3958 * 6 = 2 s/g entry or 8k
3959 * 8 = 4 s/g entry or 16k
3960 * 10 = 6 s/g entry or 24k
3961 */
3962 unsigned long register_value;
3963 BUILD_BUG_ON(28 > MAXSGENTRIES + 4);
3964
3965 h->reply_pool_wraparound = 1; /* spec: init to 1 */
3966
3967 /* Controller spec: zero out this buffer. */
3968 memset(h->reply_pool, 0, h->max_commands * sizeof(__u64));
3969 h->reply_pool_head = h->reply_pool;
3970
3971 trans_offset = readl(&(h->cfgtable->TransMethodOffset));
3972 calc_bucket_map(bft, ARRAY_SIZE(bft), h->maxsgentries,
3973 h->blockFetchTable);
3974 writel(bft[0], &h->transtable->BlockFetch0);
3975 writel(bft[1], &h->transtable->BlockFetch1);
3976 writel(bft[2], &h->transtable->BlockFetch2);
3977 writel(bft[3], &h->transtable->BlockFetch3);
3978 writel(bft[4], &h->transtable->BlockFetch4);
3979 writel(bft[5], &h->transtable->BlockFetch5);
3980 writel(bft[6], &h->transtable->BlockFetch6);
3981 writel(bft[7], &h->transtable->BlockFetch7);
3982
3983 /* size of controller ring buffer */
3984 writel(h->max_commands, &h->transtable->RepQSize);
3985 writel(1, &h->transtable->RepQCount);
3986 writel(0, &h->transtable->RepQCtrAddrLow32);
3987 writel(0, &h->transtable->RepQCtrAddrHigh32);
3988 writel(h->reply_pool_dhandle, &h->transtable->RepQAddr0Low32);
3989 writel(0, &h->transtable->RepQAddr0High32);
3990 writel(CFGTBL_Trans_Performant | use_short_tags,
3991 &(h->cfgtable->HostWrite.TransportRequest));
3992
3993 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
3994 cciss_wait_for_mode_change_ack(h);
3995 register_value = readl(&(h->cfgtable->TransportActive));
3996 if (!(register_value & CFGTBL_Trans_Performant))
3997 dev_warn(&h->pdev->dev, "cciss: unable to get board into"
3998 " performant mode\n");
3999 }
4000
4001 static void __devinit cciss_put_controller_into_performant_mode(ctlr_info_t *h)
4002 {
4003 __u32 trans_support;
4004
4005 if (cciss_simple_mode)
4006 return;
4007
4008 dev_dbg(&h->pdev->dev, "Trying to put board into Performant mode\n");
4009 /* Attempt to put controller into performant mode if supported */
4010 /* Does board support performant mode? */
4011 trans_support = readl(&(h->cfgtable->TransportSupport));
4012 if (!(trans_support & PERFORMANT_MODE))
4013 return;
4014
4015 dev_dbg(&h->pdev->dev, "Placing controller into performant mode\n");
4016 /* Performant mode demands commands on a 32 byte boundary
4017 * pci_alloc_consistent aligns on page boundarys already.
4018 * Just need to check if divisible by 32
4019 */
4020 if ((sizeof(CommandList_struct) % 32) != 0) {
4021 dev_warn(&h->pdev->dev, "%s %d %s\n",
4022 "cciss info: command size[",
4023 (int)sizeof(CommandList_struct),
4024 "] not divisible by 32, no performant mode..\n");
4025 return;
4026 }
4027
4028 /* Performant mode ring buffer and supporting data structures */
4029 h->reply_pool = (__u64 *)pci_alloc_consistent(
4030 h->pdev, h->max_commands * sizeof(__u64),
4031 &(h->reply_pool_dhandle));
4032
4033 /* Need a block fetch table for performant mode */
4034 h->blockFetchTable = kmalloc(((h->maxsgentries+1) *
4035 sizeof(__u32)), GFP_KERNEL);
4036
4037 if ((h->reply_pool == NULL) || (h->blockFetchTable == NULL))
4038 goto clean_up;
4039
4040 cciss_enter_performant_mode(h,
4041 trans_support & CFGTBL_Trans_use_short_tags);
4042
4043 /* Change the access methods to the performant access methods */
4044 h->access = SA5_performant_access;
4045 h->transMethod = CFGTBL_Trans_Performant;
4046
4047 return;
4048 clean_up:
4049 kfree(h->blockFetchTable);
4050 if (h->reply_pool)
4051 pci_free_consistent(h->pdev,
4052 h->max_commands * sizeof(__u64),
4053 h->reply_pool,
4054 h->reply_pool_dhandle);
4055 return;
4056
4057 } /* cciss_put_controller_into_performant_mode */
4058
4059 /* If MSI/MSI-X is supported by the kernel we will try to enable it on
4060 * controllers that are capable. If not, we use IO-APIC mode.
4061 */
4062
4063 static void __devinit cciss_interrupt_mode(ctlr_info_t *h)
4064 {
4065 #ifdef CONFIG_PCI_MSI
4066 int err;
4067 struct msix_entry cciss_msix_entries[4] = { {0, 0}, {0, 1},
4068 {0, 2}, {0, 3}
4069 };
4070
4071 /* Some boards advertise MSI but don't really support it */
4072 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
4073 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
4074 goto default_int_mode;
4075
4076 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
4077 err = pci_enable_msix(h->pdev, cciss_msix_entries, 4);
4078 if (!err) {
4079 h->intr[0] = cciss_msix_entries[0].vector;
4080 h->intr[1] = cciss_msix_entries[1].vector;
4081 h->intr[2] = cciss_msix_entries[2].vector;
4082 h->intr[3] = cciss_msix_entries[3].vector;
4083 h->msix_vector = 1;
4084 return;
4085 }
4086 if (err > 0) {
4087 dev_warn(&h->pdev->dev,
4088 "only %d MSI-X vectors available\n", err);
4089 goto default_int_mode;
4090 } else {
4091 dev_warn(&h->pdev->dev,
4092 "MSI-X init failed %d\n", err);
4093 goto default_int_mode;
4094 }
4095 }
4096 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
4097 if (!pci_enable_msi(h->pdev))
4098 h->msi_vector = 1;
4099 else
4100 dev_warn(&h->pdev->dev, "MSI init failed\n");
4101 }
4102 default_int_mode:
4103 #endif /* CONFIG_PCI_MSI */
4104 /* if we get here we're going to use the default interrupt mode */
4105 h->intr[h->intr_mode] = h->pdev->irq;
4106 return;
4107 }
4108
4109 static int __devinit cciss_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
4110 {
4111 int i;
4112 u32 subsystem_vendor_id, subsystem_device_id;
4113
4114 subsystem_vendor_id = pdev->subsystem_vendor;
4115 subsystem_device_id = pdev->subsystem_device;
4116 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
4117 subsystem_vendor_id;
4118
4119 for (i = 0; i < ARRAY_SIZE(products); i++)
4120 if (*board_id == products[i].board_id)
4121 return i;
4122 dev_warn(&pdev->dev, "unrecognized board ID: 0x%08x, ignoring.\n",
4123 *board_id);
4124 return -ENODEV;
4125 }
4126
4127 static inline bool cciss_board_disabled(ctlr_info_t *h)
4128 {
4129 u16 command;
4130
4131 (void) pci_read_config_word(h->pdev, PCI_COMMAND, &command);
4132 return ((command & PCI_COMMAND_MEMORY) == 0);
4133 }
4134
4135 static int __devinit cciss_pci_find_memory_BAR(struct pci_dev *pdev,
4136 unsigned long *memory_bar)
4137 {
4138 int i;
4139
4140 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
4141 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
4142 /* addressing mode bits already removed */
4143 *memory_bar = pci_resource_start(pdev, i);
4144 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
4145 *memory_bar);
4146 return 0;
4147 }
4148 dev_warn(&pdev->dev, "no memory BAR found\n");
4149 return -ENODEV;
4150 }
4151
4152 static int __devinit cciss_wait_for_board_state(struct pci_dev *pdev,
4153 void __iomem *vaddr, int wait_for_ready)
4154 #define BOARD_READY 1
4155 #define BOARD_NOT_READY 0
4156 {
4157 int i, iterations;
4158 u32 scratchpad;
4159
4160 if (wait_for_ready)
4161 iterations = CCISS_BOARD_READY_ITERATIONS;
4162 else
4163 iterations = CCISS_BOARD_NOT_READY_ITERATIONS;
4164
4165 for (i = 0; i < iterations; i++) {
4166 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
4167 if (wait_for_ready) {
4168 if (scratchpad == CCISS_FIRMWARE_READY)
4169 return 0;
4170 } else {
4171 if (scratchpad != CCISS_FIRMWARE_READY)
4172 return 0;
4173 }
4174 msleep(CCISS_BOARD_READY_POLL_INTERVAL_MSECS);
4175 }
4176 dev_warn(&pdev->dev, "board not ready, timed out.\n");
4177 return -ENODEV;
4178 }
4179
4180 static int __devinit cciss_find_cfg_addrs(struct pci_dev *pdev,
4181 void __iomem *vaddr, u32 *cfg_base_addr, u64 *cfg_base_addr_index,
4182 u64 *cfg_offset)
4183 {
4184 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
4185 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
4186 *cfg_base_addr &= (u32) 0x0000ffff;
4187 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
4188 if (*cfg_base_addr_index == -1) {
4189 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index, "
4190 "*cfg_base_addr = 0x%08x\n", *cfg_base_addr);
4191 return -ENODEV;
4192 }
4193 return 0;
4194 }
4195
4196 static int __devinit cciss_find_cfgtables(ctlr_info_t *h)
4197 {
4198 u64 cfg_offset;
4199 u32 cfg_base_addr;
4200 u64 cfg_base_addr_index;
4201 u32 trans_offset;
4202 int rc;
4203
4204 rc = cciss_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
4205 &cfg_base_addr_index, &cfg_offset);
4206 if (rc)
4207 return rc;
4208 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
4209 cfg_base_addr_index) + cfg_offset, sizeof(h->cfgtable));
4210 if (!h->cfgtable)
4211 return -ENOMEM;
4212 rc = write_driver_ver_to_cfgtable(h->cfgtable);
4213 if (rc)
4214 return rc;
4215 /* Find performant mode table. */
4216 trans_offset = readl(&h->cfgtable->TransMethodOffset);
4217 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
4218 cfg_base_addr_index)+cfg_offset+trans_offset,
4219 sizeof(*h->transtable));
4220 if (!h->transtable)
4221 return -ENOMEM;
4222 return 0;
4223 }
4224
4225 static void __devinit cciss_get_max_perf_mode_cmds(struct ctlr_info *h)
4226 {
4227 h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
4228
4229 /* Limit commands in memory limited kdump scenario. */
4230 if (reset_devices && h->max_commands > 32)
4231 h->max_commands = 32;
4232
4233 if (h->max_commands < 16) {
4234 dev_warn(&h->pdev->dev, "Controller reports "
4235 "max supported commands of %d, an obvious lie. "
4236 "Using 16. Ensure that firmware is up to date.\n",
4237 h->max_commands);
4238 h->max_commands = 16;
4239 }
4240 }
4241
4242 /* Interrogate the hardware for some limits:
4243 * max commands, max SG elements without chaining, and with chaining,
4244 * SG chain block size, etc.
4245 */
4246 static void __devinit cciss_find_board_params(ctlr_info_t *h)
4247 {
4248 cciss_get_max_perf_mode_cmds(h);
4249 h->nr_cmds = h->max_commands - 4 - cciss_tape_cmds;
4250 h->maxsgentries = readl(&(h->cfgtable->MaxSGElements));
4251 /*
4252 * Limit in-command s/g elements to 32 save dma'able memory.
4253 * Howvever spec says if 0, use 31
4254 */
4255 h->max_cmd_sgentries = 31;
4256 if (h->maxsgentries > 512) {
4257 h->max_cmd_sgentries = 32;
4258 h->chainsize = h->maxsgentries - h->max_cmd_sgentries + 1;
4259 h->maxsgentries--; /* save one for chain pointer */
4260 } else {
4261 h->maxsgentries = 31; /* default to traditional values */
4262 h->chainsize = 0;
4263 }
4264 }
4265
4266 static inline bool CISS_signature_present(ctlr_info_t *h)
4267 {
4268 if ((readb(&h->cfgtable->Signature[0]) != 'C') ||
4269 (readb(&h->cfgtable->Signature[1]) != 'I') ||
4270 (readb(&h->cfgtable->Signature[2]) != 'S') ||
4271 (readb(&h->cfgtable->Signature[3]) != 'S')) {
4272 dev_warn(&h->pdev->dev, "not a valid CISS config table\n");
4273 return false;
4274 }
4275 return true;
4276 }
4277
4278 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
4279 static inline void cciss_enable_scsi_prefetch(ctlr_info_t *h)
4280 {
4281 #ifdef CONFIG_X86
4282 u32 prefetch;
4283
4284 prefetch = readl(&(h->cfgtable->SCSI_Prefetch));
4285 prefetch |= 0x100;
4286 writel(prefetch, &(h->cfgtable->SCSI_Prefetch));
4287 #endif
4288 }
4289
4290 /* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
4291 * in a prefetch beyond physical memory.
4292 */
4293 static inline void cciss_p600_dma_prefetch_quirk(ctlr_info_t *h)
4294 {
4295 u32 dma_prefetch;
4296 __u32 dma_refetch;
4297
4298 if (h->board_id != 0x3225103C)
4299 return;
4300 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
4301 dma_prefetch |= 0x8000;
4302 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
4303 pci_read_config_dword(h->pdev, PCI_COMMAND_PARITY, &dma_refetch);
4304 dma_refetch |= 0x1;
4305 pci_write_config_dword(h->pdev, PCI_COMMAND_PARITY, dma_refetch);
4306 }
4307
4308 static int __devinit cciss_pci_init(ctlr_info_t *h)
4309 {
4310 int prod_index, err;
4311
4312 prod_index = cciss_lookup_board_id(h->pdev, &h->board_id);
4313 if (prod_index < 0)
4314 return -ENODEV;
4315 h->product_name = products[prod_index].product_name;
4316 h->access = *(products[prod_index].access);
4317
4318 if (cciss_board_disabled(h)) {
4319 dev_warn(&h->pdev->dev, "controller appears to be disabled\n");
4320 return -ENODEV;
4321 }
4322 err = pci_enable_device(h->pdev);
4323 if (err) {
4324 dev_warn(&h->pdev->dev, "Unable to Enable PCI device\n");
4325 return err;
4326 }
4327
4328 err = pci_request_regions(h->pdev, "cciss");
4329 if (err) {
4330 dev_warn(&h->pdev->dev,
4331 "Cannot obtain PCI resources, aborting\n");
4332 return err;
4333 }
4334
4335 dev_dbg(&h->pdev->dev, "irq = %x\n", h->pdev->irq);
4336 dev_dbg(&h->pdev->dev, "board_id = %x\n", h->board_id);
4337
4338 /* If the kernel supports MSI/MSI-X we will try to enable that functionality,
4339 * else we use the IO-APIC interrupt assigned to us by system ROM.
4340 */
4341 cciss_interrupt_mode(h);
4342 err = cciss_pci_find_memory_BAR(h->pdev, &h->paddr);
4343 if (err)
4344 goto err_out_free_res;
4345 h->vaddr = remap_pci_mem(h->paddr, 0x250);
4346 if (!h->vaddr) {
4347 err = -ENOMEM;
4348 goto err_out_free_res;
4349 }
4350 err = cciss_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
4351 if (err)
4352 goto err_out_free_res;
4353 err = cciss_find_cfgtables(h);
4354 if (err)
4355 goto err_out_free_res;
4356 print_cfg_table(h);
4357 cciss_find_board_params(h);
4358
4359 if (!CISS_signature_present(h)) {
4360 err = -ENODEV;
4361 goto err_out_free_res;
4362 }
4363 cciss_enable_scsi_prefetch(h);
4364 cciss_p600_dma_prefetch_quirk(h);
4365 err = cciss_enter_simple_mode(h);
4366 if (err)
4367 goto err_out_free_res;
4368 cciss_put_controller_into_performant_mode(h);
4369 return 0;
4370
4371 err_out_free_res:
4372 /*
4373 * Deliberately omit pci_disable_device(): it does something nasty to
4374 * Smart Array controllers that pci_enable_device does not undo
4375 */
4376 if (h->transtable)
4377 iounmap(h->transtable);
4378 if (h->cfgtable)
4379 iounmap(h->cfgtable);
4380 if (h->vaddr)
4381 iounmap(h->vaddr);
4382 pci_release_regions(h->pdev);
4383 return err;
4384 }
4385
4386 /* Function to find the first free pointer into our hba[] array
4387 * Returns -1 if no free entries are left.
4388 */
4389 static int alloc_cciss_hba(struct pci_dev *pdev)
4390 {
4391 int i;
4392
4393 for (i = 0; i < MAX_CTLR; i++) {
4394 if (!hba[i]) {
4395 ctlr_info_t *h;
4396
4397 h = kzalloc(sizeof(ctlr_info_t), GFP_KERNEL);
4398 if (!h)
4399 goto Enomem;
4400 hba[i] = h;
4401 return i;
4402 }
4403 }
4404 dev_warn(&pdev->dev, "This driver supports a maximum"
4405 " of %d controllers.\n", MAX_CTLR);
4406 return -1;
4407 Enomem:
4408 dev_warn(&pdev->dev, "out of memory.\n");
4409 return -1;
4410 }
4411
4412 static void free_hba(ctlr_info_t *h)
4413 {
4414 int i;
4415
4416 hba[h->ctlr] = NULL;
4417 for (i = 0; i < h->highest_lun + 1; i++)
4418 if (h->gendisk[i] != NULL)
4419 put_disk(h->gendisk[i]);
4420 kfree(h);
4421 }
4422
4423 /* Send a message CDB to the firmware. */
4424 static __devinit int cciss_message(struct pci_dev *pdev, unsigned char opcode, unsigned char type)
4425 {
4426 typedef struct {
4427 CommandListHeader_struct CommandHeader;
4428 RequestBlock_struct Request;
4429 ErrDescriptor_struct ErrorDescriptor;
4430 } Command;
4431 static const size_t cmd_sz = sizeof(Command) + sizeof(ErrorInfo_struct);
4432 Command *cmd;
4433 dma_addr_t paddr64;
4434 uint32_t paddr32, tag;
4435 void __iomem *vaddr;
4436 int i, err;
4437
4438 vaddr = ioremap_nocache(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
4439 if (vaddr == NULL)
4440 return -ENOMEM;
4441
4442 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
4443 CCISS commands, so they must be allocated from the lower 4GiB of
4444 memory. */
4445 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4446 if (err) {
4447 iounmap(vaddr);
4448 return -ENOMEM;
4449 }
4450
4451 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
4452 if (cmd == NULL) {
4453 iounmap(vaddr);
4454 return -ENOMEM;
4455 }
4456
4457 /* This must fit, because of the 32-bit consistent DMA mask. Also,
4458 although there's no guarantee, we assume that the address is at
4459 least 4-byte aligned (most likely, it's page-aligned). */
4460 paddr32 = paddr64;
4461
4462 cmd->CommandHeader.ReplyQueue = 0;
4463 cmd->CommandHeader.SGList = 0;
4464 cmd->CommandHeader.SGTotal = 0;
4465 cmd->CommandHeader.Tag.lower = paddr32;
4466 cmd->CommandHeader.Tag.upper = 0;
4467 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
4468
4469 cmd->Request.CDBLen = 16;
4470 cmd->Request.Type.Type = TYPE_MSG;
4471 cmd->Request.Type.Attribute = ATTR_HEADOFQUEUE;
4472 cmd->Request.Type.Direction = XFER_NONE;
4473 cmd->Request.Timeout = 0; /* Don't time out */
4474 cmd->Request.CDB[0] = opcode;
4475 cmd->Request.CDB[1] = type;
4476 memset(&cmd->Request.CDB[2], 0, 14); /* the rest of the CDB is reserved */
4477
4478 cmd->ErrorDescriptor.Addr.lower = paddr32 + sizeof(Command);
4479 cmd->ErrorDescriptor.Addr.upper = 0;
4480 cmd->ErrorDescriptor.Len = sizeof(ErrorInfo_struct);
4481
4482 writel(paddr32, vaddr + SA5_REQUEST_PORT_OFFSET);
4483
4484 for (i = 0; i < 10; i++) {
4485 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
4486 if ((tag & ~3) == paddr32)
4487 break;
4488 msleep(CCISS_POST_RESET_NOOP_TIMEOUT_MSECS);
4489 }
4490
4491 iounmap(vaddr);
4492
4493 /* we leak the DMA buffer here ... no choice since the controller could
4494 still complete the command. */
4495 if (i == 10) {
4496 dev_err(&pdev->dev,
4497 "controller message %02x:%02x timed out\n",
4498 opcode, type);
4499 return -ETIMEDOUT;
4500 }
4501
4502 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
4503
4504 if (tag & 2) {
4505 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
4506 opcode, type);
4507 return -EIO;
4508 }
4509
4510 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
4511 opcode, type);
4512 return 0;
4513 }
4514
4515 #define cciss_noop(p) cciss_message(p, 3, 0)
4516
4517 static int cciss_controller_hard_reset(struct pci_dev *pdev,
4518 void * __iomem vaddr, u32 use_doorbell)
4519 {
4520 u16 pmcsr;
4521 int pos;
4522
4523 if (use_doorbell) {
4524 /* For everything after the P600, the PCI power state method
4525 * of resetting the controller doesn't work, so we have this
4526 * other way using the doorbell register.
4527 */
4528 dev_info(&pdev->dev, "using doorbell to reset controller\n");
4529 writel(use_doorbell, vaddr + SA5_DOORBELL);
4530 } else { /* Try to do it the PCI power state way */
4531
4532 /* Quoting from the Open CISS Specification: "The Power
4533 * Management Control/Status Register (CSR) controls the power
4534 * state of the device. The normal operating state is D0,
4535 * CSR=00h. The software off state is D3, CSR=03h. To reset
4536 * the controller, place the interface device in D3 then to D0,
4537 * this causes a secondary PCI reset which will reset the
4538 * controller." */
4539
4540 pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
4541 if (pos == 0) {
4542 dev_err(&pdev->dev,
4543 "cciss_controller_hard_reset: "
4544 "PCI PM not supported\n");
4545 return -ENODEV;
4546 }
4547 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
4548 /* enter the D3hot power management state */
4549 pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr);
4550 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
4551 pmcsr |= PCI_D3hot;
4552 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
4553
4554 msleep(500);
4555
4556 /* enter the D0 power management state */
4557 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
4558 pmcsr |= PCI_D0;
4559 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
4560 }
4561 return 0;
4562 }
4563
4564 static __devinit void init_driver_version(char *driver_version, int len)
4565 {
4566 memset(driver_version, 0, len);
4567 strncpy(driver_version, "cciss " DRIVER_NAME, len - 1);
4568 }
4569
4570 static __devinit int write_driver_ver_to_cfgtable(
4571 CfgTable_struct __iomem *cfgtable)
4572 {
4573 char *driver_version;
4574 int i, size = sizeof(cfgtable->driver_version);
4575
4576 driver_version = kmalloc(size, GFP_KERNEL);
4577 if (!driver_version)
4578 return -ENOMEM;
4579
4580 init_driver_version(driver_version, size);
4581 for (i = 0; i < size; i++)
4582 writeb(driver_version[i], &cfgtable->driver_version[i]);
4583 kfree(driver_version);
4584 return 0;
4585 }
4586
4587 static __devinit void read_driver_ver_from_cfgtable(
4588 CfgTable_struct __iomem *cfgtable, unsigned char *driver_ver)
4589 {
4590 int i;
4591
4592 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
4593 driver_ver[i] = readb(&cfgtable->driver_version[i]);
4594 }
4595
4596 static __devinit int controller_reset_failed(
4597 CfgTable_struct __iomem *cfgtable)
4598 {
4599
4600 char *driver_ver, *old_driver_ver;
4601 int rc, size = sizeof(cfgtable->driver_version);
4602
4603 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
4604 if (!old_driver_ver)
4605 return -ENOMEM;
4606 driver_ver = old_driver_ver + size;
4607
4608 /* After a reset, the 32 bytes of "driver version" in the cfgtable
4609 * should have been changed, otherwise we know the reset failed.
4610 */
4611 init_driver_version(old_driver_ver, size);
4612 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
4613 rc = !memcmp(driver_ver, old_driver_ver, size);
4614 kfree(old_driver_ver);
4615 return rc;
4616 }
4617
4618 /* This does a hard reset of the controller using PCI power management
4619 * states or using the doorbell register. */
4620 static __devinit int cciss_kdump_hard_reset_controller(struct pci_dev *pdev)
4621 {
4622 u64 cfg_offset;
4623 u32 cfg_base_addr;
4624 u64 cfg_base_addr_index;
4625 void __iomem *vaddr;
4626 unsigned long paddr;
4627 u32 misc_fw_support;
4628 int rc;
4629 CfgTable_struct __iomem *cfgtable;
4630 u32 use_doorbell;
4631 u32 board_id;
4632 u16 command_register;
4633
4634 /* For controllers as old a the p600, this is very nearly
4635 * the same thing as
4636 *
4637 * pci_save_state(pci_dev);
4638 * pci_set_power_state(pci_dev, PCI_D3hot);
4639 * pci_set_power_state(pci_dev, PCI_D0);
4640 * pci_restore_state(pci_dev);
4641 *
4642 * For controllers newer than the P600, the pci power state
4643 * method of resetting doesn't work so we have another way
4644 * using the doorbell register.
4645 */
4646
4647 /* Exclude 640x boards. These are two pci devices in one slot
4648 * which share a battery backed cache module. One controls the
4649 * cache, the other accesses the cache through the one that controls
4650 * it. If we reset the one controlling the cache, the other will
4651 * likely not be happy. Just forbid resetting this conjoined mess.
4652 */
4653 cciss_lookup_board_id(pdev, &board_id);
4654 if (!ctlr_is_resettable(board_id)) {
4655 dev_warn(&pdev->dev, "Cannot reset Smart Array 640x "
4656 "due to shared cache module.");
4657 return -ENODEV;
4658 }
4659
4660 /* if controller is soft- but not hard resettable... */
4661 if (!ctlr_is_hard_resettable(board_id))
4662 return -ENOTSUPP; /* try soft reset later. */
4663
4664 /* Save the PCI command register */
4665 pci_read_config_word(pdev, 4, &command_register);
4666 /* Turn the board off. This is so that later pci_restore_state()
4667 * won't turn the board on before the rest of config space is ready.
4668 */
4669 pci_disable_device(pdev);
4670 pci_save_state(pdev);
4671
4672 /* find the first memory BAR, so we can find the cfg table */
4673 rc = cciss_pci_find_memory_BAR(pdev, &paddr);
4674 if (rc)
4675 return rc;
4676 vaddr = remap_pci_mem(paddr, 0x250);
4677 if (!vaddr)
4678 return -ENOMEM;
4679
4680 /* find cfgtable in order to check if reset via doorbell is supported */
4681 rc = cciss_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
4682 &cfg_base_addr_index, &cfg_offset);
4683 if (rc)
4684 goto unmap_vaddr;
4685 cfgtable = remap_pci_mem(pci_resource_start(pdev,
4686 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
4687 if (!cfgtable) {
4688 rc = -ENOMEM;
4689 goto unmap_vaddr;
4690 }
4691 rc = write_driver_ver_to_cfgtable(cfgtable);
4692 if (rc)
4693 goto unmap_vaddr;
4694
4695 /* If reset via doorbell register is supported, use that.
4696 * There are two such methods. Favor the newest method.
4697 */
4698 misc_fw_support = readl(&cfgtable->misc_fw_support);
4699 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
4700 if (use_doorbell) {
4701 use_doorbell = DOORBELL_CTLR_RESET2;
4702 } else {
4703 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
4704 if (use_doorbell) {
4705 dev_warn(&pdev->dev, "Controller claims that "
4706 "'Bit 2 doorbell reset' is "
4707 "supported, but not 'bit 5 doorbell reset'. "
4708 "Firmware update is recommended.\n");
4709 rc = -ENOTSUPP; /* use the soft reset */
4710 goto unmap_cfgtable;
4711 }
4712 }
4713
4714 rc = cciss_controller_hard_reset(pdev, vaddr, use_doorbell);
4715 if (rc)
4716 goto unmap_cfgtable;
4717 pci_restore_state(pdev);
4718 rc = pci_enable_device(pdev);
4719 if (rc) {
4720 dev_warn(&pdev->dev, "failed to enable device.\n");
4721 goto unmap_cfgtable;
4722 }
4723 pci_write_config_word(pdev, 4, command_register);
4724
4725 /* Some devices (notably the HP Smart Array 5i Controller)
4726 need a little pause here */
4727 msleep(CCISS_POST_RESET_PAUSE_MSECS);
4728
4729 /* Wait for board to become not ready, then ready. */
4730 dev_info(&pdev->dev, "Waiting for board to reset.\n");
4731 rc = cciss_wait_for_board_state(pdev, vaddr, BOARD_NOT_READY);
4732 if (rc) {
4733 dev_warn(&pdev->dev, "Failed waiting for board to hard reset."
4734 " Will try soft reset.\n");
4735 rc = -ENOTSUPP; /* Not expected, but try soft reset later */
4736 goto unmap_cfgtable;
4737 }
4738 rc = cciss_wait_for_board_state(pdev, vaddr, BOARD_READY);
4739 if (rc) {
4740 dev_warn(&pdev->dev,
4741 "failed waiting for board to become ready "
4742 "after hard reset\n");
4743 goto unmap_cfgtable;
4744 }
4745
4746 rc = controller_reset_failed(vaddr);
4747 if (rc < 0)
4748 goto unmap_cfgtable;
4749 if (rc) {
4750 dev_warn(&pdev->dev, "Unable to successfully hard reset "
4751 "controller. Will try soft reset.\n");
4752 rc = -ENOTSUPP; /* Not expected, but try soft reset later */
4753 } else {
4754 dev_info(&pdev->dev, "Board ready after hard reset.\n");
4755 }
4756
4757 unmap_cfgtable:
4758 iounmap(cfgtable);
4759
4760 unmap_vaddr:
4761 iounmap(vaddr);
4762 return rc;
4763 }
4764
4765 static __devinit int cciss_init_reset_devices(struct pci_dev *pdev)
4766 {
4767 int rc, i;
4768
4769 if (!reset_devices)
4770 return 0;
4771
4772 /* Reset the controller with a PCI power-cycle or via doorbell */
4773 rc = cciss_kdump_hard_reset_controller(pdev);
4774
4775 /* -ENOTSUPP here means we cannot reset the controller
4776 * but it's already (and still) up and running in
4777 * "performant mode". Or, it might be 640x, which can't reset
4778 * due to concerns about shared bbwc between 6402/6404 pair.
4779 */
4780 if (rc == -ENOTSUPP)
4781 return rc; /* just try to do the kdump anyhow. */
4782 if (rc)
4783 return -ENODEV;
4784
4785 /* Now try to get the controller to respond to a no-op */
4786 dev_warn(&pdev->dev, "Waiting for controller to respond to no-op\n");
4787 for (i = 0; i < CCISS_POST_RESET_NOOP_RETRIES; i++) {
4788 if (cciss_noop(pdev) == 0)
4789 break;
4790 else
4791 dev_warn(&pdev->dev, "no-op failed%s\n",
4792 (i < CCISS_POST_RESET_NOOP_RETRIES - 1 ?
4793 "; re-trying" : ""));
4794 msleep(CCISS_POST_RESET_NOOP_INTERVAL_MSECS);
4795 }
4796 return 0;
4797 }
4798
4799 static __devinit int cciss_allocate_cmd_pool(ctlr_info_t *h)
4800 {
4801 h->cmd_pool_bits = kmalloc(
4802 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
4803 sizeof(unsigned long), GFP_KERNEL);
4804 h->cmd_pool = pci_alloc_consistent(h->pdev,
4805 h->nr_cmds * sizeof(CommandList_struct),
4806 &(h->cmd_pool_dhandle));
4807 h->errinfo_pool = pci_alloc_consistent(h->pdev,
4808 h->nr_cmds * sizeof(ErrorInfo_struct),
4809 &(h->errinfo_pool_dhandle));
4810 if ((h->cmd_pool_bits == NULL)
4811 || (h->cmd_pool == NULL)
4812 || (h->errinfo_pool == NULL)) {
4813 dev_err(&h->pdev->dev, "out of memory");
4814 return -ENOMEM;
4815 }
4816 return 0;
4817 }
4818
4819 static __devinit int cciss_allocate_scatterlists(ctlr_info_t *h)
4820 {
4821 int i;
4822
4823 /* zero it, so that on free we need not know how many were alloc'ed */
4824 h->scatter_list = kzalloc(h->max_commands *
4825 sizeof(struct scatterlist *), GFP_KERNEL);
4826 if (!h->scatter_list)
4827 return -ENOMEM;
4828
4829 for (i = 0; i < h->nr_cmds; i++) {
4830 h->scatter_list[i] = kmalloc(sizeof(struct scatterlist) *
4831 h->maxsgentries, GFP_KERNEL);
4832 if (h->scatter_list[i] == NULL) {
4833 dev_err(&h->pdev->dev, "could not allocate "
4834 "s/g lists\n");
4835 return -ENOMEM;
4836 }
4837 }
4838 return 0;
4839 }
4840
4841 static void cciss_free_scatterlists(ctlr_info_t *h)
4842 {
4843 int i;
4844
4845 if (h->scatter_list) {
4846 for (i = 0; i < h->nr_cmds; i++)
4847 kfree(h->scatter_list[i]);
4848 kfree(h->scatter_list);
4849 }
4850 }
4851
4852 static void cciss_free_cmd_pool(ctlr_info_t *h)
4853 {
4854 kfree(h->cmd_pool_bits);
4855 if (h->cmd_pool)
4856 pci_free_consistent(h->pdev,
4857 h->nr_cmds * sizeof(CommandList_struct),
4858 h->cmd_pool, h->cmd_pool_dhandle);
4859 if (h->errinfo_pool)
4860 pci_free_consistent(h->pdev,
4861 h->nr_cmds * sizeof(ErrorInfo_struct),
4862 h->errinfo_pool, h->errinfo_pool_dhandle);
4863 }
4864
4865 static int cciss_request_irq(ctlr_info_t *h,
4866 irqreturn_t (*msixhandler)(int, void *),
4867 irqreturn_t (*intxhandler)(int, void *))
4868 {
4869 if (h->msix_vector || h->msi_vector) {
4870 if (!request_irq(h->intr[h->intr_mode], msixhandler,
4871 IRQF_DISABLED, h->devname, h))
4872 return 0;
4873 dev_err(&h->pdev->dev, "Unable to get msi irq %d"
4874 " for %s\n", h->intr[h->intr_mode],
4875 h->devname);
4876 return -1;
4877 }
4878
4879 if (!request_irq(h->intr[h->intr_mode], intxhandler,
4880 IRQF_DISABLED, h->devname, h))
4881 return 0;
4882 dev_err(&h->pdev->dev, "Unable to get irq %d for %s\n",
4883 h->intr[h->intr_mode], h->devname);
4884 return -1;
4885 }
4886
4887 static int __devinit cciss_kdump_soft_reset(ctlr_info_t *h)
4888 {
4889 if (cciss_send_reset(h, CTLR_LUNID, CCISS_RESET_TYPE_CONTROLLER)) {
4890 dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
4891 return -EIO;
4892 }
4893
4894 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
4895 if (cciss_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
4896 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
4897 return -1;
4898 }
4899
4900 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
4901 if (cciss_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
4902 dev_warn(&h->pdev->dev, "Board failed to become ready "
4903 "after soft reset.\n");
4904 return -1;
4905 }
4906
4907 return 0;
4908 }
4909
4910 static void cciss_undo_allocations_after_kdump_soft_reset(ctlr_info_t *h)
4911 {
4912 int ctlr = h->ctlr;
4913
4914 free_irq(h->intr[h->intr_mode], h);
4915 #ifdef CONFIG_PCI_MSI
4916 if (h->msix_vector)
4917 pci_disable_msix(h->pdev);
4918 else if (h->msi_vector)
4919 pci_disable_msi(h->pdev);
4920 #endif /* CONFIG_PCI_MSI */
4921 cciss_free_sg_chain_blocks(h->cmd_sg_list, h->nr_cmds);
4922 cciss_free_scatterlists(h);
4923 cciss_free_cmd_pool(h);
4924 kfree(h->blockFetchTable);
4925 if (h->reply_pool)
4926 pci_free_consistent(h->pdev, h->max_commands * sizeof(__u64),
4927 h->reply_pool, h->reply_pool_dhandle);
4928 if (h->transtable)
4929 iounmap(h->transtable);
4930 if (h->cfgtable)
4931 iounmap(h->cfgtable);
4932 if (h->vaddr)
4933 iounmap(h->vaddr);
4934 unregister_blkdev(h->major, h->devname);
4935 cciss_destroy_hba_sysfs_entry(h);
4936 pci_release_regions(h->pdev);
4937 kfree(h);
4938 hba[ctlr] = NULL;
4939 }
4940
4941 /*
4942 * This is it. Find all the controllers and register them. I really hate
4943 * stealing all these major device numbers.
4944 * returns the number of block devices registered.
4945 */
4946 static int __devinit cciss_init_one(struct pci_dev *pdev,
4947 const struct pci_device_id *ent)
4948 {
4949 int i;
4950 int j = 0;
4951 int rc;
4952 int try_soft_reset = 0;
4953 int dac, return_code;
4954 InquiryData_struct *inq_buff;
4955 ctlr_info_t *h;
4956 unsigned long flags;
4957
4958 rc = cciss_init_reset_devices(pdev);
4959 if (rc) {
4960 if (rc != -ENOTSUPP)
4961 return rc;
4962 /* If the reset fails in a particular way (it has no way to do
4963 * a proper hard reset, so returns -ENOTSUPP) we can try to do
4964 * a soft reset once we get the controller configured up to the
4965 * point that it can accept a command.
4966 */
4967 try_soft_reset = 1;
4968 rc = 0;
4969 }
4970
4971 reinit_after_soft_reset:
4972
4973 i = alloc_cciss_hba(pdev);
4974 if (i < 0)
4975 return -1;
4976
4977 h = hba[i];
4978 h->pdev = pdev;
4979 h->busy_initializing = 1;
4980 h->intr_mode = cciss_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
4981 INIT_LIST_HEAD(&h->cmpQ);
4982 INIT_LIST_HEAD(&h->reqQ);
4983 mutex_init(&h->busy_shutting_down);
4984
4985 if (cciss_pci_init(h) != 0)
4986 goto clean_no_release_regions;
4987
4988 sprintf(h->devname, "cciss%d", i);
4989 h->ctlr = i;
4990
4991 if (cciss_tape_cmds < 2)
4992 cciss_tape_cmds = 2;
4993 if (cciss_tape_cmds > 16)
4994 cciss_tape_cmds = 16;
4995
4996 init_completion(&h->scan_wait);
4997
4998 if (cciss_create_hba_sysfs_entry(h))
4999 goto clean0;
5000
5001 /* configure PCI DMA stuff */
5002 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))
5003 dac = 1;
5004 else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))
5005 dac = 0;
5006 else {
5007 dev_err(&h->pdev->dev, "no suitable DMA available\n");
5008 goto clean1;
5009 }
5010
5011 /*
5012 * register with the major number, or get a dynamic major number
5013 * by passing 0 as argument. This is done for greater than
5014 * 8 controller support.
5015 */
5016 if (i < MAX_CTLR_ORIG)
5017 h->major = COMPAQ_CISS_MAJOR + i;
5018 rc = register_blkdev(h->major, h->devname);
5019 if (rc == -EBUSY || rc == -EINVAL) {
5020 dev_err(&h->pdev->dev,
5021 "Unable to get major number %d for %s "
5022 "on hba %d\n", h->major, h->devname, i);
5023 goto clean1;
5024 } else {
5025 if (i >= MAX_CTLR_ORIG)
5026 h->major = rc;
5027 }
5028
5029 /* make sure the board interrupts are off */
5030 h->access.set_intr_mask(h, CCISS_INTR_OFF);
5031 rc = cciss_request_irq(h, do_cciss_msix_intr, do_cciss_intx);
5032 if (rc)
5033 goto clean2;
5034
5035 dev_info(&h->pdev->dev, "%s: <0x%x> at PCI %s IRQ %d%s using DAC\n",
5036 h->devname, pdev->device, pci_name(pdev),
5037 h->intr[h->intr_mode], dac ? "" : " not");
5038
5039 if (cciss_allocate_cmd_pool(h))
5040 goto clean4;
5041
5042 if (cciss_allocate_scatterlists(h))
5043 goto clean4;
5044
5045 h->cmd_sg_list = cciss_allocate_sg_chain_blocks(h,
5046 h->chainsize, h->nr_cmds);
5047 if (!h->cmd_sg_list && h->chainsize > 0)
5048 goto clean4;
5049
5050 spin_lock_init(&h->lock);
5051
5052 /* Initialize the pdev driver private data.
5053 have it point to h. */
5054 pci_set_drvdata(pdev, h);
5055 /* command and error info recs zeroed out before
5056 they are used */
5057 memset(h->cmd_pool_bits, 0,
5058 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG)
5059 * sizeof(unsigned long));
5060
5061 h->num_luns = 0;
5062 h->highest_lun = -1;
5063 for (j = 0; j < CISS_MAX_LUN; j++) {
5064 h->drv[j] = NULL;
5065 h->gendisk[j] = NULL;
5066 }
5067
5068 /* At this point, the controller is ready to take commands.
5069 * Now, if reset_devices and the hard reset didn't work, try
5070 * the soft reset and see if that works.
5071 */
5072 if (try_soft_reset) {
5073
5074 /* This is kind of gross. We may or may not get a completion
5075 * from the soft reset command, and if we do, then the value
5076 * from the fifo may or may not be valid. So, we wait 10 secs
5077 * after the reset throwing away any completions we get during
5078 * that time. Unregister the interrupt handler and register
5079 * fake ones to scoop up any residual completions.
5080 */
5081 spin_lock_irqsave(&h->lock, flags);
5082 h->access.set_intr_mask(h, CCISS_INTR_OFF);
5083 spin_unlock_irqrestore(&h->lock, flags);
5084 free_irq(h->intr[h->intr_mode], h);
5085 rc = cciss_request_irq(h, cciss_msix_discard_completions,
5086 cciss_intx_discard_completions);
5087 if (rc) {
5088 dev_warn(&h->pdev->dev, "Failed to request_irq after "
5089 "soft reset.\n");
5090 goto clean4;
5091 }
5092
5093 rc = cciss_kdump_soft_reset(h);
5094 if (rc) {
5095 dev_warn(&h->pdev->dev, "Soft reset failed.\n");
5096 goto clean4;
5097 }
5098
5099 dev_info(&h->pdev->dev, "Board READY.\n");
5100 dev_info(&h->pdev->dev,
5101 "Waiting for stale completions to drain.\n");
5102 h->access.set_intr_mask(h, CCISS_INTR_ON);
5103 msleep(10000);
5104 h->access.set_intr_mask(h, CCISS_INTR_OFF);
5105
5106 rc = controller_reset_failed(h->cfgtable);
5107 if (rc)
5108 dev_info(&h->pdev->dev,
5109 "Soft reset appears to have failed.\n");
5110
5111 /* since the controller's reset, we have to go back and re-init
5112 * everything. Easiest to just forget what we've done and do it
5113 * all over again.
5114 */
5115 cciss_undo_allocations_after_kdump_soft_reset(h);
5116 try_soft_reset = 0;
5117 if (rc)
5118 /* don't go to clean4, we already unallocated */
5119 return -ENODEV;
5120
5121 goto reinit_after_soft_reset;
5122 }
5123
5124 cciss_scsi_setup(h);
5125
5126 /* Turn the interrupts on so we can service requests */
5127 h->access.set_intr_mask(h, CCISS_INTR_ON);
5128
5129 /* Get the firmware version */
5130 inq_buff = kzalloc(sizeof(InquiryData_struct), GFP_KERNEL);
5131 if (inq_buff == NULL) {
5132 dev_err(&h->pdev->dev, "out of memory\n");
5133 goto clean4;
5134 }
5135
5136 return_code = sendcmd_withirq(h, CISS_INQUIRY, inq_buff,
5137 sizeof(InquiryData_struct), 0, CTLR_LUNID, TYPE_CMD);
5138 if (return_code == IO_OK) {
5139 h->firm_ver[0] = inq_buff->data_byte[32];
5140 h->firm_ver[1] = inq_buff->data_byte[33];
5141 h->firm_ver[2] = inq_buff->data_byte[34];
5142 h->firm_ver[3] = inq_buff->data_byte[35];
5143 } else { /* send command failed */
5144 dev_warn(&h->pdev->dev, "unable to determine firmware"
5145 " version of controller\n");
5146 }
5147 kfree(inq_buff);
5148
5149 cciss_procinit(h);
5150
5151 h->cciss_max_sectors = 8192;
5152
5153 rebuild_lun_table(h, 1, 0);
5154 h->busy_initializing = 0;
5155 return 1;
5156
5157 clean4:
5158 cciss_free_cmd_pool(h);
5159 cciss_free_scatterlists(h);
5160 cciss_free_sg_chain_blocks(h->cmd_sg_list, h->nr_cmds);
5161 free_irq(h->intr[h->intr_mode], h);
5162 clean2:
5163 unregister_blkdev(h->major, h->devname);
5164 clean1:
5165 cciss_destroy_hba_sysfs_entry(h);
5166 clean0:
5167 pci_release_regions(pdev);
5168 clean_no_release_regions:
5169 h->busy_initializing = 0;
5170
5171 /*
5172 * Deliberately omit pci_disable_device(): it does something nasty to
5173 * Smart Array controllers that pci_enable_device does not undo
5174 */
5175 pci_set_drvdata(pdev, NULL);
5176 free_hba(h);
5177 return -1;
5178 }
5179
5180 static void cciss_shutdown(struct pci_dev *pdev)
5181 {
5182 ctlr_info_t *h;
5183 char *flush_buf;
5184 int return_code;
5185
5186 h = pci_get_drvdata(pdev);
5187 flush_buf = kzalloc(4, GFP_KERNEL);
5188 if (!flush_buf) {
5189 dev_warn(&h->pdev->dev, "cache not flushed, out of memory.\n");
5190 return;
5191 }
5192 /* write all data in the battery backed cache to disk */
5193 memset(flush_buf, 0, 4);
5194 return_code = sendcmd_withirq(h, CCISS_CACHE_FLUSH, flush_buf,
5195 4, 0, CTLR_LUNID, TYPE_CMD);
5196 kfree(flush_buf);
5197 if (return_code != IO_OK)
5198 dev_warn(&h->pdev->dev, "Error flushing cache\n");
5199 h->access.set_intr_mask(h, CCISS_INTR_OFF);
5200 free_irq(h->intr[h->intr_mode], h);
5201 }
5202
5203 static int __devinit cciss_enter_simple_mode(struct ctlr_info *h)
5204 {
5205 u32 trans_support;
5206
5207 trans_support = readl(&(h->cfgtable->TransportSupport));
5208 if (!(trans_support & SIMPLE_MODE))
5209 return -ENOTSUPP;
5210
5211 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
5212 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
5213 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
5214 cciss_wait_for_mode_change_ack(h);
5215 print_cfg_table(h);
5216 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple)) {
5217 dev_warn(&h->pdev->dev, "unable to get board into simple mode\n");
5218 return -ENODEV;
5219 }
5220 h->transMethod = CFGTBL_Trans_Simple;
5221 return 0;
5222 }
5223
5224
5225 static void __devexit cciss_remove_one(struct pci_dev *pdev)
5226 {
5227 ctlr_info_t *h;
5228 int i, j;
5229
5230 if (pci_get_drvdata(pdev) == NULL) {
5231 dev_err(&pdev->dev, "Unable to remove device\n");
5232 return;
5233 }
5234
5235 h = pci_get_drvdata(pdev);
5236 i = h->ctlr;
5237 if (hba[i] == NULL) {
5238 dev_err(&pdev->dev, "device appears to already be removed\n");
5239 return;
5240 }
5241
5242 mutex_lock(&h->busy_shutting_down);
5243
5244 remove_from_scan_list(h);
5245 remove_proc_entry(h->devname, proc_cciss);
5246 unregister_blkdev(h->major, h->devname);
5247
5248 /* remove it from the disk list */
5249 for (j = 0; j < CISS_MAX_LUN; j++) {
5250 struct gendisk *disk = h->gendisk[j];
5251 if (disk) {
5252 struct request_queue *q = disk->queue;
5253
5254 if (disk->flags & GENHD_FL_UP) {
5255 cciss_destroy_ld_sysfs_entry(h, j, 1);
5256 del_gendisk(disk);
5257 }
5258 if (q)
5259 blk_cleanup_queue(q);
5260 }
5261 }
5262
5263 #ifdef CONFIG_CISS_SCSI_TAPE
5264 cciss_unregister_scsi(h); /* unhook from SCSI subsystem */
5265 #endif
5266
5267 cciss_shutdown(pdev);
5268
5269 #ifdef CONFIG_PCI_MSI
5270 if (h->msix_vector)
5271 pci_disable_msix(h->pdev);
5272 else if (h->msi_vector)
5273 pci_disable_msi(h->pdev);
5274 #endif /* CONFIG_PCI_MSI */
5275
5276 iounmap(h->transtable);
5277 iounmap(h->cfgtable);
5278 iounmap(h->vaddr);
5279
5280 cciss_free_cmd_pool(h);
5281 /* Free up sg elements */
5282 for (j = 0; j < h->nr_cmds; j++)
5283 kfree(h->scatter_list[j]);
5284 kfree(h->scatter_list);
5285 cciss_free_sg_chain_blocks(h->cmd_sg_list, h->nr_cmds);
5286 kfree(h->blockFetchTable);
5287 if (h->reply_pool)
5288 pci_free_consistent(h->pdev, h->max_commands * sizeof(__u64),
5289 h->reply_pool, h->reply_pool_dhandle);
5290 /*
5291 * Deliberately omit pci_disable_device(): it does something nasty to
5292 * Smart Array controllers that pci_enable_device does not undo
5293 */
5294 pci_release_regions(pdev);
5295 pci_set_drvdata(pdev, NULL);
5296 cciss_destroy_hba_sysfs_entry(h);
5297 mutex_unlock(&h->busy_shutting_down);
5298 free_hba(h);
5299 }
5300
5301 static struct pci_driver cciss_pci_driver = {
5302 .name = "cciss",
5303 .probe = cciss_init_one,
5304 .remove = __devexit_p(cciss_remove_one),
5305 .id_table = cciss_pci_device_id, /* id_table */
5306 .shutdown = cciss_shutdown,
5307 };
5308
5309 /*
5310 * This is it. Register the PCI driver information for the cards we control
5311 * the OS will call our registered routines when it finds one of our cards.
5312 */
5313 static int __init cciss_init(void)
5314 {
5315 int err;
5316
5317 /*
5318 * The hardware requires that commands are aligned on a 64-bit
5319 * boundary. Given that we use pci_alloc_consistent() to allocate an
5320 * array of them, the size must be a multiple of 8 bytes.
5321 */
5322 BUILD_BUG_ON(sizeof(CommandList_struct) % COMMANDLIST_ALIGNMENT);
5323 printk(KERN_INFO DRIVER_NAME "\n");
5324
5325 err = bus_register(&cciss_bus_type);
5326 if (err)
5327 return err;
5328
5329 /* Start the scan thread */
5330 cciss_scan_thread = kthread_run(scan_thread, NULL, "cciss_scan");
5331 if (IS_ERR(cciss_scan_thread)) {
5332 err = PTR_ERR(cciss_scan_thread);
5333 goto err_bus_unregister;
5334 }
5335
5336 /* Register for our PCI devices */
5337 err = pci_register_driver(&cciss_pci_driver);
5338 if (err)
5339 goto err_thread_stop;
5340
5341 return err;
5342
5343 err_thread_stop:
5344 kthread_stop(cciss_scan_thread);
5345 err_bus_unregister:
5346 bus_unregister(&cciss_bus_type);
5347
5348 return err;
5349 }
5350
5351 static void __exit cciss_cleanup(void)
5352 {
5353 int i;
5354
5355 pci_unregister_driver(&cciss_pci_driver);
5356 /* double check that all controller entrys have been removed */
5357 for (i = 0; i < MAX_CTLR; i++) {
5358 if (hba[i] != NULL) {
5359 dev_warn(&hba[i]->pdev->dev,
5360 "had to remove controller\n");
5361 cciss_remove_one(hba[i]->pdev);
5362 }
5363 }
5364 kthread_stop(cciss_scan_thread);
5365 if (proc_cciss)
5366 remove_proc_entry("driver/cciss", NULL);
5367 bus_unregister(&cciss_bus_type);
5368 }
5369
5370 module_init(cciss_init);
5371 module_exit(cciss_cleanup);
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