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sfc: Update version, copyright dates, authors
[linux-2.6/next.git] / drivers / net / sfc / falcon.c
blob17afcd26e870c09058e8a3df8545d76566ccdb75
1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2009 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include <linux/i2c.h>
17 #include <linux/mii.h>
18 #include "net_driver.h"
19 #include "bitfield.h"
20 #include "efx.h"
21 #include "mac.h"
22 #include "spi.h"
23 #include "nic.h"
24 #include "regs.h"
25 #include "io.h"
26 #include "mdio_10g.h"
27 #include "phy.h"
28 #include "workarounds.h"
29
30 /* Hardware control for SFC4000 (aka Falcon). */
31
32 static const unsigned int
33 /* "Large" EEPROM device: Atmel AT25640 or similar
34 * 8 KB, 16-bit address, 32 B write block */
35 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
36 | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
37 | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
38 /* Default flash device: Atmel AT25F1024
39 * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
40 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
41 | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
42 | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
43 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
44 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
45
46 /**************************************************************************
47 *
48 * I2C bus - this is a bit-bashing interface using GPIO pins
49 * Note that it uses the output enables to tristate the outputs
50 * SDA is the data pin and SCL is the clock
51 *
52 **************************************************************************
53 */
54 static void falcon_setsda(void *data, int state)
55 {
56 struct efx_nic *efx = (struct efx_nic *)data;
57 efx_oword_t reg;
58
59 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
60 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
61 efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
62 }
63
64 static void falcon_setscl(void *data, int state)
65 {
66 struct efx_nic *efx = (struct efx_nic *)data;
67 efx_oword_t reg;
68
69 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
70 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
71 efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
72 }
73
74 static int falcon_getsda(void *data)
75 {
76 struct efx_nic *efx = (struct efx_nic *)data;
77 efx_oword_t reg;
78
79 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
80 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
81 }
82
83 static int falcon_getscl(void *data)
84 {
85 struct efx_nic *efx = (struct efx_nic *)data;
86 efx_oword_t reg;
87
88 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
89 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
90 }
91
92 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
93 .setsda = falcon_setsda,
94 .setscl = falcon_setscl,
95 .getsda = falcon_getsda,
96 .getscl = falcon_getscl,
97 .udelay = 5,
98 /* Wait up to 50 ms for slave to let us pull SCL high */
99 .timeout = DIV_ROUND_UP(HZ, 20),
100 };
101
102 static void falcon_push_irq_moderation(struct efx_channel *channel)
103 {
104 efx_dword_t timer_cmd;
105 struct efx_nic *efx = channel->efx;
106
107 /* Set timer register */
108 if (channel->irq_moderation) {
109 EFX_POPULATE_DWORD_2(timer_cmd,
110 FRF_AB_TC_TIMER_MODE,
111 FFE_BB_TIMER_MODE_INT_HLDOFF,
112 FRF_AB_TC_TIMER_VAL,
113 channel->irq_moderation - 1);
114 } else {
115 EFX_POPULATE_DWORD_2(timer_cmd,
116 FRF_AB_TC_TIMER_MODE,
117 FFE_BB_TIMER_MODE_DIS,
118 FRF_AB_TC_TIMER_VAL, 0);
119 }
120 BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
121 efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
122 channel->channel);
123 }
124
125 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx);
126
127 static void falcon_prepare_flush(struct efx_nic *efx)
128 {
129 falcon_deconfigure_mac_wrapper(efx);
130
131 /* Wait for the tx and rx fifo's to get to the next packet boundary
132 * (~1ms without back-pressure), then to drain the remainder of the
133 * fifo's at data path speeds (negligible), with a healthy margin. */
134 msleep(10);
135 }
136
137 /* Acknowledge a legacy interrupt from Falcon
138 *
139 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
140 *
141 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
142 * BIU. Interrupt acknowledge is read sensitive so must write instead
143 * (then read to ensure the BIU collector is flushed)
144 *
145 * NB most hardware supports MSI interrupts
146 */
147 inline void falcon_irq_ack_a1(struct efx_nic *efx)
148 {
149 efx_dword_t reg;
150
151 EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
152 efx_writed(efx, &reg, FR_AA_INT_ACK_KER);
153 efx_readd(efx, &reg, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
154 }
155
156
157 irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
158 {
159 struct efx_nic *efx = dev_id;
160 efx_oword_t *int_ker = efx->irq_status.addr;
161 struct efx_channel *channel;
162 int syserr;
163 int queues;
164
165 /* Check to see if this is our interrupt. If it isn't, we
166 * exit without having touched the hardware.
167 */
168 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
169 EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq,
170 raw_smp_processor_id());
171 return IRQ_NONE;
172 }
173 efx->last_irq_cpu = raw_smp_processor_id();
174 EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
175 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
176
177 /* Check to see if we have a serious error condition */
178 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
179 if (unlikely(syserr))
180 return efx_nic_fatal_interrupt(efx);
181
182 /* Determine interrupting queues, clear interrupt status
183 * register and acknowledge the device interrupt.
184 */
185 BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH > EFX_MAX_CHANNELS);
186 queues = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_INT_Q);
187 EFX_ZERO_OWORD(*int_ker);
188 wmb(); /* Ensure the vector is cleared before interrupt ack */
189 falcon_irq_ack_a1(efx);
190
191 /* Schedule processing of any interrupting queues */
192 channel = &efx->channel[0];
193 while (queues) {
194 if (queues & 0x01)
195 efx_schedule_channel(channel);
196 channel++;
197 queues >>= 1;
198 }
199
200 return IRQ_HANDLED;
201 }
202 /**************************************************************************
203 *
204 * EEPROM/flash
205 *
206 **************************************************************************
207 */
208
209 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
210
211 static int falcon_spi_poll(struct efx_nic *efx)
212 {
213 efx_oword_t reg;
214 efx_reado(efx, &reg, FR_AB_EE_SPI_HCMD);
215 return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
216 }
217
218 /* Wait for SPI command completion */
219 static int falcon_spi_wait(struct efx_nic *efx)
220 {
221 /* Most commands will finish quickly, so we start polling at
222 * very short intervals. Sometimes the command may have to
223 * wait for VPD or expansion ROM access outside of our
224 * control, so we allow up to 100 ms. */
225 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
226 int i;
227
228 for (i = 0; i < 10; i++) {
229 if (!falcon_spi_poll(efx))
230 return 0;
231 udelay(10);
232 }
233
234 for (;;) {
235 if (!falcon_spi_poll(efx))
236 return 0;
237 if (time_after_eq(jiffies, timeout)) {
238 EFX_ERR(efx, "timed out waiting for SPI\n");
239 return -ETIMEDOUT;
240 }
241 schedule_timeout_uninterruptible(1);
242 }
243 }
244
245 int falcon_spi_cmd(struct efx_nic *efx, const struct efx_spi_device *spi,
246 unsigned int command, int address,
247 const void *in, void *out, size_t len)
248 {
249 bool addressed = (address >= 0);
250 bool reading = (out != NULL);
251 efx_oword_t reg;
252 int rc;
253
254 /* Input validation */
255 if (len > FALCON_SPI_MAX_LEN)
256 return -EINVAL;
257 BUG_ON(!mutex_is_locked(&efx->spi_lock));
258
259 /* Check that previous command is not still running */
260 rc = falcon_spi_poll(efx);
261 if (rc)
262 return rc;
263
264 /* Program address register, if we have an address */
265 if (addressed) {
266 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
267 efx_writeo(efx, &reg, FR_AB_EE_SPI_HADR);
268 }
269
270 /* Program data register, if we have data */
271 if (in != NULL) {
272 memcpy(&reg, in, len);
273 efx_writeo(efx, &reg, FR_AB_EE_SPI_HDATA);
274 }
275
276 /* Issue read/write command */
277 EFX_POPULATE_OWORD_7(reg,
278 FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
279 FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
280 FRF_AB_EE_SPI_HCMD_DABCNT, len,
281 FRF_AB_EE_SPI_HCMD_READ, reading,
282 FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
283 FRF_AB_EE_SPI_HCMD_ADBCNT,
284 (addressed ? spi->addr_len : 0),
285 FRF_AB_EE_SPI_HCMD_ENC, command);
286 efx_writeo(efx, &reg, FR_AB_EE_SPI_HCMD);
287
288 /* Wait for read/write to complete */
289 rc = falcon_spi_wait(efx);
290 if (rc)
291 return rc;
292
293 /* Read data */
294 if (out != NULL) {
295 efx_reado(efx, &reg, FR_AB_EE_SPI_HDATA);
296 memcpy(out, &reg, len);
297 }
298
299 return 0;
300 }
301
302 static size_t
303 falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
304 {
305 return min(FALCON_SPI_MAX_LEN,
306 (spi->block_size - (start & (spi->block_size - 1))));
307 }
308
309 static inline u8
310 efx_spi_munge_command(const struct efx_spi_device *spi,
311 const u8 command, const unsigned int address)
312 {
313 return command | (((address >> 8) & spi->munge_address) << 3);
314 }
315
316 /* Wait up to 10 ms for buffered write completion */
317 int
318 falcon_spi_wait_write(struct efx_nic *efx, const struct efx_spi_device *spi)
319 {
320 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
321 u8 status;
322 int rc;
323
324 for (;;) {
325 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
326 &status, sizeof(status));
327 if (rc)
328 return rc;
329 if (!(status & SPI_STATUS_NRDY))
330 return 0;
331 if (time_after_eq(jiffies, timeout)) {
332 EFX_ERR(efx, "SPI write timeout on device %d"
333 " last status=0x%02x\n",
334 spi->device_id, status);
335 return -ETIMEDOUT;
336 }
337 schedule_timeout_uninterruptible(1);
338 }
339 }
340
341 int falcon_spi_read(struct efx_nic *efx, const struct efx_spi_device *spi,
342 loff_t start, size_t len, size_t *retlen, u8 *buffer)
343 {
344 size_t block_len, pos = 0;
345 unsigned int command;
346 int rc = 0;
347
348 while (pos < len) {
349 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
350
351 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
352 rc = falcon_spi_cmd(efx, spi, command, start + pos, NULL,
353 buffer + pos, block_len);
354 if (rc)
355 break;
356 pos += block_len;
357
358 /* Avoid locking up the system */
359 cond_resched();
360 if (signal_pending(current)) {
361 rc = -EINTR;
362 break;
363 }
364 }
365
366 if (retlen)
367 *retlen = pos;
368 return rc;
369 }
370
371 int
372 falcon_spi_write(struct efx_nic *efx, const struct efx_spi_device *spi,
373 loff_t start, size_t len, size_t *retlen, const u8 *buffer)
374 {
375 u8 verify_buffer[FALCON_SPI_MAX_LEN];
376 size_t block_len, pos = 0;
377 unsigned int command;
378 int rc = 0;
379
380 while (pos < len) {
381 rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
382 if (rc)
383 break;
384
385 block_len = min(len - pos,
386 falcon_spi_write_limit(spi, start + pos));
387 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
388 rc = falcon_spi_cmd(efx, spi, command, start + pos,
389 buffer + pos, NULL, block_len);
390 if (rc)
391 break;
392
393 rc = falcon_spi_wait_write(efx, spi);
394 if (rc)
395 break;
396
397 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
398 rc = falcon_spi_cmd(efx, spi, command, start + pos,
399 NULL, verify_buffer, block_len);
400 if (memcmp(verify_buffer, buffer + pos, block_len)) {
401 rc = -EIO;
402 break;
403 }
404
405 pos += block_len;
406
407 /* Avoid locking up the system */
408 cond_resched();
409 if (signal_pending(current)) {
410 rc = -EINTR;
411 break;
412 }
413 }
414
415 if (retlen)
416 *retlen = pos;
417 return rc;
418 }
419
420 /**************************************************************************
421 *
422 * MAC wrapper
423 *
424 **************************************************************************
425 */
426
427 static void falcon_push_multicast_hash(struct efx_nic *efx)
428 {
429 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
430
431 WARN_ON(!mutex_is_locked(&efx->mac_lock));
432
433 efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
434 efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
435 }
436
437 static void falcon_reset_macs(struct efx_nic *efx)
438 {
439 struct falcon_nic_data *nic_data = efx->nic_data;
440 efx_oword_t reg, mac_ctrl;
441 int count;
442
443 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
444 /* It's not safe to use GLB_CTL_REG to reset the
445 * macs, so instead use the internal MAC resets
446 */
447 if (!EFX_IS10G(efx)) {
448 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 1);
449 efx_writeo(efx, &reg, FR_AB_GM_CFG1);
450 udelay(1000);
451
452 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 0);
453 efx_writeo(efx, &reg, FR_AB_GM_CFG1);
454 udelay(1000);
455 return;
456 } else {
457 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
458 efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
459
460 for (count = 0; count < 10000; count++) {
461 efx_reado(efx, &reg, FR_AB_XM_GLB_CFG);
462 if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
463 0)
464 return;
465 udelay(10);
466 }
467
468 EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
469 }
470 }
471
472 /* Mac stats will fail whist the TX fifo is draining */
473 WARN_ON(nic_data->stats_disable_count == 0);
474
475 efx_reado(efx, &mac_ctrl, FR_AB_MAC_CTRL);
476 EFX_SET_OWORD_FIELD(mac_ctrl, FRF_BB_TXFIFO_DRAIN_EN, 1);
477 efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
478
479 efx_reado(efx, &reg, FR_AB_GLB_CTL);
480 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
481 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
482 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
483 efx_writeo(efx, &reg, FR_AB_GLB_CTL);
484
485 count = 0;
486 while (1) {
487 efx_reado(efx, &reg, FR_AB_GLB_CTL);
488 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
489 !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
490 !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
491 EFX_LOG(efx, "Completed MAC reset after %d loops\n",
492 count);
493 break;
494 }
495 if (count > 20) {
496 EFX_ERR(efx, "MAC reset failed\n");
497 break;
498 }
499 count++;
500 udelay(10);
501 }
502
503 /* Ensure the correct MAC is selected before statistics
504 * are re-enabled by the caller */
505 efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
506 }
507
508 void falcon_drain_tx_fifo(struct efx_nic *efx)
509 {
510 efx_oword_t reg;
511
512 if ((efx_nic_rev(efx) < EFX_REV_FALCON_B0) ||
513 (efx->loopback_mode != LOOPBACK_NONE))
514 return;
515
516 efx_reado(efx, &reg, FR_AB_MAC_CTRL);
517 /* There is no point in draining more than once */
518 if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
519 return;
520
521 falcon_reset_macs(efx);
522 }
523
524 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
525 {
526 efx_oword_t reg;
527
528 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
529 return;
530
531 /* Isolate the MAC -> RX */
532 efx_reado(efx, &reg, FR_AZ_RX_CFG);
533 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
534 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
535
536 /* Isolate TX -> MAC */
537 falcon_drain_tx_fifo(efx);
538 }
539
540 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
541 {
542 struct efx_link_state *link_state = &efx->link_state;
543 efx_oword_t reg;
544 int link_speed;
545
546 switch (link_state->speed) {
547 case 10000: link_speed = 3; break;
548 case 1000: link_speed = 2; break;
549 case 100: link_speed = 1; break;
550 default: link_speed = 0; break;
551 }
552 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
553 * as advertised. Disable to ensure packets are not
554 * indefinitely held and TX queue can be flushed at any point
555 * while the link is down. */
556 EFX_POPULATE_OWORD_5(reg,
557 FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
558 FRF_AB_MAC_BCAD_ACPT, 1,
559 FRF_AB_MAC_UC_PROM, efx->promiscuous,
560 FRF_AB_MAC_LINK_STATUS, 1, /* always set */
561 FRF_AB_MAC_SPEED, link_speed);
562 /* On B0, MAC backpressure can be disabled and packets get
563 * discarded. */
564 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
565 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
566 !link_state->up);
567 }
568
569 efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
570
571 /* Restore the multicast hash registers. */
572 falcon_push_multicast_hash(efx);
573
574 efx_reado(efx, &reg, FR_AZ_RX_CFG);
575 /* Enable XOFF signal from RX FIFO (we enabled it during NIC
576 * initialisation but it may read back as 0) */
577 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
578 /* Unisolate the MAC -> RX */
579 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
580 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
581 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
582 }
583
584 static void falcon_stats_request(struct efx_nic *efx)
585 {
586 struct falcon_nic_data *nic_data = efx->nic_data;
587 efx_oword_t reg;
588
589 WARN_ON(nic_data->stats_pending);
590 WARN_ON(nic_data->stats_disable_count);
591
592 if (nic_data->stats_dma_done == NULL)
593 return; /* no mac selected */
594
595 *nic_data->stats_dma_done = FALCON_STATS_NOT_DONE;
596 nic_data->stats_pending = true;
597 wmb(); /* ensure done flag is clear */
598
599 /* Initiate DMA transfer of stats */
600 EFX_POPULATE_OWORD_2(reg,
601 FRF_AB_MAC_STAT_DMA_CMD, 1,
602 FRF_AB_MAC_STAT_DMA_ADR,
603 efx->stats_buffer.dma_addr);
604 efx_writeo(efx, &reg, FR_AB_MAC_STAT_DMA);
605
606 mod_timer(&nic_data->stats_timer, round_jiffies_up(jiffies + HZ / 2));
607 }
608
609 static void falcon_stats_complete(struct efx_nic *efx)
610 {
611 struct falcon_nic_data *nic_data = efx->nic_data;
612
613 if (!nic_data->stats_pending)
614 return;
615
616 nic_data->stats_pending = 0;
617 if (*nic_data->stats_dma_done == FALCON_STATS_DONE) {
618 rmb(); /* read the done flag before the stats */
619 efx->mac_op->update_stats(efx);
620 } else {
621 EFX_ERR(efx, "timed out waiting for statistics\n");
622 }
623 }
624
625 static void falcon_stats_timer_func(unsigned long context)
626 {
627 struct efx_nic *efx = (struct efx_nic *)context;
628 struct falcon_nic_data *nic_data = efx->nic_data;
629
630 spin_lock(&efx->stats_lock);
631
632 falcon_stats_complete(efx);
633 if (nic_data->stats_disable_count == 0)
634 falcon_stats_request(efx);
635
636 spin_unlock(&efx->stats_lock);
637 }
638
639 static void falcon_switch_mac(struct efx_nic *efx);
640
641 static bool falcon_loopback_link_poll(struct efx_nic *efx)
642 {
643 struct efx_link_state old_state = efx->link_state;
644
645 WARN_ON(!mutex_is_locked(&efx->mac_lock));
646 WARN_ON(!LOOPBACK_INTERNAL(efx));
647
648 efx->link_state.fd = true;
649 efx->link_state.fc = efx->wanted_fc;
650 efx->link_state.up = true;
651
652 if (efx->loopback_mode == LOOPBACK_GMAC)
653 efx->link_state.speed = 1000;
654 else
655 efx->link_state.speed = 10000;
656
657 return !efx_link_state_equal(&efx->link_state, &old_state);
658 }
659
660 static int falcon_reconfigure_port(struct efx_nic *efx)
661 {
662 int rc;
663
664 WARN_ON(efx_nic_rev(efx) > EFX_REV_FALCON_B0);
665
666 /* Poll the PHY link state *before* reconfiguring it. This means we
667 * will pick up the correct speed (in loopback) to select the correct
668 * MAC.
669 */
670 if (LOOPBACK_INTERNAL(efx))
671 falcon_loopback_link_poll(efx);
672 else
673 efx->phy_op->poll(efx);
674
675 falcon_stop_nic_stats(efx);
676 falcon_deconfigure_mac_wrapper(efx);
677
678 falcon_switch_mac(efx);
679
680 efx->phy_op->reconfigure(efx);
681 rc = efx->mac_op->reconfigure(efx);
682 BUG_ON(rc);
683
684 falcon_start_nic_stats(efx);
685
686 /* Synchronise efx->link_state with the kernel */
687 efx_link_status_changed(efx);
688
689 return 0;
690 }
691
692 /**************************************************************************
693 *
694 * PHY access via GMII
695 *
696 **************************************************************************
697 */
698
699 /* Wait for GMII access to complete */
700 static int falcon_gmii_wait(struct efx_nic *efx)
701 {
702 efx_oword_t md_stat;
703 int count;
704
705 /* wait upto 50ms - taken max from datasheet */
706 for (count = 0; count < 5000; count++) {
707 efx_reado(efx, &md_stat, FR_AB_MD_STAT);
708 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
709 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
710 EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
711 EFX_ERR(efx, "error from GMII access "
712 EFX_OWORD_FMT"\n",
713 EFX_OWORD_VAL(md_stat));
714 return -EIO;
715 }
716 return 0;
717 }
718 udelay(10);
719 }
720 EFX_ERR(efx, "timed out waiting for GMII\n");
721 return -ETIMEDOUT;
722 }
723
724 /* Write an MDIO register of a PHY connected to Falcon. */
725 static int falcon_mdio_write(struct net_device *net_dev,
726 int prtad, int devad, u16 addr, u16 value)
727 {
728 struct efx_nic *efx = netdev_priv(net_dev);
729 efx_oword_t reg;
730 int rc;
731
732 EFX_REGDUMP(efx, "writing MDIO %d register %d.%d with 0x%04x\n",
733 prtad, devad, addr, value);
734
735 mutex_lock(&efx->mdio_lock);
736
737 /* Check MDIO not currently being accessed */
738 rc = falcon_gmii_wait(efx);
739 if (rc)
740 goto out;
741
742 /* Write the address/ID register */
743 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
744 efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
745
746 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
747 FRF_AB_MD_DEV_ADR, devad);
748 efx_writeo(efx, &reg, FR_AB_MD_ID);
749
750 /* Write data */
751 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
752 efx_writeo(efx, &reg, FR_AB_MD_TXD);
753
754 EFX_POPULATE_OWORD_2(reg,
755 FRF_AB_MD_WRC, 1,
756 FRF_AB_MD_GC, 0);
757 efx_writeo(efx, &reg, FR_AB_MD_CS);
758
759 /* Wait for data to be written */
760 rc = falcon_gmii_wait(efx);
761 if (rc) {
762 /* Abort the write operation */
763 EFX_POPULATE_OWORD_2(reg,
764 FRF_AB_MD_WRC, 0,
765 FRF_AB_MD_GC, 1);
766 efx_writeo(efx, &reg, FR_AB_MD_CS);
767 udelay(10);
768 }
769
770 out:
771 mutex_unlock(&efx->mdio_lock);
772 return rc;
773 }
774
775 /* Read an MDIO register of a PHY connected to Falcon. */
776 static int falcon_mdio_read(struct net_device *net_dev,
777 int prtad, int devad, u16 addr)
778 {
779 struct efx_nic *efx = netdev_priv(net_dev);
780 efx_oword_t reg;
781 int rc;
782
783 mutex_lock(&efx->mdio_lock);
784
785 /* Check MDIO not currently being accessed */
786 rc = falcon_gmii_wait(efx);
787 if (rc)
788 goto out;
789
790 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
791 efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
792
793 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
794 FRF_AB_MD_DEV_ADR, devad);
795 efx_writeo(efx, &reg, FR_AB_MD_ID);
796
797 /* Request data to be read */
798 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
799 efx_writeo(efx, &reg, FR_AB_MD_CS);
800
801 /* Wait for data to become available */
802 rc = falcon_gmii_wait(efx);
803 if (rc == 0) {
804 efx_reado(efx, &reg, FR_AB_MD_RXD);
805 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
806 EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n",
807 prtad, devad, addr, rc);
808 } else {
809 /* Abort the read operation */
810 EFX_POPULATE_OWORD_2(reg,
811 FRF_AB_MD_RIC, 0,
812 FRF_AB_MD_GC, 1);
813 efx_writeo(efx, &reg, FR_AB_MD_CS);
814
815 EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n",
816 prtad, devad, addr, rc);
817 }
818
819 out:
820 mutex_unlock(&efx->mdio_lock);
821 return rc;
822 }
823
824 static void falcon_clock_mac(struct efx_nic *efx)
825 {
826 unsigned strap_val;
827 efx_oword_t nic_stat;
828
829 /* Configure the NIC generated MAC clock correctly */
830 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
831 strap_val = EFX_IS10G(efx) ? 5 : 3;
832 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
833 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1);
834 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val);
835 efx_writeo(efx, &nic_stat, FR_AB_NIC_STAT);
836 } else {
837 /* Falcon A1 does not support 1G/10G speed switching
838 * and must not be used with a PHY that does. */
839 BUG_ON(EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_PINS) !=
840 strap_val);
841 }
842 }
843
844 static void falcon_switch_mac(struct efx_nic *efx)
845 {
846 struct efx_mac_operations *old_mac_op = efx->mac_op;
847 struct falcon_nic_data *nic_data = efx->nic_data;
848 unsigned int stats_done_offset;
849
850 WARN_ON(!mutex_is_locked(&efx->mac_lock));
851 WARN_ON(nic_data->stats_disable_count == 0);
852
853 efx->mac_op = (EFX_IS10G(efx) ?
854 &falcon_xmac_operations : &falcon_gmac_operations);
855
856 if (EFX_IS10G(efx))
857 stats_done_offset = XgDmaDone_offset;
858 else
859 stats_done_offset = GDmaDone_offset;
860 nic_data->stats_dma_done = efx->stats_buffer.addr + stats_done_offset;
861
862 if (old_mac_op == efx->mac_op)
863 return;
864
865 falcon_clock_mac(efx);
866
867 EFX_LOG(efx, "selected %cMAC\n", EFX_IS10G(efx) ? 'X' : 'G');
868 /* Not all macs support a mac-level link state */
869 efx->xmac_poll_required = false;
870 falcon_reset_macs(efx);
871 }
872
873 /* This call is responsible for hooking in the MAC and PHY operations */
874 static int falcon_probe_port(struct efx_nic *efx)
875 {
876 int rc;
877
878 switch (efx->phy_type) {
879 case PHY_TYPE_SFX7101:
880 efx->phy_op = &falcon_sfx7101_phy_ops;
881 break;
882 case PHY_TYPE_SFT9001A:
883 case PHY_TYPE_SFT9001B:
884 efx->phy_op = &falcon_sft9001_phy_ops;
885 break;
886 case PHY_TYPE_QT2022C2:
887 case PHY_TYPE_QT2025C:
888 efx->phy_op = &falcon_qt202x_phy_ops;
889 break;
890 default:
891 EFX_ERR(efx, "Unknown PHY type %d\n",
892 efx->phy_type);
893 return -ENODEV;
894 }
895
896 /* Fill out MDIO structure and loopback modes */
897 efx->mdio.mdio_read = falcon_mdio_read;
898 efx->mdio.mdio_write = falcon_mdio_write;
899 rc = efx->phy_op->probe(efx);
900 if (rc != 0)
901 return rc;
902
903 /* Initial assumption */
904 efx->link_state.speed = 10000;
905 efx->link_state.fd = true;
906
907 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
908 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
909 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
910 else
911 efx->wanted_fc = EFX_FC_RX;
912
913 /* Allocate buffer for stats */
914 rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
915 FALCON_MAC_STATS_SIZE);
916 if (rc)
917 return rc;
918 EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n",
919 (u64)efx->stats_buffer.dma_addr,
920 efx->stats_buffer.addr,
921 (u64)virt_to_phys(efx->stats_buffer.addr));
922
923 return 0;
924 }
925
926 static void falcon_remove_port(struct efx_nic *efx)
927 {
928 efx_nic_free_buffer(efx, &efx->stats_buffer);
929 }
930
931 /**************************************************************************
932 *
933 * Falcon test code
934 *
935 **************************************************************************/
936
937 static int
938 falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
939 {
940 struct falcon_nvconfig *nvconfig;
941 struct efx_spi_device *spi;
942 void *region;
943 int rc, magic_num, struct_ver;
944 __le16 *word, *limit;
945 u32 csum;
946
947 spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
948 if (!spi)
949 return -EINVAL;
950
951 region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
952 if (!region)
953 return -ENOMEM;
954 nvconfig = region + FALCON_NVCONFIG_OFFSET;
955
956 mutex_lock(&efx->spi_lock);
957 rc = falcon_spi_read(efx, spi, 0, FALCON_NVCONFIG_END, NULL, region);
958 mutex_unlock(&efx->spi_lock);
959 if (rc) {
960 EFX_ERR(efx, "Failed to read %s\n",
961 efx->spi_flash ? "flash" : "EEPROM");
962 rc = -EIO;
963 goto out;
964 }
965
966 magic_num = le16_to_cpu(nvconfig->board_magic_num);
967 struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
968
969 rc = -EINVAL;
970 if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
971 EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num);
972 goto out;
973 }
974 if (struct_ver < 2) {
975 EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver);
976 goto out;
977 } else if (struct_ver < 4) {
978 word = &nvconfig->board_magic_num;
979 limit = (__le16 *) (nvconfig + 1);
980 } else {
981 word = region;
982 limit = region + FALCON_NVCONFIG_END;
983 }
984 for (csum = 0; word < limit; ++word)
985 csum += le16_to_cpu(*word);
986
987 if (~csum & 0xffff) {
988 EFX_ERR(efx, "NVRAM has incorrect checksum\n");
989 goto out;
990 }
991
992 rc = 0;
993 if (nvconfig_out)
994 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
995
996 out:
997 kfree(region);
998 return rc;
999 }
1000
1001 static int falcon_test_nvram(struct efx_nic *efx)
1002 {
1003 return falcon_read_nvram(efx, NULL);
1004 }
1005
1006 static const struct efx_nic_register_test falcon_b0_register_tests[] = {
1007 { FR_AZ_ADR_REGION,
1008 EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) },
1009 { FR_AZ_RX_CFG,
1010 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
1011 { FR_AZ_TX_CFG,
1012 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
1013 { FR_AZ_TX_RESERVED,
1014 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
1015 { FR_AB_MAC_CTRL,
1016 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
1017 { FR_AZ_SRM_TX_DC_CFG,
1018 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
1019 { FR_AZ_RX_DC_CFG,
1020 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
1021 { FR_AZ_RX_DC_PF_WM,
1022 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
1023 { FR_BZ_DP_CTRL,
1024 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
1025 { FR_AB_GM_CFG2,
1026 EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
1027 { FR_AB_GMF_CFG0,
1028 EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
1029 { FR_AB_XM_GLB_CFG,
1030 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
1031 { FR_AB_XM_TX_CFG,
1032 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
1033 { FR_AB_XM_RX_CFG,
1034 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
1035 { FR_AB_XM_RX_PARAM,
1036 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
1037 { FR_AB_XM_FC,
1038 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
1039 { FR_AB_XM_ADR_LO,
1040 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
1041 { FR_AB_XX_SD_CTL,
1042 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
1043 };
1044
1045 static int falcon_b0_test_registers(struct efx_nic *efx)
1046 {
1047 return efx_nic_test_registers(efx, falcon_b0_register_tests,
1048 ARRAY_SIZE(falcon_b0_register_tests));
1049 }
1050
1051 /**************************************************************************
1052 *
1053 * Device reset
1054 *
1055 **************************************************************************
1056 */
1057
1058 /* Resets NIC to known state. This routine must be called in process
1059 * context and is allowed to sleep. */
1060 static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
1061 {
1062 struct falcon_nic_data *nic_data = efx->nic_data;
1063 efx_oword_t glb_ctl_reg_ker;
1064 int rc;
1065
1066 EFX_LOG(efx, "performing %s hardware reset\n", RESET_TYPE(method));
1067
1068 /* Initiate device reset */
1069 if (method == RESET_TYPE_WORLD) {
1070 rc = pci_save_state(efx->pci_dev);
1071 if (rc) {
1072 EFX_ERR(efx, "failed to backup PCI state of primary "
1073 "function prior to hardware reset\n");
1074 goto fail1;
1075 }
1076 if (efx_nic_is_dual_func(efx)) {
1077 rc = pci_save_state(nic_data->pci_dev2);
1078 if (rc) {
1079 EFX_ERR(efx, "failed to backup PCI state of "
1080 "secondary function prior to "
1081 "hardware reset\n");
1082 goto fail2;
1083 }
1084 }
1085
1086 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
1087 FRF_AB_EXT_PHY_RST_DUR,
1088 FFE_AB_EXT_PHY_RST_DUR_10240US,
1089 FRF_AB_SWRST, 1);
1090 } else {
1091 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
1092 /* exclude PHY from "invisible" reset */
1093 FRF_AB_EXT_PHY_RST_CTL,
1094 method == RESET_TYPE_INVISIBLE,
1095 /* exclude EEPROM/flash and PCIe */
1096 FRF_AB_PCIE_CORE_RST_CTL, 1,
1097 FRF_AB_PCIE_NSTKY_RST_CTL, 1,
1098 FRF_AB_PCIE_SD_RST_CTL, 1,
1099 FRF_AB_EE_RST_CTL, 1,
1100 FRF_AB_EXT_PHY_RST_DUR,
1101 FFE_AB_EXT_PHY_RST_DUR_10240US,
1102 FRF_AB_SWRST, 1);
1103 }
1104 efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
1105
1106 EFX_LOG(efx, "waiting for hardware reset\n");
1107 schedule_timeout_uninterruptible(HZ / 20);
1108
1109 /* Restore PCI configuration if needed */
1110 if (method == RESET_TYPE_WORLD) {
1111 if (efx_nic_is_dual_func(efx)) {
1112 rc = pci_restore_state(nic_data->pci_dev2);
1113 if (rc) {
1114 EFX_ERR(efx, "failed to restore PCI config for "
1115 "the secondary function\n");
1116 goto fail3;
1117 }
1118 }
1119 rc = pci_restore_state(efx->pci_dev);
1120 if (rc) {
1121 EFX_ERR(efx, "failed to restore PCI config for the "
1122 "primary function\n");
1123 goto fail4;
1124 }
1125 EFX_LOG(efx, "successfully restored PCI config\n");
1126 }
1127
1128 /* Assert that reset complete */
1129 efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
1130 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
1131 rc = -ETIMEDOUT;
1132 EFX_ERR(efx, "timed out waiting for hardware reset\n");
1133 goto fail5;
1134 }
1135 EFX_LOG(efx, "hardware reset complete\n");
1136
1137 return 0;
1138
1139 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
1140 fail2:
1141 fail3:
1142 pci_restore_state(efx->pci_dev);
1143 fail1:
1144 fail4:
1145 fail5:
1146 return rc;
1147 }
1148
1149 static void falcon_monitor(struct efx_nic *efx)
1150 {
1151 bool link_changed;
1152 int rc;
1153
1154 BUG_ON(!mutex_is_locked(&efx->mac_lock));
1155
1156 rc = falcon_board(efx)->type->monitor(efx);
1157 if (rc) {
1158 EFX_ERR(efx, "Board sensor %s; shutting down PHY\n",
1159 (rc == -ERANGE) ? "reported fault" : "failed");
1160 efx->phy_mode |= PHY_MODE_LOW_POWER;
1161 rc = __efx_reconfigure_port(efx);
1162 WARN_ON(rc);
1163 }
1164
1165 if (LOOPBACK_INTERNAL(efx))
1166 link_changed = falcon_loopback_link_poll(efx);
1167 else
1168 link_changed = efx->phy_op->poll(efx);
1169
1170 if (link_changed) {
1171 falcon_stop_nic_stats(efx);
1172 falcon_deconfigure_mac_wrapper(efx);
1173
1174 falcon_switch_mac(efx);
1175 rc = efx->mac_op->reconfigure(efx);
1176 BUG_ON(rc);
1177
1178 falcon_start_nic_stats(efx);
1179
1180 efx_link_status_changed(efx);
1181 }
1182
1183 if (EFX_IS10G(efx))
1184 falcon_poll_xmac(efx);
1185 }
1186
1187 /* Zeroes out the SRAM contents. This routine must be called in
1188 * process context and is allowed to sleep.
1189 */
1190 static int falcon_reset_sram(struct efx_nic *efx)
1191 {
1192 efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
1193 int count;
1194
1195 /* Set the SRAM wake/sleep GPIO appropriately. */
1196 efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
1197 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
1198 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
1199 efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
1200
1201 /* Initiate SRAM reset */
1202 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
1203 FRF_AZ_SRM_INIT_EN, 1,
1204 FRF_AZ_SRM_NB_SZ, 0);
1205 efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
1206
1207 /* Wait for SRAM reset to complete */
1208 count = 0;
1209 do {
1210 EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count);
1211
1212 /* SRAM reset is slow; expect around 16ms */
1213 schedule_timeout_uninterruptible(HZ / 50);
1214
1215 /* Check for reset complete */
1216 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
1217 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
1218 EFX_LOG(efx, "SRAM reset complete\n");
1219
1220 return 0;
1221 }
1222 } while (++count < 20); /* wait upto 0.4 sec */
1223
1224 EFX_ERR(efx, "timed out waiting for SRAM reset\n");
1225 return -ETIMEDOUT;
1226 }
1227
1228 static int falcon_spi_device_init(struct efx_nic *efx,
1229 struct efx_spi_device **spi_device_ret,
1230 unsigned int device_id, u32 device_type)
1231 {
1232 struct efx_spi_device *spi_device;
1233
1234 if (device_type != 0) {
1235 spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL);
1236 if (!spi_device)
1237 return -ENOMEM;
1238 spi_device->device_id = device_id;
1239 spi_device->size =
1240 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
1241 spi_device->addr_len =
1242 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
1243 spi_device->munge_address = (spi_device->size == 1 << 9 &&
1244 spi_device->addr_len == 1);
1245 spi_device->erase_command =
1246 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
1247 spi_device->erase_size =
1248 1 << SPI_DEV_TYPE_FIELD(device_type,
1249 SPI_DEV_TYPE_ERASE_SIZE);
1250 spi_device->block_size =
1251 1 << SPI_DEV_TYPE_FIELD(device_type,
1252 SPI_DEV_TYPE_BLOCK_SIZE);
1253 } else {
1254 spi_device = NULL;
1255 }
1256
1257 kfree(*spi_device_ret);
1258 *spi_device_ret = spi_device;
1259 return 0;
1260 }
1261
1262 static void falcon_remove_spi_devices(struct efx_nic *efx)
1263 {
1264 kfree(efx->spi_eeprom);
1265 efx->spi_eeprom = NULL;
1266 kfree(efx->spi_flash);
1267 efx->spi_flash = NULL;
1268 }
1269
1270 /* Extract non-volatile configuration */
1271 static int falcon_probe_nvconfig(struct efx_nic *efx)
1272 {
1273 struct falcon_nvconfig *nvconfig;
1274 int board_rev;
1275 int rc;
1276
1277 nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
1278 if (!nvconfig)
1279 return -ENOMEM;
1280
1281 rc = falcon_read_nvram(efx, nvconfig);
1282 if (rc == -EINVAL) {
1283 EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n");
1284 efx->phy_type = PHY_TYPE_NONE;
1285 efx->mdio.prtad = MDIO_PRTAD_NONE;
1286 board_rev = 0;
1287 rc = 0;
1288 } else if (rc) {
1289 goto fail1;
1290 } else {
1291 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
1292 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
1293
1294 efx->phy_type = v2->port0_phy_type;
1295 efx->mdio.prtad = v2->port0_phy_addr;
1296 board_rev = le16_to_cpu(v2->board_revision);
1297
1298 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
1299 rc = falcon_spi_device_init(
1300 efx, &efx->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
1301 le32_to_cpu(v3->spi_device_type
1302 [FFE_AB_SPI_DEVICE_FLASH]));
1303 if (rc)
1304 goto fail2;
1305 rc = falcon_spi_device_init(
1306 efx, &efx->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
1307 le32_to_cpu(v3->spi_device_type
1308 [FFE_AB_SPI_DEVICE_EEPROM]));
1309 if (rc)
1310 goto fail2;
1311 }
1312 }
1313
1314 /* Read the MAC addresses */
1315 memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
1316
1317 EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mdio.prtad);
1318
1319 falcon_probe_board(efx, board_rev);
1320
1321 kfree(nvconfig);
1322 return 0;
1323
1324 fail2:
1325 falcon_remove_spi_devices(efx);
1326 fail1:
1327 kfree(nvconfig);
1328 return rc;
1329 }
1330
1331 /* Probe all SPI devices on the NIC */
1332 static void falcon_probe_spi_devices(struct efx_nic *efx)
1333 {
1334 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
1335 int boot_dev;
1336
1337 efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
1338 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
1339 efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
1340
1341 if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
1342 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
1343 FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
1344 EFX_LOG(efx, "Booted from %s\n",
1345 boot_dev == FFE_AB_SPI_DEVICE_FLASH ? "flash" : "EEPROM");
1346 } else {
1347 /* Disable VPD and set clock dividers to safe
1348 * values for initial programming. */
1349 boot_dev = -1;
1350 EFX_LOG(efx, "Booted from internal ASIC settings;"
1351 " setting SPI config\n");
1352 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
1353 /* 125 MHz / 7 ~= 20 MHz */
1354 FRF_AB_EE_SF_CLOCK_DIV, 7,
1355 /* 125 MHz / 63 ~= 2 MHz */
1356 FRF_AB_EE_EE_CLOCK_DIV, 63);
1357 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
1358 }
1359
1360 if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
1361 falcon_spi_device_init(efx, &efx->spi_flash,
1362 FFE_AB_SPI_DEVICE_FLASH,
1363 default_flash_type);
1364 if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
1365 falcon_spi_device_init(efx, &efx->spi_eeprom,
1366 FFE_AB_SPI_DEVICE_EEPROM,
1367 large_eeprom_type);
1368 }
1369
1370 static int falcon_probe_nic(struct efx_nic *efx)
1371 {
1372 struct falcon_nic_data *nic_data;
1373 struct falcon_board *board;
1374 int rc;
1375
1376 /* Allocate storage for hardware specific data */
1377 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
1378 if (!nic_data)
1379 return -ENOMEM;
1380 efx->nic_data = nic_data;
1381
1382 rc = -ENODEV;
1383
1384 if (efx_nic_fpga_ver(efx) != 0) {
1385 EFX_ERR(efx, "Falcon FPGA not supported\n");
1386 goto fail1;
1387 }
1388
1389 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
1390 efx_oword_t nic_stat;
1391 struct pci_dev *dev;
1392 u8 pci_rev = efx->pci_dev->revision;
1393
1394 if ((pci_rev == 0xff) || (pci_rev == 0)) {
1395 EFX_ERR(efx, "Falcon rev A0 not supported\n");
1396 goto fail1;
1397 }
1398 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
1399 if (EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) == 0) {
1400 EFX_ERR(efx, "Falcon rev A1 1G not supported\n");
1401 goto fail1;
1402 }
1403 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
1404 EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
1405 goto fail1;
1406 }
1407
1408 dev = pci_dev_get(efx->pci_dev);
1409 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
1410 dev))) {
1411 if (dev->bus == efx->pci_dev->bus &&
1412 dev->devfn == efx->pci_dev->devfn + 1) {
1413 nic_data->pci_dev2 = dev;
1414 break;
1415 }
1416 }
1417 if (!nic_data->pci_dev2) {
1418 EFX_ERR(efx, "failed to find secondary function\n");
1419 rc = -ENODEV;
1420 goto fail2;
1421 }
1422 }
1423
1424 /* Now we can reset the NIC */
1425 rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
1426 if (rc) {
1427 EFX_ERR(efx, "failed to reset NIC\n");
1428 goto fail3;
1429 }
1430
1431 /* Allocate memory for INT_KER */
1432 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
1433 if (rc)
1434 goto fail4;
1435 BUG_ON(efx->irq_status.dma_addr & 0x0f);
1436
1437 EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n",
1438 (u64)efx->irq_status.dma_addr,
1439 efx->irq_status.addr, (u64)virt_to_phys(efx->irq_status.addr));
1440
1441 falcon_probe_spi_devices(efx);
1442
1443 /* Read in the non-volatile configuration */
1444 rc = falcon_probe_nvconfig(efx);
1445 if (rc)
1446 goto fail5;
1447
1448 /* Initialise I2C adapter */
1449 board = falcon_board(efx);
1450 board->i2c_adap.owner = THIS_MODULE;
1451 board->i2c_data = falcon_i2c_bit_operations;
1452 board->i2c_data.data = efx;
1453 board->i2c_adap.algo_data = &board->i2c_data;
1454 board->i2c_adap.dev.parent = &efx->pci_dev->dev;
1455 strlcpy(board->i2c_adap.name, "SFC4000 GPIO",
1456 sizeof(board->i2c_adap.name));
1457 rc = i2c_bit_add_bus(&board->i2c_adap);
1458 if (rc)
1459 goto fail5;
1460
1461 rc = falcon_board(efx)->type->init(efx);
1462 if (rc) {
1463 EFX_ERR(efx, "failed to initialise board\n");
1464 goto fail6;
1465 }
1466
1467 nic_data->stats_disable_count = 1;
1468 setup_timer(&nic_data->stats_timer, &falcon_stats_timer_func,
1469 (unsigned long)efx);
1470
1471 return 0;
1472
1473 fail6:
1474 BUG_ON(i2c_del_adapter(&board->i2c_adap));
1475 memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
1476 fail5:
1477 falcon_remove_spi_devices(efx);
1478 efx_nic_free_buffer(efx, &efx->irq_status);
1479 fail4:
1480 fail3:
1481 if (nic_data->pci_dev2) {
1482 pci_dev_put(nic_data->pci_dev2);
1483 nic_data->pci_dev2 = NULL;
1484 }
1485 fail2:
1486 fail1:
1487 kfree(efx->nic_data);
1488 return rc;
1489 }
1490
1491 static void falcon_init_rx_cfg(struct efx_nic *efx)
1492 {
1493 /* Prior to Siena the RX DMA engine will split each frame at
1494 * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to
1495 * be so large that that never happens. */
1496 const unsigned huge_buf_size = (3 * 4096) >> 5;
1497 /* RX control FIFO thresholds (32 entries) */
1498 const unsigned ctrl_xon_thr = 20;
1499 const unsigned ctrl_xoff_thr = 25;
1500 /* RX data FIFO thresholds (256-byte units; size varies) */
1501 int data_xon_thr = efx_nic_rx_xon_thresh >> 8;
1502 int data_xoff_thr = efx_nic_rx_xoff_thresh >> 8;
1503 efx_oword_t reg;
1504
1505 efx_reado(efx, &reg, FR_AZ_RX_CFG);
1506 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
1507 /* Data FIFO size is 5.5K */
1508 if (data_xon_thr < 0)
1509 data_xon_thr = 512 >> 8;
1510 if (data_xoff_thr < 0)
1511 data_xoff_thr = 2048 >> 8;
1512 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
1513 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
1514 huge_buf_size);
1515 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr);
1516 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr);
1517 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
1518 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
1519 } else {
1520 /* Data FIFO size is 80K; register fields moved */
1521 if (data_xon_thr < 0)
1522 data_xon_thr = 27648 >> 8; /* ~3*max MTU */
1523 if (data_xoff_thr < 0)
1524 data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */
1525 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
1526 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
1527 huge_buf_size);
1528 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr);
1529 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr);
1530 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
1531 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
1532 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
1533 }
1534 /* Always enable XOFF signal from RX FIFO. We enable
1535 * or disable transmission of pause frames at the MAC. */
1536 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
1537 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
1538 }
1539
1540 /* This call performs hardware-specific global initialisation, such as
1541 * defining the descriptor cache sizes and number of RSS channels.
1542 * It does not set up any buffers, descriptor rings or event queues.
1543 */
1544 static int falcon_init_nic(struct efx_nic *efx)
1545 {
1546 efx_oword_t temp;
1547 int rc;
1548
1549 /* Use on-chip SRAM */
1550 efx_reado(efx, &temp, FR_AB_NIC_STAT);
1551 EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
1552 efx_writeo(efx, &temp, FR_AB_NIC_STAT);
1553
1554 /* Set the source of the GMAC clock */
1555 if (efx_nic_rev(efx) == EFX_REV_FALCON_B0) {
1556 efx_reado(efx, &temp, FR_AB_GPIO_CTL);
1557 EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true);
1558 efx_writeo(efx, &temp, FR_AB_GPIO_CTL);
1559 }
1560
1561 /* Select the correct MAC */
1562 falcon_clock_mac(efx);
1563
1564 rc = falcon_reset_sram(efx);
1565 if (rc)
1566 return rc;
1567
1568 /* Clear the parity enables on the TX data fifos as
1569 * they produce false parity errors because of timing issues
1570 */
1571 if (EFX_WORKAROUND_5129(efx)) {
1572 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
1573 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
1574 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
1575 }
1576
1577 if (EFX_WORKAROUND_7244(efx)) {
1578 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
1579 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
1580 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
1581 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
1582 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
1583 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
1584 }
1585
1586 /* XXX This is documented only for Falcon A0/A1 */
1587 /* Setup RX. Wait for descriptor is broken and must
1588 * be disabled. RXDP recovery shouldn't be needed, but is.
1589 */
1590 efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
1591 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
1592 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
1593 if (EFX_WORKAROUND_5583(efx))
1594 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
1595 efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
1596
1597 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
1598 * descriptors (which is bad).
1599 */
1600 efx_reado(efx, &temp, FR_AZ_TX_CFG);
1601 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
1602 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
1603
1604 falcon_init_rx_cfg(efx);
1605
1606 /* Set destination of both TX and RX Flush events */
1607 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1608 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
1609 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
1610 }
1611
1612 efx_nic_init_common(efx);
1613
1614 return 0;
1615 }
1616
1617 static void falcon_remove_nic(struct efx_nic *efx)
1618 {
1619 struct falcon_nic_data *nic_data = efx->nic_data;
1620 struct falcon_board *board = falcon_board(efx);
1621 int rc;
1622
1623 board->type->fini(efx);
1624
1625 /* Remove I2C adapter and clear it in preparation for a retry */
1626 rc = i2c_del_adapter(&board->i2c_adap);
1627 BUG_ON(rc);
1628 memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
1629
1630 falcon_remove_spi_devices(efx);
1631 efx_nic_free_buffer(efx, &efx->irq_status);
1632
1633 falcon_reset_hw(efx, RESET_TYPE_ALL);
1634
1635 /* Release the second function after the reset */
1636 if (nic_data->pci_dev2) {
1637 pci_dev_put(nic_data->pci_dev2);
1638 nic_data->pci_dev2 = NULL;
1639 }
1640
1641 /* Tear down the private nic state */
1642 kfree(efx->nic_data);
1643 efx->nic_data = NULL;
1644 }
1645
1646 static void falcon_update_nic_stats(struct efx_nic *efx)
1647 {
1648 struct falcon_nic_data *nic_data = efx->nic_data;
1649 efx_oword_t cnt;
1650
1651 if (nic_data->stats_disable_count)
1652 return;
1653
1654 efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
1655 efx->n_rx_nodesc_drop_cnt +=
1656 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
1657
1658 if (nic_data->stats_pending &&
1659 *nic_data->stats_dma_done == FALCON_STATS_DONE) {
1660 nic_data->stats_pending = false;
1661 rmb(); /* read the done flag before the stats */
1662 efx->mac_op->update_stats(efx);
1663 }
1664 }
1665
1666 void falcon_start_nic_stats(struct efx_nic *efx)
1667 {
1668 struct falcon_nic_data *nic_data = efx->nic_data;
1669
1670 spin_lock_bh(&efx->stats_lock);
1671 if (--nic_data->stats_disable_count == 0)
1672 falcon_stats_request(efx);
1673 spin_unlock_bh(&efx->stats_lock);
1674 }
1675
1676 void falcon_stop_nic_stats(struct efx_nic *efx)
1677 {
1678 struct falcon_nic_data *nic_data = efx->nic_data;
1679 int i;
1680
1681 might_sleep();
1682
1683 spin_lock_bh(&efx->stats_lock);
1684 ++nic_data->stats_disable_count;
1685 spin_unlock_bh(&efx->stats_lock);
1686
1687 del_timer_sync(&nic_data->stats_timer);
1688
1689 /* Wait enough time for the most recent transfer to
1690 * complete. */
1691 for (i = 0; i < 4 && nic_data->stats_pending; i++) {
1692 if (*nic_data->stats_dma_done == FALCON_STATS_DONE)
1693 break;
1694 msleep(1);
1695 }
1696
1697 spin_lock_bh(&efx->stats_lock);
1698 falcon_stats_complete(efx);
1699 spin_unlock_bh(&efx->stats_lock);
1700 }
1701
1702 static void falcon_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
1703 {
1704 falcon_board(efx)->type->set_id_led(efx, mode);
1705 }
1706
1707 /**************************************************************************
1708 *
1709 * Wake on LAN
1710 *
1711 **************************************************************************
1712 */
1713
1714 static void falcon_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1715 {
1716 wol->supported = 0;
1717 wol->wolopts = 0;
1718 memset(&wol->sopass, 0, sizeof(wol->sopass));
1719 }
1720
1721 static int falcon_set_wol(struct efx_nic *efx, u32 type)
1722 {
1723 if (type != 0)
1724 return -EINVAL;
1725 return 0;
1726 }
1727
1728 /**************************************************************************
1729 *
1730 * Revision-dependent attributes used by efx.c
1731 *
1732 **************************************************************************
1733 */
1734
1735 struct efx_nic_type falcon_a1_nic_type = {
1736 .probe = falcon_probe_nic,
1737 .remove = falcon_remove_nic,
1738 .init = falcon_init_nic,
1739 .fini = efx_port_dummy_op_void,
1740 .monitor = falcon_monitor,
1741 .reset = falcon_reset_hw,
1742 .probe_port = falcon_probe_port,
1743 .remove_port = falcon_remove_port,
1744 .prepare_flush = falcon_prepare_flush,
1745 .update_stats = falcon_update_nic_stats,
1746 .start_stats = falcon_start_nic_stats,
1747 .stop_stats = falcon_stop_nic_stats,
1748 .set_id_led = falcon_set_id_led,
1749 .push_irq_moderation = falcon_push_irq_moderation,
1750 .push_multicast_hash = falcon_push_multicast_hash,
1751 .reconfigure_port = falcon_reconfigure_port,
1752 .get_wol = falcon_get_wol,
1753 .set_wol = falcon_set_wol,
1754 .resume_wol = efx_port_dummy_op_void,
1755 .test_nvram = falcon_test_nvram,
1756 .default_mac_ops = &falcon_xmac_operations,
1757
1758 .revision = EFX_REV_FALCON_A1,
1759 .mem_map_size = 0x20000,
1760 .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
1761 .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
1762 .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
1763 .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
1764 .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
1765 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1766 .rx_buffer_padding = 0x24,
1767 .max_interrupt_mode = EFX_INT_MODE_MSI,
1768 .phys_addr_channels = 4,
1769 .tx_dc_base = 0x130000,
1770 .rx_dc_base = 0x100000,
1771 .offload_features = NETIF_F_IP_CSUM,
1772 .reset_world_flags = ETH_RESET_IRQ,
1773 };
1774
1775 struct efx_nic_type falcon_b0_nic_type = {
1776 .probe = falcon_probe_nic,
1777 .remove = falcon_remove_nic,
1778 .init = falcon_init_nic,
1779 .fini = efx_port_dummy_op_void,
1780 .monitor = falcon_monitor,
1781 .reset = falcon_reset_hw,
1782 .probe_port = falcon_probe_port,
1783 .remove_port = falcon_remove_port,
1784 .prepare_flush = falcon_prepare_flush,
1785 .update_stats = falcon_update_nic_stats,
1786 .start_stats = falcon_start_nic_stats,
1787 .stop_stats = falcon_stop_nic_stats,
1788 .set_id_led = falcon_set_id_led,
1789 .push_irq_moderation = falcon_push_irq_moderation,
1790 .push_multicast_hash = falcon_push_multicast_hash,
1791 .reconfigure_port = falcon_reconfigure_port,
1792 .get_wol = falcon_get_wol,
1793 .set_wol = falcon_set_wol,
1794 .resume_wol = efx_port_dummy_op_void,
1795 .test_registers = falcon_b0_test_registers,
1796 .test_nvram = falcon_test_nvram,
1797 .default_mac_ops = &falcon_xmac_operations,
1798
1799 .revision = EFX_REV_FALCON_B0,
1800 /* Map everything up to and including the RSS indirection
1801 * table. Don't map MSI-X table, MSI-X PBA since Linux
1802 * requires that they not be mapped. */
1803 .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL +
1804 FR_BZ_RX_INDIRECTION_TBL_STEP *
1805 FR_BZ_RX_INDIRECTION_TBL_ROWS),
1806 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
1807 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
1808 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
1809 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
1810 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
1811 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1812 .rx_buffer_padding = 0,
1813 .max_interrupt_mode = EFX_INT_MODE_MSIX,
1814 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
1815 * interrupt handler only supports 32
1816 * channels */
1817 .tx_dc_base = 0x130000,
1818 .rx_dc_base = 0x100000,
1819 .offload_features = NETIF_F_IP_CSUM,
1820 .reset_world_flags = ETH_RESET_IRQ,
1821 };
1822
linux-next