| commit | 2c108bfdf0859f16788c15d289b0eed1bfd8363e | |
| author | Avi Kivity <avi@redhat.com> | |
| Mon, 3 Aug 2009 17:57:54 +0000 (3 14:57 -0300) | ||
| committer | Greg Kroah-Hartman <gregkh@suse.de> | |
| Wed, 9 Sep 2009 03:33:31 +0000 (8 20:33 -0700) | ||
| tree | 917679982b675192a9620f0f27af4a2760966c16 | treesnapshot (tar.gz zip) |
| parent | 9661bf29e0bcfb17f64a4145bb283d3ab53c0971 | commitdiff |
KVM: MMU: Use different shadows when EFER.NXE changes
(cherry picked from commit 9645bb56b31a1b70ab9e470387b5264cafc04aa9)
A pte that is shadowed when the guest EFER.NXE=1 is not valid when
EFER.NXE=0; if bit 63 is set, the pte should cause a fault, and since the
shadow EFER always has NX enabled, this won't happen.
Fix by using a different shadow page table for different EFER.NXE bits. This
allows vcpus to run correctly with different values of EFER.NXE, and for
transitions on this bit to be handled correctly without requiring a full
flush.
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
(cherry picked from commit 9645bb56b31a1b70ab9e470387b5264cafc04aa9)
A pte that is shadowed when the guest EFER.NXE=1 is not valid when
EFER.NXE=0; if bit 63 is set, the pte should cause a fault, and since the
shadow EFER always has NX enabled, this won't happen.
Fix by using a different shadow page table for different EFER.NXE bits. This
allows vcpus to run correctly with different values of EFER.NXE, and for
transitions on this bit to be handled correctly without requiring a full
flush.
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| arch/x86/include/asm/kvm_host.h | diffblobblamehistory | |
| arch/x86/kvm/x86.c | diffblobblamehistory |