drivers/usb/musb/musbhsdma.c

   1 /*
   2  * MUSB OTG driver - support for Mentor's DMA controller
   3  *
   4  * Copyright 2005 Mentor Graphics Corporation
   5  * Copyright (C) 2005-2007 by Texas Instruments
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * version 2 as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  19  * 02110-1301 USA
  20  *
  21  * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
  22  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  23  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  24  * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  27  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  28  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  30  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  *
  32  */
  33 #include <linux/device.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/platform_device.h>
  36 #include "musb_core.h"
  37 #include "musbhsdma.h"
  38
  39 static int dma_controller_start(struct dma_controller *c)
  40 {
  41         /* nothing to do */
  42         return 0;
  43 }
  44
  45 static void dma_channel_release(struct dma_channel *channel);
  46
  47 static int dma_controller_stop(struct dma_controller *c)
  48 {
  49         struct musb_dma_controller *controller = container_of(c,
  50                         struct musb_dma_controller, controller);
  51         struct musb *musb = controller->private_data;
  52         struct dma_channel *channel;
  53         u8 bit;
  54
  55         if (controller->used_channels != 0) {
  56                 dev_err(musb->controller,
  57                         "Stopping DMA controller while channel active\n");
  58
  59                 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
  60                         if (controller->used_channels & (1 << bit)) {
  61                                 channel = &controller->channel[bit].channel;
  62                                 dma_channel_release(channel);
  63
  64                                 if (!controller->used_channels)
  65                                         break;
  66                         }
  67                 }
  68         }
  69
  70         return 0;
  71 }
  72
  73 static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
  74                                 struct musb_hw_ep *hw_ep, u8 transmit)
  75 {
  76         struct musb_dma_controller *controller = container_of(c,
  77                         struct musb_dma_controller, controller);
  78         struct musb_dma_channel *musb_channel = NULL;
  79         struct dma_channel *channel = NULL;
  80         u8 bit;
  81
  82         for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
  83                 if (!(controller->used_channels & (1 << bit))) {
  84                         controller->used_channels |= (1 << bit);
  85                         musb_channel = &(controller->channel[bit]);
  86                         musb_channel->controller = controller;
  87                         musb_channel->idx = bit;
  88                         musb_channel->epnum = hw_ep->epnum;
  89                         musb_channel->transmit = transmit;
  90                         channel = &(musb_channel->channel);
  91                         channel->private_data = musb_channel;
  92                         channel->status = MUSB_DMA_STATUS_FREE;
  93                         channel->max_len = 0x10000;
  94                         /* Tx => mode 1; Rx => mode 0 */
  95                         channel->desired_mode = transmit;
  96                         channel->actual_len = 0;
  97                         break;
  98                 }
  99         }
 100
 101         return channel;
 102 }
 103
 104 static void dma_channel_release(struct dma_channel *channel)
 105 {
 106         struct musb_dma_channel *musb_channel = channel->private_data;
 107
 108         channel->actual_len = 0;
 109         musb_channel->start_addr = 0;
 110         musb_channel->len = 0;
 111
 112         musb_channel->controller->used_channels &=
 113                 ~(1 << musb_channel->idx);
 114
 115         channel->status = MUSB_DMA_STATUS_UNKNOWN;
 116 }
 117
 118 static void configure_channel(struct dma_channel *channel,
 119                                 u16 packet_sz, u8 mode,
 120                                 dma_addr_t dma_addr, u32 len)
 121 {
 122         struct musb_dma_channel *musb_channel = channel->private_data;
 123         struct musb_dma_controller *controller = musb_channel->controller;
 124         void __iomem *mbase = controller->base;
 125         u8 bchannel = musb_channel->idx;
 126         u16 csr = 0;
 127
 128         DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
 129                         channel, packet_sz, dma_addr, len, mode);
 130
 131         if (mode) {
 132                 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
 133                 BUG_ON(len < packet_sz);
 134
 135                 if (packet_sz >= 64) {
 136                         csr |= MUSB_HSDMA_BURSTMODE_INCR16
 137                                         << MUSB_HSDMA_BURSTMODE_SHIFT;
 138                 } else if (packet_sz >= 32) {
 139                         csr |= MUSB_HSDMA_BURSTMODE_INCR8
 140                                         << MUSB_HSDMA_BURSTMODE_SHIFT;
 141                 } else if (packet_sz >= 16) {
 142                         csr |= MUSB_HSDMA_BURSTMODE_INCR4
 143                                         << MUSB_HSDMA_BURSTMODE_SHIFT;
 144                 }
 145         }
 146
 147         csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
 148                 | (1 << MUSB_HSDMA_ENABLE_SHIFT)
 149                 | (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
 150                 | (musb_channel->transmit
 151                                 ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
 152                                 : 0);
 153
 154         /* address/count */
 155         musb_write_hsdma_addr(mbase, bchannel, dma_addr);
 156         musb_write_hsdma_count(mbase, bchannel, len);
 157
 158         /* control (this should start things) */
 159         musb_writew(mbase,
 160                 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
 161                 csr);
 162 }
 163
 164 static int dma_channel_program(struct dma_channel *channel,
 165                                 u16 packet_sz, u8 mode,
 166                                 dma_addr_t dma_addr, u32 len)
 167 {
 168         struct musb_dma_channel *musb_channel = channel->private_data;
 169
 170         DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
 171                 musb_channel->epnum,
 172                 musb_channel->transmit ? "Tx" : "Rx",
 173                 packet_sz, dma_addr, len, mode);
 174
 175         BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
 176                 channel->status == MUSB_DMA_STATUS_BUSY);
 177
 178         channel->actual_len = 0;
 179         musb_channel->start_addr = dma_addr;
 180         musb_channel->len = len;
 181         musb_channel->max_packet_sz = packet_sz;
 182         channel->status = MUSB_DMA_STATUS_BUSY;
 183
 184         if ((mode == 1) && (len >= packet_sz))
 185                 configure_channel(channel, packet_sz, 1, dma_addr, len);
 186         else
 187                 configure_channel(channel, packet_sz, 0, dma_addr, len);
 188
 189         return true;
 190 }
 191
 192 static int dma_channel_abort(struct dma_channel *channel)
 193 {
 194         struct musb_dma_channel *musb_channel = channel->private_data;
 195         void __iomem *mbase = musb_channel->controller->base;
 196
 197         u8 bchannel = musb_channel->idx;
 198         u16 csr;
 199
 200         if (channel->status == MUSB_DMA_STATUS_BUSY) {
 201                 if (musb_channel->transmit) {
 202
 203                         csr = musb_readw(mbase,
 204                                 MUSB_EP_OFFSET(musb_channel->epnum,
 205                                                 MUSB_TXCSR));
 206                         csr &= ~(MUSB_TXCSR_AUTOSET |
 207                                  MUSB_TXCSR_DMAENAB |
 208                                  MUSB_TXCSR_DMAMODE);
 209                         musb_writew(mbase,
 210                                 MUSB_EP_OFFSET(musb_channel->epnum, MUSB_TXCSR),
 211                                 csr);
 212                 } else {
 213                         csr = musb_readw(mbase,
 214                                 MUSB_EP_OFFSET(musb_channel->epnum,
 215                                                 MUSB_RXCSR));
 216                         csr &= ~(MUSB_RXCSR_AUTOCLEAR |
 217                                  MUSB_RXCSR_DMAENAB |
 218                                  MUSB_RXCSR_DMAMODE);
 219                         musb_writew(mbase,
 220                                 MUSB_EP_OFFSET(musb_channel->epnum, MUSB_RXCSR),
 221                                 csr);
 222                 }
 223
 224                 musb_writew(mbase,
 225                         MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
 226                         0);
 227                 musb_write_hsdma_addr(mbase, bchannel, 0);
 228                 musb_write_hsdma_count(mbase, bchannel, 0);
 229                 channel->status = MUSB_DMA_STATUS_FREE;
 230         }
 231
 232         return 0;
 233 }
 234
 235 static irqreturn_t dma_controller_irq(int irq, void *private_data)
 236 {
 237         struct musb_dma_controller *controller = private_data;
 238         struct musb *musb = controller->private_data;
 239         struct musb_dma_channel *musb_channel;
 240         struct dma_channel *channel;
 241
 242         void __iomem *mbase = controller->base;
 243
 244         irqreturn_t retval = IRQ_NONE;
 245
 246         unsigned long flags;
 247
 248         u8 bchannel;
 249         u8 int_hsdma;
 250
 251         u32 addr;
 252         u16 csr;
 253
 254         spin_lock_irqsave(&musb->lock, flags);
 255
 256         int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
 257         if (!int_hsdma)
 258                 goto done;
 259
 260         for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
 261                 if (int_hsdma & (1 << bchannel)) {
 262                         musb_channel = (struct musb_dma_channel *)
 263                                         &(controller->channel[bchannel]);
 264                         channel = &musb_channel->channel;
 265
 266                         csr = musb_readw(mbase,
 267                                         MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
 268                                                         MUSB_HSDMA_CONTROL));
 269
 270                         if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
 271                                 musb_channel->channel.status =
 272                                         MUSB_DMA_STATUS_BUS_ABORT;
 273                         } else {
 274                                 u8 devctl;
 275
 276                                 addr = musb_read_hsdma_addr(mbase,
 277                                                 bchannel);
 278                                 channel->actual_len = addr
 279                                         - musb_channel->start_addr;
 280
 281                                 DBG(2, "ch %p, 0x%x -> 0x%x (%d / %d) %s\n",
 282                                         channel, musb_channel->start_addr,
 283                                         addr, channel->actual_len,
 284                                         musb_channel->len,
 285                                         (channel->actual_len
 286                                                 < musb_channel->len) ?
 287                                         "=> reconfig 0" : "=> complete");
 288
 289                                 devctl = musb_readb(mbase, MUSB_DEVCTL);
 290
 291                                 channel->status = MUSB_DMA_STATUS_FREE;
 292
 293                                 /* completed */
 294                                 if ((devctl & MUSB_DEVCTL_HM)
 295                                         && (musb_channel->transmit)
 296                                         && ((channel->desired_mode == 0)
 297                                             || (channel->actual_len &
 298                                             (musb_channel->max_packet_sz - 1)))
 299                                          ) {
 300                                         /* Send out the packet */
 301                                         musb_ep_select(mbase,
 302                                                 musb_channel->epnum);
 303                                         musb_writew(mbase, MUSB_EP_OFFSET(
 304                                                         musb_channel->epnum,
 305                                                         MUSB_TXCSR),
 306                                                 MUSB_TXCSR_TXPKTRDY);
 307                                 } else {
 308                                         musb_dma_completion(
 309                                                 musb,
 310                                                 musb_channel->epnum,
 311                                                 musb_channel->transmit);
 312                                 }
 313                         }
 314                 }
 315         }
 316
 317 #ifdef CONFIG_BLACKFIN
 318         /* Clear DMA interrup flags */
 319         musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma);
 320 #endif
 321
 322         retval = IRQ_HANDLED;
 323 done:
 324         spin_unlock_irqrestore(&musb->lock, flags);
 325         return retval;
 326 }
 327
 328 void dma_controller_destroy(struct dma_controller *c)
 329 {
 330         struct musb_dma_controller *controller = container_of(c,
 331                         struct musb_dma_controller, controller);
 332
 333         if (!controller)
 334                 return;
 335
 336         if (controller->irq)
 337                 free_irq(controller->irq, c);
 338
 339         kfree(controller);
 340 }
 341
 342 struct dma_controller *__init
 343 dma_controller_create(struct musb *musb, void __iomem *base)
 344 {
 345         struct musb_dma_controller *controller;
 346         struct device *dev = musb->controller;
 347         struct platform_device *pdev = to_platform_device(dev);
 348         int irq = platform_get_irq(pdev, 1);
 349
 350         if (irq == 0) {
 351                 dev_err(dev, "No DMA interrupt line!\n");
 352                 return NULL;
 353         }
 354
 355         controller = kzalloc(sizeof(*controller), GFP_KERNEL);
 356         if (!controller)
 357                 return NULL;
 358
 359         controller->channel_count = MUSB_HSDMA_CHANNELS;
 360         controller->private_data = musb;
 361         controller->base = base;
 362
 363         controller->controller.start = dma_controller_start;
 364         controller->controller.stop = dma_controller_stop;
 365         controller->controller.channel_alloc = dma_channel_allocate;
 366         controller->controller.channel_release = dma_channel_release;
 367         controller->controller.channel_program = dma_channel_program;
 368         controller->controller.channel_abort = dma_channel_abort;
 369
 370         if (request_irq(irq, dma_controller_irq, IRQF_DISABLED,
 371                         dev_name(musb->controller), &controller->controller)) {
 372                 dev_err(dev, "request_irq %d failed!\n", irq);
 373                 dma_controller_destroy(&controller->controller);
 374
 375                 return NULL;
 376         }
 377
 378         controller->irq = irq;
 379
 380         return &controller->controller;
 381 }