?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ext4: Fix discard of inode prealloc space with delayed allocation.
[linux-2.6/mini2440.git] / drivers / ata / pata_amd.c
blob115b1cd6dcf55c32afbe5ec2ab348b3f438db34f
1 /*
2 * pata_amd.c - AMD PATA for new ATA layer
3 * (C) 2005-2006 Red Hat Inc
4 *
5 * Based on pata-sil680. Errata information is taken from data sheets
6 * and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are
7 * claimed by sata-nv.c.
8 *
9 * TODO:
10 * Variable system clock when/if it makes sense
11 * Power management on ports
12 *
13 *
14 * Documentation publically available.
15 */
16
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/blkdev.h>
22 #include <linux/delay.h>
23 #include <scsi/scsi_host.h>
24 #include <linux/libata.h>
25
26 #define DRV_NAME "pata_amd"
27 #define DRV_VERSION "0.4.1"
28
29 /**
30 * timing_setup - shared timing computation and load
31 * @ap: ATA port being set up
32 * @adev: drive being configured
33 * @offset: port offset
34 * @speed: target speed
35 * @clock: clock multiplier (number of times 33MHz for this part)
36 *
37 * Perform the actual timing set up for Nvidia or AMD PATA devices.
38 * The actual devices vary so they all call into this helper function
39 * providing the clock multipler and offset (because AMD and Nvidia put
40 * the ports at different locations).
41 */
42
43 static void timing_setup(struct ata_port *ap, struct ata_device *adev, int offset, int speed, int clock)
44 {
45 static const unsigned char amd_cyc2udma[] = {
46 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7
47 };
48
49 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
50 struct ata_device *peer = ata_dev_pair(adev);
51 int dn = ap->port_no * 2 + adev->devno;
52 struct ata_timing at, apeer;
53 int T, UT;
54 const int amd_clock = 33333; /* KHz. */
55 u8 t;
56
57 T = 1000000000 / amd_clock;
58 UT = T;
59 if (clock >= 2)
60 UT = T / 2;
61
62 if (ata_timing_compute(adev, speed, &at, T, UT) < 0) {
63 dev_printk(KERN_ERR, &pdev->dev, "unknown mode %d.\n", speed);
64 return;
65 }
66
67 if (peer) {
68 /* This may be over conservative */
69 if (peer->dma_mode) {
70 ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT);
71 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
72 }
73 ata_timing_compute(peer, peer->pio_mode, &apeer, T, UT);
74 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
75 }
76
77 if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1;
78 if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15;
79
80 /*
81 * Now do the setup work
82 */
83
84 /* Configure the address set up timing */
85 pci_read_config_byte(pdev, offset + 0x0C, &t);
86 t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(at.setup, 1, 4) - 1) << ((3 - dn) << 1));
87 pci_write_config_byte(pdev, offset + 0x0C , t);
88
89 /* Configure the 8bit I/O timing */
90 pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)),
91 ((clamp_val(at.act8b, 1, 16) - 1) << 4) | (clamp_val(at.rec8b, 1, 16) - 1));
92
93 /* Drive timing */
94 pci_write_config_byte(pdev, offset + 0x08 + (3 - dn),
95 ((clamp_val(at.active, 1, 16) - 1) << 4) | (clamp_val(at.recover, 1, 16) - 1));
96
97 switch (clock) {
98 case 1:
99 t = at.udma ? (0xc0 | (clamp_val(at.udma, 2, 5) - 2)) : 0x03;
100 break;
101
102 case 2:
103 t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 2, 10)]) : 0x03;
104 break;
105
106 case 3:
107 t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 10)]) : 0x03;
108 break;
109
110 case 4:
111 t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 15)]) : 0x03;
112 break;
113
114 default:
115 return;
116 }
117
118 /* UDMA timing */
119 if (at.udma)
120 pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t);
121 }
122
123 /**
124 * amd_pre_reset - perform reset handling
125 * @link: ATA link
126 * @deadline: deadline jiffies for the operation
127 *
128 * Reset sequence checking enable bits to see which ports are
129 * active.
130 */
131
132 static int amd_pre_reset(struct ata_link *link, unsigned long deadline)
133 {
134 static const struct pci_bits amd_enable_bits[] = {
135 { 0x40, 1, 0x02, 0x02 },
136 { 0x40, 1, 0x01, 0x01 }
137 };
138
139 struct ata_port *ap = link->ap;
140 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
141
142 if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no]))
143 return -ENOENT;
144
145 return ata_sff_prereset(link, deadline);
146 }
147
148 /**
149 * amd_cable_detect - report cable type
150 * @ap: port
151 *
152 * AMD controller/BIOS setups record the cable type in word 0x42
153 */
154
155 static int amd_cable_detect(struct ata_port *ap)
156 {
157 static const u32 bitmask[2] = {0x03, 0x0C};
158 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
159 u8 ata66;
160
161 pci_read_config_byte(pdev, 0x42, &ata66);
162 if (ata66 & bitmask[ap->port_no])
163 return ATA_CBL_PATA80;
164 return ATA_CBL_PATA40;
165 }
166
167 /**
168 * amd_fifo_setup - set the PIO FIFO for ATA/ATAPI
169 * @ap: ATA interface
170 * @adev: ATA device
171 *
172 * Set the PCI fifo for this device according to the devices present
173 * on the bus at this point in time. We need to turn the post write buffer
174 * off for ATAPI devices as we may need to issue a word sized write to the
175 * device as the final I/O
176 */
177
178 static void amd_fifo_setup(struct ata_port *ap)
179 {
180 struct ata_device *adev;
181 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
182 static const u8 fifobit[2] = { 0xC0, 0x30};
183 u8 fifo = fifobit[ap->port_no];
184 u8 r;
185
186
187 ata_for_each_dev(adev, &ap->link, ENABLED) {
188 if (adev->class == ATA_DEV_ATAPI)
189 fifo = 0;
190 }
191 if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7411) /* FIFO is broken */
192 fifo = 0;
193
194 /* On the later chips the read prefetch bits become no-op bits */
195 pci_read_config_byte(pdev, 0x41, &r);
196 r &= ~fifobit[ap->port_no];
197 r |= fifo;
198 pci_write_config_byte(pdev, 0x41, r);
199 }
200
201 /**
202 * amd33_set_piomode - set initial PIO mode data
203 * @ap: ATA interface
204 * @adev: ATA device
205 *
206 * Program the AMD registers for PIO mode.
207 */
208
209 static void amd33_set_piomode(struct ata_port *ap, struct ata_device *adev)
210 {
211 amd_fifo_setup(ap);
212 timing_setup(ap, adev, 0x40, adev->pio_mode, 1);
213 }
214
215 static void amd66_set_piomode(struct ata_port *ap, struct ata_device *adev)
216 {
217 amd_fifo_setup(ap);
218 timing_setup(ap, adev, 0x40, adev->pio_mode, 2);
219 }
220
221 static void amd100_set_piomode(struct ata_port *ap, struct ata_device *adev)
222 {
223 amd_fifo_setup(ap);
224 timing_setup(ap, adev, 0x40, adev->pio_mode, 3);
225 }
226
227 static void amd133_set_piomode(struct ata_port *ap, struct ata_device *adev)
228 {
229 amd_fifo_setup(ap);
230 timing_setup(ap, adev, 0x40, adev->pio_mode, 4);
231 }
232
233 /**
234 * amd33_set_dmamode - set initial DMA mode data
235 * @ap: ATA interface
236 * @adev: ATA device
237 *
238 * Program the MWDMA/UDMA modes for the AMD and Nvidia
239 * chipset.
240 */
241
242 static void amd33_set_dmamode(struct ata_port *ap, struct ata_device *adev)
243 {
244 timing_setup(ap, adev, 0x40, adev->dma_mode, 1);
245 }
246
247 static void amd66_set_dmamode(struct ata_port *ap, struct ata_device *adev)
248 {
249 timing_setup(ap, adev, 0x40, adev->dma_mode, 2);
250 }
251
252 static void amd100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
253 {
254 timing_setup(ap, adev, 0x40, adev->dma_mode, 3);
255 }
256
257 static void amd133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
258 {
259 timing_setup(ap, adev, 0x40, adev->dma_mode, 4);
260 }
261
262 /* Both host-side and drive-side detection results are worthless on NV
263 * PATAs. Ignore them and just follow what BIOS configured. Both the
264 * current configuration in PCI config reg and ACPI GTM result are
265 * cached during driver attach and are consulted to select transfer
266 * mode.
267 */
268 static unsigned long nv_mode_filter(struct ata_device *dev,
269 unsigned long xfer_mask)
270 {
271 static const unsigned int udma_mask_map[] =
272 { ATA_UDMA2, ATA_UDMA1, ATA_UDMA0, 0,
273 ATA_UDMA3, ATA_UDMA4, ATA_UDMA5, ATA_UDMA6 };
274 struct ata_port *ap = dev->link->ap;
275 char acpi_str[32] = "";
276 u32 saved_udma, udma;
277 const struct ata_acpi_gtm *gtm;
278 unsigned long bios_limit = 0, acpi_limit = 0, limit;
279
280 /* find out what BIOS configured */
281 udma = saved_udma = (unsigned long)ap->host->private_data;
282
283 if (ap->port_no == 0)
284 udma >>= 16;
285 if (dev->devno == 0)
286 udma >>= 8;
287
288 if ((udma & 0xc0) == 0xc0)
289 bios_limit = ata_pack_xfermask(0, 0, udma_mask_map[udma & 0x7]);
290
291 /* consult ACPI GTM too */
292 gtm = ata_acpi_init_gtm(ap);
293 if (gtm) {
294 acpi_limit = ata_acpi_gtm_xfermask(dev, gtm);
295
296 snprintf(acpi_str, sizeof(acpi_str), " (%u:%u:0x%x)",
297 gtm->drive[0].dma, gtm->drive[1].dma, gtm->flags);
298 }
299
300 /* be optimistic, EH can take care of things if something goes wrong */
301 limit = bios_limit | acpi_limit;
302
303 /* If PIO or DMA isn't configured at all, don't limit. Let EH
304 * handle it.
305 */
306 if (!(limit & ATA_MASK_PIO))
307 limit |= ATA_MASK_PIO;
308 if (!(limit & (ATA_MASK_MWDMA | ATA_MASK_UDMA)))
309 limit |= ATA_MASK_MWDMA | ATA_MASK_UDMA;
310
311 ata_port_printk(ap, KERN_DEBUG, "nv_mode_filter: 0x%lx&0x%lx->0x%lx, "
312 "BIOS=0x%lx (0x%x) ACPI=0x%lx%s\n",
313 xfer_mask, limit, xfer_mask & limit, bios_limit,
314 saved_udma, acpi_limit, acpi_str);
315
316 return xfer_mask & limit;
317 }
318
319 /**
320 * nv_probe_init - cable detection
321 * @lin: ATA link
322 *
323 * Perform cable detection. The BIOS stores this in PCI config
324 * space for us.
325 */
326
327 static int nv_pre_reset(struct ata_link *link, unsigned long deadline)
328 {
329 static const struct pci_bits nv_enable_bits[] = {
330 { 0x50, 1, 0x02, 0x02 },
331 { 0x50, 1, 0x01, 0x01 }
332 };
333
334 struct ata_port *ap = link->ap;
335 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
336
337 if (!pci_test_config_bits(pdev, &nv_enable_bits[ap->port_no]))
338 return -ENOENT;
339
340 return ata_sff_prereset(link, deadline);
341 }
342
343 /**
344 * nv100_set_piomode - set initial PIO mode data
345 * @ap: ATA interface
346 * @adev: ATA device
347 *
348 * Program the AMD registers for PIO mode.
349 */
350
351 static void nv100_set_piomode(struct ata_port *ap, struct ata_device *adev)
352 {
353 timing_setup(ap, adev, 0x50, adev->pio_mode, 3);
354 }
355
356 static void nv133_set_piomode(struct ata_port *ap, struct ata_device *adev)
357 {
358 timing_setup(ap, adev, 0x50, adev->pio_mode, 4);
359 }
360
361 /**
362 * nv100_set_dmamode - set initial DMA mode data
363 * @ap: ATA interface
364 * @adev: ATA device
365 *
366 * Program the MWDMA/UDMA modes for the AMD and Nvidia
367 * chipset.
368 */
369
370 static void nv100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
371 {
372 timing_setup(ap, adev, 0x50, adev->dma_mode, 3);
373 }
374
375 static void nv133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
376 {
377 timing_setup(ap, adev, 0x50, adev->dma_mode, 4);
378 }
379
380 static void nv_host_stop(struct ata_host *host)
381 {
382 u32 udma = (unsigned long)host->private_data;
383
384 /* restore PCI config register 0x60 */
385 pci_write_config_dword(to_pci_dev(host->dev), 0x60, udma);
386 }
387
388 static struct scsi_host_template amd_sht = {
389 ATA_BMDMA_SHT(DRV_NAME),
390 };
391
392 static const struct ata_port_operations amd_base_port_ops = {
393 .inherits = &ata_bmdma32_port_ops,
394 .prereset = amd_pre_reset,
395 };
396
397 static struct ata_port_operations amd33_port_ops = {
398 .inherits = &amd_base_port_ops,
399 .cable_detect = ata_cable_40wire,
400 .set_piomode = amd33_set_piomode,
401 .set_dmamode = amd33_set_dmamode,
402 };
403
404 static struct ata_port_operations amd66_port_ops = {
405 .inherits = &amd_base_port_ops,
406 .cable_detect = ata_cable_unknown,
407 .set_piomode = amd66_set_piomode,
408 .set_dmamode = amd66_set_dmamode,
409 };
410
411 static struct ata_port_operations amd100_port_ops = {
412 .inherits = &amd_base_port_ops,
413 .cable_detect = ata_cable_unknown,
414 .set_piomode = amd100_set_piomode,
415 .set_dmamode = amd100_set_dmamode,
416 };
417
418 static struct ata_port_operations amd133_port_ops = {
419 .inherits = &amd_base_port_ops,
420 .cable_detect = amd_cable_detect,
421 .set_piomode = amd133_set_piomode,
422 .set_dmamode = amd133_set_dmamode,
423 };
424
425 static const struct ata_port_operations nv_base_port_ops = {
426 .inherits = &ata_bmdma_port_ops,
427 .cable_detect = ata_cable_ignore,
428 .mode_filter = nv_mode_filter,
429 .prereset = nv_pre_reset,
430 .host_stop = nv_host_stop,
431 };
432
433 static struct ata_port_operations nv100_port_ops = {
434 .inherits = &nv_base_port_ops,
435 .set_piomode = nv100_set_piomode,
436 .set_dmamode = nv100_set_dmamode,
437 };
438
439 static struct ata_port_operations nv133_port_ops = {
440 .inherits = &nv_base_port_ops,
441 .set_piomode = nv133_set_piomode,
442 .set_dmamode = nv133_set_dmamode,
443 };
444
445 static void amd_clear_fifo(struct pci_dev *pdev)
446 {
447 u8 fifo;
448 /* Disable the FIFO, the FIFO logic will re-enable it as
449 appropriate */
450 pci_read_config_byte(pdev, 0x41, &fifo);
451 fifo &= 0x0F;
452 pci_write_config_byte(pdev, 0x41, fifo);
453 }
454
455 static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
456 {
457 static const struct ata_port_info info[10] = {
458 { /* 0: AMD 7401 */
459 .flags = ATA_FLAG_SLAVE_POSS,
460 .pio_mask = 0x1f,
461 .mwdma_mask = 0x07, /* No SWDMA */
462 .udma_mask = 0x07, /* UDMA 33 */
463 .port_ops = &amd33_port_ops
464 },
465 { /* 1: Early AMD7409 - no swdma */
466 .flags = ATA_FLAG_SLAVE_POSS,
467 .pio_mask = 0x1f,
468 .mwdma_mask = 0x07,
469 .udma_mask = ATA_UDMA4, /* UDMA 66 */
470 .port_ops = &amd66_port_ops
471 },
472 { /* 2: AMD 7409, no swdma errata */
473 .flags = ATA_FLAG_SLAVE_POSS,
474 .pio_mask = 0x1f,
475 .mwdma_mask = 0x07,
476 .udma_mask = ATA_UDMA4, /* UDMA 66 */
477 .port_ops = &amd66_port_ops
478 },
479 { /* 3: AMD 7411 */
480 .flags = ATA_FLAG_SLAVE_POSS,
481 .pio_mask = 0x1f,
482 .mwdma_mask = 0x07,
483 .udma_mask = ATA_UDMA5, /* UDMA 100 */
484 .port_ops = &amd100_port_ops
485 },
486 { /* 4: AMD 7441 */
487 .flags = ATA_FLAG_SLAVE_POSS,
488 .pio_mask = 0x1f,
489 .mwdma_mask = 0x07,
490 .udma_mask = ATA_UDMA5, /* UDMA 100 */
491 .port_ops = &amd100_port_ops
492 },
493 { /* 5: AMD 8111*/
494 .flags = ATA_FLAG_SLAVE_POSS,
495 .pio_mask = 0x1f,
496 .mwdma_mask = 0x07,
497 .udma_mask = ATA_UDMA6, /* UDMA 133, no swdma */
498 .port_ops = &amd133_port_ops
499 },
500 { /* 6: AMD 8111 UDMA 100 (Serenade) */
501 .flags = ATA_FLAG_SLAVE_POSS,
502 .pio_mask = 0x1f,
503 .mwdma_mask = 0x07,
504 .udma_mask = ATA_UDMA5, /* UDMA 100, no swdma */
505 .port_ops = &amd133_port_ops
506 },
507 { /* 7: Nvidia Nforce */
508 .flags = ATA_FLAG_SLAVE_POSS,
509 .pio_mask = 0x1f,
510 .mwdma_mask = 0x07,
511 .udma_mask = ATA_UDMA5, /* UDMA 100 */
512 .port_ops = &nv100_port_ops
513 },
514 { /* 8: Nvidia Nforce2 and later */
515 .flags = ATA_FLAG_SLAVE_POSS,
516 .pio_mask = 0x1f,
517 .mwdma_mask = 0x07,
518 .udma_mask = ATA_UDMA6, /* UDMA 133, no swdma */
519 .port_ops = &nv133_port_ops
520 },
521 { /* 9: AMD CS5536 (Geode companion) */
522 .flags = ATA_FLAG_SLAVE_POSS,
523 .pio_mask = 0x1f,
524 .mwdma_mask = 0x07,
525 .udma_mask = ATA_UDMA5, /* UDMA 100 */
526 .port_ops = &amd100_port_ops
527 }
528 };
529 const struct ata_port_info *ppi[] = { NULL, NULL };
530 static int printed_version;
531 int type = id->driver_data;
532 void *hpriv = NULL;
533 u8 fifo;
534 int rc;
535
536 if (!printed_version++)
537 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
538
539 rc = pcim_enable_device(pdev);
540 if (rc)
541 return rc;
542
543 pci_read_config_byte(pdev, 0x41, &fifo);
544
545 /* Check for AMD7409 without swdma errata and if found adjust type */
546 if (type == 1 && pdev->revision > 0x7)
547 type = 2;
548
549 /* Serenade ? */
550 if (type == 5 && pdev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
551 pdev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
552 type = 6; /* UDMA 100 only */
553
554 /*
555 * Okay, type is determined now. Apply type-specific workarounds.
556 */
557 ppi[0] = &info[type];
558
559 if (type < 3)
560 ata_pci_bmdma_clear_simplex(pdev);
561 if (pdev->vendor == PCI_VENDOR_ID_AMD)
562 amd_clear_fifo(pdev);
563 /* Cable detection on Nvidia chips doesn't work too well,
564 * cache BIOS programmed UDMA mode.
565 */
566 if (type == 7 || type == 8) {
567 u32 udma;
568
569 pci_read_config_dword(pdev, 0x60, &udma);
570 hpriv = (void *)(unsigned long)udma;
571 }
572
573 /* And fire it up */
574 return ata_pci_sff_init_one(pdev, ppi, &amd_sht, hpriv);
575 }
576
577 #ifdef CONFIG_PM
578 static int amd_reinit_one(struct pci_dev *pdev)
579 {
580 struct ata_host *host = dev_get_drvdata(&pdev->dev);
581 int rc;
582
583 rc = ata_pci_device_do_resume(pdev);
584 if (rc)
585 return rc;
586
587 if (pdev->vendor == PCI_VENDOR_ID_AMD) {
588 amd_clear_fifo(pdev);
589 if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7409 ||
590 pdev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
591 ata_pci_bmdma_clear_simplex(pdev);
592 }
593 ata_host_resume(host);
594 return 0;
595 }
596 #endif
597
598 static const struct pci_device_id amd[] = {
599 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 },
600 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 },
601 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 3 },
602 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 4 },
603 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 5 },
604 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 7 },
605 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 8 },
606 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 8 },
607 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 8 },
608 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 8 },
609 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 8 },
610 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 8 },
611 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 8 },
612 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 8 },
613 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 8 },
614 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 8 },
615 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 8 },
616 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 8 },
617 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 8 },
618 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 9 },
619
620 { },
621 };
622
623 static struct pci_driver amd_pci_driver = {
624 .name = DRV_NAME,
625 .id_table = amd,
626 .probe = amd_init_one,
627 .remove = ata_pci_remove_one,
628 #ifdef CONFIG_PM
629 .suspend = ata_pci_device_suspend,
630 .resume = amd_reinit_one,
631 #endif
632 };
633
634 static int __init amd_init(void)
635 {
636 return pci_register_driver(&amd_pci_driver);
637 }
638
639 static void __exit amd_exit(void)
640 {
641 pci_unregister_driver(&amd_pci_driver);
642 }
643
644 MODULE_AUTHOR("Alan Cox");
645 MODULE_DESCRIPTION("low-level driver for AMD and Nvidia PATA IDE");
646 MODULE_LICENSE("GPL");
647 MODULE_DEVICE_TABLE(pci, amd);
648 MODULE_VERSION(DRV_VERSION);
649
650 module_init(amd_init);
651 module_exit(amd_exit);
Support for the Chinese Samsung S3C2440 based development boards