arch/x86/kernel/irqinit_32.c

   1 #include <linux/errno.h>
   2 #include <linux/signal.h>
   3 #include <linux/sched.h>
   4 #include <linux/ioport.h>
   5 #include <linux/interrupt.h>
   6 #include <linux/slab.h>
   7 #include <linux/random.h>
   8 #include <linux/init.h>
   9 #include <linux/kernel_stat.h>
  10 #include <linux/sysdev.h>
  11 #include <linux/bitops.h>
  12 #include <linux/io.h>
  13 #include <linux/delay.h>
  14
  15 #include <asm/atomic.h>
  16 #include <asm/system.h>
  17 #include <asm/timer.h>
  18 #include <asm/pgtable.h>
  19 #include <asm/desc.h>
  20 #include <asm/apic.h>
  21 #include <asm/setup.h>
  22 #include <asm/i8259.h>
  23 #include <asm/traps.h>
  24
  25
  26 /*
  27  * Note that on a 486, we don't want to do a SIGFPE on an irq13
  28  * as the irq is unreliable, and exception 16 works correctly
  29  * (ie as explained in the intel literature). On a 386, you
  30  * can't use exception 16 due to bad IBM design, so we have to
  31  * rely on the less exact irq13.
  32  *
  33  * Careful.. Not only is IRQ13 unreliable, but it is also
  34  * leads to races. IBM designers who came up with it should
  35  * be shot.
  36  */
  37
  38 static irqreturn_t math_error_irq(int cpl, void *dev_id)
  39 {
  40         outb(0, 0xF0);
  41         if (ignore_fpu_irq || !boot_cpu_data.hard_math)
  42                 return IRQ_NONE;
  43         math_error((void __user *)get_irq_regs()->ip);
  44         return IRQ_HANDLED;
  45 }
  46
  47 /*
  48  * New motherboards sometimes make IRQ 13 be a PCI interrupt,
  49  * so allow interrupt sharing.
  50  */
  51 static struct irqaction fpu_irq = {
  52         .handler = math_error_irq,
  53         .mask = CPU_MASK_NONE,
  54         .name = "fpu",
  55 };
  56
  57 void __init init_ISA_irqs(void)
  58 {
  59         int i;
  60
  61 #ifdef CONFIG_X86_LOCAL_APIC
  62         init_bsp_APIC();
  63 #endif
  64         init_8259A(0);
  65
  66         /*
  67          * 16 old-style INTA-cycle interrupts:
  68          */
  69         for (i = 0; i < NR_IRQS_LEGACY; i++) {
  70                 struct irq_desc *desc = irq_to_desc(i);
  71
  72                 desc->status = IRQ_DISABLED;
  73                 desc->action = NULL;
  74                 desc->depth = 1;
  75
  76                 set_irq_chip_and_handler_name(i, &i8259A_chip,
  77                                               handle_level_irq, "XT");
  78         }
  79 }
  80
  81 /*
  82  * IRQ2 is cascade interrupt to second interrupt controller
  83  */
  84 static struct irqaction irq2 = {
  85         .handler = no_action,
  86         .mask = CPU_MASK_NONE,
  87         .name = "cascade",
  88 };
  89
  90 DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
  91         [0 ... IRQ0_VECTOR - 1] = -1,
  92         [IRQ0_VECTOR] = 0,
  93         [IRQ1_VECTOR] = 1,
  94         [IRQ2_VECTOR] = 2,
  95         [IRQ3_VECTOR] = 3,
  96         [IRQ4_VECTOR] = 4,
  97         [IRQ5_VECTOR] = 5,
  98         [IRQ6_VECTOR] = 6,
  99         [IRQ7_VECTOR] = 7,
 100         [IRQ8_VECTOR] = 8,
 101         [IRQ9_VECTOR] = 9,
 102         [IRQ10_VECTOR] = 10,
 103         [IRQ11_VECTOR] = 11,
 104         [IRQ12_VECTOR] = 12,
 105         [IRQ13_VECTOR] = 13,
 106         [IRQ14_VECTOR] = 14,
 107         [IRQ15_VECTOR] = 15,
 108         [IRQ15_VECTOR + 1 ... NR_VECTORS - 1] = -1
 109 };
 110
 111 int vector_used_by_percpu_irq(unsigned int vector)
 112 {
 113         int cpu;
 114
 115         for_each_online_cpu(cpu) {
 116                 if (per_cpu(vector_irq, cpu)[vector] != -1)
 117                         return 1;
 118         }
 119
 120         return 0;
 121 }
 122
 123 /* Overridden in paravirt.c */
 124 void init_IRQ(void) __attribute__((weak, alias("native_init_IRQ")));
 125
 126 void __init native_init_IRQ(void)
 127 {
 128         int i;
 129
 130         /* Execute any quirks before the call gates are initialised: */
 131         x86_quirk_pre_intr_init();
 132
 133         /*
 134          * Cover the whole vector space, no vector can escape
 135          * us. (some of these will be overridden and become
 136          * 'special' SMP interrupts)
 137          */
 138         for (i =  FIRST_EXTERNAL_VECTOR; i < NR_VECTORS; i++) {
 139                 /* SYSCALL_VECTOR was reserved in trap_init. */
 140                 if (i != SYSCALL_VECTOR)
 141                         set_intr_gate(i, interrupt[i-FIRST_EXTERNAL_VECTOR]);
 142         }
 143
 144
 145 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_SMP)
 146         /*
 147          * The reschedule interrupt is a CPU-to-CPU reschedule-helper
 148          * IPI, driven by wakeup.
 149          */
 150         alloc_intr_gate(RESCHEDULE_VECTOR, reschedule_interrupt);
 151
 152         /* IPIs for invalidation */
 153         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+0, invalidate_interrupt0);
 154         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+1, invalidate_interrupt1);
 155         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+2, invalidate_interrupt2);
 156         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+3, invalidate_interrupt3);
 157         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+4, invalidate_interrupt4);
 158         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+5, invalidate_interrupt5);
 159         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+6, invalidate_interrupt6);
 160         alloc_intr_gate(INVALIDATE_TLB_VECTOR_START+7, invalidate_interrupt7);
 161
 162         /* IPI for generic function call */
 163         alloc_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt);
 164
 165         /* IPI for single call function */
 166         alloc_intr_gate(CALL_FUNCTION_SINGLE_VECTOR,
 167                                  call_function_single_interrupt);
 168
 169         /* Low priority IPI to cleanup after moving an irq */
 170         set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt);
 171         set_bit(IRQ_MOVE_CLEANUP_VECTOR, used_vectors);
 172 #endif
 173
 174 #ifdef CONFIG_X86_LOCAL_APIC
 175         /* self generated IPI for local APIC timer */
 176         alloc_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
 177
 178         /* generic IPI for platform specific use */
 179         alloc_intr_gate(GENERIC_INTERRUPT_VECTOR, generic_interrupt);
 180
 181         /* IPI vectors for APIC spurious and error interrupts */
 182         alloc_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
 183         alloc_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
 184 #endif
 185
 186 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_MCE_P4THERMAL)
 187         /* thermal monitor LVT interrupt */
 188         alloc_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
 189 #endif
 190
 191         if (!acpi_ioapic)
 192                 setup_irq(2, &irq2);
 193
 194         /*
 195          * Call quirks after call gates are initialised (usually add in
 196          * the architecture specific gates):
 197          */
 198         x86_quirk_intr_init();
 199
 200         /*
 201          * External FPU? Set up irq13 if so, for
 202          * original braindamaged IBM FERR coupling.
 203          */
 204         if (boot_cpu_data.hard_math && !cpu_has_fpu)
 205                 setup_irq(FPU_IRQ, &fpu_irq);
 206
 207         irq_ctx_init(smp_processor_id());
 208 }