2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/scatterlist.h>
24 #include <linux/iommu-helper.h>
25 #include <asm/proto.h>
27 #include <asm/amd_iommu_types.h>
28 #include <asm/amd_iommu.h>
30 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
32 #define to_pages(addr, size) \
33 (round_up(((addr) & ~PAGE_MASK) + (size), PAGE_SIZE) >> PAGE_SHIFT)
35 static DEFINE_RWLOCK(amd_iommu_devtable_lock
);
41 static int dma_ops_unity_map(struct dma_ops_domain
*dma_dom
,
42 struct unity_map_entry
*e
);
44 static int iommu_has_npcache(struct amd_iommu
*iommu
)
46 return iommu
->cap
& IOMMU_CAP_NPCACHE
;
49 static int __iommu_queue_command(struct amd_iommu
*iommu
, struct command
*cmd
)
54 tail
= readl(iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
55 target
= (iommu
->cmd_buf
+ tail
);
56 memcpy_toio(target
, cmd
, sizeof(*cmd
));
57 tail
= (tail
+ sizeof(*cmd
)) % iommu
->cmd_buf_size
;
58 head
= readl(iommu
->mmio_base
+ MMIO_CMD_HEAD_OFFSET
);
61 writel(tail
, iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
66 static int iommu_queue_command(struct amd_iommu
*iommu
, struct command
*cmd
)
71 spin_lock_irqsave(&iommu
->lock
, flags
);
72 ret
= __iommu_queue_command(iommu
, cmd
);
73 spin_unlock_irqrestore(&iommu
->lock
, flags
);
78 static int iommu_completion_wait(struct amd_iommu
*iommu
)
82 volatile u64 ready
= 0;
83 unsigned long ready_phys
= virt_to_phys(&ready
);
85 memset(&cmd
, 0, sizeof(cmd
));
86 cmd
.data
[0] = LOW_U32(ready_phys
) | CMD_COMPL_WAIT_STORE_MASK
;
87 cmd
.data
[1] = HIGH_U32(ready_phys
);
88 cmd
.data
[2] = 1; /* value written to 'ready' */
89 CMD_SET_TYPE(&cmd
, CMD_COMPL_WAIT
);
93 ret
= iommu_queue_command(iommu
, &cmd
);
104 static int iommu_queue_inv_dev_entry(struct amd_iommu
*iommu
, u16 devid
)
108 BUG_ON(iommu
== NULL
);
110 memset(&cmd
, 0, sizeof(cmd
));
111 CMD_SET_TYPE(&cmd
, CMD_INV_DEV_ENTRY
);
114 iommu
->need_sync
= 1;
116 return iommu_queue_command(iommu
, &cmd
);
119 static int iommu_queue_inv_iommu_pages(struct amd_iommu
*iommu
,
120 u64 address
, u16 domid
, int pde
, int s
)
124 memset(&cmd
, 0, sizeof(cmd
));
125 address
&= PAGE_MASK
;
126 CMD_SET_TYPE(&cmd
, CMD_INV_IOMMU_PAGES
);
127 cmd
.data
[1] |= domid
;
128 cmd
.data
[2] = LOW_U32(address
);
129 cmd
.data
[3] = HIGH_U32(address
);
131 cmd
.data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
133 cmd
.data
[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK
;
135 iommu
->need_sync
= 1;
137 return iommu_queue_command(iommu
, &cmd
);
140 static int iommu_flush_pages(struct amd_iommu
*iommu
, u16 domid
,
141 u64 address
, size_t size
)
144 unsigned pages
= to_pages(address
, size
);
146 address
&= PAGE_MASK
;
150 * If we have to flush more than one page, flush all
151 * TLB entries for this domain
153 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
157 iommu_queue_inv_iommu_pages(iommu
, address
, domid
, 0, s
);
162 static int iommu_map(struct protection_domain
*dom
,
163 unsigned long bus_addr
,
164 unsigned long phys_addr
,
167 u64 __pte
, *pte
, *page
;
169 bus_addr
= PAGE_ALIGN(bus_addr
);
170 phys_addr
= PAGE_ALIGN(bus_addr
);
172 /* only support 512GB address spaces for now */
173 if (bus_addr
> IOMMU_MAP_SIZE_L3
|| !(prot
& IOMMU_PROT_MASK
))
176 pte
= &dom
->pt_root
[IOMMU_PTE_L2_INDEX(bus_addr
)];
178 if (!IOMMU_PTE_PRESENT(*pte
)) {
179 page
= (u64
*)get_zeroed_page(GFP_KERNEL
);
182 *pte
= IOMMU_L2_PDE(virt_to_phys(page
));
185 pte
= IOMMU_PTE_PAGE(*pte
);
186 pte
= &pte
[IOMMU_PTE_L1_INDEX(bus_addr
)];
188 if (!IOMMU_PTE_PRESENT(*pte
)) {
189 page
= (u64
*)get_zeroed_page(GFP_KERNEL
);
192 *pte
= IOMMU_L1_PDE(virt_to_phys(page
));
195 pte
= IOMMU_PTE_PAGE(*pte
);
196 pte
= &pte
[IOMMU_PTE_L0_INDEX(bus_addr
)];
198 if (IOMMU_PTE_PRESENT(*pte
))
201 __pte
= phys_addr
| IOMMU_PTE_P
;
202 if (prot
& IOMMU_PROT_IR
)
203 __pte
|= IOMMU_PTE_IR
;
204 if (prot
& IOMMU_PROT_IW
)
205 __pte
|= IOMMU_PTE_IW
;
212 static int iommu_for_unity_map(struct amd_iommu
*iommu
,
213 struct unity_map_entry
*entry
)
217 for (i
= entry
->devid_start
; i
<= entry
->devid_end
; ++i
) {
218 bdf
= amd_iommu_alias_table
[i
];
219 if (amd_iommu_rlookup_table
[bdf
] == iommu
)
226 static int iommu_init_unity_mappings(struct amd_iommu
*iommu
)
228 struct unity_map_entry
*entry
;
231 list_for_each_entry(entry
, &amd_iommu_unity_map
, list
) {
232 if (!iommu_for_unity_map(iommu
, entry
))
234 ret
= dma_ops_unity_map(iommu
->default_dom
, entry
);
242 static int dma_ops_unity_map(struct dma_ops_domain
*dma_dom
,
243 struct unity_map_entry
*e
)
248 for (addr
= e
->address_start
; addr
< e
->address_end
;
250 ret
= iommu_map(&dma_dom
->domain
, addr
, addr
, e
->prot
);
254 * if unity mapping is in aperture range mark the page
255 * as allocated in the aperture
257 if (addr
< dma_dom
->aperture_size
)
258 __set_bit(addr
>> PAGE_SHIFT
, dma_dom
->bitmap
);
264 static int init_unity_mappings_for_device(struct dma_ops_domain
*dma_dom
,
267 struct unity_map_entry
*e
;
270 list_for_each_entry(e
, &amd_iommu_unity_map
, list
) {
271 if (!(devid
>= e
->devid_start
&& devid
<= e
->devid_end
))
273 ret
= dma_ops_unity_map(dma_dom
, e
);
281 static unsigned long dma_mask_to_pages(unsigned long mask
)
283 return (mask
>> PAGE_SHIFT
) +
284 (PAGE_ALIGN(mask
& ~PAGE_MASK
) >> PAGE_SHIFT
);
287 static unsigned long dma_ops_alloc_addresses(struct device
*dev
,
288 struct dma_ops_domain
*dom
,
291 unsigned long limit
= dma_mask_to_pages(*dev
->dma_mask
);
292 unsigned long address
;
293 unsigned long size
= dom
->aperture_size
>> PAGE_SHIFT
;
294 unsigned long boundary_size
;
296 boundary_size
= ALIGN(dma_get_seg_boundary(dev
) + 1,
297 PAGE_SIZE
) >> PAGE_SHIFT
;
298 limit
= limit
< size
? limit
: size
;
300 if (dom
->next_bit
>= limit
)
303 address
= iommu_area_alloc(dom
->bitmap
, limit
, dom
->next_bit
, pages
,
304 0 , boundary_size
, 0);
306 address
= iommu_area_alloc(dom
->bitmap
, limit
, 0, pages
,
307 0, boundary_size
, 0);
309 if (likely(address
!= -1)) {
310 dom
->next_bit
= address
+ pages
;
311 address
<<= PAGE_SHIFT
;
313 address
= bad_dma_address
;
315 WARN_ON((address
+ (PAGE_SIZE
*pages
)) > dom
->aperture_size
);
320 static void dma_ops_free_addresses(struct dma_ops_domain
*dom
,
321 unsigned long address
,
324 address
>>= PAGE_SHIFT
;
325 iommu_area_free(dom
->bitmap
, address
, pages
);
328 static u16
domain_id_alloc(void)
333 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
334 id
= find_first_zero_bit(amd_iommu_pd_alloc_bitmap
, MAX_DOMAIN_ID
);
336 if (id
> 0 && id
< MAX_DOMAIN_ID
)
337 __set_bit(id
, amd_iommu_pd_alloc_bitmap
);
340 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
345 static void dma_ops_reserve_addresses(struct dma_ops_domain
*dom
,
346 unsigned long start_page
,
349 unsigned int last_page
= dom
->aperture_size
>> PAGE_SHIFT
;
351 if (start_page
+ pages
> last_page
)
352 pages
= last_page
- start_page
;
354 set_bit_string(dom
->bitmap
, start_page
, pages
);
357 static void dma_ops_free_pagetable(struct dma_ops_domain
*dma_dom
)
362 p1
= dma_dom
->domain
.pt_root
;
367 for (i
= 0; i
< 512; ++i
) {
368 if (!IOMMU_PTE_PRESENT(p1
[i
]))
371 p2
= IOMMU_PTE_PAGE(p1
[i
]);
372 for (j
= 0; j
< 512; ++i
) {
373 if (!IOMMU_PTE_PRESENT(p2
[j
]))
375 p3
= IOMMU_PTE_PAGE(p2
[j
]);
376 free_page((unsigned long)p3
);
379 free_page((unsigned long)p2
);
382 free_page((unsigned long)p1
);
385 static void dma_ops_domain_free(struct dma_ops_domain
*dom
)
390 dma_ops_free_pagetable(dom
);
392 kfree(dom
->pte_pages
);
399 static struct dma_ops_domain
*dma_ops_domain_alloc(struct amd_iommu
*iommu
,
402 struct dma_ops_domain
*dma_dom
;
403 unsigned i
, num_pte_pages
;
408 * Currently the DMA aperture must be between 32 MB and 1GB in size
410 if ((order
< 25) || (order
> 30))
413 dma_dom
= kzalloc(sizeof(struct dma_ops_domain
), GFP_KERNEL
);
417 spin_lock_init(&dma_dom
->domain
.lock
);
419 dma_dom
->domain
.id
= domain_id_alloc();
420 if (dma_dom
->domain
.id
== 0)
422 dma_dom
->domain
.mode
= PAGE_MODE_3_LEVEL
;
423 dma_dom
->domain
.pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
424 dma_dom
->domain
.priv
= dma_dom
;
425 if (!dma_dom
->domain
.pt_root
)
427 dma_dom
->aperture_size
= (1ULL << order
);
428 dma_dom
->bitmap
= kzalloc(dma_dom
->aperture_size
/ (PAGE_SIZE
* 8),
430 if (!dma_dom
->bitmap
)
433 * mark the first page as allocated so we never return 0 as
434 * a valid dma-address. So we can use 0 as error value
436 dma_dom
->bitmap
[0] = 1;
437 dma_dom
->next_bit
= 0;
439 if (iommu
->exclusion_start
&&
440 iommu
->exclusion_start
< dma_dom
->aperture_size
) {
441 unsigned long startpage
= iommu
->exclusion_start
>> PAGE_SHIFT
;
442 int pages
= to_pages(iommu
->exclusion_start
,
443 iommu
->exclusion_length
);
444 dma_ops_reserve_addresses(dma_dom
, startpage
, pages
);
447 num_pte_pages
= dma_dom
->aperture_size
/ (PAGE_SIZE
* 512);
448 dma_dom
->pte_pages
= kzalloc(num_pte_pages
* sizeof(void *),
450 if (!dma_dom
->pte_pages
)
453 l2_pde
= (u64
*)get_zeroed_page(GFP_KERNEL
);
457 dma_dom
->domain
.pt_root
[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde
));
459 for (i
= 0; i
< num_pte_pages
; ++i
) {
460 dma_dom
->pte_pages
[i
] = (u64
*)get_zeroed_page(GFP_KERNEL
);
461 if (!dma_dom
->pte_pages
[i
])
463 address
= virt_to_phys(dma_dom
->pte_pages
[i
]);
464 l2_pde
[i
] = IOMMU_L1_PDE(address
);
470 dma_ops_domain_free(dma_dom
);
475 static struct protection_domain
*domain_for_device(u16 devid
)
477 struct protection_domain
*dom
;
480 read_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
481 dom
= amd_iommu_pd_table
[devid
];
482 read_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
487 static void set_device_domain(struct amd_iommu
*iommu
,
488 struct protection_domain
*domain
,
493 u64 pte_root
= virt_to_phys(domain
->pt_root
);
495 pte_root
|= (domain
->mode
& 0x07) << 9;
496 pte_root
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
| IOMMU_PTE_P
| 2;
498 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
499 amd_iommu_dev_table
[devid
].data
[0] = pte_root
;
500 amd_iommu_dev_table
[devid
].data
[1] = pte_root
>> 32;
501 amd_iommu_dev_table
[devid
].data
[2] = domain
->id
;
503 amd_iommu_pd_table
[devid
] = domain
;
504 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
506 iommu_queue_inv_dev_entry(iommu
, devid
);
508 iommu
->need_sync
= 1;
511 static int get_device_resources(struct device
*dev
,
512 struct amd_iommu
**iommu
,
513 struct protection_domain
**domain
,
516 struct dma_ops_domain
*dma_dom
;
517 struct pci_dev
*pcidev
;
520 BUG_ON(!dev
|| dev
->bus
!= &pci_bus_type
|| !dev
->dma_mask
);
522 pcidev
= to_pci_dev(dev
);
523 _bdf
= (pcidev
->bus
->number
<< 8) | pcidev
->devfn
;
525 if (_bdf
>= amd_iommu_last_bdf
) {
532 *bdf
= amd_iommu_alias_table
[_bdf
];
534 *iommu
= amd_iommu_rlookup_table
[*bdf
];
537 dma_dom
= (*iommu
)->default_dom
;
538 *domain
= domain_for_device(*bdf
);
539 if (*domain
== NULL
) {
540 *domain
= &dma_dom
->domain
;
541 set_device_domain(*iommu
, *domain
, *bdf
);
542 printk(KERN_INFO
"AMD IOMMU: Using protection domain %d for "
543 "device ", (*domain
)->id
);
544 print_devid(_bdf
, 1);
550 static dma_addr_t
dma_ops_domain_map(struct amd_iommu
*iommu
,
551 struct dma_ops_domain
*dom
,
552 unsigned long address
,
558 WARN_ON(address
> dom
->aperture_size
);
562 pte
= dom
->pte_pages
[IOMMU_PTE_L1_INDEX(address
)];
563 pte
+= IOMMU_PTE_L0_INDEX(address
);
565 __pte
= paddr
| IOMMU_PTE_P
| IOMMU_PTE_FC
;
567 if (direction
== DMA_TO_DEVICE
)
568 __pte
|= IOMMU_PTE_IR
;
569 else if (direction
== DMA_FROM_DEVICE
)
570 __pte
|= IOMMU_PTE_IW
;
571 else if (direction
== DMA_BIDIRECTIONAL
)
572 __pte
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
;
578 return (dma_addr_t
)address
;
581 static void dma_ops_domain_unmap(struct amd_iommu
*iommu
,
582 struct dma_ops_domain
*dom
,
583 unsigned long address
)
587 if (address
>= dom
->aperture_size
)
590 WARN_ON(address
& 0xfffULL
|| address
> dom
->aperture_size
);
592 pte
= dom
->pte_pages
[IOMMU_PTE_L1_INDEX(address
)];
593 pte
+= IOMMU_PTE_L0_INDEX(address
);
600 static dma_addr_t
__map_single(struct device
*dev
,
601 struct amd_iommu
*iommu
,
602 struct dma_ops_domain
*dma_dom
,
607 dma_addr_t offset
= paddr
& ~PAGE_MASK
;
608 dma_addr_t address
, start
;
612 pages
= to_pages(paddr
, size
);
615 address
= dma_ops_alloc_addresses(dev
, dma_dom
, pages
);
616 if (unlikely(address
== bad_dma_address
))
620 for (i
= 0; i
< pages
; ++i
) {
621 dma_ops_domain_map(iommu
, dma_dom
, start
, paddr
, dir
);
631 static void __unmap_single(struct amd_iommu
*iommu
,
632 struct dma_ops_domain
*dma_dom
,
640 if ((dma_addr
== 0) || (dma_addr
+ size
> dma_dom
->aperture_size
))
643 pages
= to_pages(dma_addr
, size
);
644 dma_addr
&= PAGE_MASK
;
647 for (i
= 0; i
< pages
; ++i
) {
648 dma_ops_domain_unmap(iommu
, dma_dom
, start
);
652 dma_ops_free_addresses(dma_dom
, dma_addr
, pages
);
655 static dma_addr_t
map_single(struct device
*dev
, phys_addr_t paddr
,
656 size_t size
, int dir
)
659 struct amd_iommu
*iommu
;
660 struct protection_domain
*domain
;
664 get_device_resources(dev
, &iommu
, &domain
, &devid
);
666 if (iommu
== NULL
|| domain
== NULL
)
667 return (dma_addr_t
)paddr
;
669 spin_lock_irqsave(&domain
->lock
, flags
);
670 addr
= __map_single(dev
, iommu
, domain
->priv
, paddr
, size
, dir
);
671 if (addr
== bad_dma_address
)
674 if (iommu_has_npcache(iommu
))
675 iommu_flush_pages(iommu
, domain
->id
, addr
, size
);
677 if (iommu
->need_sync
)
678 iommu_completion_wait(iommu
);
681 spin_unlock_irqrestore(&domain
->lock
, flags
);
686 static void unmap_single(struct device
*dev
, dma_addr_t dma_addr
,
687 size_t size
, int dir
)
690 struct amd_iommu
*iommu
;
691 struct protection_domain
*domain
;
694 if (!get_device_resources(dev
, &iommu
, &domain
, &devid
))
697 spin_lock_irqsave(&domain
->lock
, flags
);
699 __unmap_single(iommu
, domain
->priv
, dma_addr
, size
, dir
);
701 iommu_flush_pages(iommu
, domain
->id
, dma_addr
, size
);
703 if (iommu
->need_sync
)
704 iommu_completion_wait(iommu
);
706 spin_unlock_irqrestore(&domain
->lock
, flags
);
709 static int map_sg_no_iommu(struct device
*dev
, struct scatterlist
*sglist
,
712 struct scatterlist
*s
;
715 for_each_sg(sglist
, s
, nelems
, i
) {
716 s
->dma_address
= (dma_addr_t
)sg_phys(s
);
717 s
->dma_length
= s
->length
;
723 static int map_sg(struct device
*dev
, struct scatterlist
*sglist
,
727 struct amd_iommu
*iommu
;
728 struct protection_domain
*domain
;
731 struct scatterlist
*s
;
733 int mapped_elems
= 0;
735 get_device_resources(dev
, &iommu
, &domain
, &devid
);
737 if (!iommu
|| !domain
)
738 return map_sg_no_iommu(dev
, sglist
, nelems
, dir
);
740 spin_lock_irqsave(&domain
->lock
, flags
);
742 for_each_sg(sglist
, s
, nelems
, i
) {
745 s
->dma_address
= __map_single(dev
, iommu
, domain
->priv
,
746 paddr
, s
->length
, dir
);
748 if (s
->dma_address
) {
749 s
->dma_length
= s
->length
;
753 if (iommu_has_npcache(iommu
))
754 iommu_flush_pages(iommu
, domain
->id
, s
->dma_address
,
758 if (iommu
->need_sync
)
759 iommu_completion_wait(iommu
);
762 spin_unlock_irqrestore(&domain
->lock
, flags
);
766 for_each_sg(sglist
, s
, mapped_elems
, i
) {
768 __unmap_single(iommu
, domain
->priv
, s
->dma_address
,
770 s
->dma_address
= s
->dma_length
= 0;
778 static void unmap_sg(struct device
*dev
, struct scatterlist
*sglist
,
782 struct amd_iommu
*iommu
;
783 struct protection_domain
*domain
;
784 struct scatterlist
*s
;
788 if (!get_device_resources(dev
, &iommu
, &domain
, &devid
))
791 spin_lock_irqsave(&domain
->lock
, flags
);
793 for_each_sg(sglist
, s
, nelems
, i
) {
794 __unmap_single(iommu
, domain
->priv
, s
->dma_address
,
796 iommu_flush_pages(iommu
, domain
->id
, s
->dma_address
,
798 s
->dma_address
= s
->dma_length
= 0;
801 if (iommu
->need_sync
)
802 iommu_completion_wait(iommu
);
804 spin_unlock_irqrestore(&domain
->lock
, flags
);
807 static void *alloc_coherent(struct device
*dev
, size_t size
,
808 dma_addr_t
*dma_addr
, gfp_t flag
)
812 struct amd_iommu
*iommu
;
813 struct protection_domain
*domain
;
817 virt_addr
= (void *)__get_free_pages(flag
, get_order(size
));
821 memset(virt_addr
, 0, size
);
822 paddr
= virt_to_phys(virt_addr
);
824 get_device_resources(dev
, &iommu
, &domain
, &devid
);
826 if (!iommu
|| !domain
) {
827 *dma_addr
= (dma_addr_t
)paddr
;
831 spin_lock_irqsave(&domain
->lock
, flags
);
833 *dma_addr
= __map_single(dev
, iommu
, domain
->priv
, paddr
,
834 size
, DMA_BIDIRECTIONAL
);
836 if (*dma_addr
== bad_dma_address
) {
837 free_pages((unsigned long)virt_addr
, get_order(size
));
842 if (iommu_has_npcache(iommu
))
843 iommu_flush_pages(iommu
, domain
->id
, *dma_addr
, size
);
845 if (iommu
->need_sync
)
846 iommu_completion_wait(iommu
);
849 spin_unlock_irqrestore(&domain
->lock
, flags
);
854 static void free_coherent(struct device
*dev
, size_t size
,
855 void *virt_addr
, dma_addr_t dma_addr
)
858 struct amd_iommu
*iommu
;
859 struct protection_domain
*domain
;
862 get_device_resources(dev
, &iommu
, &domain
, &devid
);
864 if (!iommu
|| !domain
)
867 spin_lock_irqsave(&domain
->lock
, flags
);
869 __unmap_single(iommu
, domain
->priv
, dma_addr
, size
, DMA_BIDIRECTIONAL
);
870 iommu_flush_pages(iommu
, domain
->id
, dma_addr
, size
);
872 if (iommu
->need_sync
)
873 iommu_completion_wait(iommu
);
875 spin_unlock_irqrestore(&domain
->lock
, flags
);
878 free_pages((unsigned long)virt_addr
, get_order(size
));
882 * If the driver core informs the DMA layer if a driver grabs a device
883 * we don't need to preallocate the protection domains anymore.
884 * For now we have to.
886 void prealloc_protection_domains(void)
888 struct pci_dev
*dev
= NULL
;
889 struct dma_ops_domain
*dma_dom
;
890 struct amd_iommu
*iommu
;
891 int order
= amd_iommu_aperture_order
;
894 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
895 devid
= (dev
->bus
->number
<< 8) | dev
->devfn
;
896 if (devid
>= amd_iommu_last_bdf
)
898 devid
= amd_iommu_alias_table
[devid
];
899 if (domain_for_device(devid
))
901 iommu
= amd_iommu_rlookup_table
[devid
];
904 dma_dom
= dma_ops_domain_alloc(iommu
, order
);
907 init_unity_mappings_for_device(dma_dom
, devid
);
908 set_device_domain(iommu
, &dma_dom
->domain
, devid
);
909 printk(KERN_INFO
"AMD IOMMU: Allocated domain %d for device ",
911 print_devid(devid
, 1);
915 static struct dma_mapping_ops amd_iommu_dma_ops
= {
916 .alloc_coherent
= alloc_coherent
,
917 .free_coherent
= free_coherent
,
918 .map_single
= map_single
,
919 .unmap_single
= unmap_single
,
921 .unmap_sg
= unmap_sg
,
924 int __init
amd_iommu_init_dma_ops(void)
926 struct amd_iommu
*iommu
;
927 int order
= amd_iommu_aperture_order
;
930 list_for_each_entry(iommu
, &amd_iommu_list
, list
) {
931 iommu
->default_dom
= dma_ops_domain_alloc(iommu
, order
);
932 if (iommu
->default_dom
== NULL
)
934 ret
= iommu_init_unity_mappings(iommu
);
939 if (amd_iommu_isolate
)
940 prealloc_protection_domains();
945 #ifdef CONFIG_GART_IOMMU
946 gart_iommu_aperture_disabled
= 1;
947 gart_iommu_aperture
= 0;
950 dma_ops
= &amd_iommu_dma_ops
;
956 list_for_each_entry(iommu
, &amd_iommu_list
, list
) {
957 if (iommu
->default_dom
)
958 dma_ops_domain_free(iommu
->default_dom
);