2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/etherdevice.h>
21 #include <linux/device.h>
22 #include <net/mac80211.h>
23 #include <linux/leds.h>
24 #include <linux/rfkill.h>
31 /* Macro to expand scalars to 64-bit objects */
33 #define ito64(x) (sizeof(x) == 8) ? \
34 (((unsigned long long int)(x)) & (0xff)) : \
36 (((unsigned long long int)(x)) & 0xffff) : \
37 ((sizeof(x) == 32) ? \
38 (((unsigned long long int)(x)) & 0xffffffff) : \
39 (unsigned long long int)(x))
41 /* increment with wrap-around */
42 #define INCR(_l, _sz) do { \
44 (_l) &= ((_sz) - 1); \
47 /* decrement with wrap-around */
48 #define DECR(_l, _sz) do { \
50 (_l) &= ((_sz) - 1); \
53 #define A_MAX(a, b) ((a) > (b) ? (a) : (b))
55 #define ASSERT(exp) do { \
56 if (unlikely(!(exp))) { \
61 #define TSF_TO_TU(_h,_l) \
62 ((((u32)(_h)) << 22) | (((u32)(_l)) >> 10))
64 #define ATH_TXQ_SETUP(sc, i) ((sc)->tx.txqsetup & (1<<i))
66 static const u8 ath_bcast_mac
[ETH_ALEN
] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
69 ATH_DBG_RESET
= 0x00000001,
70 ATH_DBG_REG_IO
= 0x00000002,
71 ATH_DBG_QUEUE
= 0x00000004,
72 ATH_DBG_EEPROM
= 0x00000008,
73 ATH_DBG_CALIBRATE
= 0x00000010,
74 ATH_DBG_CHANNEL
= 0x00000020,
75 ATH_DBG_INTERRUPT
= 0x00000040,
76 ATH_DBG_REGULATORY
= 0x00000080,
77 ATH_DBG_ANI
= 0x00000100,
78 ATH_DBG_POWER_MGMT
= 0x00000200,
79 ATH_DBG_XMIT
= 0x00000400,
80 ATH_DBG_BEACON
= 0x00001000,
81 ATH_DBG_CONFIG
= 0x00002000,
82 ATH_DBG_KEYCACHE
= 0x00004000,
83 ATH_DBG_FATAL
= 0x00008000,
84 ATH_DBG_ANY
= 0xffffffff
87 #define DBG_DEFAULT (ATH_DBG_FATAL)
89 #ifdef CONFIG_ATH9K_DEBUG
92 * struct ath_interrupt_stats - Contains statistics about interrupts
93 * @total: Total no. of interrupts generated so far
94 * @rxok: RX with no errors
95 * @rxeol: RX with no more RXDESC available
96 * @rxorn: RX FIFO overrun
97 * @txok: TX completed at the requested rate
98 * @txurn: TX FIFO underrun
99 * @mib: MIB regs reaching its threshold
100 * @rxphyerr: RX with phy errors
101 * @rx_keycache_miss: RX with key cache misses
102 * @swba: Software Beacon Alert
103 * @bmiss: Beacon Miss
104 * @bnr: Beacon Not Ready
105 * @cst: Carrier Sense TImeout
106 * @gtt: Global TX Timeout
107 * @tim: RX beacon TIM occurrence
108 * @cabend: RX End of CAB traffic
109 * @dtimsync: DTIM sync lossage
110 * @dtim: RX Beacon with DTIM
112 struct ath_interrupt_stats
{
122 u32 rx_keycache_miss
;
134 struct ath_legacy_rc_stats
{
138 struct ath_11n_rc_stats
{
145 struct ath_interrupt_stats istats
;
146 struct ath_legacy_rc_stats legacy_rcstats
[12]; /* max(11a,11b,11g) */
147 struct ath_11n_rc_stats n_rcstats
[16]; /* 0..15 MCS rates */
152 struct dentry
*debugfs_root
;
153 struct dentry
*debugfs_phy
;
154 struct dentry
*debugfs_dma
;
155 struct dentry
*debugfs_interrupt
;
156 struct dentry
*debugfs_rcstat
;
157 struct ath_stats stats
;
160 void DPRINTF(struct ath_softc
*sc
, int dbg_mask
, const char *fmt
, ...);
161 int ath9k_init_debug(struct ath_softc
*sc
);
162 void ath9k_exit_debug(struct ath_softc
*sc
);
163 void ath_debug_stat_interrupt(struct ath_softc
*sc
, enum ath9k_int status
);
164 void ath_debug_stat_rc(struct ath_softc
*sc
, struct sk_buff
*skb
);
165 void ath_debug_stat_retries(struct ath_softc
*sc
, int rix
,
166 int xretries
, int retries
);
170 static inline void DPRINTF(struct ath_softc
*sc
, int dbg_mask
,
171 const char *fmt
, ...)
175 static inline int ath9k_init_debug(struct ath_softc
*sc
)
180 static inline void ath9k_exit_debug(struct ath_softc
*sc
)
184 static inline void ath_debug_stat_interrupt(struct ath_softc
*sc
,
185 enum ath9k_int status
)
189 static inline void ath_debug_stat_rc(struct ath_softc
*sc
,
194 static inline void ath_debug_stat_retries(struct ath_softc
*sc
, int rix
,
195 int xretries
, int retries
)
199 #endif /* CONFIG_ATH9K_DEBUG */
208 /*************************/
209 /* Descriptor Management */
210 /*************************/
212 #define ATH_TXBUF_RESET(_bf) do { \
213 (_bf)->bf_status = 0; \
214 (_bf)->bf_lastbf = NULL; \
215 (_bf)->bf_next = NULL; \
216 memset(&((_bf)->bf_state), 0, \
217 sizeof(struct ath_buf_state)); \
221 * enum buffer_type - Buffer type flags
223 * @BUF_HT: Send this buffer using HT capabilities
224 * @BUF_AMPDU: This buffer is an ampdu, as part of an aggregate (during TX)
225 * @BUF_AGGR: Indicates whether the buffer can be aggregated
226 * (used in aggregation scheduling)
227 * @BUF_RETRY: Indicates whether the buffer is retried
228 * @BUF_XRETRY: To denote excessive retries of the buffer
238 struct ath_buf_state
{
239 int bfs_nframes
; /* # frames in aggregate */
240 u16 bfs_al
; /* length of aggregate */
241 u16 bfs_frmlen
; /* length of frame */
242 int bfs_seqno
; /* sequence number */
243 int bfs_tidno
; /* tid of this frame */
244 int bfs_retries
; /* current retries */
245 u32 bf_type
; /* BUF_* (enum buffer_type) */
247 enum ath9k_key_type bfs_keytype
;
250 #define bf_nframes bf_state.bfs_nframes
251 #define bf_al bf_state.bfs_al
252 #define bf_frmlen bf_state.bfs_frmlen
253 #define bf_retries bf_state.bfs_retries
254 #define bf_seqno bf_state.bfs_seqno
255 #define bf_tidno bf_state.bfs_tidno
256 #define bf_keyix bf_state.bfs_keyix
257 #define bf_keytype bf_state.bfs_keytype
258 #define bf_isht(bf) (bf->bf_state.bf_type & BUF_HT)
259 #define bf_isampdu(bf) (bf->bf_state.bf_type & BUF_AMPDU)
260 #define bf_isaggr(bf) (bf->bf_state.bf_type & BUF_AGGR)
261 #define bf_isretried(bf) (bf->bf_state.bf_type & BUF_RETRY)
262 #define bf_isxretried(bf) (bf->bf_state.bf_type & BUF_XRETRY)
265 * Abstraction of a contiguous buffer to transmit/receive. There is only
266 * a single hw descriptor encapsulated here.
269 struct list_head list
;
270 struct ath_buf
*bf_lastbf
; /* last buf of this unit (a frame or
272 struct ath_buf
*bf_next
; /* next subframe in the aggregate */
273 void *bf_mpdu
; /* enclosing frame structure */
274 struct ath_desc
*bf_desc
; /* virtual addr of desc */
275 dma_addr_t bf_daddr
; /* physical addr of desc */
276 dma_addr_t bf_buf_addr
; /* physical addr of data buffer */
278 u16 bf_flags
; /* tx descriptor flags */
279 struct ath_buf_state bf_state
; /* buffer state */
280 dma_addr_t bf_dmacontext
;
283 #define ATH_RXBUF_RESET(_bf) ((_bf)->bf_status = 0)
284 #define ATH_BUFSTATUS_STALE 0x00000002
286 /* DMA state for tx/rx descriptors */
290 struct ath_desc
*dd_desc
; /* descriptors */
291 dma_addr_t dd_desc_paddr
; /* physical addr of dd_desc */
292 u32 dd_desc_len
; /* size of dd_desc */
293 struct ath_buf
*dd_bufptr
; /* associated buffers */
294 dma_addr_t dd_dmacontext
;
297 int ath_descdma_setup(struct ath_softc
*sc
, struct ath_descdma
*dd
,
298 struct list_head
*head
, const char *name
,
299 int nbuf
, int ndesc
);
300 void ath_descdma_cleanup(struct ath_softc
*sc
, struct ath_descdma
*dd
,
301 struct list_head
*head
);
307 #define ATH_MAX_ANTENNA 3
308 #define ATH_RXBUF 512
309 #define WME_NUM_TID 16
310 #define ATH_TXBUF 512
311 #define ATH_TXMAXTRY 13
312 #define ATH_11N_TXMAXTRY 10
313 #define ATH_MGT_TXMAXTRY 4
314 #define WME_BA_BMP_SIZE 64
315 #define WME_MAX_BA WME_BA_BMP_SIZE
316 #define ATH_TID_MAX_BUFS (2 * WME_MAX_BA)
318 #define TID_TO_WME_AC(_tid) \
319 ((((_tid) == 0) || ((_tid) == 3)) ? WME_AC_BE : \
320 (((_tid) == 1) || ((_tid) == 2)) ? WME_AC_BK : \
321 (((_tid) == 4) || ((_tid) == 5)) ? WME_AC_VI : \
330 #define ADDBA_EXCHANGE_ATTEMPTS 10
331 #define ATH_AGGR_DELIM_SZ 4
332 #define ATH_AGGR_MINPLEN 256 /* in bytes, minimum packet length */
333 /* number of delimiters for encryption padding */
334 #define ATH_AGGR_ENCRYPTDELIM 10
335 /* minimum h/w qdepth to be sustained to maximize aggregation */
336 #define ATH_AGGR_MIN_QDEPTH 2
337 #define ATH_AMPDU_SUBFRAME_DEFAULT 32
338 #define IEEE80211_SEQ_SEQ_SHIFT 4
339 #define IEEE80211_SEQ_MAX 4096
340 #define IEEE80211_MIN_AMPDU_BUF 0x8
341 #define IEEE80211_HTCAP_MAXRXAMPDU_FACTOR 13
343 /* return whether a bit at index _n in bitmap _bm is set
344 * _sz is the size of the bitmap */
345 #define ATH_BA_ISSET(_bm, _n) (((_n) < (WME_BA_BMP_SIZE)) && \
346 ((_bm)[(_n) >> 5] & (1 << ((_n) & 31))))
348 /* return block-ack bitmap index given sequence and starting sequence */
349 #define ATH_BA_INDEX(_st, _seq) (((_seq) - (_st)) & (IEEE80211_SEQ_MAX - 1))
351 /* returns delimiter padding required given the packet length */
352 #define ATH_AGGR_GET_NDELIM(_len) \
353 (((((_len) + ATH_AGGR_DELIM_SZ) < ATH_AGGR_MINPLEN) ? \
354 (ATH_AGGR_MINPLEN - (_len) - ATH_AGGR_DELIM_SZ) : 0) >> 2)
356 #define BAW_WITHIN(_start, _bawsz, _seqno) \
357 ((((_seqno) - (_start)) & 4095) < (_bawsz))
359 #define ATH_DS_BA_SEQ(_ds) ((_ds)->ds_us.tx.ts_seqnum)
360 #define ATH_DS_BA_BITMAP(_ds) (&(_ds)->ds_us.tx.ba_low)
361 #define ATH_DS_TX_BA(_ds) ((_ds)->ds_us.tx.ts_flags & ATH9K_TX_BA)
362 #define ATH_AN_2_TID(_an, _tidno) (&(_an)->tid[(_tidno)])
364 enum ATH_AGGR_STATUS
{
371 u32 axq_qnum
; /* hardware q number */
372 u32
*axq_link
; /* link ptr in last TX desc */
373 struct list_head axq_q
; /* transmit queue */
375 u32 axq_depth
; /* queue depth */
376 u8 axq_aggr_depth
; /* aggregates queued */
377 u32 axq_totalqueued
; /* total ever queued */
378 bool stopped
; /* Is mac80211 queue stopped ? */
379 struct ath_buf
*axq_linkbuf
; /* virtual addr of last buffer*/
381 /* first desc of the last descriptor that contains CTS */
382 struct ath_desc
*axq_lastdsWithCTS
;
384 /* final desc of the gating desc that determines whether
385 lastdsWithCTS has been DMA'ed or not */
386 struct ath_desc
*axq_gatingds
;
388 struct list_head axq_acq
;
391 #define AGGR_CLEANUP BIT(1)
392 #define AGGR_ADDBA_COMPLETE BIT(2)
393 #define AGGR_ADDBA_PROGRESS BIT(3)
395 /* per TID aggregate tx state for a destination */
397 struct list_head list
; /* round-robin tid entry */
398 struct list_head buf_q
; /* pending buffers */
400 struct ath_atx_ac
*ac
;
401 struct ath_buf
*tx_buf
[ATH_TID_MAX_BUFS
]; /* active tx frames */
406 int baw_head
; /* first un-acked tx buffer */
407 int baw_tail
; /* next unused tx buffer slot */
411 int addba_exchangeattempts
;
414 /* per access-category aggregate tx state for a destination */
416 int sched
; /* dest-ac is scheduled */
417 int qnum
; /* H/W queue number associated
419 struct list_head list
; /* round-robin txq entry */
420 struct list_head tid_q
; /* queue of TIDs with buffers */
423 /* per-frame tx control block */
424 struct ath_tx_control
{
429 /* per frame tx status block */
430 struct ath_xmit_status
{
431 int retries
; /* number of retries to successufully
432 transmit this frame */
433 int flags
; /* status of transmit */
434 #define ATH_TX_ERROR 0x01
435 #define ATH_TX_XRETRY 0x02
436 #define ATH_TX_BAR 0x04
439 /* All RSSI values are noise floor adjusted */
442 int rssictl
[ATH_MAX_ANTENNA
];
443 int rssiextn
[ATH_MAX_ANTENNA
];
448 u32 airtime
; /* time on air per final tx rate */
451 struct aggr_rifs_param
{
452 int param_max_frames
;
456 struct ath_rc_series
*param_rcs
;
460 struct ath_softc
*an_sc
;
461 struct ath_atx_tid tid
[WME_NUM_TID
];
462 struct ath_atx_ac ac
[WME_NUM_AC
];
470 int hwq_map
[ATH9K_WME_AC_VO
+1];
471 spinlock_t txbuflock
;
472 struct list_head txbuf
;
473 struct ath_txq txq
[ATH9K_NUM_TX_QUEUES
];
474 struct ath_descdma txdma
;
482 unsigned int rxfilter
;
483 spinlock_t rxflushlock
;
484 spinlock_t rxbuflock
;
485 struct list_head rxbuf
;
486 struct ath_descdma rxdma
;
489 int ath_startrecv(struct ath_softc
*sc
);
490 bool ath_stoprecv(struct ath_softc
*sc
);
491 void ath_flushrecv(struct ath_softc
*sc
);
492 u32
ath_calcrxfilter(struct ath_softc
*sc
);
493 int ath_rx_init(struct ath_softc
*sc
, int nbufs
);
494 void ath_rx_cleanup(struct ath_softc
*sc
);
495 int ath_rx_tasklet(struct ath_softc
*sc
, int flush
);
496 struct ath_txq
*ath_txq_setup(struct ath_softc
*sc
, int qtype
, int subtype
);
497 void ath_tx_cleanupq(struct ath_softc
*sc
, struct ath_txq
*txq
);
498 int ath_tx_setup(struct ath_softc
*sc
, int haltype
);
499 void ath_drain_all_txq(struct ath_softc
*sc
, bool retry_tx
);
500 void ath_draintxq(struct ath_softc
*sc
,
501 struct ath_txq
*txq
, bool retry_tx
);
502 void ath_tx_node_init(struct ath_softc
*sc
, struct ath_node
*an
);
503 void ath_tx_node_cleanup(struct ath_softc
*sc
, struct ath_node
*an
);
504 void ath_txq_schedule(struct ath_softc
*sc
, struct ath_txq
*txq
);
505 int ath_tx_init(struct ath_softc
*sc
, int nbufs
);
506 int ath_tx_cleanup(struct ath_softc
*sc
);
507 struct ath_txq
*ath_test_get_txq(struct ath_softc
*sc
, struct sk_buff
*skb
);
508 int ath_txq_update(struct ath_softc
*sc
, int qnum
,
509 struct ath9k_tx_queue_info
*q
);
510 int ath_tx_start(struct ath_softc
*sc
, struct sk_buff
*skb
,
511 struct ath_tx_control
*txctl
);
512 void ath_tx_tasklet(struct ath_softc
*sc
);
513 void ath_tx_cabq(struct ath_softc
*sc
, struct sk_buff
*skb
);
514 bool ath_tx_aggr_check(struct ath_softc
*sc
, struct ath_node
*an
, u8 tidno
);
515 int ath_tx_aggr_start(struct ath_softc
*sc
, struct ieee80211_sta
*sta
,
517 int ath_tx_aggr_stop(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
);
518 void ath_tx_aggr_resume(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
);
525 * Define the scheme that we select MAC address for multiple
526 * BSS on the same radio. The very first VAP will just use the MAC
527 * address from the EEPROM. For the next 3 VAPs, we set the
528 * U/L bit (bit 1) in MAC address, and use the next two bits as the
532 #define ATH_SET_VAP_BSSID_MASK(bssid_mask) \
533 ((bssid_mask)[0] &= ~(((ATH_BCBUF-1)<<2)|0x02))
537 enum nl80211_iftype av_opmode
;
538 struct ath_buf
*av_bcbuf
;
539 struct ath_tx_control av_btxctl
;
542 /*******************/
543 /* Beacon Handling */
544 /*******************/
547 * Regardless of the number of beacons we stagger, (i.e. regardless of the
548 * number of BSSIDs) if a given beacon does not go out even after waiting this
549 * number of beacon intervals, the game's up.
551 #define BSTUCK_THRESH (9 * ATH_BCBUF)
553 #define ATH_DEFAULT_BINTVAL 100 /* TU */
554 #define ATH_DEFAULT_BMISS_LIMIT 10
555 #define IEEE80211_MS_TO_TU(x) (((x) * 1000) / 1024)
557 struct ath_beacon_config
{
567 } u
; /* last received beacon/probe response timestamp of this BSS. */
572 OK
, /* no change needed */
573 UPDATE
, /* update pending */
574 COMMIT
/* beacon sent, commit change */
575 } updateslot
; /* slot time update fsm */
581 int bslot
[ATH_BCBUF
];
584 struct ath9k_tx_queue_info beacon_qi
;
585 struct ath_descdma bdma
;
586 struct ath_txq
*cabq
;
587 struct list_head bbuf
;
590 void ath9k_beacon_tasklet(unsigned long data
);
591 void ath_beacon_config(struct ath_softc
*sc
, int if_id
);
592 int ath_beaconq_setup(struct ath_hal
*ah
);
593 int ath_beacon_alloc(struct ath_softc
*sc
, int if_id
);
594 void ath_beacon_return(struct ath_softc
*sc
, struct ath_vap
*avp
);
595 void ath_beacon_sync(struct ath_softc
*sc
, int if_id
);
601 /* ANI values for STA only.
602 FIXME: Add appropriate values for AP later */
604 #define ATH_ANI_POLLINTERVAL 100 /* 100 milliseconds between ANI poll */
605 #define ATH_SHORT_CALINTERVAL 1000 /* 1 second between calibrations */
606 #define ATH_LONG_CALINTERVAL 30000 /* 30 seconds between calibrations */
607 #define ATH_RESTART_CALINTERVAL 1200000 /* 20 minutes between calibrations */
611 int16_t sc_noise_floor
;
612 unsigned int sc_longcal_timer
;
613 unsigned int sc_shortcal_timer
;
614 unsigned int sc_resetcal_timer
;
615 unsigned int sc_checkani_timer
;
616 struct timer_list timer
;
619 /********************/
621 /********************/
623 #define ATH_LED_PIN 1
624 #define ATH_LED_ON_DURATION_IDLE 350 /* in msecs */
625 #define ATH_LED_OFF_DURATION_IDLE 250 /* in msecs */
635 struct ath_softc
*sc
;
636 struct led_classdev led_cdev
;
637 enum ath_led_type led_type
;
643 #define ATH_RFKILL_POLL_INTERVAL 2000 /* msecs */
646 struct rfkill
*rfkill
;
647 struct delayed_work rfkill_poll
;
648 char rfkill_name
[32];
651 /********************/
652 /* Main driver core */
653 /********************/
656 * Default cache line size, in bytes.
657 * Used when PCI device not fully initialized by bootrom/BIOS
659 #define DEFAULT_CACHELINE 32
660 #define ATH_DEFAULT_NOISE_FLOOR -95
661 #define ATH_REGCLASSIDS_MAX 10
662 #define ATH_CABQ_READY_TIME 80 /* % of beacon interval */
663 #define ATH_MAX_SW_RETRIES 10
664 #define ATH_CHAN_MAX 255
665 #define IEEE80211_WEP_NKID 4 /* number of key ids */
668 * The key cache is used for h/w cipher state and also for
669 * tracking station state such as the current tx antenna.
670 * We also setup a mapping table between key cache slot indices
671 * and station state to short-circuit node lookups on rx.
672 * Different parts have different size key caches. We handle
673 * up to ATH_KEYMAX entries (could dynamically allocate state).
675 #define ATH_KEYMAX 128 /* max key cache size we handle */
677 #define ATH_IF_ID_ANY 0xff
678 #define ATH_TXPOWER_MAX 100 /* .5 dBm units */
679 #define ATH_RSSI_DUMMY_MARKER 0x127
680 #define ATH_RATE_DUMMY_MARKER 0
682 #define SC_OP_INVALID BIT(0)
683 #define SC_OP_BEACONS BIT(1)
684 #define SC_OP_RXAGGR BIT(2)
685 #define SC_OP_TXAGGR BIT(3)
686 #define SC_OP_CHAINMASK_UPDATE BIT(4)
687 #define SC_OP_FULL_RESET BIT(5)
688 #define SC_OP_NO_RESET BIT(6)
689 #define SC_OP_PREAMBLE_SHORT BIT(7)
690 #define SC_OP_PROTECT_ENABLE BIT(8)
691 #define SC_OP_RXFLUSH BIT(9)
692 #define SC_OP_LED_ASSOCIATED BIT(10)
693 #define SC_OP_RFKILL_REGISTERED BIT(11)
694 #define SC_OP_RFKILL_SW_BLOCKED BIT(12)
695 #define SC_OP_RFKILL_HW_BLOCKED BIT(13)
696 #define SC_OP_WAIT_FOR_BEACON BIT(14)
697 #define SC_OP_LED_ON BIT(15)
700 void (*read_cachesize
)(struct ath_softc
*sc
, int *csz
);
701 void (*cleanup
)(struct ath_softc
*sc
);
702 bool (*eeprom_read
)(struct ath_hal
*ah
, u32 off
, u16
*data
);
706 struct ieee80211_hw
*hw
;
708 struct tasklet_struct intr_tq
;
709 struct tasklet_struct bcon_tasklet
;
710 struct ath_hal
*sc_ah
;
713 spinlock_t sc_resetlock
;
716 u8 sc_curbssid
[ETH_ALEN
];
717 u8 sc_myaddr
[ETH_ALEN
];
718 u8 sc_bssidmask
[ETH_ALEN
];
720 u32 sc_flags
; /* SC_OP_* */
729 DECLARE_BITMAP(sc_keymap
, ATH_KEYMAX
);
731 atomic_t ps_usecount
;
732 enum ath9k_int sc_imask
;
733 enum ath9k_ht_extprotspacing sc_ht_extprotspacing
;
734 enum ath9k_ht_macmode tx_chan_width
;
736 struct ath_config sc_config
;
739 struct ath_beacon beacon
;
740 struct ieee80211_vif
*sc_vaps
[ATH_BCBUF
];
741 struct ieee80211_rate rates
[IEEE80211_NUM_BANDS
][ATH_RATE_MAX
];
742 struct ath_rate_table
*hw_rate_table
[ATH9K_MODE_MAX
];
743 struct ath_rate_table
*cur_rate_table
;
744 struct ieee80211_supported_band sbands
[IEEE80211_NUM_BANDS
];
746 struct ath_led radio_led
;
747 struct ath_led assoc_led
;
748 struct ath_led tx_led
;
749 struct ath_led rx_led
;
750 struct delayed_work ath_led_blink_work
;
752 int led_off_duration
;
756 struct ath_rfkill rf_kill
;
757 struct ath_ani sc_ani
;
758 struct ath9k_node_stats sc_halstats
;
759 #ifdef CONFIG_ATH9K_DEBUG
760 struct ath9k_debug sc_debug
;
762 struct ath_bus_ops
*bus_ops
;
765 int ath_reset(struct ath_softc
*sc
, bool retry_tx
);
766 int ath_get_hal_qnum(u16 queue
, struct ath_softc
*sc
);
767 int ath_get_mac80211_qnum(u32 queue
, struct ath_softc
*sc
);
768 int ath_cabq_update(struct ath_softc
*);
770 static inline void ath_read_cachesize(struct ath_softc
*sc
, int *csz
)
772 sc
->bus_ops
->read_cachesize(sc
, csz
);
775 static inline void ath_bus_cleanup(struct ath_softc
*sc
)
777 sc
->bus_ops
->cleanup(sc
);
780 extern struct ieee80211_ops ath9k_ops
;
782 irqreturn_t
ath_isr(int irq
, void *dev
);
783 void ath_cleanup(struct ath_softc
*sc
);
784 int ath_attach(u16 devid
, struct ath_softc
*sc
);
785 void ath_detach(struct ath_softc
*sc
);
786 const char *ath_mac_bb_name(u32 mac_bb_version
);
787 const char *ath_rf_name(u16 rf_version
);
790 int ath_pci_init(void);
791 void ath_pci_exit(void);
793 static inline int ath_pci_init(void) { return 0; };
794 static inline void ath_pci_exit(void) {};
797 #ifdef CONFIG_ATHEROS_AR71XX
798 int ath_ahb_init(void);
799 void ath_ahb_exit(void);
801 static inline int ath_ahb_init(void) { return 0; };
802 static inline void ath_ahb_exit(void) {};
805 static inline void ath9k_ps_wakeup(struct ath_softc
*sc
)
807 if (atomic_inc_return(&sc
->ps_usecount
) == 1)
808 if (sc
->sc_ah
->ah_power_mode
!= ATH9K_PM_AWAKE
) {
809 sc
->sc_ah
->ah_restore_mode
= sc
->sc_ah
->ah_power_mode
;
810 ath9k_hw_setpower(sc
->sc_ah
, ATH9K_PM_AWAKE
);
814 static inline void ath9k_ps_restore(struct ath_softc
*sc
)
816 if (atomic_dec_and_test(&sc
->ps_usecount
))
817 if (sc
->hw
->conf
.flags
& IEEE80211_CONF_PS
)
818 ath9k_hw_setpower(sc
->sc_ah
,
819 sc
->sc_ah
->ah_restore_mode
);