2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/ratelimit.h>
15 #include <linux/kallsyms.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/sysdev.h>
24 #include <linux/ctype.h>
25 #include <linux/sched.h>
26 #include <linux/sysfs.h>
27 #include <linux/types.h>
28 #include <linux/init.h>
29 #include <linux/kmod.h>
30 #include <linux/poll.h>
31 #include <linux/cpu.h>
32 #include <linux/smp.h>
35 #include <asm/processor.h>
36 #include <asm/hw_irq.h>
43 #include "mce-internal.h"
46 /* Handle unconfigured int18 (should never happen) */
47 static void unexpected_machine_check(struct pt_regs
*regs
, long error_code
)
49 printk(KERN_ERR
"CPU#%d: Unexpected int18 (Machine Check).\n",
53 /* Call the installed machine check handler for this CPU setup. */
54 void (*machine_check_vector
)(struct pt_regs
*, long error_code
) =
55 unexpected_machine_check
;
59 #ifdef CONFIG_X86_NEW_MCE
61 #define MISC_MCELOG_MINOR 227
65 DEFINE_PER_CPU(unsigned, mce_exception_count
);
69 * 0: always panic on uncorrected errors, log corrected errors
70 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
71 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
72 * 3: never panic or SIGBUS, log all errors (for testing only)
74 static int tolerant
= 1;
77 static unsigned long notify_user
;
79 static int mce_bootlog
= -1;
81 static char trigger
[128];
82 static char *trigger_argv
[2] = { trigger
, NULL
};
84 static unsigned long dont_init_banks
;
86 static DECLARE_WAIT_QUEUE_HEAD(mce_wait
);
88 /* MCA banks polled by the period polling timer for corrected events */
89 DEFINE_PER_CPU(mce_banks_t
, mce_poll_banks
) = {
90 [0 ... BITS_TO_LONGS(MAX_NR_BANKS
)-1] = ~0UL
93 static inline int skip_bank_init(int i
)
95 return i
< BITS_PER_LONG
&& test_bit(i
, &dont_init_banks
);
98 /* Do initial initialization of a struct mce */
99 void mce_setup(struct mce
*m
)
101 memset(m
, 0, sizeof(struct mce
));
102 m
->cpu
= m
->extcpu
= smp_processor_id();
104 /* We hope get_seconds stays lockless */
105 m
->time
= get_seconds();
106 m
->cpuvendor
= boot_cpu_data
.x86_vendor
;
107 m
->cpuid
= cpuid_eax(1);
109 m
->socketid
= cpu_data(m
->extcpu
).phys_proc_id
;
111 m
->apicid
= cpu_data(m
->extcpu
).initial_apicid
;
112 rdmsrl(MSR_IA32_MCG_CAP
, m
->mcgcap
);
115 DEFINE_PER_CPU(struct mce
, injectm
);
116 EXPORT_PER_CPU_SYMBOL_GPL(injectm
);
119 * Lockless MCE logging infrastructure.
120 * This avoids deadlocks on printk locks without having to break locks. Also
121 * separate MCEs from kernel messages to avoid bogus bug reports.
124 static struct mce_log mcelog
= {
125 .signature
= MCE_LOG_SIGNATURE
,
127 .recordlen
= sizeof(struct mce
),
130 void mce_log(struct mce
*mce
)
132 unsigned next
, entry
;
137 entry
= rcu_dereference(mcelog
.next
);
140 * When the buffer fills up discard new entries.
141 * Assume that the earlier errors are the more
144 if (entry
>= MCE_LOG_LEN
) {
145 set_bit(MCE_OVERFLOW
,
146 (unsigned long *)&mcelog
.flags
);
149 /* Old left over entry. Skip: */
150 if (mcelog
.entry
[entry
].finished
) {
158 if (cmpxchg(&mcelog
.next
, entry
, next
) == entry
)
161 memcpy(mcelog
.entry
+ entry
, mce
, sizeof(struct mce
));
163 mcelog
.entry
[entry
].finished
= 1;
167 set_bit(0, ¬ify_user
);
170 static void print_mce(struct mce
*m
)
172 printk(KERN_EMERG
"\n"
173 KERN_EMERG
"HARDWARE ERROR\n"
175 "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
176 m
->extcpu
, m
->mcgstatus
, m
->bank
, m
->status
);
178 printk(KERN_EMERG
"RIP%s %02x:<%016Lx> ",
179 !(m
->mcgstatus
& MCG_STATUS_EIPV
) ? " !INEXACT!" : "",
181 if (m
->cs
== __KERNEL_CS
)
182 print_symbol("{%s}", m
->ip
);
185 printk(KERN_EMERG
"TSC %llx ", m
->tsc
);
187 printk("ADDR %llx ", m
->addr
);
189 printk("MISC %llx ", m
->misc
);
191 printk(KERN_EMERG
"PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
192 m
->cpuvendor
, m
->cpuid
, m
->time
, m
->socketid
,
194 printk(KERN_EMERG
"This is not a software problem!\n");
195 printk(KERN_EMERG
"Run through mcelog --ascii to decode "
196 "and contact your hardware vendor\n");
199 #define PANIC_TIMEOUT 5 /* 5 seconds */
201 static atomic_t mce_paniced
;
203 /* Panic in progress. Enable interrupts and wait for final IPI */
204 static void wait_for_panic(void)
206 long timeout
= PANIC_TIMEOUT
*USEC_PER_SEC
;
209 while (timeout
-- > 0)
211 panic("Panicing machine check CPU died");
214 static void mce_panic(char *msg
, struct mce
*final
, char *exp
)
219 * Make sure only one CPU runs in machine check panic
221 if (atomic_add_return(1, &mce_paniced
) > 1)
227 /* First print corrected ones that are still unlogged */
228 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
229 struct mce
*m
= &mcelog
.entry
[i
];
230 if ((m
->status
& MCI_STATUS_VAL
) &&
231 !(m
->status
& MCI_STATUS_UC
))
234 /* Now print uncorrected but with the final one last */
235 for (i
= 0; i
< MCE_LOG_LEN
; i
++) {
236 struct mce
*m
= &mcelog
.entry
[i
];
237 if (!(m
->status
& MCI_STATUS_VAL
))
239 if (!final
|| memcmp(m
, final
, sizeof(struct mce
)))
245 printk(KERN_EMERG
"Machine check: %s\n", exp
);
249 /* Support code for software error injection */
251 static int msr_to_offset(u32 msr
)
253 unsigned bank
= __get_cpu_var(injectm
.bank
);
255 return offsetof(struct mce
, ip
);
256 if (msr
== MSR_IA32_MC0_STATUS
+ bank
*4)
257 return offsetof(struct mce
, status
);
258 if (msr
== MSR_IA32_MC0_ADDR
+ bank
*4)
259 return offsetof(struct mce
, addr
);
260 if (msr
== MSR_IA32_MC0_MISC
+ bank
*4)
261 return offsetof(struct mce
, misc
);
262 if (msr
== MSR_IA32_MCG_STATUS
)
263 return offsetof(struct mce
, mcgstatus
);
267 /* MSR access wrappers used for error injection */
268 static u64
mce_rdmsrl(u32 msr
)
271 if (__get_cpu_var(injectm
).finished
) {
272 int offset
= msr_to_offset(msr
);
275 return *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
);
281 static void mce_wrmsrl(u32 msr
, u64 v
)
283 if (__get_cpu_var(injectm
).finished
) {
284 int offset
= msr_to_offset(msr
);
286 *(u64
*)((char *)&__get_cpu_var(injectm
) + offset
) = v
;
292 int mce_available(struct cpuinfo_x86
*c
)
296 return cpu_has(c
, X86_FEATURE_MCE
) && cpu_has(c
, X86_FEATURE_MCA
);
299 static inline void mce_get_rip(struct mce
*m
, struct pt_regs
*regs
)
301 if (regs
&& (m
->mcgstatus
& MCG_STATUS_RIPV
)) {
309 /* Assume the RIP in the MSR is exact. Is this true? */
310 m
->mcgstatus
|= MCG_STATUS_EIPV
;
311 m
->ip
= mce_rdmsrl(rip_msr
);
316 #ifdef CONFIG_X86_LOCAL_APIC
318 * Called after interrupts have been reenabled again
319 * when a MCE happened during an interrupts off region
322 asmlinkage
void smp_mce_self_interrupt(struct pt_regs
*regs
)
332 static void mce_report_event(struct pt_regs
*regs
)
334 if (regs
->flags
& (X86_VM_MASK
|X86_EFLAGS_IF
)) {
339 #ifdef CONFIG_X86_LOCAL_APIC
341 * Without APIC do not notify. The event will be picked
348 * When interrupts are disabled we cannot use
349 * kernel services safely. Trigger an self interrupt
350 * through the APIC to instead do the notification
351 * after interrupts are reenabled again.
353 apic
->send_IPI_self(MCE_SELF_VECTOR
);
356 * Wait for idle afterwards again so that we don't leave the
357 * APIC in a non idle state because the normal APIC writes
360 apic_wait_icr_idle();
364 DEFINE_PER_CPU(unsigned, mce_poll_count
);
367 * Poll for corrected events or events that happened before reset.
368 * Those are just logged through /dev/mcelog.
370 * This is executed in standard interrupt context.
372 void machine_check_poll(enum mcp_flags flags
, mce_banks_t
*b
)
377 __get_cpu_var(mce_poll_count
)++;
381 m
.mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
382 for (i
= 0; i
< banks
; i
++) {
383 if (!bank
[i
] || !test_bit(i
, *b
))
392 m
.status
= mce_rdmsrl(MSR_IA32_MC0_STATUS
+ i
*4);
393 if (!(m
.status
& MCI_STATUS_VAL
))
397 * Uncorrected events are handled by the exception handler
398 * when it is enabled. But when the exception is disabled log
401 * TBD do the same check for MCI_STATUS_EN here?
403 if ((m
.status
& MCI_STATUS_UC
) && !(flags
& MCP_UC
))
406 if (m
.status
& MCI_STATUS_MISCV
)
407 m
.misc
= mce_rdmsrl(MSR_IA32_MC0_MISC
+ i
*4);
408 if (m
.status
& MCI_STATUS_ADDRV
)
409 m
.addr
= mce_rdmsrl(MSR_IA32_MC0_ADDR
+ i
*4);
411 if (!(flags
& MCP_TIMESTAMP
))
414 * Don't get the IP here because it's unlikely to
415 * have anything to do with the actual error location.
417 if (!(flags
& MCP_DONTLOG
)) {
419 add_taint(TAINT_MACHINE_CHECK
);
423 * Clear state for this bank.
425 mce_wrmsrl(MSR_IA32_MC0_STATUS
+4*i
, 0);
429 * Don't clear MCG_STATUS here because it's only defined for
435 EXPORT_SYMBOL_GPL(machine_check_poll
);
438 * Do a quick check if any of the events requires a panic.
439 * This decides if we keep the events around or clear them.
441 static int mce_no_way_out(struct mce
*m
, char **msg
)
445 for (i
= 0; i
< banks
; i
++) {
446 m
->status
= mce_rdmsrl(MSR_IA32_MC0_STATUS
+ i
*4);
447 if (mce_severity(m
, tolerant
, msg
) >= MCE_PANIC_SEVERITY
)
454 * The actual machine check handler. This only handles real
455 * exceptions when something got corrupted coming in through int 18.
457 * This is executed in NMI context not subject to normal locking rules. This
458 * implies that most kernel services cannot be safely used. Don't even
459 * think about putting a printk in there!
461 void do_machine_check(struct pt_regs
*regs
, long error_code
)
463 struct mce m
, panicm
;
464 int panicm_found
= 0;
467 * If no_way_out gets set, there is no safe way to recover from this
468 * MCE. If tolerant is cranked up, we'll try anyway.
472 * If kill_it gets set, there might be a way to recover from this
476 DECLARE_BITMAP(toclear
, MAX_NR_BANKS
);
477 char *msg
= "Unknown";
479 atomic_inc(&mce_entry
);
481 __get_cpu_var(mce_exception_count
)++;
483 if (notify_die(DIE_NMI
, "machine check", regs
, error_code
,
484 18, SIGKILL
) == NOTIFY_STOP
)
491 m
.mcgstatus
= mce_rdmsrl(MSR_IA32_MCG_STATUS
);
492 no_way_out
= mce_no_way_out(&m
, &msg
);
496 for (i
= 0; i
< banks
; i
++) {
497 __clear_bit(i
, toclear
);
505 m
.status
= mce_rdmsrl(MSR_IA32_MC0_STATUS
+ i
*4);
506 if ((m
.status
& MCI_STATUS_VAL
) == 0)
510 * Non uncorrected errors are handled by machine_check_poll
511 * Leave them alone, unless this panics.
513 if ((m
.status
& MCI_STATUS_UC
) == 0 && !no_way_out
)
517 * Set taint even when machine check was not enabled.
519 add_taint(TAINT_MACHINE_CHECK
);
521 __set_bit(i
, toclear
);
523 if (m
.status
& MCI_STATUS_EN
) {
525 * If this error was uncorrectable and there was
526 * an overflow, we're in trouble. If no overflow,
527 * we might get away with just killing a task.
529 if (m
.status
& MCI_STATUS_UC
)
533 * Machine check event was not enabled. Clear, but
539 if (m
.status
& MCI_STATUS_MISCV
)
540 m
.misc
= mce_rdmsrl(MSR_IA32_MC0_MISC
+ i
*4);
541 if (m
.status
& MCI_STATUS_ADDRV
)
542 m
.addr
= mce_rdmsrl(MSR_IA32_MC0_ADDR
+ i
*4);
544 mce_get_rip(&m
, regs
);
548 * Did this bank cause the exception?
550 * Assume that the bank with uncorrectable errors did it,
551 * and that there is only a single one:
553 if ((m
.status
& MCI_STATUS_UC
) &&
554 (m
.status
& MCI_STATUS_EN
)) {
561 * If we didn't find an uncorrectable error, pick
562 * the last one (shouldn't happen, just being safe).
568 * If we have decided that we just CAN'T continue, and the user
569 * has not set tolerant to an insane level, give up and die.
571 if (no_way_out
&& tolerant
< 3)
572 mce_panic("Machine check", &panicm
, msg
);
575 * If the error seems to be unrecoverable, something should be
576 * done. Try to kill as little as possible. If we can kill just
577 * one task, do that. If the user has set the tolerance very
578 * high, don't try to do anything at all.
580 if (kill_it
&& tolerant
< 3) {
584 * If the EIPV bit is set, it means the saved IP is the
585 * instruction which caused the MCE.
587 if (m
.mcgstatus
& MCG_STATUS_EIPV
)
588 user_space
= panicm
.ip
&& (panicm
.cs
& 3);
591 * If we know that the error was in user space, send a
592 * SIGBUS. Otherwise, panic if tolerance is low.
594 * force_sig() takes an awful lot of locks and has a slight
595 * risk of deadlocking.
598 force_sig(SIGBUS
, current
);
599 } else if (panic_on_oops
|| tolerant
< 2) {
600 mce_panic("Uncorrected machine check", &panicm
, msg
);
604 /* notify userspace ASAP */
605 set_thread_flag(TIF_MCE_NOTIFY
);
607 mce_report_event(regs
);
609 /* the last thing we do is clear state */
610 for (i
= 0; i
< banks
; i
++) {
611 if (test_bit(i
, toclear
))
612 mce_wrmsrl(MSR_IA32_MC0_STATUS
+4*i
, 0);
614 mce_wrmsrl(MSR_IA32_MCG_STATUS
, 0);
616 atomic_dec(&mce_entry
);
619 EXPORT_SYMBOL_GPL(do_machine_check
);
621 #ifdef CONFIG_X86_MCE_INTEL
623 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
624 * @cpu: The CPU on which the event occurred.
625 * @status: Event status information
627 * This function should be called by the thermal interrupt after the
628 * event has been processed and the decision was made to log the event
631 * The status parameter will be saved to the 'status' field of 'struct mce'
632 * and historically has been the register value of the
633 * MSR_IA32_THERMAL_STATUS (Intel) msr.
635 void mce_log_therm_throt_event(__u64 status
)
640 m
.bank
= MCE_THERMAL_BANK
;
644 #endif /* CONFIG_X86_MCE_INTEL */
647 * Periodic polling timer for "silent" machine check errors. If the
648 * poller finds an MCE, poll 2x faster. When the poller finds no more
649 * errors, poll 2x slower (up to check_interval seconds).
651 static int check_interval
= 5 * 60; /* 5 minutes */
653 static DEFINE_PER_CPU(int, next_interval
); /* in jiffies */
654 static DEFINE_PER_CPU(struct timer_list
, mce_timer
);
656 static void mcheck_timer(unsigned long data
)
658 struct timer_list
*t
= &per_cpu(mce_timer
, data
);
661 WARN_ON(smp_processor_id() != data
);
663 if (mce_available(¤t_cpu_data
)) {
664 machine_check_poll(MCP_TIMESTAMP
,
665 &__get_cpu_var(mce_poll_banks
));
669 * Alert userspace if needed. If we logged an MCE, reduce the
670 * polling interval, otherwise increase the polling interval.
672 n
= &__get_cpu_var(next_interval
);
673 if (mce_notify_user())
674 *n
= max(*n
/2, HZ
/100);
676 *n
= min(*n
*2, (int)round_jiffies_relative(check_interval
*HZ
));
678 t
->expires
= jiffies
+ *n
;
682 static void mce_do_trigger(struct work_struct
*work
)
684 call_usermodehelper(trigger
, trigger_argv
, NULL
, UMH_NO_WAIT
);
687 static DECLARE_WORK(mce_trigger_work
, mce_do_trigger
);
690 * Notify the user(s) about new machine check events.
691 * Can be called from interrupt context, but not from machine check/NMI
694 int mce_notify_user(void)
696 /* Not more than two messages every minute */
697 static DEFINE_RATELIMIT_STATE(ratelimit
, 60*HZ
, 2);
699 clear_thread_flag(TIF_MCE_NOTIFY
);
701 if (test_and_clear_bit(0, ¬ify_user
)) {
702 wake_up_interruptible(&mce_wait
);
705 * There is no risk of missing notifications because
706 * work_pending is always cleared before the function is
709 if (trigger
[0] && !work_pending(&mce_trigger_work
))
710 schedule_work(&mce_trigger_work
);
712 if (__ratelimit(&ratelimit
))
713 printk(KERN_INFO
"Machine check events logged\n");
719 EXPORT_SYMBOL_GPL(mce_notify_user
);
722 * Initialize Machine Checks for a CPU.
724 static int mce_cap_init(void)
729 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
731 b
= cap
& MCG_BANKCNT_MASK
;
732 printk(KERN_INFO
"mce: CPU supports %d MCE banks\n", b
);
734 if (b
> MAX_NR_BANKS
) {
736 "MCE: Using only %u machine check banks out of %u\n",
741 /* Don't support asymmetric configurations today */
742 WARN_ON(banks
!= 0 && b
!= banks
);
745 bank
= kmalloc(banks
* sizeof(u64
), GFP_KERNEL
);
748 memset(bank
, 0xff, banks
* sizeof(u64
));
751 /* Use accurate RIP reporting if available. */
752 if ((cap
& MCG_EXT_P
) && MCG_EXT_CNT(cap
) >= 9)
753 rip_msr
= MSR_IA32_MCG_EIP
;
758 static void mce_init(void)
760 mce_banks_t all_banks
;
765 * Log the machine checks left over from the previous reset.
767 bitmap_fill(all_banks
, MAX_NR_BANKS
);
768 machine_check_poll(MCP_UC
|(!mce_bootlog
? MCP_DONTLOG
: 0), &all_banks
);
770 set_in_cr4(X86_CR4_MCE
);
772 rdmsrl(MSR_IA32_MCG_CAP
, cap
);
774 wrmsr(MSR_IA32_MCG_CTL
, 0xffffffff, 0xffffffff);
776 for (i
= 0; i
< banks
; i
++) {
777 if (skip_bank_init(i
))
779 wrmsrl(MSR_IA32_MC0_CTL
+4*i
, bank
[i
]);
780 wrmsrl(MSR_IA32_MC0_STATUS
+4*i
, 0);
784 /* Add per CPU specific workarounds here */
785 static void mce_cpu_quirks(struct cpuinfo_x86
*c
)
787 /* This should be disabled by the BIOS, but isn't always */
788 if (c
->x86_vendor
== X86_VENDOR_AMD
) {
789 if (c
->x86
== 15 && banks
> 4) {
791 * disable GART TBL walk error reporting, which
792 * trips off incorrectly with the IOMMU & 3ware
795 clear_bit(10, (unsigned long *)&bank
[4]);
797 if (c
->x86
<= 17 && mce_bootlog
< 0) {
799 * Lots of broken BIOS around that don't clear them
800 * by default and leave crap in there. Don't log:
805 * Various K7s with broken bank 0 around. Always disable
812 if (c
->x86_vendor
== X86_VENDOR_INTEL
) {
814 * SDM documents that on family 6 bank 0 should not be written
815 * because it aliases to another special BIOS controlled
817 * But it's not aliased anymore on model 0x1a+
818 * Don't ignore bank 0 completely because there could be a
819 * valid event later, merely don't write CTL0.
822 if (c
->x86
== 6 && c
->x86_model
< 0x1A)
823 __set_bit(0, &dont_init_banks
);
827 static void __cpuinit
mce_ancient_init(struct cpuinfo_x86
*c
)
831 switch (c
->x86_vendor
) {
832 case X86_VENDOR_INTEL
:
833 if (mce_p5_enabled())
834 intel_p5_mcheck_init(c
);
836 case X86_VENDOR_CENTAUR
:
837 winchip_mcheck_init(c
);
842 static void mce_cpu_features(struct cpuinfo_x86
*c
)
844 switch (c
->x86_vendor
) {
845 case X86_VENDOR_INTEL
:
846 mce_intel_feature_init(c
);
849 mce_amd_feature_init(c
);
856 static void mce_init_timer(void)
858 struct timer_list
*t
= &__get_cpu_var(mce_timer
);
859 int *n
= &__get_cpu_var(next_interval
);
861 *n
= check_interval
* HZ
;
864 setup_timer(t
, mcheck_timer
, smp_processor_id());
865 t
->expires
= round_jiffies(jiffies
+ *n
);
870 * Called for each booted CPU to set up machine checks.
871 * Must be called with preempt off:
873 void __cpuinit
mcheck_init(struct cpuinfo_x86
*c
)
880 if (!mce_available(c
))
883 if (mce_cap_init() < 0) {
889 machine_check_vector
= do_machine_check
;
897 * Character device to read and clear the MCE log.
900 static DEFINE_SPINLOCK(mce_state_lock
);
901 static int open_count
; /* #times opened */
902 static int open_exclu
; /* already open exclusive? */
904 static int mce_open(struct inode
*inode
, struct file
*file
)
906 spin_lock(&mce_state_lock
);
908 if (open_exclu
|| (open_count
&& (file
->f_flags
& O_EXCL
))) {
909 spin_unlock(&mce_state_lock
);
914 if (file
->f_flags
& O_EXCL
)
918 spin_unlock(&mce_state_lock
);
920 return nonseekable_open(inode
, file
);
923 static int mce_release(struct inode
*inode
, struct file
*file
)
925 spin_lock(&mce_state_lock
);
930 spin_unlock(&mce_state_lock
);
935 static void collect_tscs(void *data
)
937 unsigned long *cpu_tsc
= (unsigned long *)data
;
939 rdtscll(cpu_tsc
[smp_processor_id()]);
942 static DEFINE_MUTEX(mce_read_mutex
);
944 static ssize_t
mce_read(struct file
*filp
, char __user
*ubuf
, size_t usize
,
947 char __user
*buf
= ubuf
;
948 unsigned long *cpu_tsc
;
952 cpu_tsc
= kmalloc(nr_cpu_ids
* sizeof(long), GFP_KERNEL
);
956 mutex_lock(&mce_read_mutex
);
957 next
= rcu_dereference(mcelog
.next
);
959 /* Only supports full reads right now */
960 if (*off
!= 0 || usize
< MCE_LOG_LEN
*sizeof(struct mce
)) {
961 mutex_unlock(&mce_read_mutex
);
970 for (i
= prev
; i
< next
; i
++) {
971 unsigned long start
= jiffies
;
973 while (!mcelog
.entry
[i
].finished
) {
974 if (time_after_eq(jiffies
, start
+ 2)) {
975 memset(mcelog
.entry
+ i
, 0,
982 err
|= copy_to_user(buf
, mcelog
.entry
+ i
,
984 buf
+= sizeof(struct mce
);
989 memset(mcelog
.entry
+ prev
, 0,
990 (next
- prev
) * sizeof(struct mce
));
992 next
= cmpxchg(&mcelog
.next
, prev
, 0);
993 } while (next
!= prev
);
998 * Collect entries that were still getting written before the
1001 on_each_cpu(collect_tscs
, cpu_tsc
, 1);
1003 for (i
= next
; i
< MCE_LOG_LEN
; i
++) {
1004 if (mcelog
.entry
[i
].finished
&&
1005 mcelog
.entry
[i
].tsc
< cpu_tsc
[mcelog
.entry
[i
].cpu
]) {
1006 err
|= copy_to_user(buf
, mcelog
.entry
+i
,
1007 sizeof(struct mce
));
1009 buf
+= sizeof(struct mce
);
1010 memset(&mcelog
.entry
[i
], 0, sizeof(struct mce
));
1013 mutex_unlock(&mce_read_mutex
);
1016 return err
? -EFAULT
: buf
- ubuf
;
1019 static unsigned int mce_poll(struct file
*file
, poll_table
*wait
)
1021 poll_wait(file
, &mce_wait
, wait
);
1022 if (rcu_dereference(mcelog
.next
))
1023 return POLLIN
| POLLRDNORM
;
1027 static long mce_ioctl(struct file
*f
, unsigned int cmd
, unsigned long arg
)
1029 int __user
*p
= (int __user
*)arg
;
1031 if (!capable(CAP_SYS_ADMIN
))
1035 case MCE_GET_RECORD_LEN
:
1036 return put_user(sizeof(struct mce
), p
);
1037 case MCE_GET_LOG_LEN
:
1038 return put_user(MCE_LOG_LEN
, p
);
1039 case MCE_GETCLEAR_FLAGS
: {
1043 flags
= mcelog
.flags
;
1044 } while (cmpxchg(&mcelog
.flags
, flags
, 0) != flags
);
1046 return put_user(flags
, p
);
1053 /* Modified in mce-inject.c, so not static or const */
1054 struct file_operations mce_chrdev_ops
= {
1056 .release
= mce_release
,
1059 .unlocked_ioctl
= mce_ioctl
,
1061 EXPORT_SYMBOL_GPL(mce_chrdev_ops
);
1063 static struct miscdevice mce_log_device
= {
1070 * mce=off disables machine check
1071 * mce=TOLERANCELEVEL (number, see above)
1072 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1073 * mce=nobootlog Don't log MCEs from before booting.
1075 static int __init
mcheck_enable(char *str
)
1081 if (!strcmp(str
, "off"))
1083 else if (!strcmp(str
, "bootlog") || !strcmp(str
, "nobootlog"))
1084 mce_bootlog
= (str
[0] == 'b');
1085 else if (isdigit(str
[0]))
1086 get_option(&str
, &tolerant
);
1088 printk(KERN_INFO
"mce argument %s ignored. Please use /sys\n",
1094 __setup("mce", mcheck_enable
);
1101 * Disable machine checks on suspend and shutdown. We can't really handle
1104 static int mce_disable(void)
1108 for (i
= 0; i
< banks
; i
++) {
1109 if (!skip_bank_init(i
))
1110 wrmsrl(MSR_IA32_MC0_CTL
+ i
*4, 0);
1115 static int mce_suspend(struct sys_device
*dev
, pm_message_t state
)
1117 return mce_disable();
1120 static int mce_shutdown(struct sys_device
*dev
)
1122 return mce_disable();
1126 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1127 * Only one CPU is active at this time, the others get re-added later using
1130 static int mce_resume(struct sys_device
*dev
)
1133 mce_cpu_features(¤t_cpu_data
);
1138 static void mce_cpu_restart(void *data
)
1140 del_timer_sync(&__get_cpu_var(mce_timer
));
1141 if (mce_available(¤t_cpu_data
))
1146 /* Reinit MCEs after user configuration changes */
1147 static void mce_restart(void)
1149 on_each_cpu(mce_cpu_restart
, NULL
, 1);
1152 static struct sysdev_class mce_sysclass
= {
1153 .suspend
= mce_suspend
,
1154 .shutdown
= mce_shutdown
,
1155 .resume
= mce_resume
,
1156 .name
= "machinecheck",
1159 DEFINE_PER_CPU(struct sys_device
, mce_dev
);
1162 void (*threshold_cpu_callback
)(unsigned long action
, unsigned int cpu
);
1164 static struct sysdev_attribute
*bank_attrs
;
1166 static ssize_t
show_bank(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1169 u64 b
= bank
[attr
- bank_attrs
];
1171 return sprintf(buf
, "%llx\n", b
);
1174 static ssize_t
set_bank(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1175 const char *buf
, size_t size
)
1179 if (strict_strtoull(buf
, 0, &new) < 0)
1182 bank
[attr
- bank_attrs
] = new;
1189 show_trigger(struct sys_device
*s
, struct sysdev_attribute
*attr
, char *buf
)
1191 strcpy(buf
, trigger
);
1193 return strlen(trigger
) + 1;
1196 static ssize_t
set_trigger(struct sys_device
*s
, struct sysdev_attribute
*attr
,
1197 const char *buf
, size_t siz
)
1202 strncpy(trigger
, buf
, sizeof(trigger
));
1203 trigger
[sizeof(trigger
)-1] = 0;
1204 len
= strlen(trigger
);
1205 p
= strchr(trigger
, '\n');
1213 static ssize_t
store_int_with_restart(struct sys_device
*s
,
1214 struct sysdev_attribute
*attr
,
1215 const char *buf
, size_t size
)
1217 ssize_t ret
= sysdev_store_int(s
, attr
, buf
, size
);
1222 static SYSDEV_ATTR(trigger
, 0644, show_trigger
, set_trigger
);
1223 static SYSDEV_INT_ATTR(tolerant
, 0644, tolerant
);
1225 static struct sysdev_ext_attribute attr_check_interval
= {
1226 _SYSDEV_ATTR(check_interval
, 0644, sysdev_show_int
,
1227 store_int_with_restart
),
1231 static struct sysdev_attribute
*mce_attrs
[] = {
1232 &attr_tolerant
.attr
, &attr_check_interval
.attr
, &attr_trigger
,
1236 static cpumask_var_t mce_dev_initialized
;
1238 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1239 static __cpuinit
int mce_create_device(unsigned int cpu
)
1244 if (!mce_available(&boot_cpu_data
))
1247 memset(&per_cpu(mce_dev
, cpu
).kobj
, 0, sizeof(struct kobject
));
1248 per_cpu(mce_dev
, cpu
).id
= cpu
;
1249 per_cpu(mce_dev
, cpu
).cls
= &mce_sysclass
;
1251 err
= sysdev_register(&per_cpu(mce_dev
, cpu
));
1255 for (i
= 0; mce_attrs
[i
]; i
++) {
1256 err
= sysdev_create_file(&per_cpu(mce_dev
, cpu
), mce_attrs
[i
]);
1260 for (i
= 0; i
< banks
; i
++) {
1261 err
= sysdev_create_file(&per_cpu(mce_dev
, cpu
),
1266 cpumask_set_cpu(cpu
, mce_dev_initialized
);
1271 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), &bank_attrs
[i
]);
1274 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), mce_attrs
[i
]);
1276 sysdev_unregister(&per_cpu(mce_dev
, cpu
));
1281 static __cpuinit
void mce_remove_device(unsigned int cpu
)
1285 if (!cpumask_test_cpu(cpu
, mce_dev_initialized
))
1288 for (i
= 0; mce_attrs
[i
]; i
++)
1289 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), mce_attrs
[i
]);
1291 for (i
= 0; i
< banks
; i
++)
1292 sysdev_remove_file(&per_cpu(mce_dev
, cpu
), &bank_attrs
[i
]);
1294 sysdev_unregister(&per_cpu(mce_dev
, cpu
));
1295 cpumask_clear_cpu(cpu
, mce_dev_initialized
);
1298 /* Make sure there are no machine checks on offlined CPUs. */
1299 static void mce_disable_cpu(void *h
)
1301 unsigned long action
= *(unsigned long *)h
;
1304 if (!mce_available(¤t_cpu_data
))
1306 if (!(action
& CPU_TASKS_FROZEN
))
1308 for (i
= 0; i
< banks
; i
++) {
1309 if (!skip_bank_init(i
))
1310 wrmsrl(MSR_IA32_MC0_CTL
+ i
*4, 0);
1314 static void mce_reenable_cpu(void *h
)
1316 unsigned long action
= *(unsigned long *)h
;
1319 if (!mce_available(¤t_cpu_data
))
1322 if (!(action
& CPU_TASKS_FROZEN
))
1324 for (i
= 0; i
< banks
; i
++) {
1325 if (!skip_bank_init(i
))
1326 wrmsrl(MSR_IA32_MC0_CTL
+ i
*4, bank
[i
]);
1330 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
1331 static int __cpuinit
1332 mce_cpu_callback(struct notifier_block
*nfb
, unsigned long action
, void *hcpu
)
1334 unsigned int cpu
= (unsigned long)hcpu
;
1335 struct timer_list
*t
= &per_cpu(mce_timer
, cpu
);
1339 case CPU_ONLINE_FROZEN
:
1340 mce_create_device(cpu
);
1341 if (threshold_cpu_callback
)
1342 threshold_cpu_callback(action
, cpu
);
1345 case CPU_DEAD_FROZEN
:
1346 if (threshold_cpu_callback
)
1347 threshold_cpu_callback(action
, cpu
);
1348 mce_remove_device(cpu
);
1350 case CPU_DOWN_PREPARE
:
1351 case CPU_DOWN_PREPARE_FROZEN
:
1353 smp_call_function_single(cpu
, mce_disable_cpu
, &action
, 1);
1355 case CPU_DOWN_FAILED
:
1356 case CPU_DOWN_FAILED_FROZEN
:
1357 t
->expires
= round_jiffies(jiffies
+
1358 __get_cpu_var(next_interval
));
1359 add_timer_on(t
, cpu
);
1360 smp_call_function_single(cpu
, mce_reenable_cpu
, &action
, 1);
1363 /* intentionally ignoring frozen here */
1364 cmci_rediscover(cpu
);
1370 static struct notifier_block mce_cpu_notifier __cpuinitdata
= {
1371 .notifier_call
= mce_cpu_callback
,
1374 static __init
int mce_init_banks(void)
1378 bank_attrs
= kzalloc(sizeof(struct sysdev_attribute
) * banks
,
1383 for (i
= 0; i
< banks
; i
++) {
1384 struct sysdev_attribute
*a
= &bank_attrs
[i
];
1386 a
->attr
.name
= kasprintf(GFP_KERNEL
, "bank%d", i
);
1390 a
->attr
.mode
= 0644;
1391 a
->show
= show_bank
;
1392 a
->store
= set_bank
;
1398 kfree(bank_attrs
[i
].attr
.name
);
1405 static __init
int mce_init_device(void)
1410 if (!mce_available(&boot_cpu_data
))
1413 alloc_cpumask_var(&mce_dev_initialized
, GFP_KERNEL
);
1415 err
= mce_init_banks();
1419 err
= sysdev_class_register(&mce_sysclass
);
1423 for_each_online_cpu(i
) {
1424 err
= mce_create_device(i
);
1429 register_hotcpu_notifier(&mce_cpu_notifier
);
1430 misc_register(&mce_log_device
);
1435 device_initcall(mce_init_device
);
1437 #else /* CONFIG_X86_OLD_MCE: */
1440 EXPORT_SYMBOL_GPL(nr_mce_banks
); /* non-fatal.o */
1442 /* This has to be run for each processor */
1443 void mcheck_init(struct cpuinfo_x86
*c
)
1445 if (mce_disabled
== 1)
1448 switch (c
->x86_vendor
) {
1449 case X86_VENDOR_AMD
:
1453 case X86_VENDOR_INTEL
:
1455 intel_p5_mcheck_init(c
);
1457 intel_p6_mcheck_init(c
);
1459 intel_p4_mcheck_init(c
);
1462 case X86_VENDOR_CENTAUR
:
1464 winchip_mcheck_init(c
);
1470 printk(KERN_INFO
"mce: CPU supports %d MCE banks\n", nr_mce_banks
);
1473 static int __init
mcheck_enable(char *str
)
1479 __setup("mce", mcheck_enable
);
1481 #endif /* CONFIG_X86_OLD_MCE */
1484 * Old style boot options parsing. Only for compatibility.
1486 static int __init
mcheck_disable(char *str
)
1491 __setup("nomce", mcheck_disable
);