arch/powerpc/platforms/86xx/pci.c

   1 /*
   2  * MPC86XX pci setup code
   3  *
   4  * Recode: ZHANG WEI <wei.zhang@freescale.com>
   5  * Initial author: Xianghua Xiao <x.xiao@freescale.com>
   6  *
   7  * Copyright 2006 Freescale Semiconductor Inc.
   8  *
   9  * This program is free software; you can redistribute  it and/or modify it
  10  * under  the terms of  the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the  License, or (at your
  12  * option) any later version.
  13  */
  14
  15 #include <linux/types.h>
  16 #include <linux/module.h>
  17 #include <linux/init.h>
  18 #include <linux/pci.h>
  19 #include <linux/serial.h>
  20
  21 #include <asm/system.h>
  22 #include <asm/atomic.h>
  23 #include <asm/io.h>
  24 #include <asm/prom.h>
  25 #include <asm/immap_86xx.h>
  26 #include <asm/pci-bridge.h>
  27 #include <sysdev/fsl_soc.h>
  28
  29 #include "mpc86xx.h"
  30
  31 #undef DEBUG
  32
  33 #ifdef DEBUG
  34 #define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
  35 #else
  36 #define DBG(fmt, args...)
  37 #endif
  38
  39 struct pcie_outbound_window_regs {
  40         uint    pexotar;               /* 0x.0 - PCI Express outbound translation address register */
  41         uint    pexotear;              /* 0x.4 - PCI Express outbound translation extended address register */
  42         uint    pexowbar;              /* 0x.8 - PCI Express outbound window base address register */
  43         char    res1[4];
  44         uint    pexowar;               /* 0x.10 - PCI Express outbound window attributes register */
  45         char    res2[12];
  46 };
  47
  48 struct pcie_inbound_window_regs {
  49         uint    pexitar;               /* 0x.0 - PCI Express inbound translation address register */
  50         char    res1[4];
  51         uint    pexiwbar;              /* 0x.8 - PCI Express inbound window base address register */
  52         uint    pexiwbear;             /* 0x.c - PCI Express inbound window base extended address register */
  53         uint    pexiwar;               /* 0x.10 - PCI Express inbound window attributes register */
  54         char    res2[12];
  55 };
  56
  57 static void __init setup_pcie_atmu(struct pci_controller *hose, struct resource *rsrc)
  58 {
  59         volatile struct ccsr_pex *pcie;
  60         volatile struct pcie_outbound_window_regs *pcieow;
  61         volatile struct pcie_inbound_window_regs *pcieiw;
  62         int i = 0;
  63
  64         DBG("PCIE memory map start 0x%x, size 0x%x\n", rsrc->start,
  65                         rsrc->end - rsrc->start + 1);
  66         pcie = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
  67
  68         /* Disable all windows (except pexowar0 since its ignored) */
  69         pcie->pexowar1 = 0;
  70         pcie->pexowar2 = 0;
  71         pcie->pexowar3 = 0;
  72         pcie->pexowar4 = 0;
  73         pcie->pexiwar1 = 0;
  74         pcie->pexiwar2 = 0;
  75         pcie->pexiwar3 = 0;
  76
  77         pcieow = (struct pcie_outbound_window_regs *)&pcie->pexotar1;
  78         pcieiw = (struct pcie_inbound_window_regs *)&pcie->pexitar1;
  79
  80         /* Setup outbound MEM window */
  81         for(i = 0; i < 3; i++)
  82                 if (hose->mem_resources[i].flags & IORESOURCE_MEM){
  83                         DBG("PCIE MEM resource start 0x%08x, size 0x%08x.\n",
  84                                 hose->mem_resources[i].start,
  85                                 hose->mem_resources[i].end
  86                                   - hose->mem_resources[i].start + 1);
  87                         pcieow->pexotar = (hose->mem_resources[i].start) >> 12
  88                                 & 0x000fffff;
  89                         pcieow->pexotear = 0;
  90                         pcieow->pexowbar = (hose->mem_resources[i].start) >> 12
  91                                 & 0x000fffff;
  92                         /* Enable, Mem R/W */
  93                         pcieow->pexowar = 0x80044000 |
  94                                 (__ilog2(hose->mem_resources[i].end
  95                                          - hose->mem_resources[i].start + 1)
  96                                  - 1);
  97                         pcieow++;
  98                 }
  99
 100         /* Setup outbound IO window */
 101         if (hose->io_resource.flags & IORESOURCE_IO){
 102                 DBG("PCIE IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n",
 103                         hose->io_resource.start,
 104                         hose->io_resource.end - hose->io_resource.start + 1,
 105                         hose->io_base_phys);
 106                 pcieow->pexotar = (hose->io_resource.start) >> 12 & 0x000fffff;
 107                 pcieow->pexotear = 0;
 108                 pcieow->pexowbar = (hose->io_base_phys) >> 12 & 0x000fffff;
 109                 /* Enable, IO R/W */
 110                 pcieow->pexowar = 0x80088000 | (__ilog2(hose->io_resource.end
 111                                         - hose->io_resource.start + 1) - 1);
 112         }
 113
 114         /* Setup 2G inbound Memory Window @ 0 */
 115         pcieiw->pexitar = 0x00000000;
 116         pcieiw->pexiwbar = 0x00000000;
 117         /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
 118         pcieiw->pexiwar = 0xa0f5501e;
 119 }
 120
 121 static void __init
 122 mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)
 123 {
 124         volatile struct ccsr_pex *pcie;
 125         u16 cmd;
 126         unsigned int temps;
 127
 128         DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n",
 129                         pcie_offset, pcie_size);
 130
 131         pcie = ioremap(pcie_offset, pcie_size);
 132
 133         early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
 134         cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
 135             | PCI_COMMAND_IO;
 136         early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
 137
 138         early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
 139
 140         /* PCIE Bus, Fix the MPC8641D host bridge's location to bus 0xFF. */
 141         early_read_config_dword(hose, 0, 0, PCI_PRIMARY_BUS, &temps);
 142         temps = (temps & 0xff000000) | (0xff) | (0x0 << 8) | (0xfe << 16);
 143         early_write_config_dword(hose, 0, 0, PCI_PRIMARY_BUS, temps);
 144 }
 145
 146 int __init add_bridge(struct device_node *dev)
 147 {
 148         int len;
 149         struct pci_controller *hose;
 150         struct resource rsrc;
 151         int *bus_range;
 152         int has_address = 0;
 153         int primary = 0;
 154
 155         DBG("Adding PCIE host bridge %s\n", dev->full_name);
 156
 157         /* Fetch host bridge registers address */
 158         has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
 159
 160         /* Get bus range if any */
 161         bus_range = (int *) get_property(dev, "bus-range", &len);
 162         if (bus_range == NULL || len < 2 * sizeof(int))
 163                 printk(KERN_WARNING "Can't get bus-range for %s, assume"
 164                        " bus 0\n", dev->full_name);
 165
 166         hose = pcibios_alloc_controller();
 167         if (!hose)
 168                 return -ENOMEM;
 169         hose->arch_data = dev;
 170         hose->set_cfg_type = 1;
 171
 172         /* last_busno = 0xfe cause by MPC8641 PCIE bug */
 173         hose->first_busno = bus_range ? bus_range[0] : 0x0;
 174         hose->last_busno = bus_range ? bus_range[1] : 0xfe;
 175
 176         setup_indirect_pcie(hose, rsrc.start, rsrc.start + 0x4);
 177
 178         /* Setup the PCIE host controller. */
 179         mpc86xx_setup_pcie(hose, rsrc.start, rsrc.end - rsrc.start + 1);
 180
 181         if ((rsrc.start & 0xfffff) == 0x8000)
 182                 primary = 1;
 183
 184         printk(KERN_INFO "Found MPC86xx PCIE host bridge at 0x%08lx. "
 185                "Firmware bus number: %d->%d\n",
 186                 rsrc.start, hose->first_busno, hose->last_busno);
 187
 188         DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
 189                 hose, hose->cfg_addr, hose->cfg_data);
 190
 191         /* Interpret the "ranges" property */
 192         /* This also maps the I/O region and sets isa_io/mem_base */
 193         pci_process_bridge_OF_ranges(hose, dev, primary);
 194
 195         /* Setup PEX window registers */
 196         setup_pcie_atmu(hose, &rsrc);
 197
 198         return 0;
 199 }
 200
 201 static void __devinit quirk_ali1575(struct pci_dev *dev)
 202 {
 203         unsigned short temp;
 204
 205         /*
 206          * ALI1575 interrupts route table setup:
 207          *
 208          * IRQ pin   IRQ#
 209          * PIRQA ---- 3
 210          * PIRQB ---- 4
 211          * PIRQC ---- 5
 212          * PIRQD ---- 6
 213          * PIRQE ---- 9
 214          * PIRQF ---- 10
 215          * PIRQG ---- 11
 216          * PIRQH ---- 12
 217          *
 218          * interrupts for PCI slot0 -- PIRQA / PIRQB / PIRQC / PIRQD
 219          *                PCI slot1 -- PIRQB / PIRQC / PIRQD / PIRQA
 220          */
 221         pci_write_config_dword(dev, 0x48, 0xb9317542);
 222
 223         /* USB 1.1 OHCI controller 1, interrupt: PIRQE */
 224         pci_write_config_byte(dev, 0x86, 0x0c);
 225
 226         /* USB 1.1 OHCI controller 2, interrupt: PIRQF */
 227         pci_write_config_byte(dev, 0x87, 0x0d);
 228
 229         /* USB 1.1 OHCI controller 3, interrupt: PIRQH */
 230         pci_write_config_byte(dev, 0x88, 0x0f);
 231
 232         /* USB 2.0 controller, interrupt: PIRQ7 */
 233         pci_write_config_byte(dev, 0x74, 0x06);
 234
 235         /* Audio controller, interrupt: PIRQE */
 236         pci_write_config_byte(dev, 0x8a, 0x0c);
 237
 238         /* Modem controller, interrupt: PIRQF */
 239         pci_write_config_byte(dev, 0x8b, 0x0d);
 240
 241         /* HD audio controller, interrupt: PIRQG */
 242         pci_write_config_byte(dev, 0x8c, 0x0e);
 243
 244         /* Serial ATA interrupt: PIRQD */
 245         pci_write_config_byte(dev, 0x8d, 0x0b);
 246
 247         /* SMB interrupt: PIRQH */
 248         pci_write_config_byte(dev, 0x8e, 0x0f);
 249
 250         /* PMU ACPI SCI interrupt: PIRQH */
 251         pci_write_config_byte(dev, 0x8f, 0x0f);
 252
 253         /* Primary PATA IDE IRQ: 14
 254          * Secondary PATA IDE IRQ: 15
 255          */
 256         pci_write_config_byte(dev, 0x44, 0x3d);
 257         pci_write_config_byte(dev, 0x75, 0x0f);
 258
 259         /* Set IRQ14 and IRQ15 to legacy IRQs */
 260         pci_read_config_word(dev, 0x46, &temp);
 261         temp |= 0xc000;
 262         pci_write_config_word(dev, 0x46, temp);
 263
 264         /* Set i8259 interrupt trigger
 265          * IRQ 3:  Level
 266          * IRQ 4:  Level
 267          * IRQ 5:  Level
 268          * IRQ 6:  Level
 269          * IRQ 7:  Level
 270          * IRQ 9:  Level
 271          * IRQ 10: Level
 272          * IRQ 11: Level
 273          * IRQ 12: Level
 274          * IRQ 14: Edge
 275          * IRQ 15: Edge
 276          */
 277         outb(0xfa, 0x4d0);
 278         outb(0x1e, 0x4d1);
 279 }
 280
 281 static void __devinit quirk_uli5288(struct pci_dev *dev)
 282 {
 283         unsigned char c;
 284
 285         pci_read_config_byte(dev,0x83,&c);
 286         c |= 0x80;
 287         pci_write_config_byte(dev, 0x83, c);
 288
 289         pci_write_config_byte(dev, 0x09, 0x01);
 290         pci_write_config_byte(dev, 0x0a, 0x06);
 291
 292         pci_read_config_byte(dev,0x83,&c);
 293         c &= 0x7f;
 294         pci_write_config_byte(dev, 0x83, c);
 295
 296         pci_read_config_byte(dev,0x84,&c);
 297         c |= 0x01;
 298         pci_write_config_byte(dev, 0x84, c);
 299 }
 300
 301 static void __devinit quirk_uli5229(struct pci_dev *dev)
 302 {
 303         unsigned short temp;
 304         pci_write_config_word(dev, 0x04, 0x0405);
 305         pci_read_config_word(dev, 0x4a, &temp);
 306         temp |= 0x1000;
 307         pci_write_config_word(dev, 0x4a, temp);
 308 }
 309
 310 static void __devinit early_uli5249(struct pci_dev *dev)
 311 {
 312         unsigned char temp;
 313         pci_write_config_word(dev, 0x04, 0x0007);
 314         pci_read_config_byte(dev, 0x7c, &temp);
 315         pci_write_config_byte(dev, 0x7c, 0x80);
 316         pci_write_config_byte(dev, 0x09, 0x01);
 317         pci_write_config_byte(dev, 0x7c, temp);
 318         dev->class |= 0x1;
 319 }
 320
 321 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_ali1575);
 322 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
 323 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
 324 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);