drivers/net/wireless/ath5k/eeprom.h

   1 /*
   2  * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
   3  * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
   4  *
   5  * Permission to use, copy, modify, and distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  *
  17  */
  18
  19 /*
  20  * Common ar5xxx EEPROM data offsets (set these on AR5K_EEPROM_BASE)
  21  */
  22 #define AR5K_EEPROM_MAGIC               0x003d  /* EEPROM Magic number */
  23 #define AR5K_EEPROM_MAGIC_VALUE         0x5aa5  /* Default - found on EEPROM */
  24 #define AR5K_EEPROM_MAGIC_5212          0x0000145c /* 5212 */
  25 #define AR5K_EEPROM_MAGIC_5211          0x0000145b /* 5211 */
  26 #define AR5K_EEPROM_MAGIC_5210          0x0000145a /* 5210 */
  27
  28 #define AR5K_EEPROM_REG_DOMAIN          0x00bf  /* EEPROM regdom */
  29 #define AR5K_EEPROM_CHECKSUM            0x00c0  /* EEPROM checksum */
  30 #define AR5K_EEPROM_INFO_BASE           0x00c0  /* EEPROM header */
  31 #define AR5K_EEPROM_INFO_MAX            (0x400 - AR5K_EEPROM_INFO_BASE)
  32 #define AR5K_EEPROM_INFO_CKSUM          0xffff
  33 #define AR5K_EEPROM_INFO(_n)            (AR5K_EEPROM_INFO_BASE + (_n))
  34
  35 #define AR5K_EEPROM_VERSION             AR5K_EEPROM_INFO(1)     /* EEPROM Version */
  36 #define AR5K_EEPROM_VERSION_3_0         0x3000  /* No idea what's going on before this version */
  37 #define AR5K_EEPROM_VERSION_3_1         0x3001  /* ob/db values for 2Ghz (ar5211_rfregs) */
  38 #define AR5K_EEPROM_VERSION_3_2         0x3002  /* different frequency representation (eeprom_bin2freq) */
  39 #define AR5K_EEPROM_VERSION_3_3         0x3003  /* offsets changed, has 32 CTLs (see below) and ee_false_detect (eeprom_read_modes) */
  40 #define AR5K_EEPROM_VERSION_3_4         0x3004  /* has ee_i_gain, ee_cck_ofdm_power_delta (eeprom_read_modes) */
  41 #define AR5K_EEPROM_VERSION_4_0         0x4000  /* has ee_misc, ee_cal_pier, ee_turbo_max_power and ee_xr_power (eeprom_init) */
  42 #define AR5K_EEPROM_VERSION_4_1         0x4001  /* has ee_margin_tx_rx (eeprom_init) */
  43 #define AR5K_EEPROM_VERSION_4_2         0x4002  /* has ee_cck_ofdm_gain_delta (eeprom_init) */
  44 #define AR5K_EEPROM_VERSION_4_3         0x4003  /* power calibration changes */
  45 #define AR5K_EEPROM_VERSION_4_4         0x4004
  46 #define AR5K_EEPROM_VERSION_4_5         0x4005
  47 #define AR5K_EEPROM_VERSION_4_6         0x4006  /* has ee_scaled_cck_delta */
  48 #define AR5K_EEPROM_VERSION_4_7         0x3007  /* 4007 ? */
  49 #define AR5K_EEPROM_VERSION_4_9         0x4009  /* EAR futureproofing */
  50 #define AR5K_EEPROM_VERSION_5_0         0x5000  /* Has 2413 PDADC calibration etc */
  51 #define AR5K_EEPROM_VERSION_5_1         0x5001  /* Has capability values */
  52 #define AR5K_EEPROM_VERSION_5_3         0x5003  /* Has spur mitigation tables */
  53
  54 #define AR5K_EEPROM_MODE_11A            0
  55 #define AR5K_EEPROM_MODE_11B            1
  56 #define AR5K_EEPROM_MODE_11G            2
  57
  58 #define AR5K_EEPROM_HDR                 AR5K_EEPROM_INFO(2)     /* Header that contains the device caps */
  59 #define AR5K_EEPROM_HDR_11A(_v)         (((_v) >> AR5K_EEPROM_MODE_11A) & 0x1)
  60 #define AR5K_EEPROM_HDR_11B(_v)         (((_v) >> AR5K_EEPROM_MODE_11B) & 0x1)
  61 #define AR5K_EEPROM_HDR_11G(_v)         (((_v) >> AR5K_EEPROM_MODE_11G) & 0x1)
  62 #define AR5K_EEPROM_HDR_T_2GHZ_DIS(_v)  (((_v) >> 3) & 0x1)     /* Disable turbo for 2Ghz (?) */
  63 #define AR5K_EEPROM_HDR_T_5GHZ_DBM(_v)  (((_v) >> 4) & 0x7f)    /* Max turbo power for a/XR mode (eeprom_init) */
  64 #define AR5K_EEPROM_HDR_DEVICE(_v)      (((_v) >> 11) & 0x7)
  65 #define AR5K_EEPROM_HDR_RFKILL(_v)      (((_v) >> 14) & 0x1)    /* Device has RFKill support */
  66 #define AR5K_EEPROM_HDR_T_5GHZ_DIS(_v)  (((_v) >> 15) & 0x1)    /* Disable turbo for 5Ghz */
  67
  68 #define AR5K_EEPROM_RFKILL_GPIO_SEL     0x0000001c
  69 #define AR5K_EEPROM_RFKILL_GPIO_SEL_S   2
  70 #define AR5K_EEPROM_RFKILL_POLARITY     0x00000002
  71 #define AR5K_EEPROM_RFKILL_POLARITY_S   1
  72
  73 /* Newer EEPROMs are using a different offset */
  74 #define AR5K_EEPROM_OFF(_v, _v3_0, _v3_3) \
  75         (((_v) >= AR5K_EEPROM_VERSION_3_3) ? _v3_3 : _v3_0)
  76
  77 #define AR5K_EEPROM_ANT_GAIN(_v)        AR5K_EEPROM_OFF(_v, 0x00c4, 0x00c3)
  78 #define AR5K_EEPROM_ANT_GAIN_5GHZ(_v)   ((s8)(((_v) >> 8) & 0xff))
  79 #define AR5K_EEPROM_ANT_GAIN_2GHZ(_v)   ((s8)((_v) & 0xff))
  80
  81 /* Misc values available since EEPROM 4.0 */
  82 #define AR5K_EEPROM_MISC0               AR5K_EEPROM_INFO(4)
  83 #define AR5K_EEPROM_EARSTART(_v)        ((_v) & 0xfff)
  84 #define AR5K_EEPROM_HDR_XR2_DIS(_v)     (((_v) >> 12) & 0x1)
  85 #define AR5K_EEPROM_HDR_XR5_DIS(_v)     (((_v) >> 13) & 0x1)
  86 #define AR5K_EEPROM_EEMAP(_v)           (((_v) >> 14) & 0x3)
  87
  88 #define AR5K_EEPROM_MISC1                       AR5K_EEPROM_INFO(5)
  89 #define AR5K_EEPROM_TARGET_PWRSTART(_v)         ((_v) & 0xfff)
  90 #define AR5K_EEPROM_HAS32KHZCRYSTAL(_v)         (((_v) >> 14) & 0x1)
  91 #define AR5K_EEPROM_HAS32KHZCRYSTAL_OLD(_v)     (((_v) >> 15) & 0x1)
  92
  93 #define AR5K_EEPROM_MISC2                       AR5K_EEPROM_INFO(6)
  94 #define AR5K_EEPROM_EEP_FILE_VERSION(_v)        (((_v) >> 8) & 0xff)
  95 #define AR5K_EEPROM_EAR_FILE_VERSION(_v)        ((_v) & 0xff)
  96
  97 #define AR5K_EEPROM_MISC3               AR5K_EEPROM_INFO(7)
  98 #define AR5K_EEPROM_ART_BUILD_NUM(_v)   (((_v) >> 10) & 0x3f)
  99 #define AR5K_EEPROM_EAR_FILE_ID(_v)     ((_v) & 0xff)
 100
 101 #define AR5K_EEPROM_MISC4               AR5K_EEPROM_INFO(8)
 102 #define AR5K_EEPROM_CAL_DATA_START(_v)  (((_v) >> 4) & 0xfff)
 103 #define AR5K_EEPROM_MASK_R0(_v)         (((_v) >> 2) & 0x3)
 104 #define AR5K_EEPROM_MASK_R1(_v)         ((_v) & 0x3)
 105
 106 #define AR5K_EEPROM_MISC5               AR5K_EEPROM_INFO(9)
 107 #define AR5K_EEPROM_COMP_DIS(_v)        ((_v) & 0x1)
 108 #define AR5K_EEPROM_AES_DIS(_v)         (((_v) >> 1) & 0x1)
 109 #define AR5K_EEPROM_FF_DIS(_v)          (((_v) >> 2) & 0x1)
 110 #define AR5K_EEPROM_BURST_DIS(_v)       (((_v) >> 3) & 0x1)
 111 #define AR5K_EEPROM_MAX_QCU(_v)         (((_v) >> 4) & 0xf)
 112 #define AR5K_EEPROM_HEAVY_CLIP_EN(_v)   (((_v) >> 8) & 0x1)
 113 #define AR5K_EEPROM_KEY_CACHE_SIZE(_v)  (((_v) >> 12) & 0xf)
 114
 115 #define AR5K_EEPROM_MISC6               AR5K_EEPROM_INFO(10)
 116 #define AR5K_EEPROM_TX_CHAIN_DIS        ((_v) & 0x8)
 117 #define AR5K_EEPROM_RX_CHAIN_DIS        (((_v) >> 3) & 0x8)
 118 #define AR5K_EEPROM_FCC_MID_EN          (((_v) >> 6) & 0x1)
 119 #define AR5K_EEPROM_JAP_U1EVEN_EN       (((_v) >> 7) & 0x1)
 120 #define AR5K_EEPROM_JAP_U2_EN           (((_v) >> 8) & 0x1)
 121 #define AR5K_EEPROM_JAP_U1ODD_EN        (((_v) >> 9) & 0x1)
 122 #define AR5K_EEPROM_JAP_11A_NEW_EN      (((_v) >> 10) & 0x1)
 123
 124 /* calibration settings */
 125 #define AR5K_EEPROM_MODES_11A(_v)       AR5K_EEPROM_OFF(_v, 0x00c5, 0x00d4)
 126 #define AR5K_EEPROM_MODES_11B(_v)       AR5K_EEPROM_OFF(_v, 0x00d0, 0x00f2)
 127 #define AR5K_EEPROM_MODES_11G(_v)       AR5K_EEPROM_OFF(_v, 0x00da, 0x010d)
 128 #define AR5K_EEPROM_CTL(_v)             AR5K_EEPROM_OFF(_v, 0x00e4, 0x0128)     /* Conformance test limits */
 129 #define AR5K_EEPROM_GROUPS_START(_v)    AR5K_EEPROM_OFF(_v, 0x0100, 0x0150)     /* Start of Groups */
 130 #define AR5K_EEPROM_GROUP1_OFFSET       0x0
 131 #define AR5K_EEPROM_GROUP2_OFFSET       0x5
 132 #define AR5K_EEPROM_GROUP3_OFFSET       0x37
 133 #define AR5K_EEPROM_GROUP4_OFFSET       0x46
 134 #define AR5K_EEPROM_GROUP5_OFFSET       0x55
 135 #define AR5K_EEPROM_GROUP6_OFFSET       0x65
 136 #define AR5K_EEPROM_GROUP7_OFFSET       0x69
 137 #define AR5K_EEPROM_GROUP8_OFFSET       0x6f
 138
 139 #define AR5K_EEPROM_TARGET_PWR_OFF_11A(_v)      AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \
 140                                                                 AR5K_EEPROM_GROUP5_OFFSET, 0x0000)
 141 #define AR5K_EEPROM_TARGET_PWR_OFF_11B(_v)      AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \
 142                                                                 AR5K_EEPROM_GROUP6_OFFSET, 0x0010)
 143 #define AR5K_EEPROM_TARGET_PWR_OFF_11G(_v)      AR5K_EEPROM_OFF(_v, AR5K_EEPROM_GROUPS_START(_v) + \
 144                                                                 AR5K_EEPROM_GROUP7_OFFSET, 0x0014)
 145
 146 /* [3.1 - 3.3] */
 147 #define AR5K_EEPROM_OBDB0_2GHZ          0x00ec
 148 #define AR5K_EEPROM_OBDB1_2GHZ          0x00ed
 149
 150 #define AR5K_EEPROM_PROTECT             0x003f  /* EEPROM protect status */
 151 #define AR5K_EEPROM_PROTECT_RD_0_31     0x0001  /* Read protection bit for offsets 0x0 - 0x1f */
 152 #define AR5K_EEPROM_PROTECT_WR_0_31     0x0002  /* Write protection bit for offsets 0x0 - 0x1f */
 153 #define AR5K_EEPROM_PROTECT_RD_32_63    0x0004  /* 0x20 - 0x3f */
 154 #define AR5K_EEPROM_PROTECT_WR_32_63    0x0008
 155 #define AR5K_EEPROM_PROTECT_RD_64_127   0x0010  /* 0x40 - 0x7f */
 156 #define AR5K_EEPROM_PROTECT_WR_64_127   0x0020
 157 #define AR5K_EEPROM_PROTECT_RD_128_191  0x0040  /* 0x80 - 0xbf (regdom) */
 158 #define AR5K_EEPROM_PROTECT_WR_128_191  0x0080
 159 #define AR5K_EEPROM_PROTECT_RD_192_207  0x0100  /* 0xc0 - 0xcf */
 160 #define AR5K_EEPROM_PROTECT_WR_192_207  0x0200
 161 #define AR5K_EEPROM_PROTECT_RD_208_223  0x0400  /* 0xd0 - 0xdf */
 162 #define AR5K_EEPROM_PROTECT_WR_208_223  0x0800
 163 #define AR5K_EEPROM_PROTECT_RD_224_239  0x1000  /* 0xe0 - 0xef */
 164 #define AR5K_EEPROM_PROTECT_WR_224_239  0x2000
 165 #define AR5K_EEPROM_PROTECT_RD_240_255  0x4000  /* 0xf0 - 0xff */
 166 #define AR5K_EEPROM_PROTECT_WR_240_255  0x8000
 167
 168 /* Some EEPROM defines */
 169 #define AR5K_EEPROM_EEP_SCALE           100
 170 #define AR5K_EEPROM_EEP_DELTA           10
 171 #define AR5K_EEPROM_N_MODES             3
 172 #define AR5K_EEPROM_N_5GHZ_CHAN         10
 173 #define AR5K_EEPROM_N_2GHZ_CHAN         3
 174 #define AR5K_EEPROM_N_2GHZ_CHAN_2413    4
 175 #define AR5K_EEPROM_MAX_CHAN            10
 176 #define AR5K_EEPROM_N_PWR_POINTS_5111   11
 177 #define AR5K_EEPROM_N_PCDAC             11
 178 #define AR5K_EEPROM_N_PHASE_CAL         5
 179 #define AR5K_EEPROM_N_TEST_FREQ         8
 180 #define AR5K_EEPROM_N_EDGES             8
 181 #define AR5K_EEPROM_N_INTERCEPTS        11
 182 #define AR5K_EEPROM_FREQ_M(_v)          AR5K_EEPROM_OFF(_v, 0x7f, 0xff)
 183 #define AR5K_EEPROM_PCDAC_M             0x3f
 184 #define AR5K_EEPROM_PCDAC_START         1
 185 #define AR5K_EEPROM_PCDAC_STOP          63
 186 #define AR5K_EEPROM_PCDAC_STEP          1
 187 #define AR5K_EEPROM_NON_EDGE_M          0x40
 188 #define AR5K_EEPROM_CHANNEL_POWER       8
 189 #define AR5K_EEPROM_N_OBDB              4
 190 #define AR5K_EEPROM_OBDB_DIS            0xffff
 191 #define AR5K_EEPROM_CHANNEL_DIS         0xff
 192 #define AR5K_EEPROM_SCALE_OC_DELTA(_x)  (((_x) * 2) / 10)
 193 #define AR5K_EEPROM_N_CTLS(_v)          AR5K_EEPROM_OFF(_v, 16, 32)
 194 #define AR5K_EEPROM_MAX_CTLS            32
 195 #define AR5K_EEPROM_N_XPD_PER_CHANNEL   4
 196 #define AR5K_EEPROM_N_XPD0_POINTS       4
 197 #define AR5K_EEPROM_N_XPD3_POINTS       3
 198 #define AR5K_EEPROM_N_PD_GAINS          4
 199 #define AR5K_EEPROM_N_PD_POINTS         5
 200 #define AR5K_EEPROM_N_INTERCEPT_10_2GHZ 35
 201 #define AR5K_EEPROM_N_INTERCEPT_10_5GHZ 55
 202 #define AR5K_EEPROM_POWER_M             0x3f
 203 #define AR5K_EEPROM_POWER_MIN           0
 204 #define AR5K_EEPROM_POWER_MAX           3150
 205 #define AR5K_EEPROM_POWER_STEP          50
 206 #define AR5K_EEPROM_POWER_TABLE_SIZE    64
 207 #define AR5K_EEPROM_N_POWER_LOC_11B     4
 208 #define AR5K_EEPROM_N_POWER_LOC_11G     6
 209 #define AR5K_EEPROM_I_GAIN              10
 210 #define AR5K_EEPROM_CCK_OFDM_DELTA      15
 211 #define AR5K_EEPROM_N_IQ_CAL            2
 212
 213 #define AR5K_EEPROM_READ(_o, _v) do {                   \
 214         ret = ath5k_hw_eeprom_read(ah, (_o), &(_v));    \
 215         if (ret)                                        \
 216                 return ret;                             \
 217 } while (0)
 218
 219 #define AR5K_EEPROM_READ_HDR(_o, _v)                                    \
 220         AR5K_EEPROM_READ(_o, ah->ah_capabilities.cap_eeprom._v);        \
 221
 222 enum ath5k_ant_setting {
 223         AR5K_ANT_VARIABLE       = 0,    /* variable by programming */
 224         AR5K_ANT_FIXED_A        = 1,    /* fixed to 11a frequencies */
 225         AR5K_ANT_FIXED_B        = 2,    /* fixed to 11b frequencies */
 226         AR5K_ANT_MAX            = 3,
 227 };
 228
 229 enum ath5k_ctl_mode {
 230         AR5K_CTL_11A = 0,
 231         AR5K_CTL_11B = 1,
 232         AR5K_CTL_11G = 2,
 233         AR5K_CTL_TURBO = 3,
 234         AR5K_CTL_108G = 4,
 235         AR5K_CTL_2GHT20 = 5,
 236         AR5K_CTL_5GHT20 = 6,
 237         AR5K_CTL_2GHT40 = 7,
 238         AR5K_CTL_5GHT40 = 8,
 239         AR5K_CTL_MODE_M = 15,
 240 };
 241
 242 /* Per channel calibration data, used for power table setup */
 243 struct ath5k_chan_pcal_info_rf5111 {
 244         /* Power levels in half dbm units
 245          * for one power curve. */
 246         u8              pwr[AR5K_EEPROM_N_PWR_POINTS_5111];
 247         /* PCDAC table steps
 248          * for the above values */
 249         u8              pcdac[AR5K_EEPROM_N_PWR_POINTS_5111];
 250         /* Starting PCDAC step */
 251         u8              pcdac_min;
 252         /* Final PCDAC step */
 253         u8              pcdac_max;
 254 };
 255
 256 struct ath5k_chan_pcal_info_rf5112 {
 257         /* Power levels in quarter dBm units
 258          * for lower (0) and higher (3)
 259          * level curves */
 260         s8              pwr_x0[AR5K_EEPROM_N_XPD0_POINTS];
 261         s8              pwr_x3[AR5K_EEPROM_N_XPD3_POINTS];
 262         /* PCDAC table steps
 263          * for the above values */
 264         u8      pcdac_x0[AR5K_EEPROM_N_XPD0_POINTS];
 265         u8      pcdac_x3[AR5K_EEPROM_N_XPD3_POINTS];
 266 };
 267
 268 struct ath5k_chan_pcal_info_rf2413 {
 269         /* Starting pwr/pddac values */
 270         s8              pwr_i[AR5K_EEPROM_N_PD_GAINS];
 271         u8      pddac_i[AR5K_EEPROM_N_PD_GAINS];
 272         /* (pwr,pddac) points */
 273         s8              pwr[AR5K_EEPROM_N_PD_GAINS]
 274                                 [AR5K_EEPROM_N_PD_POINTS];
 275         u8      pddac[AR5K_EEPROM_N_PD_GAINS]
 276                                 [AR5K_EEPROM_N_PD_POINTS];
 277 };
 278
 279 struct ath5k_chan_pcal_info {
 280         /* Frequency */
 281         u16     freq;
 282         /* Max available power */
 283         s8              max_pwr;
 284         union {
 285                 struct ath5k_chan_pcal_info_rf5111 rf5111_info;
 286                 struct ath5k_chan_pcal_info_rf5112 rf5112_info;
 287                 struct ath5k_chan_pcal_info_rf2413 rf2413_info;
 288         };
 289 };
 290
 291 /* Per rate calibration data for each mode, used for power table setup */
 292 struct ath5k_rate_pcal_info {
 293         u16     freq; /* Frequency */
 294         /* Power level for 6-24Mbit/s rates */
 295         u16     target_power_6to24;
 296         /* Power level for 36Mbit rate */
 297         u16     target_power_36;
 298         /* Power level for 48Mbit rate */
 299         u16     target_power_48;
 300         /* Power level for 54Mbit rate */
 301         u16     target_power_54;
 302 };
 303
 304 /* Power edges for conformance test limits */
 305 struct ath5k_edge_power {
 306         u16 freq;
 307         u16 edge; /* in half dBm */
 308         bool flag;
 309 };
 310
 311 /* EEPROM calibration data */
 312 struct ath5k_eeprom_info {
 313
 314         /* Header information */
 315         u16     ee_magic;
 316         u16     ee_protect;
 317         u16     ee_regdomain;
 318         u16     ee_version;
 319         u16     ee_header;
 320         u16     ee_ant_gain;
 321         u16     ee_misc0;
 322         u16     ee_misc1;
 323         u16     ee_misc2;
 324         u16     ee_misc3;
 325         u16     ee_misc4;
 326         u16     ee_misc5;
 327         u16     ee_misc6;
 328         u16     ee_cck_ofdm_gain_delta;
 329         u16     ee_cck_ofdm_power_delta;
 330         u16     ee_scaled_cck_delta;
 331
 332         /* Used for tx thermal adjustment (eeprom_init, rfregs) */
 333         u16     ee_tx_clip;
 334         u16     ee_pwd_84;
 335         u16     ee_pwd_90;
 336         u16     ee_gain_select;
 337
 338         /* RF Calibration settings (reset, rfregs) */
 339         u16     ee_i_cal[AR5K_EEPROM_N_MODES];
 340         u16     ee_q_cal[AR5K_EEPROM_N_MODES];
 341         u16     ee_fixed_bias[AR5K_EEPROM_N_MODES];
 342         u16     ee_turbo_max_power[AR5K_EEPROM_N_MODES];
 343         u16     ee_xr_power[AR5K_EEPROM_N_MODES];
 344         u16     ee_switch_settling[AR5K_EEPROM_N_MODES];
 345         u16     ee_atn_tx_rx[AR5K_EEPROM_N_MODES];
 346         u16     ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC];
 347         u16     ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
 348         u16     ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
 349         u16     ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES];
 350         u16     ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES];
 351         u16     ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES];
 352         u16     ee_thr_62[AR5K_EEPROM_N_MODES];
 353         u16     ee_xlna_gain[AR5K_EEPROM_N_MODES];
 354         u16     ee_xpd[AR5K_EEPROM_N_MODES];
 355         u16     ee_x_gain[AR5K_EEPROM_N_MODES];
 356         u16     ee_i_gain[AR5K_EEPROM_N_MODES];
 357         u16     ee_margin_tx_rx[AR5K_EEPROM_N_MODES];
 358         u16     ee_switch_settling_turbo[AR5K_EEPROM_N_MODES];
 359         u16     ee_margin_tx_rx_turbo[AR5K_EEPROM_N_MODES];
 360         u16     ee_atn_tx_rx_turbo[AR5K_EEPROM_N_MODES];
 361
 362         /* Power calibration data */
 363         u16     ee_false_detect[AR5K_EEPROM_N_MODES];
 364
 365         /* Number of pd gain curves per mode (RF2413) */
 366         u8 ee_pd_gains[AR5K_EEPROM_N_MODES];
 367
 368         u8 ee_n_piers[AR5K_EEPROM_N_MODES];
 369         struct ath5k_chan_pcal_info     ee_pwr_cal_a[AR5K_EEPROM_N_5GHZ_CHAN];
 370         struct ath5k_chan_pcal_info     ee_pwr_cal_b[AR5K_EEPROM_N_2GHZ_CHAN];
 371         struct ath5k_chan_pcal_info     ee_pwr_cal_g[AR5K_EEPROM_N_2GHZ_CHAN];
 372
 373         /* Per rate target power levels */
 374         u16     ee_rate_target_pwr_num[AR5K_EEPROM_N_MODES];
 375         struct ath5k_rate_pcal_info     ee_rate_tpwr_a[AR5K_EEPROM_N_5GHZ_CHAN];
 376         struct ath5k_rate_pcal_info     ee_rate_tpwr_b[AR5K_EEPROM_N_2GHZ_CHAN];
 377         struct ath5k_rate_pcal_info     ee_rate_tpwr_g[AR5K_EEPROM_N_2GHZ_CHAN];
 378
 379         /* Conformance test limits (Unused) */
 380         u16     ee_ctls;
 381         u16     ee_ctl[AR5K_EEPROM_MAX_CTLS];
 382         struct ath5k_edge_power ee_ctl_pwr[AR5K_EEPROM_N_EDGES * AR5K_EEPROM_MAX_CTLS];
 383
 384         /* Noise Floor Calibration settings */
 385         s16     ee_noise_floor_thr[AR5K_EEPROM_N_MODES];
 386         s8      ee_adc_desired_size[AR5K_EEPROM_N_MODES];
 387         s8      ee_pga_desired_size[AR5K_EEPROM_N_MODES];
 388         s8      ee_adc_desired_size_turbo[AR5K_EEPROM_N_MODES];
 389         s8      ee_pga_desired_size_turbo[AR5K_EEPROM_N_MODES];
 390         s8      ee_pd_gain_overlap;
 391
 392         u32     ee_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
 393 };
 394