arch/x86_64/kernel/pci-gart.c

   1 /*
   2  * Dynamic DMA mapping support for AMD Hammer.
   3  *
   4  * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI.
   5  * This allows to use PCI devices that only support 32bit addresses on systems
   6  * with more than 4GB.
   7  *
   8  * See Documentation/DMA-mapping.txt for the interface specification.
   9  *
  10  * Copyright 2002 Andi Kleen, SuSE Labs.
  11  */
  12
  13 #include <linux/types.h>
  14 #include <linux/ctype.h>
  15 #include <linux/agp_backend.h>
  16 #include <linux/init.h>
  17 #include <linux/mm.h>
  18 #include <linux/string.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/pci.h>
  21 #include <linux/module.h>
  22 #include <linux/topology.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/bitops.h>
  25 #include <asm/atomic.h>
  26 #include <asm/io.h>
  27 #include <asm/mtrr.h>
  28 #include <asm/pgtable.h>
  29 #include <asm/proto.h>
  30 #include <asm/cacheflush.h>
  31 #include <asm/kdebug.h>
  32 #include <asm/swiotlb.h>
  33 #include <asm/dma.h>
  34 #include <asm/k8.h>
  35
  36 unsigned long iommu_bus_base;   /* GART remapping area (physical) */
  37 static unsigned long iommu_size;        /* size of remapping area bytes */
  38 static unsigned long iommu_pages;       /* .. and in pages */
  39
  40 u32 *iommu_gatt_base;           /* Remapping table */
  41
  42 /* If this is disabled the IOMMU will use an optimized flushing strategy
  43    of only flushing when an mapping is reused. With it true the GART is flushed
  44    for every mapping. Problem is that doing the lazy flush seems to trigger
  45    bugs with some popular PCI cards, in particular 3ware (but has been also
  46    also seen with Qlogic at least). */
  47 int iommu_fullflush = 1;
  48
  49 /* Allocation bitmap for the remapping area */
  50 static DEFINE_SPINLOCK(iommu_bitmap_lock);
  51 static unsigned long *iommu_gart_bitmap; /* guarded by iommu_bitmap_lock */
  52
  53 static u32 gart_unmapped_entry;
  54
  55 #define GPTE_VALID    1
  56 #define GPTE_COHERENT 2
  57 #define GPTE_ENCODE(x) \
  58         (((x) & 0xfffff000) | (((x) >> 32) << 4) | GPTE_VALID | GPTE_COHERENT)
  59 #define GPTE_DECODE(x) (((x) & 0xfffff000) | (((u64)(x) & 0xff0) << 28))
  60
  61 #define to_pages(addr,size) \
  62         (round_up(((addr) & ~PAGE_MASK) + (size), PAGE_SIZE) >> PAGE_SHIFT)
  63
  64 #define EMERGENCY_PAGES 32 /* = 128KB */
  65
  66 #ifdef CONFIG_AGP
  67 #define AGPEXTERN extern
  68 #else
  69 #define AGPEXTERN
  70 #endif
  71
  72 /* backdoor interface to AGP driver */
  73 AGPEXTERN int agp_memory_reserved;
  74 AGPEXTERN __u32 *agp_gatt_table;
  75
  76 static unsigned long next_bit;  /* protected by iommu_bitmap_lock */
  77 static int need_flush;          /* global flush state. set for each gart wrap */
  78
  79 static unsigned long alloc_iommu(int size)
  80 {
  81         unsigned long offset, flags;
  82
  83         spin_lock_irqsave(&iommu_bitmap_lock, flags);
  84         offset = find_next_zero_string(iommu_gart_bitmap,next_bit,iommu_pages,size);
  85         if (offset == -1) {
  86                 need_flush = 1;
  87                 offset = find_next_zero_string(iommu_gart_bitmap,0,iommu_pages,size);
  88         }
  89         if (offset != -1) {
  90                 set_bit_string(iommu_gart_bitmap, offset, size);
  91                 next_bit = offset+size;
  92                 if (next_bit >= iommu_pages) {
  93                         next_bit = 0;
  94                         need_flush = 1;
  95                 }
  96         }
  97         if (iommu_fullflush)
  98                 need_flush = 1;
  99         spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
 100         return offset;
 101 }
 102
 103 static void free_iommu(unsigned long offset, int size)
 104 {
 105         unsigned long flags;
 106         spin_lock_irqsave(&iommu_bitmap_lock, flags);
 107         __clear_bit_string(iommu_gart_bitmap, offset, size);
 108         spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
 109 }
 110
 111 /*
 112  * Use global flush state to avoid races with multiple flushers.
 113  */
 114 static void flush_gart(void)
 115 {
 116         unsigned long flags;
 117         spin_lock_irqsave(&iommu_bitmap_lock, flags);
 118         if (need_flush) {
 119                 k8_flush_garts();
 120                 need_flush = 0;
 121         }
 122         spin_unlock_irqrestore(&iommu_bitmap_lock, flags);
 123 }
 124
 125 #ifdef CONFIG_IOMMU_LEAK
 126
 127 #define SET_LEAK(x) if (iommu_leak_tab) \
 128                         iommu_leak_tab[x] = __builtin_return_address(0);
 129 #define CLEAR_LEAK(x) if (iommu_leak_tab) \
 130                         iommu_leak_tab[x] = NULL;
 131
 132 /* Debugging aid for drivers that don't free their IOMMU tables */
 133 static void **iommu_leak_tab;
 134 static int leak_trace;
 135 int iommu_leak_pages = 20;
 136 void dump_leak(void)
 137 {
 138         int i;
 139         static int dump;
 140         if (dump || !iommu_leak_tab) return;
 141         dump = 1;
 142         show_stack(NULL,NULL);
 143         /* Very crude. dump some from the end of the table too */
 144         printk("Dumping %d pages from end of IOMMU:\n", iommu_leak_pages);
 145         for (i = 0; i < iommu_leak_pages; i+=2) {
 146                 printk("%lu: ", iommu_pages-i);
 147                 printk_address((unsigned long) iommu_leak_tab[iommu_pages-i]);
 148                 printk("%c", (i+1)%2 == 0 ? '\n' : ' ');
 149         }
 150         printk("\n");
 151 }
 152 #else
 153 #define SET_LEAK(x)
 154 #define CLEAR_LEAK(x)
 155 #endif
 156
 157 static void iommu_full(struct device *dev, size_t size, int dir)
 158 {
 159         /*
 160          * Ran out of IOMMU space for this operation. This is very bad.
 161          * Unfortunately the drivers cannot handle this operation properly.
 162          * Return some non mapped prereserved space in the aperture and
 163          * let the Northbridge deal with it. This will result in garbage
 164          * in the IO operation. When the size exceeds the prereserved space
 165          * memory corruption will occur or random memory will be DMAed
 166          * out. Hopefully no network devices use single mappings that big.
 167          */
 168
 169         printk(KERN_ERR
 170   "PCI-DMA: Out of IOMMU space for %lu bytes at device %s\n",
 171                size, dev->bus_id);
 172
 173         if (size > PAGE_SIZE*EMERGENCY_PAGES) {
 174                 if (dir == PCI_DMA_FROMDEVICE || dir == PCI_DMA_BIDIRECTIONAL)
 175                         panic("PCI-DMA: Memory would be corrupted\n");
 176                 if (dir == PCI_DMA_TODEVICE || dir == PCI_DMA_BIDIRECTIONAL)
 177                         panic(KERN_ERR "PCI-DMA: Random memory would be DMAed\n");
 178         }
 179
 180 #ifdef CONFIG_IOMMU_LEAK
 181         dump_leak();
 182 #endif
 183 }
 184
 185 static inline int need_iommu(struct device *dev, unsigned long addr, size_t size)
 186 {
 187         u64 mask = *dev->dma_mask;
 188         int high = addr + size >= mask;
 189         int mmu = high;
 190         if (force_iommu)
 191                 mmu = 1;
 192         return mmu;
 193 }
 194
 195 static inline int nonforced_iommu(struct device *dev, unsigned long addr, size_t size)
 196 {
 197         u64 mask = *dev->dma_mask;
 198         int high = addr + size >= mask;
 199         int mmu = high;
 200         return mmu;
 201 }
 202
 203 /* Map a single continuous physical area into the IOMMU.
 204  * Caller needs to check if the iommu is needed and flush.
 205  */
 206 static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem,
 207                                 size_t size, int dir)
 208 {
 209         unsigned long npages = to_pages(phys_mem, size);
 210         unsigned long iommu_page = alloc_iommu(npages);
 211         int i;
 212         if (iommu_page == -1) {
 213                 if (!nonforced_iommu(dev, phys_mem, size))
 214                         return phys_mem;
 215                 if (panic_on_overflow)
 216                         panic("dma_map_area overflow %lu bytes\n", size);
 217                 iommu_full(dev, size, dir);
 218                 return bad_dma_address;
 219         }
 220
 221         for (i = 0; i < npages; i++) {
 222                 iommu_gatt_base[iommu_page + i] = GPTE_ENCODE(phys_mem);
 223                 SET_LEAK(iommu_page + i);
 224                 phys_mem += PAGE_SIZE;
 225         }
 226         return iommu_bus_base + iommu_page*PAGE_SIZE + (phys_mem & ~PAGE_MASK);
 227 }
 228
 229 static dma_addr_t gart_map_simple(struct device *dev, char *buf,
 230                                  size_t size, int dir)
 231 {
 232         dma_addr_t map = dma_map_area(dev, virt_to_bus(buf), size, dir);
 233         flush_gart();
 234         return map;
 235 }
 236
 237 /* Map a single area into the IOMMU */
 238 dma_addr_t gart_map_single(struct device *dev, void *addr, size_t size, int dir)
 239 {
 240         unsigned long phys_mem, bus;
 241
 242         BUG_ON(dir == DMA_NONE);
 243
 244         if (!dev)
 245                 dev = &fallback_dev;
 246
 247         phys_mem = virt_to_phys(addr);
 248         if (!need_iommu(dev, phys_mem, size))
 249                 return phys_mem;
 250
 251         bus = gart_map_simple(dev, addr, size, dir);
 252         return bus;
 253 }
 254
 255 /*
 256  * Free a DMA mapping.
 257  */
 258 void gart_unmap_single(struct device *dev, dma_addr_t dma_addr,
 259                       size_t size, int direction)
 260 {
 261         unsigned long iommu_page;
 262         int npages;
 263         int i;
 264
 265         if (dma_addr < iommu_bus_base + EMERGENCY_PAGES*PAGE_SIZE ||
 266             dma_addr >= iommu_bus_base + iommu_size)
 267                 return;
 268         iommu_page = (dma_addr - iommu_bus_base)>>PAGE_SHIFT;
 269         npages = to_pages(dma_addr, size);
 270         for (i = 0; i < npages; i++) {
 271                 iommu_gatt_base[iommu_page + i] = gart_unmapped_entry;
 272                 CLEAR_LEAK(iommu_page + i);
 273         }
 274         free_iommu(iommu_page, npages);
 275 }
 276
 277 /*
 278  * Wrapper for pci_unmap_single working with scatterlists.
 279  */
 280 void gart_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, int dir)
 281 {
 282         int i;
 283
 284         for (i = 0; i < nents; i++) {
 285                 struct scatterlist *s = &sg[i];
 286                 if (!s->dma_length || !s->length)
 287                         break;
 288                 gart_unmap_single(dev, s->dma_address, s->dma_length, dir);
 289         }
 290 }
 291
 292 /* Fallback for dma_map_sg in case of overflow */
 293 static int dma_map_sg_nonforce(struct device *dev, struct scatterlist *sg,
 294                                int nents, int dir)
 295 {
 296         int i;
 297
 298 #ifdef CONFIG_IOMMU_DEBUG
 299         printk(KERN_DEBUG "dma_map_sg overflow\n");
 300 #endif
 301
 302         for (i = 0; i < nents; i++ ) {
 303                 struct scatterlist *s = &sg[i];
 304                 unsigned long addr = page_to_phys(s->page) + s->offset;
 305                 if (nonforced_iommu(dev, addr, s->length)) {
 306                         addr = dma_map_area(dev, addr, s->length, dir);
 307                         if (addr == bad_dma_address) {
 308                                 if (i > 0)
 309                                         gart_unmap_sg(dev, sg, i, dir);
 310                                 nents = 0;
 311                                 sg[0].dma_length = 0;
 312                                 break;
 313                         }
 314                 }
 315                 s->dma_address = addr;
 316                 s->dma_length = s->length;
 317         }
 318         flush_gart();
 319         return nents;
 320 }
 321
 322 /* Map multiple scatterlist entries continuous into the first. */
 323 static int __dma_map_cont(struct scatterlist *sg, int start, int stopat,
 324                       struct scatterlist *sout, unsigned long pages)
 325 {
 326         unsigned long iommu_start = alloc_iommu(pages);
 327         unsigned long iommu_page = iommu_start;
 328         int i;
 329
 330         if (iommu_start == -1)
 331                 return -1;
 332
 333         for (i = start; i < stopat; i++) {
 334                 struct scatterlist *s = &sg[i];
 335                 unsigned long pages, addr;
 336                 unsigned long phys_addr = s->dma_address;
 337
 338                 BUG_ON(i > start && s->offset);
 339                 if (i == start) {
 340                         *sout = *s;
 341                         sout->dma_address = iommu_bus_base;
 342                         sout->dma_address += iommu_page*PAGE_SIZE + s->offset;
 343                         sout->dma_length = s->length;
 344                 } else {
 345                         sout->dma_length += s->length;
 346                 }
 347
 348                 addr = phys_addr;
 349                 pages = to_pages(s->offset, s->length);
 350                 while (pages--) {
 351                         iommu_gatt_base[iommu_page] = GPTE_ENCODE(addr);
 352                         SET_LEAK(iommu_page);
 353                         addr += PAGE_SIZE;
 354                         iommu_page++;
 355                 }
 356         }
 357         BUG_ON(iommu_page - iommu_start != pages);
 358         return 0;
 359 }
 360
 361 static inline int dma_map_cont(struct scatterlist *sg, int start, int stopat,
 362                       struct scatterlist *sout,
 363                       unsigned long pages, int need)
 364 {
 365         if (!need) {
 366                 BUG_ON(stopat - start != 1);
 367                 *sout = sg[start];
 368                 sout->dma_length = sg[start].length;
 369                 return 0;
 370         }
 371         return __dma_map_cont(sg, start, stopat, sout, pages);
 372 }
 373
 374 /*
 375  * DMA map all entries in a scatterlist.
 376  * Merge chunks that have page aligned sizes into a continuous mapping.
 377  */
 378 int gart_map_sg(struct device *dev, struct scatterlist *sg, int nents, int dir)
 379 {
 380         int i;
 381         int out;
 382         int start;
 383         unsigned long pages = 0;
 384         int need = 0, nextneed;
 385
 386         BUG_ON(dir == DMA_NONE);
 387         if (nents == 0)
 388                 return 0;
 389
 390         if (!dev)
 391                 dev = &fallback_dev;
 392
 393         out = 0;
 394         start = 0;
 395         for (i = 0; i < nents; i++) {
 396                 struct scatterlist *s = &sg[i];
 397                 dma_addr_t addr = page_to_phys(s->page) + s->offset;
 398                 s->dma_address = addr;
 399                 BUG_ON(s->length == 0);
 400
 401                 nextneed = need_iommu(dev, addr, s->length);
 402
 403                 /* Handle the previous not yet processed entries */
 404                 if (i > start) {
 405                         struct scatterlist *ps = &sg[i-1];
 406                         /* Can only merge when the last chunk ends on a page
 407                            boundary and the new one doesn't have an offset. */
 408                         if (!iommu_merge || !nextneed || !need || s->offset ||
 409                             (ps->offset + ps->length) % PAGE_SIZE) {
 410                                 if (dma_map_cont(sg, start, i, sg+out, pages,
 411                                                  need) < 0)
 412                                         goto error;
 413                                 out++;
 414                                 pages = 0;
 415                                 start = i;
 416                         }
 417                 }
 418
 419                 need = nextneed;
 420                 pages += to_pages(s->offset, s->length);
 421         }
 422         if (dma_map_cont(sg, start, i, sg+out, pages, need) < 0)
 423                 goto error;
 424         out++;
 425         flush_gart();
 426         if (out < nents)
 427                 sg[out].dma_length = 0;
 428         return out;
 429
 430 error:
 431         flush_gart();
 432         gart_unmap_sg(dev, sg, nents, dir);
 433         /* When it was forced or merged try again in a dumb way */
 434         if (force_iommu || iommu_merge) {
 435                 out = dma_map_sg_nonforce(dev, sg, nents, dir);
 436                 if (out > 0)
 437                         return out;
 438         }
 439         if (panic_on_overflow)
 440                 panic("dma_map_sg: overflow on %lu pages\n", pages);
 441         iommu_full(dev, pages << PAGE_SHIFT, dir);
 442         for (i = 0; i < nents; i++)
 443                 sg[i].dma_address = bad_dma_address;
 444         return 0;
 445 }
 446
 447 static int no_agp;
 448
 449 static __init unsigned long check_iommu_size(unsigned long aper, u64 aper_size)
 450 {
 451         unsigned long a;
 452         if (!iommu_size) {
 453                 iommu_size = aper_size;
 454                 if (!no_agp)
 455                         iommu_size /= 2;
 456         }
 457
 458         a = aper + iommu_size;
 459         iommu_size -= round_up(a, LARGE_PAGE_SIZE) - a;
 460
 461         if (iommu_size < 64*1024*1024)
 462                 printk(KERN_WARNING
 463   "PCI-DMA: Warning: Small IOMMU %luMB. Consider increasing the AGP aperture in BIOS\n",iommu_size>>20);
 464
 465         return iommu_size;
 466 }
 467
 468 static __init unsigned read_aperture(struct pci_dev *dev, u32 *size)
 469 {
 470         unsigned aper_size = 0, aper_base_32;
 471         u64 aper_base;
 472         unsigned aper_order;
 473
 474         pci_read_config_dword(dev, 0x94, &aper_base_32);
 475         pci_read_config_dword(dev, 0x90, &aper_order);
 476         aper_order = (aper_order >> 1) & 7;
 477
 478         aper_base = aper_base_32 & 0x7fff;
 479         aper_base <<= 25;
 480
 481         aper_size = (32 * 1024 * 1024) << aper_order;
 482         if (aper_base + aper_size >= 0xffffffff || !aper_size)
 483                 aper_base = 0;
 484
 485         *size = aper_size;
 486         return aper_base;
 487 }
 488
 489 /*
 490  * Private Northbridge GATT initialization in case we cannot use the
 491  * AGP driver for some reason.
 492  */
 493 static __init int init_k8_gatt(struct agp_kern_info *info)
 494 {
 495         struct pci_dev *dev;
 496         void *gatt;
 497         unsigned aper_base, new_aper_base;
 498         unsigned aper_size, gatt_size, new_aper_size;
 499         int i;
 500
 501         printk(KERN_INFO "PCI-DMA: Disabling AGP.\n");
 502         aper_size = aper_base = info->aper_size = 0;
 503         dev = NULL;
 504         for (i = 0; i < num_k8_northbridges; i++) {
 505                 dev = k8_northbridges[i];
 506                 new_aper_base = read_aperture(dev, &new_aper_size);
 507                 if (!new_aper_base)
 508                         goto nommu;
 509
 510                 if (!aper_base) {
 511                         aper_size = new_aper_size;
 512                         aper_base = new_aper_base;
 513                 }
 514                 if (aper_size != new_aper_size || aper_base != new_aper_base)
 515                         goto nommu;
 516         }
 517         if (!aper_base)
 518                 goto nommu;
 519         info->aper_base = aper_base;
 520         info->aper_size = aper_size>>20;
 521
 522         gatt_size = (aper_size >> PAGE_SHIFT) * sizeof(u32);
 523         gatt = (void *)__get_free_pages(GFP_KERNEL, get_order(gatt_size));
 524         if (!gatt)
 525                 panic("Cannot allocate GATT table");
 526         memset(gatt, 0, gatt_size);
 527         agp_gatt_table = gatt;
 528
 529         for (i = 0; i < num_k8_northbridges; i++) {
 530                 u32 ctl;
 531                 u32 gatt_reg;
 532
 533                 dev = k8_northbridges[i];
 534                 gatt_reg = __pa(gatt) >> 12;
 535                 gatt_reg <<= 4;
 536                 pci_write_config_dword(dev, 0x98, gatt_reg);
 537                 pci_read_config_dword(dev, 0x90, &ctl);
 538
 539                 ctl |= 1;
 540                 ctl &= ~((1<<4) | (1<<5));
 541
 542                 pci_write_config_dword(dev, 0x90, ctl);
 543         }
 544         flush_gart();
 545
 546         printk("PCI-DMA: aperture base @ %x size %u KB\n",aper_base, aper_size>>10);
 547         return 0;
 548
 549  nommu:
 550         /* Should not happen anymore */
 551         printk(KERN_ERR "PCI-DMA: More than 4GB of RAM and no IOMMU\n"
 552                KERN_ERR "PCI-DMA: 32bit PCI IO may malfunction.\n");
 553         return -1;
 554 }
 555
 556 extern int agp_amd64_init(void);
 557
 558 static struct dma_mapping_ops gart_dma_ops = {
 559         .mapping_error = NULL,
 560         .map_single = gart_map_single,
 561         .map_simple = gart_map_simple,
 562         .unmap_single = gart_unmap_single,
 563         .sync_single_for_cpu = NULL,
 564         .sync_single_for_device = NULL,
 565         .sync_single_range_for_cpu = NULL,
 566         .sync_single_range_for_device = NULL,
 567         .sync_sg_for_cpu = NULL,
 568         .sync_sg_for_device = NULL,
 569         .map_sg = gart_map_sg,
 570         .unmap_sg = gart_unmap_sg,
 571 };
 572
 573 void __init gart_iommu_init(void)
 574 {
 575         struct agp_kern_info info;
 576         unsigned long aper_size;
 577         unsigned long iommu_start;
 578         unsigned long scratch;
 579         long i;
 580
 581         if (cache_k8_northbridges() < 0 || num_k8_northbridges == 0) {
 582                 printk(KERN_INFO "PCI-GART: No AMD northbridge found.\n");
 583                 return;
 584         }
 585
 586 #ifndef CONFIG_AGP_AMD64
 587         no_agp = 1;
 588 #else
 589         /* Makefile puts PCI initialization via subsys_initcall first. */
 590         /* Add other K8 AGP bridge drivers here */
 591         no_agp = no_agp ||
 592                 (agp_amd64_init() < 0) ||
 593                 (agp_copy_info(agp_bridge, &info) < 0);
 594 #endif
 595
 596         if (swiotlb)
 597                 return;
 598
 599         /* Did we detect a different HW IOMMU? */
 600         if (iommu_detected && !iommu_aperture)
 601                 return;
 602
 603         if (no_iommu ||
 604             (!force_iommu && end_pfn <= MAX_DMA32_PFN) ||
 605             !iommu_aperture ||
 606             (no_agp && init_k8_gatt(&info) < 0)) {
 607                 printk(KERN_INFO "PCI-DMA: Disabling IOMMU.\n");
 608                 if (end_pfn > MAX_DMA32_PFN) {
 609                         printk(KERN_ERR "WARNING more than 4GB of memory "
 610                                         "but IOMMU not available.\n"
 611                                KERN_ERR "WARNING 32bit PCI may malfunction.\n");
 612                 }
 613                 return;
 614         }
 615
 616         printk(KERN_INFO "PCI-DMA: using GART IOMMU.\n");
 617         aper_size = info.aper_size * 1024 * 1024;
 618         iommu_size = check_iommu_size(info.aper_base, aper_size);
 619         iommu_pages = iommu_size >> PAGE_SHIFT;
 620
 621         iommu_gart_bitmap = (void*)__get_free_pages(GFP_KERNEL,
 622                                                     get_order(iommu_pages/8));
 623         if (!iommu_gart_bitmap)
 624                 panic("Cannot allocate iommu bitmap\n");
 625         memset(iommu_gart_bitmap, 0, iommu_pages/8);
 626
 627 #ifdef CONFIG_IOMMU_LEAK
 628         if (leak_trace) {
 629                 iommu_leak_tab = (void *)__get_free_pages(GFP_KERNEL,
 630                                   get_order(iommu_pages*sizeof(void *)));
 631                 if (iommu_leak_tab)
 632                         memset(iommu_leak_tab, 0, iommu_pages * 8);
 633                 else
 634                         printk("PCI-DMA: Cannot allocate leak trace area\n");
 635         }
 636 #endif
 637
 638         /*
 639          * Out of IOMMU space handling.
 640          * Reserve some invalid pages at the beginning of the GART.
 641          */
 642         set_bit_string(iommu_gart_bitmap, 0, EMERGENCY_PAGES);
 643
 644         agp_memory_reserved = iommu_size;
 645         printk(KERN_INFO
 646                "PCI-DMA: Reserving %luMB of IOMMU area in the AGP aperture\n",
 647                iommu_size>>20);
 648
 649         iommu_start = aper_size - iommu_size;
 650         iommu_bus_base = info.aper_base + iommu_start;
 651         bad_dma_address = iommu_bus_base;
 652         iommu_gatt_base = agp_gatt_table + (iommu_start>>PAGE_SHIFT);
 653
 654         /*
 655          * Unmap the IOMMU part of the GART. The alias of the page is
 656          * always mapped with cache enabled and there is no full cache
 657          * coherency across the GART remapping. The unmapping avoids
 658          * automatic prefetches from the CPU allocating cache lines in
 659          * there. All CPU accesses are done via the direct mapping to
 660          * the backing memory. The GART address is only used by PCI
 661          * devices.
 662          */
 663         clear_kernel_mapping((unsigned long)__va(iommu_bus_base), iommu_size);
 664
 665         /*
 666          * Try to workaround a bug (thanks to BenH)
 667          * Set unmapped entries to a scratch page instead of 0.
 668          * Any prefetches that hit unmapped entries won't get an bus abort
 669          * then.
 670          */
 671         scratch = get_zeroed_page(GFP_KERNEL);
 672         if (!scratch)
 673                 panic("Cannot allocate iommu scratch page");
 674         gart_unmapped_entry = GPTE_ENCODE(__pa(scratch));
 675         for (i = EMERGENCY_PAGES; i < iommu_pages; i++)
 676                 iommu_gatt_base[i] = gart_unmapped_entry;
 677
 678         flush_gart();
 679         dma_ops = &gart_dma_ops;
 680 }
 681
 682 void gart_parse_options(char *p)
 683 {
 684         int arg;
 685
 686 #ifdef CONFIG_IOMMU_LEAK
 687         if (!strncmp(p,"leak",4)) {
 688                 leak_trace = 1;
 689                 p += 4;
 690                 if (*p == '=') ++p;
 691                 if (isdigit(*p) && get_option(&p, &arg))
 692                         iommu_leak_pages = arg;
 693         }
 694 #endif
 695         if (isdigit(*p) && get_option(&p, &arg))
 696                 iommu_size = arg;
 697         if (!strncmp(p, "fullflush",8))
 698                 iommu_fullflush = 1;
 699         if (!strncmp(p, "nofullflush",11))
 700                 iommu_fullflush = 0;
 701         if (!strncmp(p,"noagp",5))
 702                 no_agp = 1;
 703         if (!strncmp(p, "noaperture",10))
 704                 fix_aperture = 0;
 705         /* duplicated from pci-dma.c */
 706         if (!strncmp(p,"force",5))
 707                 iommu_aperture_allowed = 1;
 708         if (!strncmp(p,"allowed",7))
 709                 iommu_aperture_allowed = 1;
 710         if (!strncmp(p, "memaper", 7)) {
 711                 fallback_aper_force = 1;
 712                 p += 7;
 713                 if (*p == '=') {
 714                         ++p;
 715                         if (get_option(&p, &arg))
 716                                 fallback_aper_order = arg;
 717                 }
 718         }
 719 }