drivers/video/geode/lxfb_ops.c

   1 /* Geode LX framebuffer driver
   2  *
   3  * Copyright (C) 2006-2007, Advanced Micro Devices,Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/errno.h>
  13 #include <linux/fb.h>
  14 #include <linux/uaccess.h>
  15 #include <linux/delay.h>
  16
  17 #include "lxfb.h"
  18
  19 /* TODO
  20  * Support panel scaling
  21  * Add acceleration
  22  * Add support for interlacing (TV out)
  23  * Support compression
  24  */
  25
  26 /* This is the complete list of PLL frequencies that we can set -
  27  * we will choose the closest match to the incoming clock.
  28  * freq is the frequency of the dotclock * 1000 (for example,
  29  * 24823 = 24.983 Mhz).
  30  * pllval is the corresponding PLL value
  31 */
  32
  33 static const struct {
  34   unsigned int pllval;
  35   unsigned int freq;
  36 } pll_table[] = {
  37   { 0x000031AC, 24923 },
  38   { 0x0000215D, 25175 },
  39   { 0x00001087, 27000 },
  40   { 0x0000216C, 28322 },
  41   { 0x0000218D, 28560 },
  42   { 0x000010C9, 31200 },
  43   { 0x00003147, 31500 },
  44   { 0x000010A7, 33032 },
  45   { 0x00002159, 35112 },
  46   { 0x00004249, 35500 },
  47   { 0x00000057, 36000 },
  48   { 0x0000219A, 37889 },
  49   { 0x00002158, 39168 },
  50   { 0x00000045, 40000 },
  51   { 0x00000089, 43163 },
  52   { 0x000010E7, 44900 },
  53   { 0x00002136, 45720 },
  54   { 0x00003207, 49500 },
  55   { 0x00002187, 50000 },
  56   { 0x00004286, 56250 },
  57   { 0x000010E5, 60065 },
  58   { 0x00004214, 65000 },
  59   { 0x00001105, 68179 },
  60   { 0x000031E4, 74250 },
  61   { 0x00003183, 75000 },
  62   { 0x00004284, 78750 },
  63   { 0x00001104, 81600 },
  64   { 0x00006363, 94500 },
  65   { 0x00005303, 97520 },
  66   { 0x00002183, 100187 },
  67   { 0x00002122, 101420 },
  68   { 0x00001081, 108000 },
  69   { 0x00006201, 113310 },
  70   { 0x00000041, 119650 },
  71   { 0x000041A1, 129600 },
  72   { 0x00002182, 133500 },
  73   { 0x000041B1, 135000 },
  74   { 0x00000051, 144000 },
  75   { 0x000041E1, 148500 },
  76   { 0x000062D1, 157500 },
  77   { 0x000031A1, 162000 },
  78   { 0x00000061, 169203 },
  79   { 0x00004231, 172800 },
  80   { 0x00002151, 175500 },
  81   { 0x000052E1, 189000 },
  82   { 0x00000071, 192000 },
  83   { 0x00003201, 198000 },
  84   { 0x00004291, 202500 },
  85   { 0x00001101, 204750 },
  86   { 0x00007481, 218250 },
  87   { 0x00004170, 229500 },
  88   { 0x00006210, 234000 },
  89   { 0x00003140, 251182 },
  90   { 0x00006250, 261000 },
  91   { 0x000041C0, 278400 },
  92   { 0x00005220, 280640 },
  93   { 0x00000050, 288000 },
  94   { 0x000041E0, 297000 },
  95   { 0x00002130, 320207 }
  96 };
  97
  98
  99 static void lx_set_dotpll(u32 pllval)
 100 {
 101         u32 dotpll_lo, dotpll_hi;
 102         int i;
 103
 104         rdmsr(MSR_LX_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
 105
 106         if ((dotpll_lo & GLCP_DOTPLL_LOCK) && (dotpll_hi == pllval))
 107                 return;
 108
 109         dotpll_hi = pllval;
 110         dotpll_lo &= ~(GLCP_DOTPLL_BYPASS | GLCP_DOTPLL_HALFPIX);
 111         dotpll_lo |= GLCP_DOTPLL_RESET;
 112
 113         wrmsr(MSR_LX_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
 114
 115         /* Wait 100us for the PLL to lock */
 116
 117         udelay(100);
 118
 119         /* Now, loop for the lock bit */
 120
 121         for (i = 0; i < 1000; i++) {
 122                 rdmsr(MSR_LX_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
 123                 if (dotpll_lo & GLCP_DOTPLL_LOCK)
 124                         break;
 125         }
 126
 127         /* Clear the reset bit */
 128
 129         dotpll_lo &= ~GLCP_DOTPLL_RESET;
 130         wrmsr(MSR_LX_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
 131 }
 132
 133 /* Set the clock based on the frequency specified by the current mode */
 134
 135 static void lx_set_clock(struct fb_info *info)
 136 {
 137         unsigned int diff, min, best = 0;
 138         unsigned int freq, i;
 139
 140         freq = (unsigned int) (0x3b9aca00 / info->var.pixclock);
 141
 142         min = abs(pll_table[0].freq - freq);
 143
 144         for (i = 0; i < ARRAY_SIZE(pll_table); i++) {
 145                 diff = abs(pll_table[i].freq - freq);
 146                 if (diff < min) {
 147                         min = diff;
 148                         best = i;
 149                 }
 150         }
 151
 152         lx_set_dotpll(pll_table[best].pllval & 0x7FFF);
 153 }
 154
 155 static void lx_graphics_disable(struct fb_info *info)
 156 {
 157         struct lxfb_par *par = info->par;
 158         unsigned int val, gcfg;
 159
 160         /* Note:  This assumes that the video is in a quitet state */
 161
 162         writel(0, par->df_regs + DF_ALPHA_CONTROL_1);
 163         writel(0, par->df_regs + DF_ALPHA_CONTROL_1 + 32);
 164         writel(0, par->df_regs + DF_ALPHA_CONTROL_1 + 64);
 165
 166         /* Turn off the VGA and video enable */
 167         val = readl (par->dc_regs + DC_GENERAL_CFG) &
 168                 ~(DC_GCFG_VGAE | DC_GCFG_VIDE);
 169
 170         writel(val, par->dc_regs + DC_GENERAL_CFG);
 171
 172         val = readl(par->df_regs + DF_VIDEO_CFG) & ~DF_VCFG_VID_EN;
 173         writel(val, par->df_regs + DF_VIDEO_CFG);
 174
 175         writel( DC_IRQ_MASK | DC_VSYNC_IRQ_MASK |
 176                 DC_IRQ_STATUS | DC_VSYNC_IRQ_STATUS,
 177                 par->dc_regs + DC_IRQ);
 178
 179         val = readl(par->dc_regs + DC_GENLCK_CTRL) & ~DC_GENLCK_ENABLE;
 180         writel(val, par->dc_regs + DC_GENLCK_CTRL);
 181
 182         val = readl(par->dc_regs + DC_COLOR_KEY) & ~DC_CLR_KEY_ENABLE;
 183         writel(val & ~DC_CLR_KEY_ENABLE, par->dc_regs + DC_COLOR_KEY);
 184
 185         /* We don't actually blank the panel, due to the long latency
 186            involved with bringing it back */
 187
 188         val = readl(par->df_regs + DF_MISC) | DF_MISC_DAC_PWRDN;
 189         writel(val, par->df_regs + DF_MISC);
 190
 191         /* Turn off the display */
 192
 193         val = readl(par->df_regs + DF_DISPLAY_CFG);
 194         writel(val & ~(DF_DCFG_CRT_EN | DF_DCFG_HSYNC_EN | DF_DCFG_VSYNC_EN |
 195                        DF_DCFG_DAC_BL_EN), par->df_regs + DF_DISPLAY_CFG);
 196
 197         gcfg = readl(par->dc_regs + DC_GENERAL_CFG);
 198         gcfg &= ~(DC_GCFG_CMPE | DC_GCFG_DECE);
 199         writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
 200
 201         /* Turn off the TGEN */
 202         val = readl(par->dc_regs + DC_DISPLAY_CFG);
 203         val &= ~DC_DCFG_TGEN;
 204         writel(val, par->dc_regs + DC_DISPLAY_CFG);
 205
 206         /* Wait 1000 usecs to ensure that the TGEN is clear */
 207         udelay(1000);
 208
 209         /* Turn off the FIFO loader */
 210
 211         gcfg &= ~DC_GCFG_DFLE;
 212         writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
 213
 214         /* Lastly, wait for the GP to go idle */
 215
 216         do {
 217                 val = readl(par->gp_regs + GP_BLT_STATUS);
 218         } while ((val & GP_BS_BLT_BUSY) || !(val & GP_BS_CB_EMPTY));
 219 }
 220
 221 static void lx_graphics_enable(struct fb_info *info)
 222 {
 223         struct lxfb_par *par = info->par;
 224         u32 temp, config;
 225
 226         /* Set the video request register */
 227         writel(0, par->df_regs + DF_VIDEO_REQUEST);
 228
 229         /* Set up the polarities */
 230
 231         config = readl(par->df_regs + DF_DISPLAY_CFG);
 232
 233         config &= ~(DF_DCFG_CRT_SYNC_SKW_MASK | DF_DCFG_PWR_SEQ_DLY_MASK |
 234                   DF_DCFG_CRT_HSYNC_POL     | DF_DCFG_CRT_VSYNC_POL);
 235
 236         config |= (DF_DCFG_CRT_SYNC_SKW_INIT | DF_DCFG_PWR_SEQ_DLY_INIT  |
 237                    DF_DCFG_GV_PAL_BYP);
 238
 239         if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
 240                 config |= DF_DCFG_CRT_HSYNC_POL;
 241
 242         if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
 243                 config |= DF_DCFG_CRT_VSYNC_POL;
 244
 245         if (par->output & OUTPUT_PANEL) {
 246                 u32 msrlo, msrhi;
 247
 248                 writel(DF_DEFAULT_TFT_PMTIM1,
 249                        par->df_regs + DF_PANEL_TIM1);
 250                 writel(DF_DEFAULT_TFT_PMTIM2,
 251                        par->df_regs + DF_PANEL_TIM2);
 252                 writel(DF_DEFAULT_TFT_DITHCTL,
 253                        par->df_regs + DF_DITHER_CONTROL);
 254
 255                 msrlo = DF_DEFAULT_TFT_PAD_SEL_LOW;
 256                 msrhi = DF_DEFAULT_TFT_PAD_SEL_HIGH;
 257
 258                 wrmsr(MSR_LX_DF_PADSEL, msrlo, msrhi);
 259         }
 260
 261         if (par->output & OUTPUT_CRT) {
 262                 config |= DF_DCFG_CRT_EN   | DF_DCFG_HSYNC_EN |
 263                         DF_DCFG_VSYNC_EN | DF_DCFG_DAC_BL_EN;
 264         }
 265
 266         writel(config, par->df_regs + DF_DISPLAY_CFG);
 267
 268         /* Turn the CRT dacs back on */
 269
 270         if (par->output & OUTPUT_CRT) {
 271                 temp = readl(par->df_regs + DF_MISC);
 272                 temp &= ~(DF_MISC_DAC_PWRDN  | DF_MISC_A_PWRDN);
 273                 writel(temp, par->df_regs + DF_MISC);
 274         }
 275
 276         /* Turn the panel on (if it isn't already) */
 277
 278         if (par->output & OUTPUT_PANEL) {
 279                 temp = readl(par->df_regs + DF_FP_PM);
 280
 281                 if (!(temp & 0x09))
 282                         writel(temp | DF_FP_PM_P, par->df_regs + DF_FP_PM);
 283         }
 284
 285         temp = readl(par->df_regs + DF_MISC);
 286         temp = readl(par->df_regs + DF_DISPLAY_CFG);
 287 }
 288
 289 unsigned int lx_framebuffer_size(void)
 290 {
 291         unsigned int val;
 292
 293         /* The frame buffer size is reported by a VSM in VSA II */
 294         /* Virtual Register Class    = 0x02                     */
 295         /* VG_MEM_SIZE (1MB units)   = 0x00                     */
 296
 297         outw(0xFC53, 0xAC1C);
 298         outw(0x0200, 0xAC1C);
 299
 300         val = (unsigned int)(inw(0xAC1E)) & 0xFE;
 301         return (val << 20);
 302 }
 303
 304 void lx_set_mode(struct fb_info *info)
 305 {
 306         struct lxfb_par *par = info->par;
 307         u64 msrval;
 308
 309         unsigned int max, dv, val, size;
 310
 311         unsigned int gcfg, dcfg;
 312         int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
 313         int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
 314
 315         /* Unlock the DC registers */
 316         writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK);
 317
 318         lx_graphics_disable(info);
 319
 320         lx_set_clock(info);
 321
 322         /* Set output mode */
 323
 324         rdmsrl(MSR_LX_DF_GLCONFIG, msrval);
 325         msrval &= ~DF_CONFIG_OUTPUT_MASK;
 326
 327         if (par->output & OUTPUT_PANEL) {
 328                 msrval |= DF_OUTPUT_PANEL;
 329
 330                 if (par->output & OUTPUT_CRT)
 331                         msrval |= DF_SIMULTANEOUS_CRT_AND_FP;
 332                 else
 333                         msrval &= ~DF_SIMULTANEOUS_CRT_AND_FP;
 334         } else {
 335                 msrval |= DF_OUTPUT_CRT;
 336         }
 337
 338         wrmsrl(MSR_LX_DF_GLCONFIG, msrval);
 339
 340         /* Clear the various buffers */
 341         /* FIXME:  Adjust for panning here */
 342
 343         writel(0, par->dc_regs + DC_FB_START);
 344         writel(0, par->dc_regs + DC_CB_START);
 345         writel(0, par->dc_regs + DC_CURSOR_START);
 346
 347         /* FIXME: Add support for interlacing */
 348         /* FIXME: Add support for scaling */
 349
 350         val = readl(par->dc_regs + DC_GENLCK_CTRL);
 351         val &= ~(DC_GC_ALPHA_FLICK_ENABLE |
 352                  DC_GC_FLICKER_FILTER_ENABLE | DC_GC_FLICKER_FILTER_MASK);
 353
 354         /* Default scaling params */
 355
 356         writel((0x4000 << 16) | 0x4000, par->dc_regs + DC_GFX_SCALE);
 357         writel(0, par->dc_regs + DC_IRQ_FILT_CTL);
 358         writel(val, par->dc_regs + DC_GENLCK_CTRL);
 359
 360         /* FIXME:  Support compression */
 361
 362         if (info->fix.line_length > 4096)
 363                 dv = DC_DV_LINE_SIZE_8192;
 364         else if (info->fix.line_length > 2048)
 365                 dv = DC_DV_LINE_SIZE_4096;
 366         else if (info->fix.line_length > 1024)
 367                 dv = DC_DV_LINE_SIZE_2048;
 368         else
 369                 dv = DC_DV_LINE_SIZE_1024;
 370
 371         max = info->fix.line_length * info->var.yres;
 372         max = (max + 0x3FF) & 0xFFFFFC00;
 373
 374         writel(max | DC_DV_TOP_ENABLE, par->dc_regs + DC_DV_TOP);
 375
 376         val = readl(par->dc_regs + DC_DV_CTL) & ~DC_DV_LINE_SIZE_MASK;
 377         writel(val | dv, par->dc_regs + DC_DV_CTL);
 378
 379         size = info->var.xres * (info->var.bits_per_pixel >> 3);
 380
 381         writel(info->fix.line_length >> 3, par->dc_regs + DC_GRAPHICS_PITCH);
 382         writel((size + 7) >> 3, par->dc_regs + DC_LINE_SIZE);
 383
 384         /* Set default watermark values */
 385
 386         rdmsrl(MSR_LX_DC_SPARE, msrval);
 387
 388         msrval &= ~(DC_SPARE_DISABLE_CFIFO_HGO | DC_SPARE_VFIFO_ARB_SELECT |
 389                     DC_SPARE_LOAD_WM_LPEN_MASK | DC_SPARE_WM_LPEN_OVRD |
 390                     DC_SPARE_DISABLE_INIT_VID_PRI | DC_SPARE_DISABLE_VFIFO_WM);
 391         msrval |= DC_SPARE_DISABLE_VFIFO_WM | DC_SPARE_DISABLE_INIT_VID_PRI;
 392         wrmsrl(MSR_LX_DC_SPARE, msrval);
 393
 394         gcfg = DC_GCFG_DFLE;   /* Display fifo enable */
 395         gcfg |= 0xB600;         /* Set default priority */
 396         gcfg |= DC_GCFG_FDTY;  /* Set the frame dirty mode */
 397
 398         dcfg  = DC_DCFG_VDEN;  /* Enable video data */
 399         dcfg |= DC_DCFG_GDEN;  /* Enable graphics */
 400         dcfg |= DC_DCFG_TGEN;  /* Turn on the timing generator */
 401         dcfg |= DC_DCFG_TRUP;  /* Update timings immediately */
 402         dcfg |= DC_DCFG_PALB;  /* Palette bypass in > 8 bpp modes */
 403         dcfg |= DC_DCFG_VISL;
 404         dcfg |= DC_DCFG_DCEN;  /* Always center the display */
 405
 406         /* Set the current BPP mode */
 407
 408         switch (info->var.bits_per_pixel) {
 409         case 8:
 410                 dcfg |= DC_DCFG_DISP_MODE_8BPP;
 411                 break;
 412
 413         case 16:
 414                 dcfg |= DC_DCFG_DISP_MODE_16BPP | DC_DCFG_16BPP;
 415                 break;
 416
 417         case 32:
 418         case 24:
 419                 dcfg |= DC_DCFG_DISP_MODE_24BPP;
 420                 break;
 421         }
 422
 423         /* Now - set up the timings */
 424
 425         hactive = info->var.xres;
 426         hblankstart = hactive;
 427         hsyncstart = hblankstart + info->var.right_margin;
 428         hsyncend =  hsyncstart + info->var.hsync_len;
 429         hblankend = hsyncend + info->var.left_margin;
 430         htotal = hblankend;
 431
 432         vactive = info->var.yres;
 433         vblankstart = vactive;
 434         vsyncstart = vblankstart + info->var.lower_margin;
 435         vsyncend =  vsyncstart + info->var.vsync_len;
 436         vblankend = vsyncend + info->var.upper_margin;
 437         vtotal = vblankend;
 438
 439         writel((hactive - 1) | ((htotal - 1) << 16),
 440                par->dc_regs + DC_H_ACTIVE_TIMING);
 441         writel((hblankstart - 1) | ((hblankend - 1) << 16),
 442                par->dc_regs + DC_H_BLANK_TIMING);
 443         writel((hsyncstart - 1) | ((hsyncend - 1) << 16),
 444                par->dc_regs + DC_H_SYNC_TIMING);
 445
 446         writel((vactive - 1) | ((vtotal - 1) << 16),
 447                par->dc_regs + DC_V_ACTIVE_TIMING);
 448
 449         writel((vblankstart - 1) | ((vblankend - 1) << 16),
 450                par->dc_regs + DC_V_BLANK_TIMING);
 451
 452         writel((vsyncstart - 1)  | ((vsyncend - 1) << 16),
 453                par->dc_regs + DC_V_SYNC_TIMING);
 454
 455         writel( (info->var.xres - 1) << 16 | (info->var.yres - 1),
 456                 par->dc_regs + DC_FB_ACTIVE);
 457
 458         /* And re-enable the graphics output */
 459         lx_graphics_enable(info);
 460
 461         /* Write the two main configuration registers */
 462         writel(dcfg, par->dc_regs + DC_DISPLAY_CFG);
 463         writel(0, par->dc_regs + DC_ARB_CFG);
 464         writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
 465
 466         /* Lock the DC registers */
 467         writel(0, par->dc_regs + DC_UNLOCK);
 468 }
 469
 470 void lx_set_palette_reg(struct fb_info *info, unsigned regno,
 471                         unsigned red, unsigned green, unsigned blue)
 472 {
 473         struct lxfb_par *par = info->par;
 474         int val;
 475
 476         /* Hardware palette is in RGB 8-8-8 format. */
 477
 478         val  = (red   << 8) & 0xff0000;
 479         val |= (green)      & 0x00ff00;
 480         val |= (blue  >> 8) & 0x0000ff;
 481
 482         writel(regno, par->dc_regs + DC_PAL_ADDRESS);
 483         writel(val, par->dc_regs + DC_PAL_DATA);
 484 }
 485
 486 int lx_blank_display(struct fb_info *info, int blank_mode)
 487 {
 488         struct lxfb_par *par = info->par;
 489         u32 dcfg, fp_pm;
 490         int blank, hsync, vsync;
 491
 492         /* CRT power saving modes. */
 493         switch (blank_mode) {
 494         case FB_BLANK_UNBLANK:
 495                 blank = 0; hsync = 1; vsync = 1;
 496                 break;
 497         case FB_BLANK_NORMAL:
 498                 blank = 1; hsync = 1; vsync = 1;
 499                 break;
 500         case FB_BLANK_VSYNC_SUSPEND:
 501                 blank = 1; hsync = 1; vsync = 0;
 502                 break;
 503         case FB_BLANK_HSYNC_SUSPEND:
 504                 blank = 1; hsync = 0; vsync = 1;
 505                 break;
 506         case FB_BLANK_POWERDOWN:
 507                 blank = 1; hsync = 0; vsync = 0;
 508                 break;
 509         default:
 510                 return -EINVAL;
 511         }
 512
 513         dcfg = readl(par->df_regs + DF_DISPLAY_CFG);
 514         dcfg &= ~(DF_DCFG_DAC_BL_EN
 515                   | DF_DCFG_HSYNC_EN | DF_DCFG_VSYNC_EN);
 516         if (!blank)
 517                 dcfg |= DF_DCFG_DAC_BL_EN;
 518         if (hsync)
 519                 dcfg |= DF_DCFG_HSYNC_EN;
 520         if (vsync)
 521                 dcfg |= DF_DCFG_VSYNC_EN;
 522         writel(dcfg, par->df_regs + DF_DISPLAY_CFG);
 523
 524         /* Power on/off flat panel */
 525
 526         if (par->output & OUTPUT_PANEL) {
 527                 fp_pm = readl(par->df_regs + DF_FP_PM);
 528                 if (blank_mode == FB_BLANK_POWERDOWN)
 529                         fp_pm &= ~DF_FP_PM_P;
 530                 else
 531                         fp_pm |= DF_FP_PM_P;
 532                 writel(fp_pm, par->df_regs + DF_FP_PM);
 533         }
 534
 535         return 0;
 536 }