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ath9k: Check for pci_map_single() errors
[linux-2.6/mini2440.git] / drivers / net / wireless / ath9k / xmit.c
blob17fd05e2f247c485259681017369120de70e7e29
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "core.h"
18
19 #define BITS_PER_BYTE 8
20 #define OFDM_PLCP_BITS 22
21 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
22 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
23 #define L_STF 8
24 #define L_LTF 8
25 #define L_SIG 4
26 #define HT_SIG 8
27 #define HT_STF 4
28 #define HT_LTF(_ns) (4 * (_ns))
29 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
30 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
31 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
32 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
33
34 #define OFDM_SIFS_TIME 16
35
36 static u32 bits_per_symbol[][2] = {
37 /* 20MHz 40MHz */
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
46 { 52, 108 }, /* 8: BPSK */
47 { 104, 216 }, /* 9: QPSK 1/2 */
48 { 156, 324 }, /* 10: QPSK 3/4 */
49 { 208, 432 }, /* 11: 16-QAM 1/2 */
50 { 312, 648 }, /* 12: 16-QAM 3/4 */
51 { 416, 864 }, /* 13: 64-QAM 2/3 */
52 { 468, 972 }, /* 14: 64-QAM 3/4 */
53 { 520, 1080 }, /* 15: 64-QAM 5/6 */
54 };
55
56 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
57
58 /*
59 * Insert a chain of ath_buf (descriptors) on a txq and
60 * assume the descriptors are already chained together by caller.
61 * NB: must be called with txq lock held
62 */
63
64 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
65 struct list_head *head)
66 {
67 struct ath_hal *ah = sc->sc_ah;
68 struct ath_buf *bf;
69
70 /*
71 * Insert the frame on the outbound list and
72 * pass it on to the hardware.
73 */
74
75 if (list_empty(head))
76 return;
77
78 bf = list_first_entry(head, struct ath_buf, list);
79
80 list_splice_tail_init(head, &txq->axq_q);
81 txq->axq_depth++;
82 txq->axq_totalqueued++;
83 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
84
85 DPRINTF(sc, ATH_DBG_QUEUE,
86 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
87
88 if (txq->axq_link == NULL) {
89 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
90 DPRINTF(sc, ATH_DBG_XMIT,
91 "TXDP[%u] = %llx (%p)\n",
92 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
93 } else {
94 *txq->axq_link = bf->bf_daddr;
95 DPRINTF(sc, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
96 txq->axq_qnum, txq->axq_link,
97 ito64(bf->bf_daddr), bf->bf_desc);
98 }
99 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
100 ath9k_hw_txstart(ah, txq->axq_qnum);
101 }
102
103 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
104 struct ath_xmit_status *tx_status)
105 {
106 struct ieee80211_hw *hw = sc->hw;
107 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
108 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
109
110 DPRINTF(sc, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
111
112 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK ||
113 tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) {
114 kfree(tx_info_priv);
115 tx_info->rate_driver_data[0] = NULL;
116 }
117
118 if (tx_status->flags & ATH_TX_BAR) {
119 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
120 tx_status->flags &= ~ATH_TX_BAR;
121 }
122
123 if (!(tx_status->flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
124 /* Frame was ACKed */
125 tx_info->flags |= IEEE80211_TX_STAT_ACK;
126 }
127
128 tx_info->status.rates[0].count = tx_status->retries + 1;
129
130 ieee80211_tx_status(hw, skb);
131 }
132
133 /* Check if it's okay to send out aggregates */
134
135 static int ath_aggr_query(struct ath_softc *sc, struct ath_node *an, u8 tidno)
136 {
137 struct ath_atx_tid *tid;
138 tid = ATH_AN_2_TID(an, tidno);
139
140 if (tid->state & AGGR_ADDBA_COMPLETE ||
141 tid->state & AGGR_ADDBA_PROGRESS)
142 return 1;
143 else
144 return 0;
145 }
146
147 static void ath_get_beaconconfig(struct ath_softc *sc, int if_id,
148 struct ath_beacon_config *conf)
149 {
150 struct ieee80211_hw *hw = sc->hw;
151
152 /* fill in beacon config data */
153
154 conf->beacon_interval = hw->conf.beacon_int;
155 conf->listen_interval = 100;
156 conf->dtim_count = 1;
157 conf->bmiss_timeout = ATH_DEFAULT_BMISS_LIMIT * conf->listen_interval;
158 }
159
160 /* Calculate Atheros packet type from IEEE80211 packet header */
161
162 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
163 {
164 struct ieee80211_hdr *hdr;
165 enum ath9k_pkt_type htype;
166 __le16 fc;
167
168 hdr = (struct ieee80211_hdr *)skb->data;
169 fc = hdr->frame_control;
170
171 if (ieee80211_is_beacon(fc))
172 htype = ATH9K_PKT_TYPE_BEACON;
173 else if (ieee80211_is_probe_resp(fc))
174 htype = ATH9K_PKT_TYPE_PROBE_RESP;
175 else if (ieee80211_is_atim(fc))
176 htype = ATH9K_PKT_TYPE_ATIM;
177 else if (ieee80211_is_pspoll(fc))
178 htype = ATH9K_PKT_TYPE_PSPOLL;
179 else
180 htype = ATH9K_PKT_TYPE_NORMAL;
181
182 return htype;
183 }
184
185 static bool is_pae(struct sk_buff *skb)
186 {
187 struct ieee80211_hdr *hdr;
188 __le16 fc;
189
190 hdr = (struct ieee80211_hdr *)skb->data;
191 fc = hdr->frame_control;
192
193 if (ieee80211_is_data(fc)) {
194 if (ieee80211_is_nullfunc(fc) ||
195 /* Port Access Entity (IEEE 802.1X) */
196 (skb->protocol == cpu_to_be16(ETH_P_PAE))) {
197 return true;
198 }
199 }
200
201 return false;
202 }
203
204 static int get_hw_crypto_keytype(struct sk_buff *skb)
205 {
206 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
207
208 if (tx_info->control.hw_key) {
209 if (tx_info->control.hw_key->alg == ALG_WEP)
210 return ATH9K_KEY_TYPE_WEP;
211 else if (tx_info->control.hw_key->alg == ALG_TKIP)
212 return ATH9K_KEY_TYPE_TKIP;
213 else if (tx_info->control.hw_key->alg == ALG_CCMP)
214 return ATH9K_KEY_TYPE_AES;
215 }
216
217 return ATH9K_KEY_TYPE_CLEAR;
218 }
219
220 /* Called only when tx aggregation is enabled and HT is supported */
221
222 static void assign_aggr_tid_seqno(struct sk_buff *skb,
223 struct ath_buf *bf)
224 {
225 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
226 struct ieee80211_hdr *hdr;
227 struct ath_node *an;
228 struct ath_atx_tid *tid;
229 __le16 fc;
230 u8 *qc;
231
232 if (!tx_info->control.sta)
233 return;
234
235 an = (struct ath_node *)tx_info->control.sta->drv_priv;
236 hdr = (struct ieee80211_hdr *)skb->data;
237 fc = hdr->frame_control;
238
239 /* Get tidno */
240
241 if (ieee80211_is_data_qos(fc)) {
242 qc = ieee80211_get_qos_ctl(hdr);
243 bf->bf_tidno = qc[0] & 0xf;
244 }
245
246 /* Get seqno */
247
248 if (ieee80211_is_data(fc) && !is_pae(skb)) {
249 /* For HT capable stations, we save tidno for later use.
250 * We also override seqno set by upper layer with the one
251 * in tx aggregation state.
252 *
253 * If fragmentation is on, the sequence number is
254 * not overridden, since it has been
255 * incremented by the fragmentation routine.
256 *
257 * FIXME: check if the fragmentation threshold exceeds
258 * IEEE80211 max.
259 */
260 tid = ATH_AN_2_TID(an, bf->bf_tidno);
261 hdr->seq_ctrl = cpu_to_le16(tid->seq_next <<
262 IEEE80211_SEQ_SEQ_SHIFT);
263 bf->bf_seqno = tid->seq_next;
264 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
265 }
266 }
267
268 static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb,
269 struct ath_txq *txq)
270 {
271 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
272 int flags = 0;
273
274 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
275 flags |= ATH9K_TXDESC_INTREQ;
276
277 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
278 flags |= ATH9K_TXDESC_NOACK;
279 if (tx_info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
280 flags |= ATH9K_TXDESC_RTSENA;
281
282 return flags;
283 }
284
285 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
286 {
287 struct ath_buf *bf = NULL;
288
289 spin_lock_bh(&sc->sc_txbuflock);
290
291 if (unlikely(list_empty(&sc->sc_txbuf))) {
292 spin_unlock_bh(&sc->sc_txbuflock);
293 return NULL;
294 }
295
296 bf = list_first_entry(&sc->sc_txbuf, struct ath_buf, list);
297 list_del(&bf->list);
298
299 spin_unlock_bh(&sc->sc_txbuflock);
300
301 return bf;
302 }
303
304 /* To complete a chain of buffers associated a frame */
305
306 static void ath_tx_complete_buf(struct ath_softc *sc,
307 struct ath_buf *bf,
308 struct list_head *bf_q,
309 int txok, int sendbar)
310 {
311 struct sk_buff *skb = bf->bf_mpdu;
312 struct ath_xmit_status tx_status;
313
314 /*
315 * Set retry information.
316 * NB: Don't use the information in the descriptor, because the frame
317 * could be software retried.
318 */
319 tx_status.retries = bf->bf_retries;
320 tx_status.flags = 0;
321
322 if (sendbar)
323 tx_status.flags = ATH_TX_BAR;
324
325 if (!txok) {
326 tx_status.flags |= ATH_TX_ERROR;
327
328 if (bf_isxretried(bf))
329 tx_status.flags |= ATH_TX_XRETRY;
330 }
331
332 /* Unmap this frame */
333 pci_unmap_single(sc->pdev,
334 bf->bf_dmacontext,
335 skb->len,
336 PCI_DMA_TODEVICE);
337 /* complete this frame */
338 ath_tx_complete(sc, skb, &tx_status);
339
340 /*
341 * Return the list of ath_buf of this mpdu to free queue
342 */
343 spin_lock_bh(&sc->sc_txbuflock);
344 list_splice_tail_init(bf_q, &sc->sc_txbuf);
345 spin_unlock_bh(&sc->sc_txbuflock);
346 }
347
348 /*
349 * queue up a dest/ac pair for tx scheduling
350 * NB: must be called with txq lock held
351 */
352
353 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
354 {
355 struct ath_atx_ac *ac = tid->ac;
356
357 /*
358 * if tid is paused, hold off
359 */
360 if (tid->paused)
361 return;
362
363 /*
364 * add tid to ac atmost once
365 */
366 if (tid->sched)
367 return;
368
369 tid->sched = true;
370 list_add_tail(&tid->list, &ac->tid_q);
371
372 /*
373 * add node ac to txq atmost once
374 */
375 if (ac->sched)
376 return;
377
378 ac->sched = true;
379 list_add_tail(&ac->list, &txq->axq_acq);
380 }
381
382 /* pause a tid */
383
384 static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
385 {
386 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum];
387
388 spin_lock_bh(&txq->axq_lock);
389
390 tid->paused++;
391
392 spin_unlock_bh(&txq->axq_lock);
393 }
394
395 /* resume a tid and schedule aggregate */
396
397 void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
398 {
399 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum];
400
401 ASSERT(tid->paused > 0);
402 spin_lock_bh(&txq->axq_lock);
403
404 tid->paused--;
405
406 if (tid->paused > 0)
407 goto unlock;
408
409 if (list_empty(&tid->buf_q))
410 goto unlock;
411
412 /*
413 * Add this TID to scheduler and try to send out aggregates
414 */
415 ath_tx_queue_tid(txq, tid);
416 ath_txq_schedule(sc, txq);
417 unlock:
418 spin_unlock_bh(&txq->axq_lock);
419 }
420
421 /* Compute the number of bad frames */
422
423 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
424 int txok)
425 {
426 struct ath_buf *bf_last = bf->bf_lastbf;
427 struct ath_desc *ds = bf_last->bf_desc;
428 u16 seq_st = 0;
429 u32 ba[WME_BA_BMP_SIZE >> 5];
430 int ba_index;
431 int nbad = 0;
432 int isaggr = 0;
433
434 if (ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED)
435 return 0;
436
437 isaggr = bf_isaggr(bf);
438 if (isaggr) {
439 seq_st = ATH_DS_BA_SEQ(ds);
440 memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3);
441 }
442
443 while (bf) {
444 ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
445 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
446 nbad++;
447
448 bf = bf->bf_next;
449 }
450
451 return nbad;
452 }
453
454 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf)
455 {
456 struct sk_buff *skb;
457 struct ieee80211_hdr *hdr;
458
459 bf->bf_state.bf_type |= BUF_RETRY;
460 bf->bf_retries++;
461
462 skb = bf->bf_mpdu;
463 hdr = (struct ieee80211_hdr *)skb->data;
464 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
465 }
466
467 /* Update block ack window */
468
469 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
470 int seqno)
471 {
472 int index, cindex;
473
474 index = ATH_BA_INDEX(tid->seq_start, seqno);
475 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
476
477 tid->tx_buf[cindex] = NULL;
478
479 while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) {
480 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
481 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
482 }
483 }
484
485 /*
486 * ath_pkt_dur - compute packet duration (NB: not NAV)
487 *
488 * rix - rate index
489 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
490 * width - 0 for 20 MHz, 1 for 40 MHz
491 * half_gi - to use 4us v/s 3.6 us for symbol time
492 */
493 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
494 int width, int half_gi, bool shortPreamble)
495 {
496 struct ath_rate_table *rate_table = sc->hw_rate_table[sc->sc_curmode];
497 u32 nbits, nsymbits, duration, nsymbols;
498 u8 rc;
499 int streams, pktlen;
500
501 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
502 rc = rate_table->info[rix].ratecode;
503
504 /* for legacy rates, use old function to compute packet duration */
505 if (!IS_HT_RATE(rc))
506 return ath9k_hw_computetxtime(sc->sc_ah, rate_table, pktlen,
507 rix, shortPreamble);
508
509 /* find number of symbols: PLCP + data */
510 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
511 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
512 nsymbols = (nbits + nsymbits - 1) / nsymbits;
513
514 if (!half_gi)
515 duration = SYMBOL_TIME(nsymbols);
516 else
517 duration = SYMBOL_TIME_HALFGI(nsymbols);
518
519 /* addup duration for legacy/ht training and signal fields */
520 streams = HT_RC_2_STREAMS(rc);
521 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
522
523 return duration;
524 }
525
526 /* Rate module function to set rate related fields in tx descriptor */
527
528 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
529 {
530 struct ath_hal *ah = sc->sc_ah;
531 struct ath_rate_table *rt;
532 struct ath_desc *ds = bf->bf_desc;
533 struct ath_desc *lastds = bf->bf_lastbf->bf_desc;
534 struct ath9k_11n_rate_series series[4];
535 struct sk_buff *skb;
536 struct ieee80211_tx_info *tx_info;
537 struct ieee80211_tx_rate *rates;
538 struct ieee80211_hdr *hdr;
539 int i, flags, rtsctsena = 0;
540 u32 ctsduration = 0;
541 u8 rix = 0, cix, ctsrate = 0;
542 __le16 fc;
543
544 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
545
546 skb = (struct sk_buff *)bf->bf_mpdu;
547 hdr = (struct ieee80211_hdr *)skb->data;
548 fc = hdr->frame_control;
549 tx_info = IEEE80211_SKB_CB(skb);
550 rates = tx_info->control.rates;
551
552 if (ieee80211_has_morefrags(fc) ||
553 (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG)) {
554 rates[1].count = rates[2].count = rates[3].count = 0;
555 rates[1].idx = rates[2].idx = rates[3].idx = 0;
556 rates[0].count = ATH_TXMAXTRY;
557 }
558
559 /* get the cix for the lowest valid rix */
560 rt = sc->hw_rate_table[sc->sc_curmode];
561 for (i = 3; i >= 0; i--) {
562 if (rates[i].count && (rates[i].idx >= 0)) {
563 rix = rates[i].idx;
564 break;
565 }
566 }
567
568 flags = (bf->bf_flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA));
569 cix = rt->info[rix].ctrl_rate;
570
571 /*
572 * If 802.11g protection is enabled, determine whether to use RTS/CTS or
573 * just CTS. Note that this is only done for OFDM/HT unicast frames.
574 */
575 if (sc->sc_protmode != PROT_M_NONE && !(bf->bf_flags & ATH9K_TXDESC_NOACK)
576 && (rt->info[rix].phy == WLAN_RC_PHY_OFDM ||
577 WLAN_RC_PHY_HT(rt->info[rix].phy))) {
578 if (sc->sc_protmode == PROT_M_RTSCTS)
579 flags = ATH9K_TXDESC_RTSENA;
580 else if (sc->sc_protmode == PROT_M_CTSONLY)
581 flags = ATH9K_TXDESC_CTSENA;
582
583 cix = rt->info[sc->sc_protrix].ctrl_rate;
584 rtsctsena = 1;
585 }
586
587 /* For 11n, the default behavior is to enable RTS for hw retried frames.
588 * We enable the global flag here and let rate series flags determine
589 * which rates will actually use RTS.
590 */
591 if ((ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) && bf_isdata(bf)) {
592 /* 802.11g protection not needed, use our default behavior */
593 if (!rtsctsena)
594 flags = ATH9K_TXDESC_RTSENA;
595 }
596
597 /* Set protection if aggregate protection on */
598 if (sc->sc_config.ath_aggr_prot &&
599 (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) {
600 flags = ATH9K_TXDESC_RTSENA;
601 cix = rt->info[sc->sc_protrix].ctrl_rate;
602 rtsctsena = 1;
603 }
604
605 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
606 if (bf_isaggr(bf) && (bf->bf_al > ah->ah_caps.rts_aggr_limit))
607 flags &= ~(ATH9K_TXDESC_RTSENA);
608
609 /*
610 * CTS transmit rate is derived from the transmit rate by looking in the
611 * h/w rate table. We must also factor in whether or not a short
612 * preamble is to be used. NB: cix is set above where RTS/CTS is enabled
613 */
614 ctsrate = rt->info[cix].ratecode |
615 (bf_isshpreamble(bf) ? rt->info[cix].short_preamble : 0);
616
617 for (i = 0; i < 4; i++) {
618 if (!rates[i].count || (rates[i].idx < 0))
619 continue;
620
621 rix = rates[i].idx;
622
623 series[i].Rate = rt->info[rix].ratecode |
624 (bf_isshpreamble(bf) ? rt->info[rix].short_preamble : 0);
625
626 series[i].Tries = rates[i].count;
627
628 series[i].RateFlags = (
629 (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) ?
630 ATH9K_RATESERIES_RTS_CTS : 0) |
631 ((rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ?
632 ATH9K_RATESERIES_2040 : 0) |
633 ((rates[i].flags & IEEE80211_TX_RC_SHORT_GI) ?
634 ATH9K_RATESERIES_HALFGI : 0);
635
636 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
637 (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) != 0,
638 (rates[i].flags & IEEE80211_TX_RC_SHORT_GI),
639 bf_isshpreamble(bf));
640
641 series[i].ChSel = sc->sc_tx_chainmask;
642
643 if (rtsctsena)
644 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
645 }
646
647 /* set dur_update_en for l-sig computation except for PS-Poll frames */
648 ath9k_hw_set11n_ratescenario(ah, ds, lastds, !bf_ispspoll(bf),
649 ctsrate, ctsduration,
650 series, 4, flags);
651
652 if (sc->sc_config.ath_aggr_prot && flags)
653 ath9k_hw_set11n_burstduration(ah, ds, 8192);
654 }
655
656 /*
657 * Function to send a normal HT (non-AMPDU) frame
658 * NB: must be called with txq lock held
659 */
660 static int ath_tx_send_normal(struct ath_softc *sc,
661 struct ath_txq *txq,
662 struct ath_atx_tid *tid,
663 struct list_head *bf_head)
664 {
665 struct ath_buf *bf;
666
667 BUG_ON(list_empty(bf_head));
668
669 bf = list_first_entry(bf_head, struct ath_buf, list);
670 bf->bf_state.bf_type &= ~BUF_AMPDU; /* regular HT frame */
671
672 /* update starting sequence number for subsequent ADDBA request */
673 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
674
675 /* Queue to h/w without aggregation */
676 bf->bf_nframes = 1;
677 bf->bf_lastbf = bf->bf_lastfrm; /* one single frame */
678 ath_buf_set_rate(sc, bf);
679 ath_tx_txqaddbuf(sc, txq, bf_head);
680
681 return 0;
682 }
683
684 /* flush tid's software queue and send frames as non-ampdu's */
685
686 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
687 {
688 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum];
689 struct ath_buf *bf;
690 struct list_head bf_head;
691 INIT_LIST_HEAD(&bf_head);
692
693 ASSERT(tid->paused > 0);
694 spin_lock_bh(&txq->axq_lock);
695
696 tid->paused--;
697
698 if (tid->paused > 0) {
699 spin_unlock_bh(&txq->axq_lock);
700 return;
701 }
702
703 while (!list_empty(&tid->buf_q)) {
704 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
705 ASSERT(!bf_isretried(bf));
706 list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list);
707 ath_tx_send_normal(sc, txq, tid, &bf_head);
708 }
709
710 spin_unlock_bh(&txq->axq_lock);
711 }
712
713 /* Completion routine of an aggregate */
714
715 static void ath_tx_complete_aggr_rifs(struct ath_softc *sc,
716 struct ath_txq *txq,
717 struct ath_buf *bf,
718 struct list_head *bf_q,
719 int txok)
720 {
721 struct ath_node *an = NULL;
722 struct sk_buff *skb;
723 struct ieee80211_tx_info *tx_info;
724 struct ath_atx_tid *tid = NULL;
725 struct ath_buf *bf_last = bf->bf_lastbf;
726 struct ath_desc *ds = bf_last->bf_desc;
727 struct ath_buf *bf_next, *bf_lastq = NULL;
728 struct list_head bf_head, bf_pending;
729 u16 seq_st = 0;
730 u32 ba[WME_BA_BMP_SIZE >> 5];
731 int isaggr, txfail, txpending, sendbar = 0, needreset = 0;
732
733 skb = (struct sk_buff *)bf->bf_mpdu;
734 tx_info = IEEE80211_SKB_CB(skb);
735
736 if (tx_info->control.sta) {
737 an = (struct ath_node *)tx_info->control.sta->drv_priv;
738 tid = ATH_AN_2_TID(an, bf->bf_tidno);
739 }
740
741 isaggr = bf_isaggr(bf);
742 if (isaggr) {
743 if (txok) {
744 if (ATH_DS_TX_BA(ds)) {
745 /*
746 * extract starting sequence and
747 * block-ack bitmap
748 */
749 seq_st = ATH_DS_BA_SEQ(ds);
750 memcpy(ba,
751 ATH_DS_BA_BITMAP(ds),
752 WME_BA_BMP_SIZE >> 3);
753 } else {
754 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
755
756 /*
757 * AR5416 can become deaf/mute when BA
758 * issue happens. Chip needs to be reset.
759 * But AP code may have sychronization issues
760 * when perform internal reset in this routine.
761 * Only enable reset in STA mode for now.
762 */
763 if (sc->sc_ah->ah_opmode ==
764 NL80211_IFTYPE_STATION)
765 needreset = 1;
766 }
767 } else {
768 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
769 }
770 }
771
772 INIT_LIST_HEAD(&bf_pending);
773 INIT_LIST_HEAD(&bf_head);
774
775 while (bf) {
776 txfail = txpending = 0;
777 bf_next = bf->bf_next;
778
779 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
780 /* transmit completion, subframe is
781 * acked by block ack */
782 } else if (!isaggr && txok) {
783 /* transmit completion */
784 } else {
785
786 if (!(tid->state & AGGR_CLEANUP) &&
787 ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) {
788 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
789 ath_tx_set_retry(sc, bf);
790 txpending = 1;
791 } else {
792 bf->bf_state.bf_type |= BUF_XRETRY;
793 txfail = 1;
794 sendbar = 1;
795 }
796 } else {
797 /*
798 * cleanup in progress, just fail
799 * the un-acked sub-frames
800 */
801 txfail = 1;
802 }
803 }
804 /*
805 * Remove ath_buf's of this sub-frame from aggregate queue.
806 */
807 if (bf_next == NULL) { /* last subframe in the aggregate */
808 ASSERT(bf->bf_lastfrm == bf_last);
809
810 /*
811 * The last descriptor of the last sub frame could be
812 * a holding descriptor for h/w. If that's the case,
813 * bf->bf_lastfrm won't be in the bf_q.
814 * Make sure we handle bf_q properly here.
815 */
816
817 if (!list_empty(bf_q)) {
818 bf_lastq = list_entry(bf_q->prev,
819 struct ath_buf, list);
820 list_cut_position(&bf_head,
821 bf_q, &bf_lastq->list);
822 } else {
823 /*
824 * XXX: if the last subframe only has one
825 * descriptor which is also being used as
826 * a holding descriptor. Then the ath_buf
827 * is not in the bf_q at all.
828 */
829 INIT_LIST_HEAD(&bf_head);
830 }
831 } else {
832 ASSERT(!list_empty(bf_q));
833 list_cut_position(&bf_head,
834 bf_q, &bf->bf_lastfrm->list);
835 }
836
837 if (!txpending) {
838 /*
839 * complete the acked-ones/xretried ones; update
840 * block-ack window
841 */
842 spin_lock_bh(&txq->axq_lock);
843 ath_tx_update_baw(sc, tid, bf->bf_seqno);
844 spin_unlock_bh(&txq->axq_lock);
845
846 /* complete this sub-frame */
847 ath_tx_complete_buf(sc, bf, &bf_head, !txfail, sendbar);
848 } else {
849 /*
850 * retry the un-acked ones
851 */
852 /*
853 * XXX: if the last descriptor is holding descriptor,
854 * in order to requeue the frame to software queue, we
855 * need to allocate a new descriptor and
856 * copy the content of holding descriptor to it.
857 */
858 if (bf->bf_next == NULL &&
859 bf_last->bf_status & ATH_BUFSTATUS_STALE) {
860 struct ath_buf *tbf;
861
862 /* allocate new descriptor */
863 spin_lock_bh(&sc->sc_txbuflock);
864 ASSERT(!list_empty((&sc->sc_txbuf)));
865 tbf = list_first_entry(&sc->sc_txbuf,
866 struct ath_buf, list);
867 list_del(&tbf->list);
868 spin_unlock_bh(&sc->sc_txbuflock);
869
870 ATH_TXBUF_RESET(tbf);
871
872 /* copy descriptor content */
873 tbf->bf_mpdu = bf_last->bf_mpdu;
874 tbf->bf_buf_addr = bf_last->bf_buf_addr;
875 *(tbf->bf_desc) = *(bf_last->bf_desc);
876
877 /* link it to the frame */
878 if (bf_lastq) {
879 bf_lastq->bf_desc->ds_link =
880 tbf->bf_daddr;
881 bf->bf_lastfrm = tbf;
882 ath9k_hw_cleartxdesc(sc->sc_ah,
883 bf->bf_lastfrm->bf_desc);
884 } else {
885 tbf->bf_state = bf_last->bf_state;
886 tbf->bf_lastfrm = tbf;
887 ath9k_hw_cleartxdesc(sc->sc_ah,
888 tbf->bf_lastfrm->bf_desc);
889
890 /* copy the DMA context */
891 tbf->bf_dmacontext =
892 bf_last->bf_dmacontext;
893 }
894 list_add_tail(&tbf->list, &bf_head);
895 } else {
896 /*
897 * Clear descriptor status words for
898 * software retry
899 */
900 ath9k_hw_cleartxdesc(sc->sc_ah,
901 bf->bf_lastfrm->bf_desc);
902 }
903
904 /*
905 * Put this buffer to the temporary pending
906 * queue to retain ordering
907 */
908 list_splice_tail_init(&bf_head, &bf_pending);
909 }
910
911 bf = bf_next;
912 }
913
914 if (tid->state & AGGR_CLEANUP) {
915 /* check to see if we're done with cleaning the h/w queue */
916 spin_lock_bh(&txq->axq_lock);
917
918 if (tid->baw_head == tid->baw_tail) {
919 tid->state &= ~AGGR_ADDBA_COMPLETE;
920 tid->addba_exchangeattempts = 0;
921 spin_unlock_bh(&txq->axq_lock);
922
923 tid->state &= ~AGGR_CLEANUP;
924
925 /* send buffered frames as singles */
926 ath_tx_flush_tid(sc, tid);
927 } else
928 spin_unlock_bh(&txq->axq_lock);
929
930 return;
931 }
932
933 /*
934 * prepend un-acked frames to the beginning of the pending frame queue
935 */
936 if (!list_empty(&bf_pending)) {
937 spin_lock_bh(&txq->axq_lock);
938 /* Note: we _prepend_, we _do_not_ at to
939 * the end of the queue ! */
940 list_splice(&bf_pending, &tid->buf_q);
941 ath_tx_queue_tid(txq, tid);
942 spin_unlock_bh(&txq->axq_lock);
943 }
944
945 if (needreset)
946 ath_reset(sc, false);
947
948 return;
949 }
950
951 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds, int nbad)
952 {
953 struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu;
954 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
955 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
956
957 tx_info_priv->update_rc = false;
958 if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
959 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
960
961 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
962 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) {
963 if (bf_isdata(bf)) {
964 memcpy(&tx_info_priv->tx, &ds->ds_txstat,
965 sizeof(tx_info_priv->tx));
966 tx_info_priv->n_frames = bf->bf_nframes;
967 tx_info_priv->n_bad_frames = nbad;
968 tx_info_priv->update_rc = true;
969 }
970 }
971 }
972
973 /* Process completed xmit descriptors from the specified queue */
974
975 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
976 {
977 struct ath_hal *ah = sc->sc_ah;
978 struct ath_buf *bf, *lastbf, *bf_held = NULL;
979 struct list_head bf_head;
980 struct ath_desc *ds;
981 int txok, nbad = 0;
982 int status;
983
984 DPRINTF(sc, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
985 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
986 txq->axq_link);
987
988 for (;;) {
989 spin_lock_bh(&txq->axq_lock);
990 if (list_empty(&txq->axq_q)) {
991 txq->axq_link = NULL;
992 txq->axq_linkbuf = NULL;
993 spin_unlock_bh(&txq->axq_lock);
994 break;
995 }
996 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
997
998 /*
999 * There is a race condition that a BH gets scheduled
1000 * after sw writes TxE and before hw re-load the last
1001 * descriptor to get the newly chained one.
1002 * Software must keep the last DONE descriptor as a
1003 * holding descriptor - software does so by marking
1004 * it with the STALE flag.
1005 */
1006 bf_held = NULL;
1007 if (bf->bf_status & ATH_BUFSTATUS_STALE) {
1008 bf_held = bf;
1009 if (list_is_last(&bf_held->list, &txq->axq_q)) {
1010 /* FIXME:
1011 * The holding descriptor is the last
1012 * descriptor in queue. It's safe to remove
1013 * the last holding descriptor in BH context.
1014 */
1015 spin_unlock_bh(&txq->axq_lock);
1016 break;
1017 } else {
1018 /* Lets work with the next buffer now */
1019 bf = list_entry(bf_held->list.next,
1020 struct ath_buf, list);
1021 }
1022 }
1023
1024 lastbf = bf->bf_lastbf;
1025 ds = lastbf->bf_desc; /* NB: last decriptor */
1026
1027 status = ath9k_hw_txprocdesc(ah, ds);
1028 if (status == -EINPROGRESS) {
1029 spin_unlock_bh(&txq->axq_lock);
1030 break;
1031 }
1032 if (bf->bf_desc == txq->axq_lastdsWithCTS)
1033 txq->axq_lastdsWithCTS = NULL;
1034 if (ds == txq->axq_gatingds)
1035 txq->axq_gatingds = NULL;
1036
1037 /*
1038 * Remove ath_buf's of the same transmit unit from txq,
1039 * however leave the last descriptor back as the holding
1040 * descriptor for hw.
1041 */
1042 lastbf->bf_status |= ATH_BUFSTATUS_STALE;
1043 INIT_LIST_HEAD(&bf_head);
1044
1045 if (!list_is_singular(&lastbf->list))
1046 list_cut_position(&bf_head,
1047 &txq->axq_q, lastbf->list.prev);
1048
1049 txq->axq_depth--;
1050
1051 if (bf_isaggr(bf))
1052 txq->axq_aggr_depth--;
1053
1054 txok = (ds->ds_txstat.ts_status == 0);
1055
1056 spin_unlock_bh(&txq->axq_lock);
1057
1058 if (bf_held) {
1059 list_del(&bf_held->list);
1060 spin_lock_bh(&sc->sc_txbuflock);
1061 list_add_tail(&bf_held->list, &sc->sc_txbuf);
1062 spin_unlock_bh(&sc->sc_txbuflock);
1063 }
1064
1065 if (!bf_isampdu(bf)) {
1066 /*
1067 * This frame is sent out as a single frame.
1068 * Use hardware retry status for this frame.
1069 */
1070 bf->bf_retries = ds->ds_txstat.ts_longretry;
1071 if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY)
1072 bf->bf_state.bf_type |= BUF_XRETRY;
1073 nbad = 0;
1074 } else {
1075 nbad = ath_tx_num_badfrms(sc, bf, txok);
1076 }
1077
1078 ath_tx_rc_status(bf, ds, nbad);
1079
1080 /*
1081 * Complete this transmit unit
1082 */
1083 if (bf_isampdu(bf))
1084 ath_tx_complete_aggr_rifs(sc, txq, bf, &bf_head, txok);
1085 else
1086 ath_tx_complete_buf(sc, bf, &bf_head, txok, 0);
1087
1088 /* Wake up mac80211 queue */
1089
1090 spin_lock_bh(&txq->axq_lock);
1091 if (txq->stopped && ath_txq_depth(sc, txq->axq_qnum) <=
1092 (ATH_TXBUF - 20)) {
1093 int qnum;
1094 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc);
1095 if (qnum != -1) {
1096 ieee80211_wake_queue(sc->hw, qnum);
1097 txq->stopped = 0;
1098 }
1099
1100 }
1101
1102 /*
1103 * schedule any pending packets if aggregation is enabled
1104 */
1105 if (sc->sc_flags & SC_OP_TXAGGR)
1106 ath_txq_schedule(sc, txq);
1107 spin_unlock_bh(&txq->axq_lock);
1108 }
1109 }
1110
1111 static void ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
1112 {
1113 struct ath_hal *ah = sc->sc_ah;
1114
1115 (void) ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1116 DPRINTF(sc, ATH_DBG_XMIT, "tx queue [%u] %x, link %p\n",
1117 txq->axq_qnum, ath9k_hw_gettxbuf(ah, txq->axq_qnum),
1118 txq->axq_link);
1119 }
1120
1121 /* Drain only the data queues */
1122
1123 static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx)
1124 {
1125 struct ath_hal *ah = sc->sc_ah;
1126 int i, status, npend = 0;
1127
1128 if (!(sc->sc_flags & SC_OP_INVALID)) {
1129 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1130 if (ATH_TXQ_SETUP(sc, i)) {
1131 ath_tx_stopdma(sc, &sc->sc_txq[i]);
1132 /* The TxDMA may not really be stopped.
1133 * Double check the hal tx pending count */
1134 npend += ath9k_hw_numtxpending(ah,
1135 sc->sc_txq[i].axq_qnum);
1136 }
1137 }
1138 }
1139
1140 if (npend) {
1141 /* TxDMA not stopped, reset the hal */
1142 DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n");
1143
1144 spin_lock_bh(&sc->sc_resetlock);
1145 if (!ath9k_hw_reset(ah,
1146 sc->sc_ah->ah_curchan,
1147 sc->tx_chan_width,
1148 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1149 sc->sc_ht_extprotspacing, true, &status)) {
1150
1151 DPRINTF(sc, ATH_DBG_FATAL,
1152 "Unable to reset hardware; hal status %u\n",
1153 status);
1154 }
1155 spin_unlock_bh(&sc->sc_resetlock);
1156 }
1157
1158 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1159 if (ATH_TXQ_SETUP(sc, i))
1160 ath_tx_draintxq(sc, &sc->sc_txq[i], retry_tx);
1161 }
1162 }
1163
1164 /* Add a sub-frame to block ack window */
1165
1166 static void ath_tx_addto_baw(struct ath_softc *sc,
1167 struct ath_atx_tid *tid,
1168 struct ath_buf *bf)
1169 {
1170 int index, cindex;
1171
1172 if (bf_isretried(bf))
1173 return;
1174
1175 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
1176 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
1177
1178 ASSERT(tid->tx_buf[cindex] == NULL);
1179 tid->tx_buf[cindex] = bf;
1180
1181 if (index >= ((tid->baw_tail - tid->baw_head) &
1182 (ATH_TID_MAX_BUFS - 1))) {
1183 tid->baw_tail = cindex;
1184 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
1185 }
1186 }
1187
1188 /*
1189 * Function to send an A-MPDU
1190 * NB: must be called with txq lock held
1191 */
1192 static int ath_tx_send_ampdu(struct ath_softc *sc,
1193 struct ath_atx_tid *tid,
1194 struct list_head *bf_head,
1195 struct ath_tx_control *txctl)
1196 {
1197 struct ath_buf *bf;
1198
1199 BUG_ON(list_empty(bf_head));
1200
1201 bf = list_first_entry(bf_head, struct ath_buf, list);
1202 bf->bf_state.bf_type |= BUF_AMPDU;
1203
1204 /*
1205 * Do not queue to h/w when any of the following conditions is true:
1206 * - there are pending frames in software queue
1207 * - the TID is currently paused for ADDBA/BAR request
1208 * - seqno is not within block-ack window
1209 * - h/w queue depth exceeds low water mark
1210 */
1211 if (!list_empty(&tid->buf_q) || tid->paused ||
1212 !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
1213 txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
1214 /*
1215 * Add this frame to software queue for scheduling later
1216 * for aggregation.
1217 */
1218 list_splice_tail_init(bf_head, &tid->buf_q);
1219 ath_tx_queue_tid(txctl->txq, tid);
1220 return 0;
1221 }
1222
1223 /* Add sub-frame to BAW */
1224 ath_tx_addto_baw(sc, tid, bf);
1225
1226 /* Queue to h/w without aggregation */
1227 bf->bf_nframes = 1;
1228 bf->bf_lastbf = bf->bf_lastfrm; /* one single frame */
1229 ath_buf_set_rate(sc, bf);
1230 ath_tx_txqaddbuf(sc, txctl->txq, bf_head);
1231
1232 return 0;
1233 }
1234
1235 /*
1236 * looks up the rate
1237 * returns aggr limit based on lowest of the rates
1238 */
1239 static u32 ath_lookup_rate(struct ath_softc *sc,
1240 struct ath_buf *bf,
1241 struct ath_atx_tid *tid)
1242 {
1243 struct ath_rate_table *rate_table = sc->hw_rate_table[sc->sc_curmode];
1244 struct sk_buff *skb;
1245 struct ieee80211_tx_info *tx_info;
1246 struct ieee80211_tx_rate *rates;
1247 struct ath_tx_info_priv *tx_info_priv;
1248 u32 max_4ms_framelen, frame_length;
1249 u16 aggr_limit, legacy = 0, maxampdu;
1250 int i;
1251
1252 skb = (struct sk_buff *)bf->bf_mpdu;
1253 tx_info = IEEE80211_SKB_CB(skb);
1254 rates = tx_info->control.rates;
1255 tx_info_priv =
1256 (struct ath_tx_info_priv *)tx_info->rate_driver_data[0];
1257
1258 /*
1259 * Find the lowest frame length among the rate series that will have a
1260 * 4ms transmit duration.
1261 * TODO - TXOP limit needs to be considered.
1262 */
1263 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
1264
1265 for (i = 0; i < 4; i++) {
1266 if (rates[i].count) {
1267 if (!WLAN_RC_PHY_HT(rate_table->info[rates[i].idx].phy)) {
1268 legacy = 1;
1269 break;
1270 }
1271
1272 frame_length =
1273 rate_table->info[rates[i].idx].max_4ms_framelen;
1274 max_4ms_framelen = min(max_4ms_framelen, frame_length);
1275 }
1276 }
1277
1278 /*
1279 * limit aggregate size by the minimum rate if rate selected is
1280 * not a probe rate, if rate selected is a probe rate then
1281 * avoid aggregation of this packet.
1282 */
1283 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
1284 return 0;
1285
1286 aggr_limit = min(max_4ms_framelen,
1287 (u32)ATH_AMPDU_LIMIT_DEFAULT);
1288
1289 /*
1290 * h/w can accept aggregates upto 16 bit lengths (65535).
1291 * The IE, however can hold upto 65536, which shows up here
1292 * as zero. Ignore 65536 since we are constrained by hw.
1293 */
1294 maxampdu = tid->an->maxampdu;
1295 if (maxampdu)
1296 aggr_limit = min(aggr_limit, maxampdu);
1297
1298 return aggr_limit;
1299 }
1300
1301 /*
1302 * returns the number of delimiters to be added to
1303 * meet the minimum required mpdudensity.
1304 * caller should make sure that the rate is HT rate .
1305 */
1306 static int ath_compute_num_delims(struct ath_softc *sc,
1307 struct ath_atx_tid *tid,
1308 struct ath_buf *bf,
1309 u16 frmlen)
1310 {
1311 struct ath_rate_table *rt = sc->hw_rate_table[sc->sc_curmode];
1312 struct sk_buff *skb = bf->bf_mpdu;
1313 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1314 u32 nsymbits, nsymbols, mpdudensity;
1315 u16 minlen;
1316 u8 rc, flags, rix;
1317 int width, half_gi, ndelim, mindelim;
1318
1319 /* Select standard number of delimiters based on frame length alone */
1320 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
1321
1322 /*
1323 * If encryption enabled, hardware requires some more padding between
1324 * subframes.
1325 * TODO - this could be improved to be dependent on the rate.
1326 * The hardware can keep up at lower rates, but not higher rates
1327 */
1328 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
1329 ndelim += ATH_AGGR_ENCRYPTDELIM;
1330
1331 /*
1332 * Convert desired mpdu density from microeconds to bytes based
1333 * on highest rate in rate series (i.e. first rate) to determine
1334 * required minimum length for subframe. Take into account
1335 * whether high rate is 20 or 40Mhz and half or full GI.
1336 */
1337 mpdudensity = tid->an->mpdudensity;
1338
1339 /*
1340 * If there is no mpdu density restriction, no further calculation
1341 * is needed.
1342 */
1343 if (mpdudensity == 0)
1344 return ndelim;
1345
1346 rix = tx_info->control.rates[0].idx;
1347 flags = tx_info->control.rates[0].flags;
1348 rc = rt->info[rix].ratecode;
1349 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
1350 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
1351
1352 if (half_gi)
1353 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity);
1354 else
1355 nsymbols = NUM_SYMBOLS_PER_USEC(mpdudensity);
1356
1357 if (nsymbols == 0)
1358 nsymbols = 1;
1359
1360 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
1361 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
1362
1363 /* Is frame shorter than required minimum length? */
1364 if (frmlen < minlen) {
1365 /* Get the minimum number of delimiters required. */
1366 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
1367 ndelim = max(mindelim, ndelim);
1368 }
1369
1370 return ndelim;
1371 }
1372
1373 /*
1374 * For aggregation from software buffer queue.
1375 * NB: must be called with txq lock held
1376 */
1377 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
1378 struct ath_atx_tid *tid,
1379 struct list_head *bf_q,
1380 struct ath_buf **bf_last,
1381 struct aggr_rifs_param *param,
1382 int *prev_frames)
1383 {
1384 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
1385 struct ath_buf *bf, *tbf, *bf_first, *bf_prev = NULL;
1386 struct list_head bf_head;
1387 int rl = 0, nframes = 0, ndelim;
1388 u16 aggr_limit = 0, al = 0, bpad = 0,
1389 al_delta, h_baw = tid->baw_size / 2;
1390 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
1391 int prev_al = 0;
1392 INIT_LIST_HEAD(&bf_head);
1393
1394 BUG_ON(list_empty(&tid->buf_q));
1395
1396 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
1397
1398 do {
1399 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
1400
1401 /*
1402 * do not step over block-ack window
1403 */
1404 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
1405 status = ATH_AGGR_BAW_CLOSED;
1406 break;
1407 }
1408
1409 if (!rl) {
1410 aggr_limit = ath_lookup_rate(sc, bf, tid);
1411 rl = 1;
1412 }
1413
1414 /*
1415 * do not exceed aggregation limit
1416 */
1417 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
1418
1419 if (nframes && (aggr_limit <
1420 (al + bpad + al_delta + prev_al))) {
1421 status = ATH_AGGR_LIMITED;
1422 break;
1423 }
1424
1425 /*
1426 * do not exceed subframe limit
1427 */
1428 if ((nframes + *prev_frames) >=
1429 min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
1430 status = ATH_AGGR_LIMITED;
1431 break;
1432 }
1433
1434 /*
1435 * add padding for previous frame to aggregation length
1436 */
1437 al += bpad + al_delta;
1438
1439 /*
1440 * Get the delimiters needed to meet the MPDU
1441 * density for this node.
1442 */
1443 ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen);
1444
1445 bpad = PADBYTES(al_delta) + (ndelim << 2);
1446
1447 bf->bf_next = NULL;
1448 bf->bf_lastfrm->bf_desc->ds_link = 0;
1449
1450 /*
1451 * this packet is part of an aggregate
1452 * - remove all descriptors belonging to this frame from
1453 * software queue
1454 * - add it to block ack window
1455 * - set up descriptors for aggregation
1456 */
1457 list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list);
1458 ath_tx_addto_baw(sc, tid, bf);
1459
1460 list_for_each_entry(tbf, &bf_head, list) {
1461 ath9k_hw_set11n_aggr_middle(sc->sc_ah,
1462 tbf->bf_desc, ndelim);
1463 }
1464
1465 /*
1466 * link buffers of this frame to the aggregate
1467 */
1468 list_splice_tail_init(&bf_head, bf_q);
1469 nframes++;
1470
1471 if (bf_prev) {
1472 bf_prev->bf_next = bf;
1473 bf_prev->bf_lastfrm->bf_desc->ds_link = bf->bf_daddr;
1474 }
1475 bf_prev = bf;
1476
1477 #ifdef AGGR_NOSHORT
1478 /*
1479 * terminate aggregation on a small packet boundary
1480 */
1481 if (bf->bf_frmlen < ATH_AGGR_MINPLEN) {
1482 status = ATH_AGGR_SHORTPKT;
1483 break;
1484 }
1485 #endif
1486 } while (!list_empty(&tid->buf_q));
1487
1488 bf_first->bf_al = al;
1489 bf_first->bf_nframes = nframes;
1490 *bf_last = bf_prev;
1491 return status;
1492 #undef PADBYTES
1493 }
1494
1495 /*
1496 * process pending frames possibly doing a-mpdu aggregation
1497 * NB: must be called with txq lock held
1498 */
1499 static void ath_tx_sched_aggr(struct ath_softc *sc,
1500 struct ath_txq *txq, struct ath_atx_tid *tid)
1501 {
1502 struct ath_buf *bf, *tbf, *bf_last, *bf_lastaggr = NULL;
1503 enum ATH_AGGR_STATUS status;
1504 struct list_head bf_q;
1505 struct aggr_rifs_param param = {0, 0, 0, 0, NULL};
1506 int prev_frames = 0;
1507
1508 do {
1509 if (list_empty(&tid->buf_q))
1510 return;
1511
1512 INIT_LIST_HEAD(&bf_q);
1513
1514 status = ath_tx_form_aggr(sc, tid, &bf_q, &bf_lastaggr, &param,
1515 &prev_frames);
1516
1517 /*
1518 * no frames picked up to be aggregated; block-ack
1519 * window is not open
1520 */
1521 if (list_empty(&bf_q))
1522 break;
1523
1524 bf = list_first_entry(&bf_q, struct ath_buf, list);
1525 bf_last = list_entry(bf_q.prev, struct ath_buf, list);
1526 bf->bf_lastbf = bf_last;
1527
1528 /*
1529 * if only one frame, send as non-aggregate
1530 */
1531 if (bf->bf_nframes == 1) {
1532 ASSERT(bf->bf_lastfrm == bf_last);
1533
1534 bf->bf_state.bf_type &= ~BUF_AGGR;
1535 /*
1536 * clear aggr bits for every descriptor
1537 * XXX TODO: is there a way to optimize it?
1538 */
1539 list_for_each_entry(tbf, &bf_q, list) {
1540 ath9k_hw_clr11n_aggr(sc->sc_ah, tbf->bf_desc);
1541 }
1542
1543 ath_buf_set_rate(sc, bf);
1544 ath_tx_txqaddbuf(sc, txq, &bf_q);
1545 continue;
1546 }
1547
1548 /*
1549 * setup first desc with rate and aggr info
1550 */
1551 bf->bf_state.bf_type |= BUF_AGGR;
1552 ath_buf_set_rate(sc, bf);
1553 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
1554
1555 /*
1556 * anchor last frame of aggregate correctly
1557 */
1558 ASSERT(bf_lastaggr);
1559 ASSERT(bf_lastaggr->bf_lastfrm == bf_last);
1560 tbf = bf_lastaggr;
1561 ath9k_hw_set11n_aggr_last(sc->sc_ah, tbf->bf_desc);
1562
1563 /* XXX: We don't enter into this loop, consider removing this */
1564 while (!list_empty(&bf_q) && !list_is_last(&tbf->list, &bf_q)) {
1565 tbf = list_entry(tbf->list.next, struct ath_buf, list);
1566 ath9k_hw_set11n_aggr_last(sc->sc_ah, tbf->bf_desc);
1567 }
1568
1569 txq->axq_aggr_depth++;
1570
1571 /*
1572 * Normal aggregate, queue to hardware
1573 */
1574 ath_tx_txqaddbuf(sc, txq, &bf_q);
1575
1576 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
1577 status != ATH_AGGR_BAW_CLOSED);
1578 }
1579
1580 /* Called with txq lock held */
1581
1582 static void ath_tid_drain(struct ath_softc *sc,
1583 struct ath_txq *txq,
1584 struct ath_atx_tid *tid)
1585
1586 {
1587 struct ath_buf *bf;
1588 struct list_head bf_head;
1589 INIT_LIST_HEAD(&bf_head);
1590
1591 for (;;) {
1592 if (list_empty(&tid->buf_q))
1593 break;
1594 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
1595
1596 list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list);
1597
1598 /* update baw for software retried frame */
1599 if (bf_isretried(bf))
1600 ath_tx_update_baw(sc, tid, bf->bf_seqno);
1601
1602 /*
1603 * do not indicate packets while holding txq spinlock.
1604 * unlock is intentional here
1605 */
1606 spin_unlock(&txq->axq_lock);
1607
1608 /* complete this sub-frame */
1609 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
1610
1611 spin_lock(&txq->axq_lock);
1612 }
1613
1614 /*
1615 * TODO: For frame(s) that are in the retry state, we will reuse the
1616 * sequence number(s) without setting the retry bit. The
1617 * alternative is to give up on these and BAR the receiver's window
1618 * forward.
1619 */
1620 tid->seq_next = tid->seq_start;
1621 tid->baw_tail = tid->baw_head;
1622 }
1623
1624 /*
1625 * Drain all pending buffers
1626 * NB: must be called with txq lock held
1627 */
1628 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
1629 struct ath_txq *txq)
1630 {
1631 struct ath_atx_ac *ac, *ac_tmp;
1632 struct ath_atx_tid *tid, *tid_tmp;
1633
1634 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1635 list_del(&ac->list);
1636 ac->sched = false;
1637 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
1638 list_del(&tid->list);
1639 tid->sched = false;
1640 ath_tid_drain(sc, txq, tid);
1641 }
1642 }
1643 }
1644
1645 static int ath_tx_setup_buffer(struct ath_softc *sc, struct ath_buf *bf,
1646 struct sk_buff *skb,
1647 struct ath_tx_control *txctl)
1648 {
1649 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1650 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1651 struct ath_tx_info_priv *tx_info_priv;
1652 int hdrlen;
1653 __le16 fc;
1654
1655 tx_info_priv = kzalloc(sizeof(*tx_info_priv), GFP_KERNEL);
1656 tx_info->rate_driver_data[0] = tx_info_priv;
1657 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1658 fc = hdr->frame_control;
1659
1660 ATH_TXBUF_RESET(bf);
1661
1662 /* Frame type */
1663
1664 bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3);
1665
1666 ieee80211_is_data(fc) ?
1667 (bf->bf_state.bf_type |= BUF_DATA) :
1668 (bf->bf_state.bf_type &= ~BUF_DATA);
1669 ieee80211_is_back_req(fc) ?
1670 (bf->bf_state.bf_type |= BUF_BAR) :
1671 (bf->bf_state.bf_type &= ~BUF_BAR);
1672 ieee80211_is_pspoll(fc) ?
1673 (bf->bf_state.bf_type |= BUF_PSPOLL) :
1674 (bf->bf_state.bf_type &= ~BUF_PSPOLL);
1675 (sc->sc_flags & SC_OP_PREAMBLE_SHORT) ?
1676 (bf->bf_state.bf_type |= BUF_SHORT_PREAMBLE) :
1677 (bf->bf_state.bf_type &= ~BUF_SHORT_PREAMBLE);
1678 (sc->hw->conf.ht.enabled && !is_pae(skb) &&
1679 (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) ?
1680 (bf->bf_state.bf_type |= BUF_HT) :
1681 (bf->bf_state.bf_type &= ~BUF_HT);
1682
1683 bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq);
1684
1685 /* Crypto */
1686
1687 bf->bf_keytype = get_hw_crypto_keytype(skb);
1688
1689 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
1690 bf->bf_frmlen += tx_info->control.hw_key->icv_len;
1691 bf->bf_keyix = tx_info->control.hw_key->hw_key_idx;
1692 } else {
1693 bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
1694 }
1695
1696 /* Assign seqno, tidno */
1697
1698 if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR))
1699 assign_aggr_tid_seqno(skb, bf);
1700
1701 /* DMA setup */
1702
1703 bf->bf_mpdu = skb;
1704
1705 bf->bf_dmacontext = pci_map_single(sc->pdev, skb->data,
1706 skb->len, PCI_DMA_TODEVICE);
1707 if (unlikely(pci_dma_mapping_error(sc->pdev, bf->bf_dmacontext))) {
1708 bf->bf_mpdu = NULL;
1709 DPRINTF(sc, ATH_DBG_CONFIG,
1710 "pci_dma_mapping_error() on TX\n");
1711 return -ENOMEM;
1712 }
1713
1714 bf->bf_buf_addr = bf->bf_dmacontext;
1715 return 0;
1716 }
1717
1718 /* FIXME: tx power */
1719 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1720 struct ath_tx_control *txctl)
1721 {
1722 struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu;
1723 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1724 struct ath_node *an = NULL;
1725 struct list_head bf_head;
1726 struct ath_desc *ds;
1727 struct ath_atx_tid *tid;
1728 struct ath_hal *ah = sc->sc_ah;
1729 int frm_type;
1730
1731 frm_type = get_hw_packet_type(skb);
1732
1733 INIT_LIST_HEAD(&bf_head);
1734 list_add_tail(&bf->list, &bf_head);
1735
1736 /* setup descriptor */
1737
1738 ds = bf->bf_desc;
1739 ds->ds_link = 0;
1740 ds->ds_data = bf->bf_buf_addr;
1741
1742 /* Formulate first tx descriptor with tx controls */
1743
1744 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
1745 bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
1746
1747 ath9k_hw_filltxdesc(ah, ds,
1748 skb->len, /* segment length */
1749 true, /* first segment */
1750 true, /* last segment */
1751 ds); /* first descriptor */
1752
1753 bf->bf_lastfrm = bf;
1754
1755 spin_lock_bh(&txctl->txq->axq_lock);
1756
1757 if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) &&
1758 tx_info->control.sta) {
1759 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1760 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1761
1762 if (ath_aggr_query(sc, an, bf->bf_tidno)) {
1763 /*
1764 * Try aggregation if it's a unicast data frame
1765 * and the destination is HT capable.
1766 */
1767 ath_tx_send_ampdu(sc, tid, &bf_head, txctl);
1768 } else {
1769 /*
1770 * Send this frame as regular when ADDBA
1771 * exchange is neither complete nor pending.
1772 */
1773 ath_tx_send_normal(sc, txctl->txq,
1774 tid, &bf_head);
1775 }
1776 } else {
1777 bf->bf_lastbf = bf;
1778 bf->bf_nframes = 1;
1779
1780 ath_buf_set_rate(sc, bf);
1781 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head);
1782 }
1783
1784 spin_unlock_bh(&txctl->txq->axq_lock);
1785 }
1786
1787 /* Upon failure caller should free skb */
1788 int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
1789 struct ath_tx_control *txctl)
1790 {
1791 struct ath_buf *bf;
1792 int r;
1793
1794 /* Check if a tx buffer is available */
1795
1796 bf = ath_tx_get_buffer(sc);
1797 if (!bf) {
1798 DPRINTF(sc, ATH_DBG_XMIT, "TX buffers are full\n");
1799 return -1;
1800 }
1801
1802 r = ath_tx_setup_buffer(sc, bf, skb, txctl);
1803 if (unlikely(r)) {
1804 spin_lock_bh(&sc->sc_txbuflock);
1805 DPRINTF(sc, ATH_DBG_FATAL, "TX mem alloc failure\n");
1806 list_add_tail(&bf->list, &sc->sc_txbuf);
1807 spin_unlock_bh(&sc->sc_txbuflock);
1808 return r;
1809 }
1810
1811 ath_tx_start_dma(sc, bf, txctl);
1812
1813 return 0;
1814 }
1815
1816 /* Initialize TX queue and h/w */
1817
1818 int ath_tx_init(struct ath_softc *sc, int nbufs)
1819 {
1820 int error = 0;
1821
1822 do {
1823 spin_lock_init(&sc->sc_txbuflock);
1824
1825 /* Setup tx descriptors */
1826 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
1827 "tx", nbufs, 1);
1828 if (error != 0) {
1829 DPRINTF(sc, ATH_DBG_FATAL,
1830 "Failed to allocate tx descriptors: %d\n",
1831 error);
1832 break;
1833 }
1834
1835 /* XXX allocate beacon state together with vap */
1836 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
1837 "beacon", ATH_BCBUF, 1);
1838 if (error != 0) {
1839 DPRINTF(sc, ATH_DBG_FATAL,
1840 "Failed to allocate beacon descriptors: %d\n",
1841 error);
1842 break;
1843 }
1844
1845 } while (0);
1846
1847 if (error != 0)
1848 ath_tx_cleanup(sc);
1849
1850 return error;
1851 }
1852
1853 /* Reclaim all tx queue resources */
1854
1855 int ath_tx_cleanup(struct ath_softc *sc)
1856 {
1857 /* cleanup beacon descriptors */
1858 if (sc->sc_bdma.dd_desc_len != 0)
1859 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
1860
1861 /* cleanup tx descriptors */
1862 if (sc->sc_txdma.dd_desc_len != 0)
1863 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
1864
1865 return 0;
1866 }
1867
1868 /* Setup a h/w transmit queue */
1869
1870 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1871 {
1872 struct ath_hal *ah = sc->sc_ah;
1873 struct ath9k_tx_queue_info qi;
1874 int qnum;
1875
1876 memset(&qi, 0, sizeof(qi));
1877 qi.tqi_subtype = subtype;
1878 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1879 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1880 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1881 qi.tqi_physCompBuf = 0;
1882
1883 /*
1884 * Enable interrupts only for EOL and DESC conditions.
1885 * We mark tx descriptors to receive a DESC interrupt
1886 * when a tx queue gets deep; otherwise waiting for the
1887 * EOL to reap descriptors. Note that this is done to
1888 * reduce interrupt load and this only defers reaping
1889 * descriptors, never transmitting frames. Aside from
1890 * reducing interrupts this also permits more concurrency.
1891 * The only potential downside is if the tx queue backs
1892 * up in which case the top half of the kernel may backup
1893 * due to a lack of tx descriptors.
1894 *
1895 * The UAPSD queue is an exception, since we take a desc-
1896 * based intr on the EOSP frames.
1897 */
1898 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1899 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1900 else
1901 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1902 TXQ_FLAG_TXDESCINT_ENABLE;
1903 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1904 if (qnum == -1) {
1905 /*
1906 * NB: don't print a message, this happens
1907 * normally on parts with too few tx queues
1908 */
1909 return NULL;
1910 }
1911 if (qnum >= ARRAY_SIZE(sc->sc_txq)) {
1912 DPRINTF(sc, ATH_DBG_FATAL,
1913 "qnum %u out of range, max %u!\n",
1914 qnum, (unsigned int)ARRAY_SIZE(sc->sc_txq));
1915 ath9k_hw_releasetxqueue(ah, qnum);
1916 return NULL;
1917 }
1918 if (!ATH_TXQ_SETUP(sc, qnum)) {
1919 struct ath_txq *txq = &sc->sc_txq[qnum];
1920
1921 txq->axq_qnum = qnum;
1922 txq->axq_link = NULL;
1923 INIT_LIST_HEAD(&txq->axq_q);
1924 INIT_LIST_HEAD(&txq->axq_acq);
1925 spin_lock_init(&txq->axq_lock);
1926 txq->axq_depth = 0;
1927 txq->axq_aggr_depth = 0;
1928 txq->axq_totalqueued = 0;
1929 txq->axq_linkbuf = NULL;
1930 sc->sc_txqsetup |= 1<<qnum;
1931 }
1932 return &sc->sc_txq[qnum];
1933 }
1934
1935 /* Reclaim resources for a setup queue */
1936
1937 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1938 {
1939 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1940 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
1941 }
1942
1943 /*
1944 * Setup a hardware data transmit queue for the specified
1945 * access control. The hal may not support all requested
1946 * queues in which case it will return a reference to a
1947 * previously setup queue. We record the mapping from ac's
1948 * to h/w queues for use by ath_tx_start and also track
1949 * the set of h/w queues being used to optimize work in the
1950 * transmit interrupt handler and related routines.
1951 */
1952
1953 int ath_tx_setup(struct ath_softc *sc, int haltype)
1954 {
1955 struct ath_txq *txq;
1956
1957 if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) {
1958 DPRINTF(sc, ATH_DBG_FATAL,
1959 "HAL AC %u out of range, max %zu!\n",
1960 haltype, ARRAY_SIZE(sc->sc_haltype2q));
1961 return 0;
1962 }
1963 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
1964 if (txq != NULL) {
1965 sc->sc_haltype2q[haltype] = txq->axq_qnum;
1966 return 1;
1967 } else
1968 return 0;
1969 }
1970
1971 int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
1972 {
1973 int qnum;
1974
1975 switch (qtype) {
1976 case ATH9K_TX_QUEUE_DATA:
1977 if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) {
1978 DPRINTF(sc, ATH_DBG_FATAL,
1979 "HAL AC %u out of range, max %zu!\n",
1980 haltype, ARRAY_SIZE(sc->sc_haltype2q));
1981 return -1;
1982 }
1983 qnum = sc->sc_haltype2q[haltype];
1984 break;
1985 case ATH9K_TX_QUEUE_BEACON:
1986 qnum = sc->sc_bhalq;
1987 break;
1988 case ATH9K_TX_QUEUE_CAB:
1989 qnum = sc->sc_cabq->axq_qnum;
1990 break;
1991 default:
1992 qnum = -1;
1993 }
1994 return qnum;
1995 }
1996
1997 /* Get a transmit queue, if available */
1998
1999 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
2000 {
2001 struct ath_txq *txq = NULL;
2002 int qnum;
2003
2004 qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
2005 txq = &sc->sc_txq[qnum];
2006
2007 spin_lock_bh(&txq->axq_lock);
2008
2009 /* Try to avoid running out of descriptors */
2010 if (txq->axq_depth >= (ATH_TXBUF - 20)) {
2011 DPRINTF(sc, ATH_DBG_FATAL,
2012 "TX queue: %d is full, depth: %d\n",
2013 qnum, txq->axq_depth);
2014 ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb));
2015 txq->stopped = 1;
2016 spin_unlock_bh(&txq->axq_lock);
2017 return NULL;
2018 }
2019
2020 spin_unlock_bh(&txq->axq_lock);
2021
2022 return txq;
2023 }
2024
2025 /* Update parameters for a transmit queue */
2026
2027 int ath_txq_update(struct ath_softc *sc, int qnum,
2028 struct ath9k_tx_queue_info *qinfo)
2029 {
2030 struct ath_hal *ah = sc->sc_ah;
2031 int error = 0;
2032 struct ath9k_tx_queue_info qi;
2033
2034 if (qnum == sc->sc_bhalq) {
2035 /*
2036 * XXX: for beacon queue, we just save the parameter.
2037 * It will be picked up by ath_beaconq_config when
2038 * it's necessary.
2039 */
2040 sc->sc_beacon_qi = *qinfo;
2041 return 0;
2042 }
2043
2044 ASSERT(sc->sc_txq[qnum].axq_qnum == qnum);
2045
2046 ath9k_hw_get_txq_props(ah, qnum, &qi);
2047 qi.tqi_aifs = qinfo->tqi_aifs;
2048 qi.tqi_cwmin = qinfo->tqi_cwmin;
2049 qi.tqi_cwmax = qinfo->tqi_cwmax;
2050 qi.tqi_burstTime = qinfo->tqi_burstTime;
2051 qi.tqi_readyTime = qinfo->tqi_readyTime;
2052
2053 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
2054 DPRINTF(sc, ATH_DBG_FATAL,
2055 "Unable to update hardware queue %u!\n", qnum);
2056 error = -EIO;
2057 } else {
2058 ath9k_hw_resettxqueue(ah, qnum); /* push to h/w */
2059 }
2060
2061 return error;
2062 }
2063
2064 int ath_cabq_update(struct ath_softc *sc)
2065 {
2066 struct ath9k_tx_queue_info qi;
2067 int qnum = sc->sc_cabq->axq_qnum;
2068 struct ath_beacon_config conf;
2069
2070 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
2071 /*
2072 * Ensure the readytime % is within the bounds.
2073 */
2074 if (sc->sc_config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
2075 sc->sc_config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
2076 else if (sc->sc_config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
2077 sc->sc_config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
2078
2079 ath_get_beaconconfig(sc, ATH_IF_ID_ANY, &conf);
2080 qi.tqi_readyTime =
2081 (conf.beacon_interval * sc->sc_config.cabqReadytime) / 100;
2082 ath_txq_update(sc, qnum, &qi);
2083
2084 return 0;
2085 }
2086
2087 /* Deferred processing of transmit interrupt */
2088
2089 void ath_tx_tasklet(struct ath_softc *sc)
2090 {
2091 int i;
2092 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2093
2094 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2095
2096 /*
2097 * Process each active queue.
2098 */
2099 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2100 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2101 ath_tx_processq(sc, &sc->sc_txq[i]);
2102 }
2103 }
2104
2105 void ath_tx_draintxq(struct ath_softc *sc,
2106 struct ath_txq *txq, bool retry_tx)
2107 {
2108 struct ath_buf *bf, *lastbf;
2109 struct list_head bf_head;
2110
2111 INIT_LIST_HEAD(&bf_head);
2112
2113 /*
2114 * NB: this assumes output has been stopped and
2115 * we do not need to block ath_tx_tasklet
2116 */
2117 for (;;) {
2118 spin_lock_bh(&txq->axq_lock);
2119
2120 if (list_empty(&txq->axq_q)) {
2121 txq->axq_link = NULL;
2122 txq->axq_linkbuf = NULL;
2123 spin_unlock_bh(&txq->axq_lock);
2124 break;
2125 }
2126
2127 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2128
2129 if (bf->bf_status & ATH_BUFSTATUS_STALE) {
2130 list_del(&bf->list);
2131 spin_unlock_bh(&txq->axq_lock);
2132
2133 spin_lock_bh(&sc->sc_txbuflock);
2134 list_add_tail(&bf->list, &sc->sc_txbuf);
2135 spin_unlock_bh(&sc->sc_txbuflock);
2136 continue;
2137 }
2138
2139 lastbf = bf->bf_lastbf;
2140 if (!retry_tx)
2141 lastbf->bf_desc->ds_txstat.ts_flags =
2142 ATH9K_TX_SW_ABORTED;
2143
2144 /* remove ath_buf's of the same mpdu from txq */
2145 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
2146 txq->axq_depth--;
2147
2148 spin_unlock_bh(&txq->axq_lock);
2149
2150 if (bf_isampdu(bf))
2151 ath_tx_complete_aggr_rifs(sc, txq, bf, &bf_head, 0);
2152 else
2153 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
2154 }
2155
2156 /* flush any pending frames if aggregation is enabled */
2157 if (sc->sc_flags & SC_OP_TXAGGR) {
2158 if (!retry_tx) {
2159 spin_lock_bh(&txq->axq_lock);
2160 ath_txq_drain_pending_buffers(sc, txq);
2161 spin_unlock_bh(&txq->axq_lock);
2162 }
2163 }
2164 }
2165
2166 /* Drain the transmit queues and reclaim resources */
2167
2168 void ath_draintxq(struct ath_softc *sc, bool retry_tx)
2169 {
2170 /* stop beacon queue. The beacon will be freed when
2171 * we go to INIT state */
2172 if (!(sc->sc_flags & SC_OP_INVALID)) {
2173 (void) ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
2174 DPRINTF(sc, ATH_DBG_XMIT, "beacon queue %x\n",
2175 ath9k_hw_gettxbuf(sc->sc_ah, sc->sc_bhalq));
2176 }
2177
2178 ath_drain_txdataq(sc, retry_tx);
2179 }
2180
2181 u32 ath_txq_depth(struct ath_softc *sc, int qnum)
2182 {
2183 return sc->sc_txq[qnum].axq_depth;
2184 }
2185
2186 u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum)
2187 {
2188 return sc->sc_txq[qnum].axq_aggr_depth;
2189 }
2190
2191 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno)
2192 {
2193 struct ath_atx_tid *txtid;
2194
2195 if (!(sc->sc_flags & SC_OP_TXAGGR))
2196 return false;
2197
2198 txtid = ATH_AN_2_TID(an, tidno);
2199
2200 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
2201 if (!(txtid->state & AGGR_ADDBA_PROGRESS) &&
2202 (txtid->addba_exchangeattempts < ADDBA_EXCHANGE_ATTEMPTS)) {
2203 txtid->addba_exchangeattempts++;
2204 return true;
2205 }
2206 }
2207
2208 return false;
2209 }
2210
2211 /* Start TX aggregation */
2212
2213 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
2214 u16 tid, u16 *ssn)
2215 {
2216 struct ath_atx_tid *txtid;
2217 struct ath_node *an;
2218
2219 an = (struct ath_node *)sta->drv_priv;
2220
2221 if (sc->sc_flags & SC_OP_TXAGGR) {
2222 txtid = ATH_AN_2_TID(an, tid);
2223 txtid->state |= AGGR_ADDBA_PROGRESS;
2224 ath_tx_pause_tid(sc, txtid);
2225 }
2226
2227 return 0;
2228 }
2229
2230 /* Stop tx aggregation */
2231
2232 int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
2233 {
2234 struct ath_node *an = (struct ath_node *)sta->drv_priv;
2235
2236 ath_tx_aggr_teardown(sc, an, tid);
2237 return 0;
2238 }
2239
2240 /* Resume tx aggregation */
2241
2242 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
2243 {
2244 struct ath_atx_tid *txtid;
2245 struct ath_node *an;
2246
2247 an = (struct ath_node *)sta->drv_priv;
2248
2249 if (sc->sc_flags & SC_OP_TXAGGR) {
2250 txtid = ATH_AN_2_TID(an, tid);
2251 txtid->baw_size =
2252 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
2253 txtid->state |= AGGR_ADDBA_COMPLETE;
2254 txtid->state &= ~AGGR_ADDBA_PROGRESS;
2255 ath_tx_resume_tid(sc, txtid);
2256 }
2257 }
2258
2259 /*
2260 * Performs transmit side cleanup when TID changes from aggregated to
2261 * unaggregated.
2262 * - Pause the TID and mark cleanup in progress
2263 * - Discard all retry frames from the s/w queue.
2264 */
2265
2266 void ath_tx_aggr_teardown(struct ath_softc *sc, struct ath_node *an, u8 tid)
2267 {
2268 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
2269 struct ath_txq *txq = &sc->sc_txq[txtid->ac->qnum];
2270 struct ath_buf *bf;
2271 struct list_head bf_head;
2272 INIT_LIST_HEAD(&bf_head);
2273
2274 if (txtid->state & AGGR_CLEANUP) /* cleanup is in progress */
2275 return;
2276
2277 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
2278 txtid->addba_exchangeattempts = 0;
2279 return;
2280 }
2281
2282 /* TID must be paused first */
2283 ath_tx_pause_tid(sc, txtid);
2284
2285 /* drop all software retried frames and mark this TID */
2286 spin_lock_bh(&txq->axq_lock);
2287 while (!list_empty(&txtid->buf_q)) {
2288 bf = list_first_entry(&txtid->buf_q, struct ath_buf, list);
2289 if (!bf_isretried(bf)) {
2290 /*
2291 * NB: it's based on the assumption that
2292 * software retried frame will always stay
2293 * at the head of software queue.
2294 */
2295 break;
2296 }
2297 list_cut_position(&bf_head,
2298 &txtid->buf_q, &bf->bf_lastfrm->list);
2299 ath_tx_update_baw(sc, txtid, bf->bf_seqno);
2300
2301 /* complete this sub-frame */
2302 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
2303 }
2304
2305 if (txtid->baw_head != txtid->baw_tail) {
2306 spin_unlock_bh(&txq->axq_lock);
2307 txtid->state |= AGGR_CLEANUP;
2308 } else {
2309 txtid->state &= ~AGGR_ADDBA_COMPLETE;
2310 txtid->addba_exchangeattempts = 0;
2311 spin_unlock_bh(&txq->axq_lock);
2312 ath_tx_flush_tid(sc, txtid);
2313 }
2314 }
2315
2316 /*
2317 * Tx scheduling logic
2318 * NB: must be called with txq lock held
2319 */
2320
2321 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
2322 {
2323 struct ath_atx_ac *ac;
2324 struct ath_atx_tid *tid;
2325
2326 /* nothing to schedule */
2327 if (list_empty(&txq->axq_acq))
2328 return;
2329 /*
2330 * get the first node/ac pair on the queue
2331 */
2332 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
2333 list_del(&ac->list);
2334 ac->sched = false;
2335
2336 /*
2337 * process a single tid per destination
2338 */
2339 do {
2340 /* nothing to schedule */
2341 if (list_empty(&ac->tid_q))
2342 return;
2343
2344 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
2345 list_del(&tid->list);
2346 tid->sched = false;
2347
2348 if (tid->paused) /* check next tid to keep h/w busy */
2349 continue;
2350
2351 if ((txq->axq_depth % 2) == 0)
2352 ath_tx_sched_aggr(sc, txq, tid);
2353
2354 /*
2355 * add tid to round-robin queue if more frames
2356 * are pending for the tid
2357 */
2358 if (!list_empty(&tid->buf_q))
2359 ath_tx_queue_tid(txq, tid);
2360
2361 /* only schedule one TID at a time */
2362 break;
2363 } while (!list_empty(&ac->tid_q));
2364
2365 /*
2366 * schedule AC if more TIDs need processing
2367 */
2368 if (!list_empty(&ac->tid_q)) {
2369 /*
2370 * add dest ac to txq if not already added
2371 */
2372 if (!ac->sched) {
2373 ac->sched = true;
2374 list_add_tail(&ac->list, &txq->axq_acq);
2375 }
2376 }
2377 }
2378
2379 /* Initialize per-node transmit state */
2380
2381 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2382 {
2383 struct ath_atx_tid *tid;
2384 struct ath_atx_ac *ac;
2385 int tidno, acno;
2386
2387 /*
2388 * Init per tid tx state
2389 */
2390 for (tidno = 0, tid = &an->an_aggr.tx.tid[tidno];
2391 tidno < WME_NUM_TID;
2392 tidno++, tid++) {
2393 tid->an = an;
2394 tid->tidno = tidno;
2395 tid->seq_start = tid->seq_next = 0;
2396 tid->baw_size = WME_MAX_BA;
2397 tid->baw_head = tid->baw_tail = 0;
2398 tid->sched = false;
2399 tid->paused = false;
2400 tid->state &= ~AGGR_CLEANUP;
2401 INIT_LIST_HEAD(&tid->buf_q);
2402
2403 acno = TID_TO_WME_AC(tidno);
2404 tid->ac = &an->an_aggr.tx.ac[acno];
2405
2406 /* ADDBA state */
2407 tid->state &= ~AGGR_ADDBA_COMPLETE;
2408 tid->state &= ~AGGR_ADDBA_PROGRESS;
2409 tid->addba_exchangeattempts = 0;
2410 }
2411
2412 /*
2413 * Init per ac tx state
2414 */
2415 for (acno = 0, ac = &an->an_aggr.tx.ac[acno];
2416 acno < WME_NUM_AC; acno++, ac++) {
2417 ac->sched = false;
2418 INIT_LIST_HEAD(&ac->tid_q);
2419
2420 switch (acno) {
2421 case WME_AC_BE:
2422 ac->qnum = ath_tx_get_qnum(sc,
2423 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
2424 break;
2425 case WME_AC_BK:
2426 ac->qnum = ath_tx_get_qnum(sc,
2427 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK);
2428 break;
2429 case WME_AC_VI:
2430 ac->qnum = ath_tx_get_qnum(sc,
2431 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI);
2432 break;
2433 case WME_AC_VO:
2434 ac->qnum = ath_tx_get_qnum(sc,
2435 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO);
2436 break;
2437 }
2438 }
2439 }
2440
2441 /* Cleanupthe pending buffers for the node. */
2442
2443 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2444 {
2445 int i;
2446 struct ath_atx_ac *ac, *ac_tmp;
2447 struct ath_atx_tid *tid, *tid_tmp;
2448 struct ath_txq *txq;
2449 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2450 if (ATH_TXQ_SETUP(sc, i)) {
2451 txq = &sc->sc_txq[i];
2452
2453 spin_lock(&txq->axq_lock);
2454
2455 list_for_each_entry_safe(ac,
2456 ac_tmp, &txq->axq_acq, list) {
2457 tid = list_first_entry(&ac->tid_q,
2458 struct ath_atx_tid, list);
2459 if (tid && tid->an != an)
2460 continue;
2461 list_del(&ac->list);
2462 ac->sched = false;
2463
2464 list_for_each_entry_safe(tid,
2465 tid_tmp, &ac->tid_q, list) {
2466 list_del(&tid->list);
2467 tid->sched = false;
2468 ath_tid_drain(sc, txq, tid);
2469 tid->state &= ~AGGR_ADDBA_COMPLETE;
2470 tid->addba_exchangeattempts = 0;
2471 tid->state &= ~AGGR_CLEANUP;
2472 }
2473 }
2474
2475 spin_unlock(&txq->axq_lock);
2476 }
2477 }
2478 }
2479
2480 void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb)
2481 {
2482 int hdrlen, padsize;
2483 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2484 struct ath_tx_control txctl;
2485
2486 memset(&txctl, 0, sizeof(struct ath_tx_control));
2487
2488 /*
2489 * As a temporary workaround, assign seq# here; this will likely need
2490 * to be cleaned up to work better with Beacon transmission and virtual
2491 * BSSes.
2492 */
2493 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2494 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2495 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2496 sc->seq_no += 0x10;
2497 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2498 hdr->seq_ctrl |= cpu_to_le16(sc->seq_no);
2499 }
2500
2501 /* Add the padding after the header if this is not already done */
2502 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2503 if (hdrlen & 3) {
2504 padsize = hdrlen % 4;
2505 if (skb_headroom(skb) < padsize) {
2506 DPRINTF(sc, ATH_DBG_XMIT, "TX CABQ padding failed\n");
2507 dev_kfree_skb_any(skb);
2508 return;
2509 }
2510 skb_push(skb, padsize);
2511 memmove(skb->data, skb->data + padsize, hdrlen);
2512 }
2513
2514 txctl.txq = sc->sc_cabq;
2515
2516 DPRINTF(sc, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb);
2517
2518 if (ath_tx_start(sc, skb, &txctl) != 0) {
2519 DPRINTF(sc, ATH_DBG_XMIT, "CABQ TX failed\n");
2520 goto exit;
2521 }
2522
2523 return;
2524 exit:
2525 dev_kfree_skb_any(skb);
2526 }
Support for the Chinese Samsung S3C2440 based development boards