2 * linux/drivers/video/savagefb.c -- S3 Savage Framebuffer Driver
4 * Copyright (c) 2001-2002 Denis Oliver Kropp <dok@directfb.org>
5 * Sven Neumann <neo@directfb.org>
8 * Card specific code is based on XFree86's savage driver.
9 * Framebuffer framework code is based on code of cyber2000fb and tdfxfb.
11 * This file is subject to the terms and conditions of the GNU General
12 * Public License. See the file COPYING in the main directory of this
13 * archive for more details.
16 * - hardware accelerated clear and move
19 * - wait for vertical retrace before writing to cr67
20 * at the beginning of savagefb_set_par
21 * - use synchronization registers cr23 and cr26
25 * - don't return alpha bits for 32bit format
28 * - added WaitIdle functions for all Savage types
29 * - do WaitIdle before mode switching
33 * - first working version
37 * - clock validations in decode_var
40 * - white margin on bootup
44 #include <linux/config.h>
45 #include <linux/module.h>
46 #include <linux/kernel.h>
47 #include <linux/errno.h>
48 #include <linux/string.h>
50 #include <linux/tty.h>
51 #include <linux/slab.h>
52 #include <linux/delay.h>
54 #include <linux/pci.h>
55 #include <linux/init.h>
56 #include <linux/console.h>
60 #include <asm/pgtable.h>
61 #include <asm/system.h>
62 #include <asm/uaccess.h>
71 #define SAVAGEFB_VERSION "0.4.0_2.6"
73 /* --------------------------------------------------------------------- */
76 static char *mode_option __devinitdata
= NULL
;
80 MODULE_AUTHOR("(c) 2001-2002 Denis Oliver Kropp <dok@directfb.org>");
81 MODULE_LICENSE("GPL");
82 MODULE_DESCRIPTION("FBDev driver for S3 Savage PCI/AGP Chips");
87 /* --------------------------------------------------------------------- */
89 static void vgaHWSeqReset (struct savagefb_par
*par
, int start
)
92 VGAwSEQ (0x00, 0x01, par
); /* Synchronous Reset */
94 VGAwSEQ (0x00, 0x03, par
); /* End Reset */
97 static void vgaHWProtect (struct savagefb_par
*par
, int on
)
103 * Turn off screen and disable sequencer.
105 tmp
= VGArSEQ (0x01, par
);
107 vgaHWSeqReset (par
, 1); /* start synchronous reset */
108 VGAwSEQ (0x01, tmp
| 0x20, par
);/* disable the display */
110 VGAenablePalette(par
);
113 * Reenable sequencer, then turn on screen.
116 tmp
= VGArSEQ (0x01, par
);
118 VGAwSEQ (0x01, tmp
& ~0x20, par
);/* reenable display */
119 vgaHWSeqReset (par
, 0); /* clear synchronous reset */
121 VGAdisablePalette(par
);
125 static void vgaHWRestore (struct savagefb_par
*par
, struct savage_reg
*reg
)
129 VGAwMISC (reg
->MiscOutReg
, par
);
131 for (i
= 1; i
< 5; i
++)
132 VGAwSEQ (i
, reg
->Sequencer
[i
], par
);
134 /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 or
136 VGAwCR (17, reg
->CRTC
[17] & ~0x80, par
);
138 for (i
= 0; i
< 25; i
++)
139 VGAwCR (i
, reg
->CRTC
[i
], par
);
141 for (i
= 0; i
< 9; i
++)
142 VGAwGR (i
, reg
->Graphics
[i
], par
);
144 VGAenablePalette(par
);
146 for (i
= 0; i
< 21; i
++)
147 VGAwATTR (i
, reg
->Attribute
[i
], par
);
149 VGAdisablePalette(par
);
152 static void vgaHWInit (struct fb_var_screeninfo
*var
,
153 struct savagefb_par
*par
,
154 struct xtimings
*timings
,
155 struct savage_reg
*reg
)
157 reg
->MiscOutReg
= 0x23;
159 if (!(timings
->sync
& FB_SYNC_HOR_HIGH_ACT
))
160 reg
->MiscOutReg
|= 0x40;
162 if (!(timings
->sync
& FB_SYNC_VERT_HIGH_ACT
))
163 reg
->MiscOutReg
|= 0x80;
168 reg
->Sequencer
[0x00] = 0x00;
169 reg
->Sequencer
[0x01] = 0x01;
170 reg
->Sequencer
[0x02] = 0x0F;
171 reg
->Sequencer
[0x03] = 0x00; /* Font select */
172 reg
->Sequencer
[0x04] = 0x0E; /* Misc */
177 reg
->CRTC
[0x00] = (timings
->HTotal
>> 3) - 5;
178 reg
->CRTC
[0x01] = (timings
->HDisplay
>> 3) - 1;
179 reg
->CRTC
[0x02] = (timings
->HSyncStart
>> 3) - 1;
180 reg
->CRTC
[0x03] = (((timings
->HSyncEnd
>> 3) - 1) & 0x1f) | 0x80;
181 reg
->CRTC
[0x04] = (timings
->HSyncStart
>> 3);
182 reg
->CRTC
[0x05] = ((((timings
->HSyncEnd
>> 3) - 1) & 0x20) << 2) |
183 (((timings
->HSyncEnd
>> 3)) & 0x1f);
184 reg
->CRTC
[0x06] = (timings
->VTotal
- 2) & 0xFF;
185 reg
->CRTC
[0x07] = (((timings
->VTotal
- 2) & 0x100) >> 8) |
186 (((timings
->VDisplay
- 1) & 0x100) >> 7) |
187 ((timings
->VSyncStart
& 0x100) >> 6) |
188 (((timings
->VSyncStart
- 1) & 0x100) >> 5) |
190 (((timings
->VTotal
- 2) & 0x200) >> 4) |
191 (((timings
->VDisplay
- 1) & 0x200) >> 3) |
192 ((timings
->VSyncStart
& 0x200) >> 2);
193 reg
->CRTC
[0x08] = 0x00;
194 reg
->CRTC
[0x09] = (((timings
->VSyncStart
- 1) & 0x200) >> 4) | 0x40;
196 if (timings
->dblscan
)
197 reg
->CRTC
[0x09] |= 0x80;
199 reg
->CRTC
[0x0a] = 0x00;
200 reg
->CRTC
[0x0b] = 0x00;
201 reg
->CRTC
[0x0c] = 0x00;
202 reg
->CRTC
[0x0d] = 0x00;
203 reg
->CRTC
[0x0e] = 0x00;
204 reg
->CRTC
[0x0f] = 0x00;
205 reg
->CRTC
[0x10] = timings
->VSyncStart
& 0xff;
206 reg
->CRTC
[0x11] = (timings
->VSyncEnd
& 0x0f) | 0x20;
207 reg
->CRTC
[0x12] = (timings
->VDisplay
- 1) & 0xff;
208 reg
->CRTC
[0x13] = var
->xres_virtual
>> 4;
209 reg
->CRTC
[0x14] = 0x00;
210 reg
->CRTC
[0x15] = (timings
->VSyncStart
- 1) & 0xff;
211 reg
->CRTC
[0x16] = (timings
->VSyncEnd
- 1) & 0xff;
212 reg
->CRTC
[0x17] = 0xc3;
213 reg
->CRTC
[0x18] = 0xff;
216 * are these unnecessary?
217 * vgaHWHBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN|KGA_ENABLE_ON_ZERO);
218 * vgaHWVBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN|KGA_ENABLE_ON_ZERO);
222 * Graphics Display Controller
224 reg
->Graphics
[0x00] = 0x00;
225 reg
->Graphics
[0x01] = 0x00;
226 reg
->Graphics
[0x02] = 0x00;
227 reg
->Graphics
[0x03] = 0x00;
228 reg
->Graphics
[0x04] = 0x00;
229 reg
->Graphics
[0x05] = 0x40;
230 reg
->Graphics
[0x06] = 0x05; /* only map 64k VGA memory !!!! */
231 reg
->Graphics
[0x07] = 0x0F;
232 reg
->Graphics
[0x08] = 0xFF;
235 reg
->Attribute
[0x00] = 0x00; /* standard colormap translation */
236 reg
->Attribute
[0x01] = 0x01;
237 reg
->Attribute
[0x02] = 0x02;
238 reg
->Attribute
[0x03] = 0x03;
239 reg
->Attribute
[0x04] = 0x04;
240 reg
->Attribute
[0x05] = 0x05;
241 reg
->Attribute
[0x06] = 0x06;
242 reg
->Attribute
[0x07] = 0x07;
243 reg
->Attribute
[0x08] = 0x08;
244 reg
->Attribute
[0x09] = 0x09;
245 reg
->Attribute
[0x0a] = 0x0A;
246 reg
->Attribute
[0x0b] = 0x0B;
247 reg
->Attribute
[0x0c] = 0x0C;
248 reg
->Attribute
[0x0d] = 0x0D;
249 reg
->Attribute
[0x0e] = 0x0E;
250 reg
->Attribute
[0x0f] = 0x0F;
251 reg
->Attribute
[0x10] = 0x41;
252 reg
->Attribute
[0x11] = 0xFF;
253 reg
->Attribute
[0x12] = 0x0F;
254 reg
->Attribute
[0x13] = 0x00;
255 reg
->Attribute
[0x14] = 0x00;
258 /* -------------------- Hardware specific routines ------------------------- */
261 * Hardware Acceleration for SavageFB
264 /* Wait for fifo space */
266 savage3D_waitfifo(struct savagefb_par
*par
, int space
)
268 int slots
= MAXFIFO
- space
;
270 while ((savage_in32(0x48C00, par
) & 0x0000ffff) > slots
);
274 savage4_waitfifo(struct savagefb_par
*par
, int space
)
276 int slots
= MAXFIFO
- space
;
278 while ((savage_in32(0x48C60, par
) & 0x001fffff) > slots
);
282 savage2000_waitfifo(struct savagefb_par
*par
, int space
)
284 int slots
= MAXFIFO
- space
;
286 while ((savage_in32(0x48C60, par
) & 0x0000ffff) > slots
);
289 /* Wait for idle accelerator */
291 savage3D_waitidle(struct savagefb_par
*par
)
293 while ((savage_in32(0x48C00, par
) & 0x0008ffff) != 0x80000);
297 savage4_waitidle(struct savagefb_par
*par
)
299 while ((savage_in32(0x48C60, par
) & 0x00a00000) != 0x00a00000);
303 savage2000_waitidle(struct savagefb_par
*par
)
305 while ((savage_in32(0x48C60, par
) & 0x009fffff));
308 #ifdef CONFIG_FB_SAVAGE_ACCEL
310 SavageSetup2DEngine (struct savagefb_par
*par
)
312 unsigned long GlobalBitmapDescriptor
;
314 GlobalBitmapDescriptor
= 1 | 8 | BCI_BD_BW_DISABLE
;
315 BCI_BD_SET_BPP (GlobalBitmapDescriptor
, par
->depth
);
316 BCI_BD_SET_STRIDE (GlobalBitmapDescriptor
, par
->vwidth
);
322 savage_out32(0x48C18, savage_in32(0x48C18, par
) & 0x3FF0, par
);
323 /* Setup BCI command overflow buffer */
324 savage_out32(0x48C14,
325 (par
->cob_offset
>> 11) | (par
->cob_index
<< 29),
327 /* Program shadow status update. */
328 savage_out32(0x48C10, 0x78207220, par
);
329 savage_out32(0x48C0C, 0, par
);
330 /* Enable BCI and command overflow buffer */
331 savage_out32(0x48C18, savage_in32(0x48C18, par
) | 0x0C, par
);
337 savage_out32(0x48C18, savage_in32(0x48C18, par
) & 0x3FF0, par
);
338 /* Program shadow status update */
339 savage_out32(0x48C10, 0x00700040, par
);
340 savage_out32(0x48C0C, 0, par
);
341 /* Enable BCI without the COB */
342 savage_out32(0x48C18, savage_in32(0x48C18, par
) | 0x08, par
);
346 savage_out32(0x48C18, 0, par
);
347 /* Setup BCI command overflow buffer */
348 savage_out32(0x48C18,
349 (par
->cob_offset
>> 7) | (par
->cob_index
),
351 /* Disable shadow status update */
352 savage_out32(0x48A30, 0, par
);
353 /* Enable BCI and command overflow buffer */
354 savage_out32(0x48C18, savage_in32(0x48C18, par
) | 0x00280000,
360 /* Turn on 16-bit register access. */
361 vga_out8(0x3d4, 0x31, par
);
362 vga_out8(0x3d5, 0x0c, par
);
364 /* Set stride to use GBD. */
365 vga_out8 (0x3d4, 0x50, par
);
366 vga_out8 (0x3d5, vga_in8(0x3d5, par
) | 0xC1, par
);
368 /* Enable 2D engine. */
369 vga_out8 (0x3d4, 0x40, par
);
370 vga_out8 (0x3d5, 0x01, par
);
372 savage_out32 (MONO_PAT_0
, ~0, par
);
373 savage_out32 (MONO_PAT_1
, ~0, par
);
375 /* Setup plane masks */
376 savage_out32 (0x8128, ~0, par
); /* enable all write planes */
377 savage_out32 (0x812C, ~0, par
); /* enable all read planes */
378 savage_out16 (0x8134, 0x27, par
);
379 savage_out16 (0x8136, 0x07, par
);
381 /* Now set the GBD */
383 par
->SavageWaitFifo (par
, 4);
385 BCI_SEND( BCI_CMD_SETREG
| (1 << 16) | BCI_GBD1
);
387 BCI_SEND( BCI_CMD_SETREG
| (1 << 16) | BCI_GBD2
);
388 BCI_SEND( GlobalBitmapDescriptor
);
391 static void savagefb_set_clip(struct fb_info
*info
)
393 struct savagefb_par
*par
= info
->par
;
396 cmd
= BCI_CMD_NOP
| BCI_CMD_CLIP_NEW
;
398 par
->SavageWaitFifo(par
,3);
400 BCI_SEND(BCI_CLIP_TL(0, 0));
401 BCI_SEND(BCI_CLIP_BR(0xfff, 0xfff));
404 static void SavageSetup2DEngine (struct savagefb_par
*par
) {}
408 static void SavageCalcClock(long freq
, int min_m
, int min_n1
, int max_n1
,
409 int min_n2
, int max_n2
, long freq_min
,
410 long freq_max
, unsigned int *mdiv
,
411 unsigned int *ndiv
, unsigned int *r
)
413 long diff
, best_diff
;
415 unsigned char n1
, n2
, best_n1
=16+2, best_n2
=2, best_m
=125+2;
417 if (freq
< freq_min
/ (1 << max_n2
)) {
418 printk (KERN_ERR
"invalid frequency %ld Khz\n", freq
);
419 freq
= freq_min
/ (1 << max_n2
);
421 if (freq
> freq_max
/ (1 << min_n2
)) {
422 printk (KERN_ERR
"invalid frequency %ld Khz\n", freq
);
423 freq
= freq_max
/ (1 << min_n2
);
426 /* work out suitable timings */
429 for (n2
=min_n2
; n2
<=max_n2
; n2
++) {
430 for (n1
=min_n1
+2; n1
<=max_n1
+2; n1
++) {
431 m
= (freq
* n1
* (1 << n2
) + HALF_BASE_FREQ
) /
433 if (m
< min_m
+2 || m
> 127+2)
435 if ((m
* BASE_FREQ
>= freq_min
* n1
) &&
436 (m
* BASE_FREQ
<= freq_max
* n1
)) {
437 diff
= freq
* (1 << n2
) * n1
- BASE_FREQ
* m
;
440 if (diff
< best_diff
) {
455 static int common_calc_clock(long freq
, int min_m
, int min_n1
, int max_n1
,
456 int min_n2
, int max_n2
, long freq_min
,
457 long freq_max
, unsigned char *mdiv
,
460 long diff
, best_diff
;
462 unsigned char n1
, n2
;
463 unsigned char best_n1
= 16+2, best_n2
= 2, best_m
= 125+2;
467 for (n2
= min_n2
; n2
<= max_n2
; n2
++) {
468 for (n1
= min_n1
+2; n1
<= max_n1
+2; n1
++) {
469 m
= (freq
* n1
* (1 << n2
) + HALF_BASE_FREQ
) /
471 if (m
< min_m
+ 2 || m
> 127+2)
473 if((m
* BASE_FREQ
>= freq_min
* n1
) &&
474 (m
* BASE_FREQ
<= freq_max
* n1
)) {
475 diff
= freq
* (1 << n2
) * n1
- BASE_FREQ
* m
;
478 if(diff
< best_diff
) {
489 *ndiv
= (best_n1
- 2) | (best_n2
<< 6);
491 *ndiv
= (best_n1
- 2) | (best_n2
<< 5);
498 #ifdef SAVAGEFB_DEBUG
499 /* This function is used to debug, it prints out the contents of s3 regs */
501 static void SavagePrintRegs(void)
504 int vgaCRIndex
= 0x3d4;
505 int vgaCRReg
= 0x3d5;
507 printk(KERN_DEBUG
"SR x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE "
510 for( i
= 0; i
< 0x70; i
++ ) {
512 printk(KERN_DEBUG
"\nSR%xx ", i
>> 4 );
513 vga_out8( 0x3c4, i
, par
);
514 printk(KERN_DEBUG
" %02x", vga_in8(0x3c5, par
) );
517 printk(KERN_DEBUG
"\n\nCR x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC "
520 for( i
= 0; i
< 0xB7; i
++ ) {
522 printk(KERN_DEBUG
"\nCR%xx ", i
>> 4 );
523 vga_out8( vgaCRIndex
, i
, par
);
524 printk(KERN_DEBUG
" %02x", vga_in8(vgaCRReg
, par
) );
527 printk(KERN_DEBUG
"\n\n");
531 /* --------------------------------------------------------------------- */
533 static void savage_get_default_par(struct savagefb_par
*par
, struct savage_reg
*reg
)
535 unsigned char cr3a
, cr53
, cr66
;
537 vga_out16 (0x3d4, 0x4838, par
);
538 vga_out16 (0x3d4, 0xa039, par
);
539 vga_out16 (0x3c4, 0x0608, par
);
541 vga_out8 (0x3d4, 0x66, par
);
542 cr66
= vga_in8 (0x3d5, par
);
543 vga_out8 (0x3d5, cr66
| 0x80, par
);
544 vga_out8 (0x3d4, 0x3a, par
);
545 cr3a
= vga_in8 (0x3d5, par
);
546 vga_out8 (0x3d5, cr3a
| 0x80, par
);
547 vga_out8 (0x3d4, 0x53, par
);
548 cr53
= vga_in8 (0x3d5, par
);
549 vga_out8 (0x3d5, cr53
& 0x7f, par
);
551 vga_out8 (0x3d4, 0x66, par
);
552 vga_out8 (0x3d5, cr66
, par
);
553 vga_out8 (0x3d4, 0x3a, par
);
554 vga_out8 (0x3d5, cr3a
, par
);
556 vga_out8 (0x3d4, 0x66, par
);
557 vga_out8 (0x3d5, cr66
, par
);
558 vga_out8 (0x3d4, 0x3a, par
);
559 vga_out8 (0x3d5, cr3a
, par
);
561 /* unlock extended seq regs */
562 vga_out8 (0x3c4, 0x08, par
);
563 reg
->SR08
= vga_in8 (0x3c5, par
);
564 vga_out8 (0x3c5, 0x06, par
);
566 /* now save all the extended regs we need */
567 vga_out8 (0x3d4, 0x31, par
);
568 reg
->CR31
= vga_in8 (0x3d5, par
);
569 vga_out8 (0x3d4, 0x32, par
);
570 reg
->CR32
= vga_in8 (0x3d5, par
);
571 vga_out8 (0x3d4, 0x34, par
);
572 reg
->CR34
= vga_in8 (0x3d5, par
);
573 vga_out8 (0x3d4, 0x36, par
);
574 reg
->CR36
= vga_in8 (0x3d5, par
);
575 vga_out8 (0x3d4, 0x3a, par
);
576 reg
->CR3A
= vga_in8 (0x3d5, par
);
577 vga_out8 (0x3d4, 0x40, par
);
578 reg
->CR40
= vga_in8 (0x3d5, par
);
579 vga_out8 (0x3d4, 0x42, par
);
580 reg
->CR42
= vga_in8 (0x3d5, par
);
581 vga_out8 (0x3d4, 0x45, par
);
582 reg
->CR45
= vga_in8 (0x3d5, par
);
583 vga_out8 (0x3d4, 0x50, par
);
584 reg
->CR50
= vga_in8 (0x3d5, par
);
585 vga_out8 (0x3d4, 0x51, par
);
586 reg
->CR51
= vga_in8 (0x3d5, par
);
587 vga_out8 (0x3d4, 0x53, par
);
588 reg
->CR53
= vga_in8 (0x3d5, par
);
589 vga_out8 (0x3d4, 0x58, par
);
590 reg
->CR58
= vga_in8 (0x3d5, par
);
591 vga_out8 (0x3d4, 0x60, par
);
592 reg
->CR60
= vga_in8 (0x3d5, par
);
593 vga_out8 (0x3d4, 0x66, par
);
594 reg
->CR66
= vga_in8 (0x3d5, par
);
595 vga_out8 (0x3d4, 0x67, par
);
596 reg
->CR67
= vga_in8 (0x3d5, par
);
597 vga_out8 (0x3d4, 0x68, par
);
598 reg
->CR68
= vga_in8 (0x3d5, par
);
599 vga_out8 (0x3d4, 0x69, par
);
600 reg
->CR69
= vga_in8 (0x3d5, par
);
601 vga_out8 (0x3d4, 0x6f, par
);
602 reg
->CR6F
= vga_in8 (0x3d5, par
);
604 vga_out8 (0x3d4, 0x33, par
);
605 reg
->CR33
= vga_in8 (0x3d5, par
);
606 vga_out8 (0x3d4, 0x86, par
);
607 reg
->CR86
= vga_in8 (0x3d5, par
);
608 vga_out8 (0x3d4, 0x88, par
);
609 reg
->CR88
= vga_in8 (0x3d5, par
);
610 vga_out8 (0x3d4, 0x90, par
);
611 reg
->CR90
= vga_in8 (0x3d5, par
);
612 vga_out8 (0x3d4, 0x91, par
);
613 reg
->CR91
= vga_in8 (0x3d5, par
);
614 vga_out8 (0x3d4, 0xb0, par
);
615 reg
->CRB0
= vga_in8 (0x3d5, par
) | 0x80;
617 /* extended mode timing regs */
618 vga_out8 (0x3d4, 0x3b, par
);
619 reg
->CR3B
= vga_in8 (0x3d5, par
);
620 vga_out8 (0x3d4, 0x3c, par
);
621 reg
->CR3C
= vga_in8 (0x3d5, par
);
622 vga_out8 (0x3d4, 0x43, par
);
623 reg
->CR43
= vga_in8 (0x3d5, par
);
624 vga_out8 (0x3d4, 0x5d, par
);
625 reg
->CR5D
= vga_in8 (0x3d5, par
);
626 vga_out8 (0x3d4, 0x5e, par
);
627 reg
->CR5E
= vga_in8 (0x3d5, par
);
628 vga_out8 (0x3d4, 0x65, par
);
629 reg
->CR65
= vga_in8 (0x3d5, par
);
631 /* save seq extended regs for DCLK PLL programming */
632 vga_out8 (0x3c4, 0x0e, par
);
633 reg
->SR0E
= vga_in8 (0x3c5, par
);
634 vga_out8 (0x3c4, 0x0f, par
);
635 reg
->SR0F
= vga_in8 (0x3c5, par
);
636 vga_out8 (0x3c4, 0x10, par
);
637 reg
->SR10
= vga_in8 (0x3c5, par
);
638 vga_out8 (0x3c4, 0x11, par
);
639 reg
->SR11
= vga_in8 (0x3c5, par
);
640 vga_out8 (0x3c4, 0x12, par
);
641 reg
->SR12
= vga_in8 (0x3c5, par
);
642 vga_out8 (0x3c4, 0x13, par
);
643 reg
->SR13
= vga_in8 (0x3c5, par
);
644 vga_out8 (0x3c4, 0x29, par
);
645 reg
->SR29
= vga_in8 (0x3c5, par
);
647 vga_out8 (0x3c4, 0x15, par
);
648 reg
->SR15
= vga_in8 (0x3c5, par
);
649 vga_out8 (0x3c4, 0x30, par
);
650 reg
->SR30
= vga_in8 (0x3c5, par
);
651 vga_out8 (0x3c4, 0x18, par
);
652 reg
->SR18
= vga_in8 (0x3c5, par
);
654 /* Save flat panel expansion regsters. */
655 if (par
->chip
== S3_SAVAGE_MX
) {
658 for (i
= 0; i
< 8; i
++) {
659 vga_out8 (0x3c4, 0x54+i
, par
);
660 reg
->SR54
[i
] = vga_in8 (0x3c5, par
);
664 vga_out8 (0x3d4, 0x66, par
);
665 cr66
= vga_in8 (0x3d5, par
);
666 vga_out8 (0x3d5, cr66
| 0x80, par
);
667 vga_out8 (0x3d4, 0x3a, par
);
668 cr3a
= vga_in8 (0x3d5, par
);
669 vga_out8 (0x3d5, cr3a
| 0x80, par
);
671 /* now save MIU regs */
672 if (par
->chip
!= S3_SAVAGE_MX
) {
673 reg
->MMPR0
= savage_in32(FIFO_CONTROL_REG
, par
);
674 reg
->MMPR1
= savage_in32(MIU_CONTROL_REG
, par
);
675 reg
->MMPR2
= savage_in32(STREAMS_TIMEOUT_REG
, par
);
676 reg
->MMPR3
= savage_in32(MISC_TIMEOUT_REG
, par
);
679 vga_out8 (0x3d4, 0x3a, par
);
680 vga_out8 (0x3d5, cr3a
, par
);
681 vga_out8 (0x3d4, 0x66, par
);
682 vga_out8 (0x3d5, cr66
, par
);
685 static void savage_set_default_par(struct savagefb_par
*par
,
686 struct savage_reg
*reg
)
688 unsigned char cr3a
, cr53
, cr66
;
690 vga_out16(0x3d4, 0x4838, par
);
691 vga_out16(0x3d4, 0xa039, par
);
692 vga_out16(0x3c4, 0x0608, par
);
694 vga_out8(0x3d4, 0x66, par
);
695 cr66
= vga_in8(0x3d5, par
);
696 vga_out8(0x3d5, cr66
| 0x80, par
);
697 vga_out8(0x3d4, 0x3a, par
);
698 cr3a
= vga_in8(0x3d5, par
);
699 vga_out8(0x3d5, cr3a
| 0x80, par
);
700 vga_out8(0x3d4, 0x53, par
);
701 cr53
= vga_in8(0x3d5, par
);
702 vga_out8(0x3d5, cr53
& 0x7f, par
);
704 vga_out8(0x3d4, 0x66, par
);
705 vga_out8(0x3d5, cr66
, par
);
706 vga_out8(0x3d4, 0x3a, par
);
707 vga_out8(0x3d5, cr3a
, par
);
709 vga_out8(0x3d4, 0x66, par
);
710 vga_out8(0x3d5, cr66
, par
);
711 vga_out8(0x3d4, 0x3a, par
);
712 vga_out8(0x3d5, cr3a
, par
);
714 /* unlock extended seq regs */
715 vga_out8(0x3c4, 0x08, par
);
716 vga_out8(0x3c5, reg
->SR08
, par
);
717 vga_out8(0x3c5, 0x06, par
);
719 /* now restore all the extended regs we need */
720 vga_out8(0x3d4, 0x31, par
);
721 vga_out8(0x3d5, reg
->CR31
, par
);
722 vga_out8(0x3d4, 0x32, par
);
723 vga_out8(0x3d5, reg
->CR32
, par
);
724 vga_out8(0x3d4, 0x34, par
);
725 vga_out8(0x3d5, reg
->CR34
, par
);
726 vga_out8(0x3d4, 0x36, par
);
727 vga_out8(0x3d5,reg
->CR36
, par
);
728 vga_out8(0x3d4, 0x3a, par
);
729 vga_out8(0x3d5, reg
->CR3A
, par
);
730 vga_out8(0x3d4, 0x40, par
);
731 vga_out8(0x3d5, reg
->CR40
, par
);
732 vga_out8(0x3d4, 0x42, par
);
733 vga_out8(0x3d5, reg
->CR42
, par
);
734 vga_out8(0x3d4, 0x45, par
);
735 vga_out8(0x3d5, reg
->CR45
, par
);
736 vga_out8(0x3d4, 0x50, par
);
737 vga_out8(0x3d5, reg
->CR50
, par
);
738 vga_out8(0x3d4, 0x51, par
);
739 vga_out8(0x3d5, reg
->CR51
, par
);
740 vga_out8(0x3d4, 0x53, par
);
741 vga_out8(0x3d5, reg
->CR53
, par
);
742 vga_out8(0x3d4, 0x58, par
);
743 vga_out8(0x3d5, reg
->CR58
, par
);
744 vga_out8(0x3d4, 0x60, par
);
745 vga_out8(0x3d5, reg
->CR60
, par
);
746 vga_out8(0x3d4, 0x66, par
);
747 vga_out8(0x3d5, reg
->CR66
, par
);
748 vga_out8(0x3d4, 0x67, par
);
749 vga_out8(0x3d5, reg
->CR67
, par
);
750 vga_out8(0x3d4, 0x68, par
);
751 vga_out8(0x3d5, reg
->CR68
, par
);
752 vga_out8(0x3d4, 0x69, par
);
753 vga_out8(0x3d5, reg
->CR69
, par
);
754 vga_out8(0x3d4, 0x6f, par
);
755 vga_out8(0x3d5, reg
->CR6F
, par
);
757 vga_out8(0x3d4, 0x33, par
);
758 vga_out8(0x3d5, reg
->CR33
, par
);
759 vga_out8(0x3d4, 0x86, par
);
760 vga_out8(0x3d5, reg
->CR86
, par
);
761 vga_out8(0x3d4, 0x88, par
);
762 vga_out8(0x3d5, reg
->CR88
, par
);
763 vga_out8(0x3d4, 0x90, par
);
764 vga_out8(0x3d5, reg
->CR90
, par
);
765 vga_out8(0x3d4, 0x91, par
);
766 vga_out8(0x3d5, reg
->CR91
, par
);
767 vga_out8(0x3d4, 0xb0, par
);
768 vga_out8(0x3d5, reg
->CRB0
, par
);
770 /* extended mode timing regs */
771 vga_out8(0x3d4, 0x3b, par
);
772 vga_out8(0x3d5, reg
->CR3B
, par
);
773 vga_out8(0x3d4, 0x3c, par
);
774 vga_out8(0x3d5, reg
->CR3C
, par
);
775 vga_out8(0x3d4, 0x43, par
);
776 vga_out8(0x3d5, reg
->CR43
, par
);
777 vga_out8(0x3d4, 0x5d, par
);
778 vga_out8(0x3d5, reg
->CR5D
, par
);
779 vga_out8(0x3d4, 0x5e, par
);
780 vga_out8(0x3d5, reg
->CR5E
, par
);
781 vga_out8(0x3d4, 0x65, par
);
782 vga_out8(0x3d5, reg
->CR65
, par
);
784 /* save seq extended regs for DCLK PLL programming */
785 vga_out8(0x3c4, 0x0e, par
);
786 vga_out8(0x3c5, reg
->SR0E
, par
);
787 vga_out8(0x3c4, 0x0f, par
);
788 vga_out8(0x3c5, reg
->SR0F
, par
);
789 vga_out8(0x3c4, 0x10, par
);
790 vga_out8(0x3c5, reg
->SR10
, par
);
791 vga_out8(0x3c4, 0x11, par
);
792 vga_out8(0x3c5, reg
->SR11
, par
);
793 vga_out8(0x3c4, 0x12, par
);
794 vga_out8(0x3c5, reg
->SR12
, par
);
795 vga_out8(0x3c4, 0x13, par
);
796 vga_out8(0x3c5, reg
->SR13
, par
);
797 vga_out8(0x3c4, 0x29, par
);
798 vga_out8(0x3c5, reg
->SR29
, par
);
800 vga_out8(0x3c4, 0x15, par
);
801 vga_out8(0x3c5, reg
->SR15
, par
);
802 vga_out8(0x3c4, 0x30, par
);
803 vga_out8(0x3c5, reg
->SR30
, par
);
804 vga_out8(0x3c4, 0x18, par
);
805 vga_out8(0x3c5, reg
->SR18
, par
);
807 /* Save flat panel expansion regsters. */
808 if (par
->chip
== S3_SAVAGE_MX
) {
811 for (i
= 0; i
< 8; i
++) {
812 vga_out8(0x3c4, 0x54+i
, par
);
813 vga_out8(0x3c5, reg
->SR54
[i
], par
);
817 vga_out8(0x3d4, 0x66, par
);
818 cr66
= vga_in8(0x3d5, par
);
819 vga_out8(0x3d5, cr66
| 0x80, par
);
820 vga_out8(0x3d4, 0x3a, par
);
821 cr3a
= vga_in8(0x3d5, par
);
822 vga_out8(0x3d5, cr3a
| 0x80, par
);
824 /* now save MIU regs */
825 if (par
->chip
!= S3_SAVAGE_MX
) {
826 savage_out32(FIFO_CONTROL_REG
, reg
->MMPR0
, par
);
827 savage_out32(MIU_CONTROL_REG
, reg
->MMPR1
, par
);
828 savage_out32(STREAMS_TIMEOUT_REG
, reg
->MMPR2
, par
);
829 savage_out32(MISC_TIMEOUT_REG
, reg
->MMPR3
, par
);
832 vga_out8(0x3d4, 0x3a, par
);
833 vga_out8(0x3d5, cr3a
, par
);
834 vga_out8(0x3d4, 0x66, par
);
835 vga_out8(0x3d5, cr66
, par
);
838 static void savage_update_var(struct fb_var_screeninfo
*var
, struct fb_videomode
*modedb
)
840 var
->xres
= var
->xres_virtual
= modedb
->xres
;
841 var
->yres
= modedb
->yres
;
842 if (var
->yres_virtual
< var
->yres
)
843 var
->yres_virtual
= var
->yres
;
844 var
->xoffset
= var
->yoffset
= 0;
845 var
->pixclock
= modedb
->pixclock
;
846 var
->left_margin
= modedb
->left_margin
;
847 var
->right_margin
= modedb
->right_margin
;
848 var
->upper_margin
= modedb
->upper_margin
;
849 var
->lower_margin
= modedb
->lower_margin
;
850 var
->hsync_len
= modedb
->hsync_len
;
851 var
->vsync_len
= modedb
->vsync_len
;
852 var
->sync
= modedb
->sync
;
853 var
->vmode
= modedb
->vmode
;
856 static int savagefb_check_var (struct fb_var_screeninfo
*var
,
857 struct fb_info
*info
)
859 struct savagefb_par
*par
= info
->par
;
860 int memlen
, vramlen
, mode_valid
= 0;
862 DBG("savagefb_check_var");
864 var
->transp
.offset
= 0;
865 var
->transp
.length
= 0;
866 switch (var
->bits_per_pixel
) {
868 var
->red
.offset
= var
->green
.offset
=
869 var
->blue
.offset
= 0;
870 var
->red
.length
= var
->green
.length
=
871 var
->blue
.length
= var
->bits_per_pixel
;
874 var
->red
.offset
= 11;
876 var
->green
.offset
= 5;
877 var
->green
.length
= 6;
878 var
->blue
.offset
= 0;
879 var
->blue
.length
= 5;
882 var
->transp
.offset
= 24;
883 var
->transp
.length
= 8;
884 var
->red
.offset
= 16;
886 var
->green
.offset
= 8;
887 var
->green
.length
= 8;
888 var
->blue
.offset
= 0;
889 var
->blue
.length
= 8;
896 if (!info
->monspecs
.hfmax
|| !info
->monspecs
.vfmax
||
897 !info
->monspecs
.dclkmax
|| !fb_validate_mode(var
, info
))
900 /* calculate modeline if supported by monitor */
901 if (!mode_valid
&& info
->monspecs
.gtf
) {
902 if (!fb_get_mode(FB_MAXTIMINGS
, 0, var
, info
))
907 struct fb_videomode
*mode
;
909 mode
= fb_find_best_mode(var
, &info
->modelist
);
911 savage_update_var(var
, mode
);
916 if (!mode_valid
&& info
->monspecs
.modedb_len
)
919 /* Is the mode larger than the LCD panel? */
920 if (par
->SavagePanelWidth
&&
921 (var
->xres
> par
->SavagePanelWidth
||
922 var
->yres
> par
->SavagePanelHeight
)) {
923 printk (KERN_INFO
"Mode (%dx%d) larger than the LCD panel "
924 "(%dx%d)\n", var
->xres
, var
->yres
,
925 par
->SavagePanelWidth
,
926 par
->SavagePanelHeight
);
930 if (var
->yres_virtual
< var
->yres
)
931 var
->yres_virtual
= var
->yres
;
932 if (var
->xres_virtual
< var
->xres
)
933 var
->xres_virtual
= var
->xres
;
935 vramlen
= info
->fix
.smem_len
;
937 memlen
= var
->xres_virtual
* var
->bits_per_pixel
*
938 var
->yres_virtual
/ 8;
939 if (memlen
> vramlen
) {
940 var
->yres_virtual
= vramlen
* 8 /
941 (var
->xres_virtual
* var
->bits_per_pixel
);
942 memlen
= var
->xres_virtual
* var
->bits_per_pixel
*
943 var
->yres_virtual
/ 8;
946 /* we must round yres/xres down, we already rounded y/xres_virtual up
947 if it was possible. We should return -EINVAL, but I disagree */
948 if (var
->yres_virtual
< var
->yres
)
949 var
->yres
= var
->yres_virtual
;
950 if (var
->xres_virtual
< var
->xres
)
951 var
->xres
= var
->xres_virtual
;
952 if (var
->xoffset
+ var
->xres
> var
->xres_virtual
)
953 var
->xoffset
= var
->xres_virtual
- var
->xres
;
954 if (var
->yoffset
+ var
->yres
> var
->yres_virtual
)
955 var
->yoffset
= var
->yres_virtual
- var
->yres
;
961 static int savagefb_decode_var (struct fb_var_screeninfo
*var
,
962 struct savagefb_par
*par
,
963 struct savage_reg
*reg
)
965 struct xtimings timings
;
966 int width
, dclk
, i
, j
; /*, refresh; */
967 unsigned int m
, n
, r
;
968 unsigned char tmp
= 0;
969 unsigned int pixclock
= var
->pixclock
;
971 DBG("savagefb_decode_var");
973 memset (&timings
, 0, sizeof(timings
));
975 if (!pixclock
) pixclock
= 10000; /* 10ns = 100MHz */
976 timings
.Clock
= 1000000000 / pixclock
;
977 if (timings
.Clock
< 1) timings
.Clock
= 1;
978 timings
.dblscan
= var
->vmode
& FB_VMODE_DOUBLE
;
979 timings
.interlaced
= var
->vmode
& FB_VMODE_INTERLACED
;
980 timings
.HDisplay
= var
->xres
;
981 timings
.HSyncStart
= timings
.HDisplay
+ var
->right_margin
;
982 timings
.HSyncEnd
= timings
.HSyncStart
+ var
->hsync_len
;
983 timings
.HTotal
= timings
.HSyncEnd
+ var
->left_margin
;
984 timings
.VDisplay
= var
->yres
;
985 timings
.VSyncStart
= timings
.VDisplay
+ var
->lower_margin
;
986 timings
.VSyncEnd
= timings
.VSyncStart
+ var
->vsync_len
;
987 timings
.VTotal
= timings
.VSyncEnd
+ var
->upper_margin
;
988 timings
.sync
= var
->sync
;
991 par
->depth
= var
->bits_per_pixel
;
992 par
->vwidth
= var
->xres_virtual
;
994 if (var
->bits_per_pixel
== 16 && par
->chip
== S3_SAVAGE3D
) {
995 timings
.HDisplay
*= 2;
996 timings
.HSyncStart
*= 2;
997 timings
.HSyncEnd
*= 2;
1002 * This will allocate the datastructure and initialize all of the
1003 * generic VGA registers.
1005 vgaHWInit (var
, par
, &timings
, reg
);
1007 /* We need to set CR67 whether or not we use the BIOS. */
1009 dclk
= timings
.Clock
;
1012 switch( var
->bits_per_pixel
) {
1014 if( (par
->chip
== S3_SAVAGE2000
) && (dclk
>= 230000) )
1015 reg
->CR67
= 0x10; /* 8bpp, 2 pixels/clock */
1017 reg
->CR67
= 0x00; /* 8bpp, 1 pixel/clock */
1020 if ( S3_SAVAGE_MOBILE_SERIES(par
->chip
) ||
1021 ((par
->chip
== S3_SAVAGE2000
) && (dclk
>= 230000)) )
1022 reg
->CR67
= 0x30; /* 15bpp, 2 pixel/clock */
1024 reg
->CR67
= 0x20; /* 15bpp, 1 pixels/clock */
1027 if( S3_SAVAGE_MOBILE_SERIES(par
->chip
) ||
1028 ((par
->chip
== S3_SAVAGE2000
) && (dclk
>= 230000)) )
1029 reg
->CR67
= 0x50; /* 16bpp, 2 pixel/clock */
1031 reg
->CR67
= 0x40; /* 16bpp, 1 pixels/clock */
1042 * Either BIOS use is disabled, or we failed to find a suitable
1043 * match. Fall back to traditional register-crunching.
1046 vga_out8 (0x3d4, 0x3a, par
);
1047 tmp
= vga_in8 (0x3d5, par
);
1048 if (1 /*FIXME:psav->pci_burst*/)
1049 reg
->CR3A
= (tmp
& 0x7f) | 0x15;
1051 reg
->CR3A
= tmp
| 0x95;
1057 vga_out8 (0x3d4, 0x58, par
);
1058 reg
->CR58
= vga_in8 (0x3d5, par
) & 0x80;
1061 reg
->SR15
= 0x03 | 0x80;
1063 reg
->CR43
= reg
->CR45
= reg
->CR65
= 0x00;
1065 vga_out8 (0x3d4, 0x40, par
);
1066 reg
->CR40
= vga_in8 (0x3d5, par
) & ~0x01;
1068 reg
->MMPR0
= 0x010400;
1070 reg
->MMPR2
= 0x0808;
1071 reg
->MMPR3
= 0x08080810;
1073 SavageCalcClock (dclk
, 1, 1, 127, 0, 4, 180000, 360000, &m
, &n
, &r
);
1074 /* m = 107; n = 4; r = 2; */
1076 if (par
->MCLK
<= 0) {
1080 common_calc_clock (par
->MCLK
, 1, 1, 31, 0, 3, 135000, 270000,
1081 ®
->SR11
, ®
->SR10
);
1082 /* reg->SR10 = 80; // MCLK == 286000 */
1083 /* reg->SR11 = 125; */
1086 reg
->SR12
= (r
<< 6) | (n
& 0x3f);
1087 reg
->SR13
= m
& 0xff;
1088 reg
->SR29
= (r
& 4) | (m
& 0x100) >> 5 | (n
& 0x40) >> 2;
1090 if (var
->bits_per_pixel
< 24)
1091 reg
->MMPR0
-= 0x8000;
1093 reg
->MMPR0
-= 0x4000;
1095 if (timings
.interlaced
)
1100 reg
->CR34
= 0x10; /* display fifo */
1102 i
= ((((timings
.HTotal
>> 3) - 5) & 0x100) >> 8) |
1103 ((((timings
.HDisplay
>> 3) - 1) & 0x100) >> 7) |
1104 ((((timings
.HSyncStart
>> 3) - 1) & 0x100) >> 6) |
1105 ((timings
.HSyncStart
& 0x800) >> 7);
1107 if ((timings
.HSyncEnd
>> 3) - (timings
.HSyncStart
>> 3) > 64)
1109 if ((timings
.HSyncEnd
>> 3) - (timings
.HSyncStart
>> 3) > 32)
1112 j
= (reg
->CRTC
[0] + ((i
& 0x01) << 8) +
1113 reg
->CRTC
[4] + ((i
& 0x10) << 4) + 1) / 2;
1115 if (j
- (reg
->CRTC
[4] + ((i
& 0x10) << 4)) < 4) {
1116 if (reg
->CRTC
[4] + ((i
& 0x10) << 4) + 4 <=
1117 reg
->CRTC
[0] + ((i
& 0x01) << 8))
1118 j
= reg
->CRTC
[4] + ((i
& 0x10) << 4) + 4;
1120 j
= reg
->CRTC
[0] + ((i
& 0x01) << 8) + 1;
1123 reg
->CR3B
= j
& 0xff;
1124 i
|= (j
& 0x100) >> 2;
1125 reg
->CR3C
= (reg
->CRTC
[0] + ((i
& 0x01) << 8)) / 2;
1127 reg
->CR5E
= (((timings
.VTotal
- 2) & 0x400) >> 10) |
1128 (((timings
.VDisplay
- 1) & 0x400) >> 9) |
1129 (((timings
.VSyncStart
) & 0x400) >> 8) |
1130 (((timings
.VSyncStart
) & 0x400) >> 6) | 0x40;
1131 width
= (var
->xres_virtual
* ((var
->bits_per_pixel
+7) / 8)) >> 3;
1132 reg
->CR91
= reg
->CRTC
[19] = 0xff & width
;
1133 reg
->CR51
= (0x300 & width
) >> 4;
1134 reg
->CR90
= 0x80 | (width
>> 8);
1135 reg
->MiscOutReg
|= 0x0c;
1137 /* Set frame buffer description. */
1139 if (var
->bits_per_pixel
<= 8)
1141 else if (var
->bits_per_pixel
<= 16)
1146 if (var
->xres_virtual
<= 640)
1148 else if (var
->xres_virtual
== 800)
1150 else if (var
->xres_virtual
== 1024)
1152 else if (var
->xres_virtual
== 1152)
1154 else if (var
->xres_virtual
== 1280)
1156 else if (var
->xres_virtual
== 1600)
1159 reg
->CR50
|= 0xc1; /* Use GBD */
1161 if( par
->chip
== S3_SAVAGE2000
)
1166 reg
->CRTC
[0x17] = 0xeb;
1170 vga_out8(0x3d4, 0x36, par
);
1171 reg
->CR36
= vga_in8 (0x3d5, par
);
1172 vga_out8 (0x3d4, 0x68, par
);
1173 reg
->CR68
= vga_in8 (0x3d5, par
);
1175 vga_out8 (0x3d4, 0x6f, par
);
1176 reg
->CR6F
= vga_in8 (0x3d5, par
);
1177 vga_out8 (0x3d4, 0x86, par
);
1178 reg
->CR86
= vga_in8 (0x3d5, par
);
1179 vga_out8 (0x3d4, 0x88, par
);
1180 reg
->CR88
= vga_in8 (0x3d5, par
) | 0x08;
1181 vga_out8 (0x3d4, 0xb0, par
);
1182 reg
->CRB0
= vga_in8 (0x3d5, par
) | 0x80;
1187 /* --------------------------------------------------------------------- */
1190 * Set a single color register. Return != 0 for invalid regno.
1192 static int savagefb_setcolreg(unsigned regno
,
1197 struct fb_info
*info
)
1199 struct savagefb_par
*par
= info
->par
;
1201 if (regno
>= NR_PALETTE
)
1204 par
->palette
[regno
].red
= red
;
1205 par
->palette
[regno
].green
= green
;
1206 par
->palette
[regno
].blue
= blue
;
1207 par
->palette
[regno
].transp
= transp
;
1209 switch (info
->var
.bits_per_pixel
) {
1211 vga_out8 (0x3c8, regno
, par
);
1213 vga_out8 (0x3c9, red
>> 10, par
);
1214 vga_out8 (0x3c9, green
>> 10, par
);
1215 vga_out8 (0x3c9, blue
>> 10, par
);
1220 ((u32
*)info
->pseudo_palette
)[regno
] =
1222 ((green
& 0xfc00) >> 5) |
1223 ((blue
& 0xf800) >> 11);
1228 ((u32
*)info
->pseudo_palette
)[regno
] =
1229 ((red
& 0xff00) << 8) |
1230 ((green
& 0xff00) ) |
1231 ((blue
& 0xff00) >> 8);
1235 ((u32
*)info
->pseudo_palette
)[regno
] =
1236 ((transp
& 0xff00) << 16) |
1237 ((red
& 0xff00) << 8) |
1238 ((green
& 0xff00) ) |
1239 ((blue
& 0xff00) >> 8);
1249 static void savagefb_set_par_int (struct savagefb_par
*par
, struct savage_reg
*reg
)
1251 unsigned char tmp
, cr3a
, cr66
, cr67
;
1253 DBG ("savagefb_set_par_int");
1255 par
->SavageWaitIdle (par
);
1257 vga_out8 (0x3c2, 0x23, par
);
1259 vga_out16 (0x3d4, 0x4838, par
);
1260 vga_out16 (0x3d4, 0xa539, par
);
1261 vga_out16 (0x3c4, 0x0608, par
);
1263 vgaHWProtect (par
, 1);
1266 * Some Savage/MX and /IX systems go nuts when trying to exit the
1267 * server after WindowMaker has displayed a gradient background. I
1268 * haven't been able to find what causes it, but a non-destructive
1269 * switch to mode 3 here seems to eliminate the issue.
1272 VerticalRetraceWait(par
);
1273 vga_out8 (0x3d4, 0x67, par
);
1274 cr67
= vga_in8 (0x3d5, par
);
1275 vga_out8 (0x3d5, cr67
/*par->CR67*/ & ~0x0c, par
); /* no STREAMS yet */
1277 vga_out8 (0x3d4, 0x23, par
);
1278 vga_out8 (0x3d5, 0x00, par
);
1279 vga_out8 (0x3d4, 0x26, par
);
1280 vga_out8 (0x3d5, 0x00, par
);
1282 /* restore extended regs */
1283 vga_out8 (0x3d4, 0x66, par
);
1284 vga_out8 (0x3d5, reg
->CR66
, par
);
1285 vga_out8 (0x3d4, 0x3a, par
);
1286 vga_out8 (0x3d5, reg
->CR3A
, par
);
1287 vga_out8 (0x3d4, 0x31, par
);
1288 vga_out8 (0x3d5, reg
->CR31
, par
);
1289 vga_out8 (0x3d4, 0x32, par
);
1290 vga_out8 (0x3d5, reg
->CR32
, par
);
1291 vga_out8 (0x3d4, 0x58, par
);
1292 vga_out8 (0x3d5, reg
->CR58
, par
);
1293 vga_out8 (0x3d4, 0x53, par
);
1294 vga_out8 (0x3d5, reg
->CR53
& 0x7f, par
);
1296 vga_out16 (0x3c4, 0x0608, par
);
1298 /* Restore DCLK registers. */
1300 vga_out8 (0x3c4, 0x0e, par
);
1301 vga_out8 (0x3c5, reg
->SR0E
, par
);
1302 vga_out8 (0x3c4, 0x0f, par
);
1303 vga_out8 (0x3c5, reg
->SR0F
, par
);
1304 vga_out8 (0x3c4, 0x29, par
);
1305 vga_out8 (0x3c5, reg
->SR29
, par
);
1306 vga_out8 (0x3c4, 0x15, par
);
1307 vga_out8 (0x3c5, reg
->SR15
, par
);
1309 /* Restore flat panel expansion regsters. */
1310 if( par
->chip
== S3_SAVAGE_MX
) {
1313 for( i
= 0; i
< 8; i
++ ) {
1314 vga_out8 (0x3c4, 0x54+i
, par
);
1315 vga_out8 (0x3c5, reg
->SR54
[i
], par
);
1319 vgaHWRestore (par
, reg
);
1321 /* extended mode timing registers */
1322 vga_out8 (0x3d4, 0x53, par
);
1323 vga_out8 (0x3d5, reg
->CR53
, par
);
1324 vga_out8 (0x3d4, 0x5d, par
);
1325 vga_out8 (0x3d5, reg
->CR5D
, par
);
1326 vga_out8 (0x3d4, 0x5e, par
);
1327 vga_out8 (0x3d5, reg
->CR5E
, par
);
1328 vga_out8 (0x3d4, 0x3b, par
);
1329 vga_out8 (0x3d5, reg
->CR3B
, par
);
1330 vga_out8 (0x3d4, 0x3c, par
);
1331 vga_out8 (0x3d5, reg
->CR3C
, par
);
1332 vga_out8 (0x3d4, 0x43, par
);
1333 vga_out8 (0x3d5, reg
->CR43
, par
);
1334 vga_out8 (0x3d4, 0x65, par
);
1335 vga_out8 (0x3d5, reg
->CR65
, par
);
1337 /* restore the desired video mode with cr67 */
1338 vga_out8 (0x3d4, 0x67, par
);
1339 /* following part not present in X11 driver */
1340 cr67
= vga_in8 (0x3d5, par
) & 0xf;
1341 vga_out8 (0x3d5, 0x50 | cr67
, par
);
1343 vga_out8 (0x3d4, 0x67, par
);
1345 vga_out8 (0x3d5, reg
->CR67
& ~0x0c, par
);
1347 /* other mode timing and extended regs */
1348 vga_out8 (0x3d4, 0x34, par
);
1349 vga_out8 (0x3d5, reg
->CR34
, par
);
1350 vga_out8 (0x3d4, 0x40, par
);
1351 vga_out8 (0x3d5, reg
->CR40
, par
);
1352 vga_out8 (0x3d4, 0x42, par
);
1353 vga_out8 (0x3d5, reg
->CR42
, par
);
1354 vga_out8 (0x3d4, 0x45, par
);
1355 vga_out8 (0x3d5, reg
->CR45
, par
);
1356 vga_out8 (0x3d4, 0x50, par
);
1357 vga_out8 (0x3d5, reg
->CR50
, par
);
1358 vga_out8 (0x3d4, 0x51, par
);
1359 vga_out8 (0x3d5, reg
->CR51
, par
);
1361 /* memory timings */
1362 vga_out8 (0x3d4, 0x36, par
);
1363 vga_out8 (0x3d5, reg
->CR36
, par
);
1364 vga_out8 (0x3d4, 0x60, par
);
1365 vga_out8 (0x3d5, reg
->CR60
, par
);
1366 vga_out8 (0x3d4, 0x68, par
);
1367 vga_out8 (0x3d5, reg
->CR68
, par
);
1368 vga_out8 (0x3d4, 0x69, par
);
1369 vga_out8 (0x3d5, reg
->CR69
, par
);
1370 vga_out8 (0x3d4, 0x6f, par
);
1371 vga_out8 (0x3d5, reg
->CR6F
, par
);
1373 vga_out8 (0x3d4, 0x33, par
);
1374 vga_out8 (0x3d5, reg
->CR33
, par
);
1375 vga_out8 (0x3d4, 0x86, par
);
1376 vga_out8 (0x3d5, reg
->CR86
, par
);
1377 vga_out8 (0x3d4, 0x88, par
);
1378 vga_out8 (0x3d5, reg
->CR88
, par
);
1379 vga_out8 (0x3d4, 0x90, par
);
1380 vga_out8 (0x3d5, reg
->CR90
, par
);
1381 vga_out8 (0x3d4, 0x91, par
);
1382 vga_out8 (0x3d5, reg
->CR91
, par
);
1384 if (par
->chip
== S3_SAVAGE4
) {
1385 vga_out8 (0x3d4, 0xb0, par
);
1386 vga_out8 (0x3d5, reg
->CRB0
, par
);
1389 vga_out8 (0x3d4, 0x32, par
);
1390 vga_out8 (0x3d5, reg
->CR32
, par
);
1392 /* unlock extended seq regs */
1393 vga_out8 (0x3c4, 0x08, par
);
1394 vga_out8 (0x3c5, 0x06, par
);
1396 /* Restore extended sequencer regs for MCLK. SR10 == 255 indicates
1397 * that we should leave the default SR10 and SR11 values there.
1399 if (reg
->SR10
!= 255) {
1400 vga_out8 (0x3c4, 0x10, par
);
1401 vga_out8 (0x3c5, reg
->SR10
, par
);
1402 vga_out8 (0x3c4, 0x11, par
);
1403 vga_out8 (0x3c5, reg
->SR11
, par
);
1406 /* restore extended seq regs for dclk */
1407 vga_out8 (0x3c4, 0x0e, par
);
1408 vga_out8 (0x3c5, reg
->SR0E
, par
);
1409 vga_out8 (0x3c4, 0x0f, par
);
1410 vga_out8 (0x3c5, reg
->SR0F
, par
);
1411 vga_out8 (0x3c4, 0x12, par
);
1412 vga_out8 (0x3c5, reg
->SR12
, par
);
1413 vga_out8 (0x3c4, 0x13, par
);
1414 vga_out8 (0x3c5, reg
->SR13
, par
);
1415 vga_out8 (0x3c4, 0x29, par
);
1416 vga_out8 (0x3c5, reg
->SR29
, par
);
1418 vga_out8 (0x3c4, 0x18, par
);
1419 vga_out8 (0x3c5, reg
->SR18
, par
);
1421 /* load new m, n pll values for dclk & mclk */
1422 vga_out8 (0x3c4, 0x15, par
);
1423 tmp
= vga_in8 (0x3c5, par
) & ~0x21;
1425 vga_out8 (0x3c5, tmp
| 0x03, par
);
1426 vga_out8 (0x3c5, tmp
| 0x23, par
);
1427 vga_out8 (0x3c5, tmp
| 0x03, par
);
1428 vga_out8 (0x3c5, reg
->SR15
, par
);
1431 vga_out8 (0x3c4, 0x30, par
);
1432 vga_out8 (0x3c5, reg
->SR30
, par
);
1433 vga_out8 (0x3c4, 0x08, par
);
1434 vga_out8 (0x3c5, reg
->SR08
, par
);
1436 /* now write out cr67 in full, possibly starting STREAMS */
1437 VerticalRetraceWait(par
);
1438 vga_out8 (0x3d4, 0x67, par
);
1439 vga_out8 (0x3d5, reg
->CR67
, par
);
1441 vga_out8 (0x3d4, 0x66, par
);
1442 cr66
= vga_in8 (0x3d5, par
);
1443 vga_out8 (0x3d5, cr66
| 0x80, par
);
1444 vga_out8 (0x3d4, 0x3a, par
);
1445 cr3a
= vga_in8 (0x3d5, par
);
1446 vga_out8 (0x3d5, cr3a
| 0x80, par
);
1448 if (par
->chip
!= S3_SAVAGE_MX
) {
1449 VerticalRetraceWait(par
);
1450 savage_out32 (FIFO_CONTROL_REG
, reg
->MMPR0
, par
);
1451 par
->SavageWaitIdle (par
);
1452 savage_out32 (MIU_CONTROL_REG
, reg
->MMPR1
, par
);
1453 par
->SavageWaitIdle (par
);
1454 savage_out32 (STREAMS_TIMEOUT_REG
, reg
->MMPR2
, par
);
1455 par
->SavageWaitIdle (par
);
1456 savage_out32 (MISC_TIMEOUT_REG
, reg
->MMPR3
, par
);
1459 vga_out8 (0x3d4, 0x66, par
);
1460 vga_out8 (0x3d5, cr66
, par
);
1461 vga_out8 (0x3d4, 0x3a, par
);
1462 vga_out8 (0x3d5, cr3a
, par
);
1464 SavageSetup2DEngine (par
);
1465 vgaHWProtect (par
, 0);
1468 static void savagefb_update_start (struct savagefb_par
*par
,
1469 struct fb_var_screeninfo
*var
)
1473 base
= ((var
->yoffset
* var
->xres_virtual
+ (var
->xoffset
& ~1))
1474 * ((var
->bits_per_pixel
+7) / 8)) >> 2;
1476 /* now program the start address registers */
1477 vga_out16(0x3d4, (base
& 0x00ff00) | 0x0c, par
);
1478 vga_out16(0x3d4, ((base
& 0x00ff) << 8) | 0x0d, par
);
1479 vga_out8 (0x3d4, 0x69, par
);
1480 vga_out8 (0x3d5, (base
& 0x7f0000) >> 16, par
);
1484 static void savagefb_set_fix(struct fb_info
*info
)
1486 info
->fix
.line_length
= info
->var
.xres_virtual
*
1487 info
->var
.bits_per_pixel
/ 8;
1489 if (info
->var
.bits_per_pixel
== 8) {
1490 info
->fix
.visual
= FB_VISUAL_PSEUDOCOLOR
;
1491 info
->fix
.xpanstep
= 4;
1493 info
->fix
.visual
= FB_VISUAL_TRUECOLOR
;
1494 info
->fix
.xpanstep
= 2;
1499 static int savagefb_set_par (struct fb_info
*info
)
1501 struct savagefb_par
*par
= info
->par
;
1502 struct fb_var_screeninfo
*var
= &info
->var
;
1505 DBG("savagefb_set_par");
1506 err
= savagefb_decode_var (var
, par
, &par
->state
);
1510 if (par
->dacSpeedBpp
<= 0) {
1511 if (var
->bits_per_pixel
> 24)
1512 par
->dacSpeedBpp
= par
->clock
[3];
1513 else if (var
->bits_per_pixel
>= 24)
1514 par
->dacSpeedBpp
= par
->clock
[2];
1515 else if ((var
->bits_per_pixel
> 8) && (var
->bits_per_pixel
< 24))
1516 par
->dacSpeedBpp
= par
->clock
[1];
1517 else if (var
->bits_per_pixel
<= 8)
1518 par
->dacSpeedBpp
= par
->clock
[0];
1521 /* Set ramdac limits */
1522 par
->maxClock
= par
->dacSpeedBpp
;
1523 par
->minClock
= 10000;
1525 savagefb_set_par_int (par
, &par
->state
);
1526 fb_set_cmap (&info
->cmap
, info
);
1527 savagefb_set_fix(info
);
1528 savagefb_set_clip(info
);
1535 * Pan or Wrap the Display
1537 static int savagefb_pan_display (struct fb_var_screeninfo
*var
,
1538 struct fb_info
*info
)
1540 struct savagefb_par
*par
= info
->par
;
1542 savagefb_update_start (par
, var
);
1546 static int savagefb_blank(int blank
, struct fb_info
*info
)
1548 struct savagefb_par
*par
= info
->par
;
1549 u8 sr8
= 0, srd
= 0;
1551 if (par
->display_type
== DISP_CRT
) {
1552 vga_out8(0x3c4, 0x08, par
);
1553 sr8
= vga_in8(0x3c5, par
);
1555 vga_out8(0x3c5, sr8
, par
);
1556 vga_out8(0x3c4, 0x0d, par
);
1557 srd
= vga_in8(0x3c5, par
);
1561 case FB_BLANK_UNBLANK
:
1562 case FB_BLANK_NORMAL
:
1564 case FB_BLANK_VSYNC_SUSPEND
:
1567 case FB_BLANK_HSYNC_SUSPEND
:
1570 case FB_BLANK_POWERDOWN
:
1575 vga_out8(0x3c4, 0x0d, par
);
1576 vga_out8(0x3c5, srd
, par
);
1579 if (par
->display_type
== DISP_LCD
||
1580 par
->display_type
== DISP_DFP
) {
1582 case FB_BLANK_UNBLANK
:
1583 case FB_BLANK_NORMAL
:
1584 vga_out8(0x3c4, 0x31, par
); /* SR31 bit 4 - FP enable */
1585 vga_out8(0x3c5, vga_in8(0x3c5, par
) | 0x10, par
);
1587 case FB_BLANK_VSYNC_SUSPEND
:
1588 case FB_BLANK_HSYNC_SUSPEND
:
1589 case FB_BLANK_POWERDOWN
:
1590 vga_out8(0x3c4, 0x31, par
); /* SR31 bit 4 - FP enable */
1591 vga_out8(0x3c5, vga_in8(0x3c5, par
) & ~0x10, par
);
1596 return (blank
== FB_BLANK_NORMAL
) ? 1 : 0;
1599 static void savagefb_save_state(struct fb_info
*info
)
1601 struct savagefb_par
*par
= info
->par
;
1603 savage_get_default_par(par
, &par
->save
);
1606 static void savagefb_restore_state(struct fb_info
*info
)
1608 struct savagefb_par
*par
= info
->par
;
1610 savagefb_blank(FB_BLANK_POWERDOWN
, info
);
1611 savage_set_default_par(par
, &par
->save
);
1612 savagefb_blank(FB_BLANK_UNBLANK
, info
);
1615 static struct fb_ops savagefb_ops
= {
1616 .owner
= THIS_MODULE
,
1617 .fb_check_var
= savagefb_check_var
,
1618 .fb_set_par
= savagefb_set_par
,
1619 .fb_setcolreg
= savagefb_setcolreg
,
1620 .fb_pan_display
= savagefb_pan_display
,
1621 .fb_blank
= savagefb_blank
,
1622 .fb_save_state
= savagefb_save_state
,
1623 .fb_restore_state
= savagefb_restore_state
,
1624 #if defined(CONFIG_FB_SAVAGE_ACCEL)
1625 .fb_fillrect
= savagefb_fillrect
,
1626 .fb_copyarea
= savagefb_copyarea
,
1627 .fb_imageblit
= savagefb_imageblit
,
1628 .fb_sync
= savagefb_sync
,
1630 .fb_fillrect
= cfb_fillrect
,
1631 .fb_copyarea
= cfb_copyarea
,
1632 .fb_imageblit
= cfb_imageblit
,
1636 /* --------------------------------------------------------------------- */
1638 static struct fb_var_screeninfo __devinitdata savagefb_var800x600x8
= {
1639 .accel_flags
= FB_ACCELF_TEXT
,
1642 .xres_virtual
= 800,
1643 .yres_virtual
= 600,
1644 .bits_per_pixel
= 8,
1652 .sync
= FB_SYNC_HOR_HIGH_ACT
| FB_SYNC_VERT_HIGH_ACT
,
1653 .vmode
= FB_VMODE_NONINTERLACED
1656 static void savage_enable_mmio (struct savagefb_par
*par
)
1660 DBG ("savage_enable_mmio\n");
1662 val
= vga_in8 (0x3c3, par
);
1663 vga_out8 (0x3c3, val
| 0x01, par
);
1664 val
= vga_in8 (0x3cc, par
);
1665 vga_out8 (0x3c2, val
| 0x01, par
);
1667 if (par
->chip
>= S3_SAVAGE4
) {
1668 vga_out8 (0x3d4, 0x40, par
);
1669 val
= vga_in8 (0x3d5, par
);
1670 vga_out8 (0x3d5, val
| 1, par
);
1675 static void savage_disable_mmio (struct savagefb_par
*par
)
1679 DBG ("savage_disable_mmio\n");
1681 if(par
->chip
>= S3_SAVAGE4
) {
1682 vga_out8 (0x3d4, 0x40, par
);
1683 val
= vga_in8 (0x3d5, par
);
1684 vga_out8 (0x3d5, val
| 1, par
);
1689 static int __devinit
savage_map_mmio (struct fb_info
*info
)
1691 struct savagefb_par
*par
= info
->par
;
1692 DBG ("savage_map_mmio");
1694 if (S3_SAVAGE3D_SERIES (par
->chip
))
1695 par
->mmio
.pbase
= pci_resource_start (par
->pcidev
, 0) +
1696 SAVAGE_NEWMMIO_REGBASE_S3
;
1698 par
->mmio
.pbase
= pci_resource_start (par
->pcidev
, 0) +
1699 SAVAGE_NEWMMIO_REGBASE_S4
;
1701 par
->mmio
.len
= SAVAGE_NEWMMIO_REGSIZE
;
1703 par
->mmio
.vbase
= ioremap (par
->mmio
.pbase
, par
->mmio
.len
);
1704 if (!par
->mmio
.vbase
) {
1705 printk ("savagefb: unable to map memory mapped IO\n");
1708 printk (KERN_INFO
"savagefb: mapped io at %p\n",
1711 info
->fix
.mmio_start
= par
->mmio
.pbase
;
1712 info
->fix
.mmio_len
= par
->mmio
.len
;
1714 par
->bci_base
= (u32 __iomem
*)(par
->mmio
.vbase
+ BCI_BUFFER_OFFSET
);
1717 savage_enable_mmio (par
);
1722 static void savage_unmap_mmio (struct fb_info
*info
)
1724 struct savagefb_par
*par
= info
->par
;
1725 DBG ("savage_unmap_mmio");
1727 savage_disable_mmio(par
);
1729 if (par
->mmio
.vbase
) {
1730 iounmap(par
->mmio
.vbase
);
1731 par
->mmio
.vbase
= NULL
;
1735 static int __devinit
savage_map_video (struct fb_info
*info
,
1738 struct savagefb_par
*par
= info
->par
;
1741 DBG("savage_map_video");
1743 if (S3_SAVAGE3D_SERIES (par
->chip
))
1748 par
->video
.pbase
= pci_resource_start (par
->pcidev
, resource
);
1749 par
->video
.len
= video_len
;
1750 par
->video
.vbase
= ioremap (par
->video
.pbase
, par
->video
.len
);
1752 if (!par
->video
.vbase
) {
1753 printk ("savagefb: unable to map screen memory\n");
1756 printk (KERN_INFO
"savagefb: mapped framebuffer at %p, "
1757 "pbase == %x\n", par
->video
.vbase
, par
->video
.pbase
);
1759 info
->fix
.smem_start
= par
->video
.pbase
;
1760 info
->fix
.smem_len
= par
->video
.len
- par
->cob_size
;
1761 info
->screen_base
= par
->video
.vbase
;
1764 par
->video
.mtrr
= mtrr_add (par
->video
.pbase
, video_len
,
1765 MTRR_TYPE_WRCOMB
, 1);
1768 /* Clear framebuffer, it's all white in memory after boot */
1769 memset_io (par
->video
.vbase
, 0, par
->video
.len
);
1774 static void savage_unmap_video (struct fb_info
*info
)
1776 struct savagefb_par
*par
= info
->par
;
1778 DBG("savage_unmap_video");
1780 if (par
->video
.vbase
) {
1782 mtrr_del (par
->video
.mtrr
, par
->video
.pbase
, par
->video
.len
);
1785 iounmap (par
->video
.vbase
);
1786 par
->video
.vbase
= NULL
;
1787 info
->screen_base
= NULL
;
1791 static int savage_init_hw (struct savagefb_par
*par
)
1793 unsigned char config1
, m
, n
, n1
, n2
, sr8
, cr3f
, cr66
= 0, tmp
;
1795 static unsigned char RamSavage3D
[] = { 8, 4, 4, 2 };
1796 static unsigned char RamSavage4
[] = { 2, 4, 8, 12, 16, 32, 64, 32 };
1797 static unsigned char RamSavageMX
[] = { 2, 8, 4, 16, 8, 16, 4, 16 };
1798 static unsigned char RamSavageNB
[] = { 0, 2, 4, 8, 16, 32, 2, 2 };
1799 int videoRam
, videoRambytes
, dvi
;
1801 DBG("savage_init_hw");
1803 /* unprotect CRTC[0-7] */
1804 vga_out8(0x3d4, 0x11, par
);
1805 tmp
= vga_in8(0x3d5, par
);
1806 vga_out8(0x3d5, tmp
& 0x7f, par
);
1808 /* unlock extended regs */
1809 vga_out16(0x3d4, 0x4838, par
);
1810 vga_out16(0x3d4, 0xa039, par
);
1811 vga_out16(0x3c4, 0x0608, par
);
1813 vga_out8(0x3d4, 0x40, par
);
1814 tmp
= vga_in8(0x3d5, par
);
1815 vga_out8(0x3d5, tmp
& ~0x01, par
);
1817 /* unlock sys regs */
1818 vga_out8(0x3d4, 0x38, par
);
1819 vga_out8(0x3d5, 0x48, par
);
1821 /* Unlock system registers. */
1822 vga_out16(0x3d4, 0x4838, par
);
1824 /* Next go on to detect amount of installed ram */
1826 vga_out8(0x3d4, 0x36, par
); /* for register CR36 (CONFG_REG1), */
1827 config1
= vga_in8(0x3d5, par
); /* get amount of vram installed */
1829 /* Compute the amount of video memory and offscreen memory. */
1831 switch (par
->chip
) {
1833 videoRam
= RamSavage3D
[ (config1
& 0xC0) >> 6 ] * 1024;
1838 * The Savage4 has one ugly special case to consider. On
1839 * systems with 4 banks of 2Mx32 SDRAM, the BIOS says 4MB
1840 * when it really means 8MB. Why do it the same when you
1841 * can do it different...
1843 vga_out8(0x3d4, 0x68, par
); /* memory control 1 */
1844 if( (vga_in8(0x3d5, par
) & 0xC0) == (0x01 << 6) )
1850 videoRam
= RamSavage4
[ (config1
& 0xE0) >> 5 ] * 1024;
1854 case S3_SUPERSAVAGE
:
1855 videoRam
= RamSavageMX
[ (config1
& 0x0E) >> 1 ] * 1024;
1859 videoRam
= RamSavageNB
[ (config1
& 0xE0) >> 5 ] * 1024;
1863 /* How did we get here? */
1868 videoRambytes
= videoRam
* 1024;
1870 printk (KERN_INFO
"savagefb: probed videoram: %dk\n", videoRam
);
1872 /* reset graphics engine to avoid memory corruption */
1873 vga_out8 (0x3d4, 0x66, par
);
1874 cr66
= vga_in8 (0x3d5, par
);
1875 vga_out8 (0x3d5, cr66
| 0x02, par
);
1878 vga_out8 (0x3d4, 0x66, par
);
1879 vga_out8 (0x3d5, cr66
& ~0x02, par
); /* clear reset flag */
1884 * reset memory interface, 3D engine, AGP master, PCI master,
1885 * master engine unit, motion compensation/LPB
1887 vga_out8 (0x3d4, 0x3f, par
);
1888 cr3f
= vga_in8 (0x3d5, par
);
1889 vga_out8 (0x3d5, cr3f
| 0x08, par
);
1892 vga_out8 (0x3d4, 0x3f, par
);
1893 vga_out8 (0x3d5, cr3f
& ~0x08, par
); /* clear reset flags */
1896 /* Savage ramdac speeds */
1898 par
->clock
[0] = 250000;
1899 par
->clock
[1] = 250000;
1900 par
->clock
[2] = 220000;
1901 par
->clock
[3] = 220000;
1903 /* detect current mclk */
1904 vga_out8(0x3c4, 0x08, par
);
1905 sr8
= vga_in8(0x3c5, par
);
1906 vga_out8(0x3c5, 0x06, par
);
1907 vga_out8(0x3c4, 0x10, par
);
1908 n
= vga_in8(0x3c5, par
);
1909 vga_out8(0x3c4, 0x11, par
);
1910 m
= vga_in8(0x3c5, par
);
1911 vga_out8(0x3c4, 0x08, par
);
1912 vga_out8(0x3c5, sr8
, par
);
1915 n2
= (n
>> 5) & 0x03;
1916 par
->MCLK
= ((1431818 * (m
+2)) / (n1
+2) / (1 << n2
) + 50) / 100;
1917 printk (KERN_INFO
"savagefb: Detected current MCLK value of %d kHz\n",
1920 /* check for DVI/flat panel */
1923 if (par
->chip
== S3_SAVAGE4
) {
1924 unsigned char sr30
= 0x00;
1926 vga_out8(0x3c4, 0x30, par
);
1928 vga_out8(0x3c5, vga_in8(0x3c5, par
) & ~0x02, par
);
1929 sr30
= vga_in8(0x3c5, par
);
1930 if (sr30
& 0x02 /*0x04 */) {
1932 printk("savagefb: Digital Flat Panel Detected\n");
1936 if (S3_SAVAGE_MOBILE_SERIES(par
->chip
) && !par
->crtonly
)
1937 par
->display_type
= DISP_LCD
;
1938 else if (dvi
|| (par
->chip
== S3_SAVAGE4
&& par
->dvi
))
1939 par
->display_type
= DISP_DFP
;
1941 par
->display_type
= DISP_CRT
;
1943 /* Check LCD panel parrmation */
1945 if (par
->display_type
== DISP_LCD
) {
1946 unsigned char cr6b
= VGArCR( 0x6b, par
);
1948 int panelX
= (VGArSEQ (0x61, par
) +
1949 ((VGArSEQ (0x66, par
) & 0x02) << 7) + 1) * 8;
1950 int panelY
= (VGArSEQ (0x69, par
) +
1951 ((VGArSEQ (0x6e, par
) & 0x70) << 4) + 1);
1953 char * sTechnology
= "Unknown";
1955 /* OK, I admit it. I don't know how to limit the max dot clock
1956 * for LCD panels of various sizes. I thought I copied the
1957 * formula from the BIOS, but many users have parrmed me of
1960 * Instead, I'll abandon any attempt to automatically limit the
1961 * clock, and add an LCDClock option to XF86Config. Some day,
1962 * I should come back to this.
1965 enum ACTIVE_DISPLAYS
{ /* These are the bits in CR6B */
1973 if ((VGArSEQ (0x39, par
) & 0x03) == 0) {
1974 sTechnology
= "TFT";
1975 } else if ((VGArSEQ (0x30, par
) & 0x01) == 0) {
1976 sTechnology
= "DSTN";
1978 sTechnology
= "STN";
1981 printk (KERN_INFO
"savagefb: %dx%d %s LCD panel detected %s\n",
1982 panelX
, panelY
, sTechnology
,
1983 cr6b
& ActiveLCD
? "and active" : "but not active");
1985 if( cr6b
& ActiveLCD
) {
1987 * If the LCD is active and panel expansion is enabled,
1988 * we probably want to kill the HW cursor.
1991 printk (KERN_INFO
"savagefb: Limiting video mode to "
1992 "%dx%d\n", panelX
, panelY
);
1994 par
->SavagePanelWidth
= panelX
;
1995 par
->SavagePanelHeight
= panelY
;
1998 par
->display_type
= DISP_CRT
;
2001 savage_get_default_par (par
, &par
->state
);
2002 par
->save
= par
->state
;
2004 if( S3_SAVAGE4_SERIES(par
->chip
) ) {
2006 * The Savage4 and ProSavage have COB coherency bugs which
2007 * render the buffer useless. We disable it.
2010 par
->cob_size
= 0x8000 << par
->cob_index
;
2011 par
->cob_offset
= videoRambytes
;
2013 /* We use 128kB for the COB on all chips. */
2016 par
->cob_size
= 0x400 << par
->cob_index
;
2017 par
->cob_offset
= videoRambytes
- par
->cob_size
;
2020 return videoRambytes
;
2023 static int __devinit
savage_init_fb_info (struct fb_info
*info
,
2024 struct pci_dev
*dev
,
2025 const struct pci_device_id
*id
)
2027 struct savagefb_par
*par
= info
->par
;
2032 info
->fix
.type
= FB_TYPE_PACKED_PIXELS
;
2033 info
->fix
.type_aux
= 0;
2034 info
->fix
.ypanstep
= 1;
2035 info
->fix
.ywrapstep
= 0;
2036 info
->fix
.accel
= id
->driver_data
;
2038 switch (info
->fix
.accel
) {
2039 case FB_ACCEL_SUPERSAVAGE
:
2040 par
->chip
= S3_SUPERSAVAGE
;
2041 snprintf (info
->fix
.id
, 16, "SuperSavage");
2043 case FB_ACCEL_SAVAGE4
:
2044 par
->chip
= S3_SAVAGE4
;
2045 snprintf (info
->fix
.id
, 16, "Savage4");
2047 case FB_ACCEL_SAVAGE3D
:
2048 par
->chip
= S3_SAVAGE3D
;
2049 snprintf (info
->fix
.id
, 16, "Savage3D");
2051 case FB_ACCEL_SAVAGE3D_MV
:
2052 par
->chip
= S3_SAVAGE3D
;
2053 snprintf (info
->fix
.id
, 16, "Savage3D-MV");
2055 case FB_ACCEL_SAVAGE2000
:
2056 par
->chip
= S3_SAVAGE2000
;
2057 snprintf (info
->fix
.id
, 16, "Savage2000");
2059 case FB_ACCEL_SAVAGE_MX_MV
:
2060 par
->chip
= S3_SAVAGE_MX
;
2061 snprintf (info
->fix
.id
, 16, "Savage/MX-MV");
2063 case FB_ACCEL_SAVAGE_MX
:
2064 par
->chip
= S3_SAVAGE_MX
;
2065 snprintf (info
->fix
.id
, 16, "Savage/MX");
2067 case FB_ACCEL_SAVAGE_IX_MV
:
2068 par
->chip
= S3_SAVAGE_MX
;
2069 snprintf (info
->fix
.id
, 16, "Savage/IX-MV");
2071 case FB_ACCEL_SAVAGE_IX
:
2072 par
->chip
= S3_SAVAGE_MX
;
2073 snprintf (info
->fix
.id
, 16, "Savage/IX");
2075 case FB_ACCEL_PROSAVAGE_PM
:
2076 par
->chip
= S3_PROSAVAGE
;
2077 snprintf (info
->fix
.id
, 16, "ProSavagePM");
2079 case FB_ACCEL_PROSAVAGE_KM
:
2080 par
->chip
= S3_PROSAVAGE
;
2081 snprintf (info
->fix
.id
, 16, "ProSavageKM");
2083 case FB_ACCEL_S3TWISTER_P
:
2084 par
->chip
= S3_PROSAVAGE
;
2085 snprintf (info
->fix
.id
, 16, "TwisterP");
2087 case FB_ACCEL_S3TWISTER_K
:
2088 par
->chip
= S3_PROSAVAGE
;
2089 snprintf (info
->fix
.id
, 16, "TwisterK");
2091 case FB_ACCEL_PROSAVAGE_DDR
:
2092 par
->chip
= S3_PROSAVAGE
;
2093 snprintf (info
->fix
.id
, 16, "ProSavageDDR");
2095 case FB_ACCEL_PROSAVAGE_DDRK
:
2096 par
->chip
= S3_PROSAVAGE
;
2097 snprintf (info
->fix
.id
, 16, "ProSavage8");
2101 if (S3_SAVAGE3D_SERIES(par
->chip
)) {
2102 par
->SavageWaitIdle
= savage3D_waitidle
;
2103 par
->SavageWaitFifo
= savage3D_waitfifo
;
2104 } else if (S3_SAVAGE4_SERIES(par
->chip
) ||
2105 S3_SUPERSAVAGE
== par
->chip
) {
2106 par
->SavageWaitIdle
= savage4_waitidle
;
2107 par
->SavageWaitFifo
= savage4_waitfifo
;
2109 par
->SavageWaitIdle
= savage2000_waitidle
;
2110 par
->SavageWaitFifo
= savage2000_waitfifo
;
2113 info
->var
.nonstd
= 0;
2114 info
->var
.activate
= FB_ACTIVATE_NOW
;
2115 info
->var
.width
= -1;
2116 info
->var
.height
= -1;
2117 info
->var
.accel_flags
= 0;
2119 info
->fbops
= &savagefb_ops
;
2120 info
->flags
= FBINFO_DEFAULT
|
2121 FBINFO_HWACCEL_YPAN
|
2122 FBINFO_HWACCEL_XPAN
;
2124 info
->pseudo_palette
= par
->pseudo_palette
;
2126 #if defined(CONFIG_FB_SAVAGE_ACCEL)
2127 /* FIFO size + padding for commands */
2128 info
->pixmap
.addr
= kmalloc(8*1024, GFP_KERNEL
);
2131 if (info
->pixmap
.addr
) {
2132 memset(info
->pixmap
.addr
, 0, 8*1024);
2133 info
->pixmap
.size
= 8*1024;
2134 info
->pixmap
.scan_align
= 4;
2135 info
->pixmap
.buf_align
= 4;
2136 info
->pixmap
.access_align
= 32;
2138 err
= fb_alloc_cmap (&info
->cmap
, NR_PALETTE
, 0);
2140 info
->flags
|= FBINFO_HWACCEL_COPYAREA
|
2141 FBINFO_HWACCEL_FILLRECT
|
2142 FBINFO_HWACCEL_IMAGEBLIT
;
2148 /* --------------------------------------------------------------------- */
2150 static int __devinit
savagefb_probe (struct pci_dev
* dev
,
2151 const struct pci_device_id
* id
)
2153 struct fb_info
*info
;
2154 struct savagefb_par
*par
;
2155 u_int h_sync
, v_sync
;
2159 DBG("savagefb_probe");
2162 info
= framebuffer_alloc(sizeof(struct savagefb_par
), &dev
->dev
);
2166 err
= pci_enable_device(dev
);
2170 if ((err
= pci_request_regions(dev
, "savagefb"))) {
2171 printk(KERN_ERR
"cannot request PCI regions\n");
2177 if ((err
= savage_init_fb_info(info
, dev
, id
)))
2180 err
= savage_map_mmio(info
);
2184 video_len
= savage_init_hw(par
);
2185 /* FIXME: cant be negative */
2186 if (video_len
< 0) {
2191 err
= savage_map_video(info
, video_len
);
2195 INIT_LIST_HEAD(&info
->modelist
);
2196 #if defined(CONFIG_FB_SAVAGE_I2C)
2197 savagefb_create_i2c_busses(info
);
2198 savagefb_probe_i2c_connector(info
, &par
->edid
);
2199 fb_edid_to_monspecs(par
->edid
, &info
->monspecs
);
2201 fb_videomode_to_modelist(info
->monspecs
.modedb
,
2202 info
->monspecs
.modedb_len
,
2205 info
->var
= savagefb_var800x600x8
;
2208 fb_find_mode(&info
->var
, info
, mode_option
,
2209 info
->monspecs
.modedb
, info
->monspecs
.modedb_len
,
2211 } else if (info
->monspecs
.modedb
!= NULL
) {
2212 struct fb_videomode
*modedb
;
2214 modedb
= fb_find_best_display(&info
->monspecs
,
2216 savage_update_var(&info
->var
, modedb
);
2219 /* maximize virtual vertical length */
2220 lpitch
= info
->var
.xres_virtual
*((info
->var
.bits_per_pixel
+ 7) >> 3);
2221 info
->var
.yres_virtual
= info
->fix
.smem_len
/lpitch
;
2223 if (info
->var
.yres_virtual
< info
->var
.yres
)
2226 #if defined(CONFIG_FB_SAVAGE_ACCEL)
2228 * The clipping coordinates are masked with 0xFFF, so limit our
2229 * virtual resolutions to these sizes.
2231 if (info
->var
.yres_virtual
> 0x1000)
2232 info
->var
.yres_virtual
= 0x1000;
2234 if (info
->var
.xres_virtual
> 0x1000)
2235 info
->var
.xres_virtual
= 0x1000;
2237 savagefb_check_var(&info
->var
, info
);
2238 savagefb_set_fix(info
);
2241 * Calculate the hsync and vsync frequencies. Note that
2242 * we split the 1e12 constant up so that we can preserve
2243 * the precision and fit the results into 32-bit registers.
2244 * (1953125000 * 512 = 1e12)
2246 h_sync
= 1953125000 / info
->var
.pixclock
;
2247 h_sync
= h_sync
* 512 / (info
->var
.xres
+ info
->var
.left_margin
+
2248 info
->var
.right_margin
+
2249 info
->var
.hsync_len
);
2250 v_sync
= h_sync
/ (info
->var
.yres
+ info
->var
.upper_margin
+
2251 info
->var
.lower_margin
+ info
->var
.vsync_len
);
2253 printk(KERN_INFO
"savagefb v" SAVAGEFB_VERSION
": "
2254 "%dkB VRAM, using %dx%d, %d.%03dkHz, %dHz\n",
2255 info
->fix
.smem_len
>> 10,
2256 info
->var
.xres
, info
->var
.yres
,
2257 h_sync
/ 1000, h_sync
% 1000, v_sync
);
2260 fb_destroy_modedb(info
->monspecs
.modedb
);
2261 info
->monspecs
.modedb
= NULL
;
2263 err
= register_framebuffer (info
);
2267 printk (KERN_INFO
"fb: S3 %s frame buffer device\n",
2273 pci_set_drvdata(dev
, info
);
2278 #ifdef CONFIG_FB_SAVAGE_I2C
2279 savagefb_delete_i2c_busses(info
);
2281 fb_alloc_cmap (&info
->cmap
, 0, 0);
2282 savage_unmap_video(info
);
2284 savage_unmap_mmio (info
);
2286 kfree(info
->pixmap
.addr
);
2288 pci_release_regions(dev
);
2290 framebuffer_release(info
);
2295 static void __devexit
savagefb_remove (struct pci_dev
*dev
)
2297 struct fb_info
*info
= pci_get_drvdata(dev
);
2299 DBG("savagefb_remove");
2303 * If unregister_framebuffer fails, then
2304 * we will be leaving hooks that could cause
2305 * oopsen laying around.
2307 if (unregister_framebuffer (info
))
2308 printk (KERN_WARNING
"savagefb: danger danger! "
2309 "Oopsen imminent!\n");
2311 #ifdef CONFIG_FB_SAVAGE_I2C
2312 savagefb_delete_i2c_busses(info
);
2314 fb_alloc_cmap (&info
->cmap
, 0, 0);
2315 savage_unmap_video (info
);
2316 savage_unmap_mmio (info
);
2317 kfree(info
->pixmap
.addr
);
2318 pci_release_regions(dev
);
2319 framebuffer_release(info
);
2322 * Ensure that the driver data is no longer
2325 pci_set_drvdata(dev
, NULL
);
2329 static int savagefb_suspend (struct pci_dev
* dev
, pm_message_t state
)
2331 struct fb_info
*info
= pci_get_drvdata(dev
);
2332 struct savagefb_par
*par
= info
->par
;
2334 DBG("savagefb_suspend");
2337 par
->pm_state
= state
.event
;
2340 * For PM_EVENT_FREEZE, do not power down so the console
2341 * can remain active.
2343 if (state
.event
== PM_EVENT_FREEZE
) {
2344 dev
->dev
.power
.power_state
= state
;
2348 acquire_console_sem();
2349 fb_set_suspend(info
, 1);
2351 if (info
->fbops
->fb_sync
)
2352 info
->fbops
->fb_sync(info
);
2354 savagefb_blank(FB_BLANK_POWERDOWN
, info
);
2355 savage_set_default_par(par
, &par
->save
);
2356 savage_disable_mmio(par
);
2357 pci_save_state(dev
);
2358 pci_disable_device(dev
);
2359 pci_set_power_state(dev
, pci_choose_state(dev
, state
));
2360 release_console_sem();
2365 static int savagefb_resume (struct pci_dev
* dev
)
2367 struct fb_info
*info
= pci_get_drvdata(dev
);
2368 struct savagefb_par
*par
= info
->par
;
2369 int cur_state
= par
->pm_state
;
2371 DBG("savage_resume");
2373 par
->pm_state
= PM_EVENT_ON
;
2376 * The adapter was not powered down coming back from a
2379 if (cur_state
== PM_EVENT_FREEZE
) {
2380 pci_set_power_state(dev
, PCI_D0
);
2384 acquire_console_sem();
2386 pci_set_power_state(dev
, PCI_D0
);
2387 pci_restore_state(dev
);
2389 if(pci_enable_device(dev
))
2392 pci_set_master(dev
);
2393 savage_enable_mmio(par
);
2394 savage_init_hw(par
);
2395 savagefb_set_par(info
);
2396 fb_set_suspend (info
, 0);
2397 savagefb_blank(FB_BLANK_UNBLANK
, info
);
2398 release_console_sem();
2404 static struct pci_device_id savagefb_devices
[] __devinitdata
= {
2405 {PCI_VENDOR_ID_S3
, PCI_CHIP_SUPSAV_MX128
,
2406 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, FB_ACCEL_SUPERSAVAGE
},
2408 {PCI_VENDOR_ID_S3
, PCI_CHIP_SUPSAV_MX64
,
2409 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, FB_ACCEL_SUPERSAVAGE
},
2411 {PCI_VENDOR_ID_S3
, PCI_CHIP_SUPSAV_MX64C
,
2412 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, FB_ACCEL_SUPERSAVAGE
},
2414 {PCI_VENDOR_ID_S3
, PCI_CHIP_SUPSAV_IX128SDR
,
2415 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, FB_ACCEL_SUPERSAVAGE
},
2417 {PCI_VENDOR_ID_S3
, PCI_CHIP_SUPSAV_IX128DDR
,
2418 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, FB_ACCEL_SUPERSAVAGE
},
2420 {PCI_VENDOR_ID_S3
, PCI_CHIP_SUPSAV_IX64SDR
,
2421 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, FB_ACCEL_SUPERSAVAGE
},
2423 {PCI_VENDOR_ID_S3
, PCI_CHIP_SUPSAV_IX64DDR
,
2424 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, FB_ACCEL_SUPERSAVAGE
},
2426 {PCI_VENDOR_ID_S3
, PCI_CHIP_SUPSAV_IXCSDR
,
2427 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, FB_ACCEL_SUPERSAVAGE
},
2429 {PCI_VENDOR_ID_S3
, PCI_CHIP_SUPSAV_IXCDDR
,
2430 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, FB_ACCEL_SUPERSAVAGE
},
2432 {PCI_VENDOR_ID_S3
, PCI_CHIP_SAVAGE4
,
2433 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, FB_ACCEL_SAVAGE4
},
2435 {PCI_VENDOR_ID_S3
, PCI_CHIP_SAVAGE3D
,
2436 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, FB_ACCEL_SAVAGE3D
},
2438 {PCI_VENDOR_ID_S3
, PCI_CHIP_SAVAGE3D_MV
,
2439 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, FB_ACCEL_SAVAGE3D_MV
},
2441 {PCI_VENDOR_ID_S3
, PCI_CHIP_SAVAGE2000
,
2442 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, FB_ACCEL_SAVAGE2000
},
2444 {PCI_VENDOR_ID_S3
, PCI_CHIP_SAVAGE_MX_MV
,
2445 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, FB_ACCEL_SAVAGE_MX_MV
},
2447 {PCI_VENDOR_ID_S3
, PCI_CHIP_SAVAGE_MX
,
2448 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, FB_ACCEL_SAVAGE_MX
},
2450 {PCI_VENDOR_ID_S3
, PCI_CHIP_SAVAGE_IX_MV
,
2451 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, FB_ACCEL_SAVAGE_IX_MV
},
2453 {PCI_VENDOR_ID_S3
, PCI_CHIP_SAVAGE_IX
,
2454 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, FB_ACCEL_SAVAGE_IX
},
2456 {PCI_VENDOR_ID_S3
, PCI_CHIP_PROSAVAGE_PM
,
2457 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, FB_ACCEL_PROSAVAGE_PM
},
2459 {PCI_VENDOR_ID_S3
, PCI_CHIP_PROSAVAGE_KM
,
2460 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, FB_ACCEL_PROSAVAGE_KM
},
2462 {PCI_VENDOR_ID_S3
, PCI_CHIP_S3TWISTER_P
,
2463 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, FB_ACCEL_S3TWISTER_P
},
2465 {PCI_VENDOR_ID_S3
, PCI_CHIP_S3TWISTER_K
,
2466 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, FB_ACCEL_S3TWISTER_K
},
2468 {PCI_VENDOR_ID_S3
, PCI_CHIP_PROSAVAGE_DDR
,
2469 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, FB_ACCEL_PROSAVAGE_DDR
},
2471 {PCI_VENDOR_ID_S3
, PCI_CHIP_PROSAVAGE_DDRK
,
2472 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, FB_ACCEL_PROSAVAGE_DDRK
},
2474 {0, 0, 0, 0, 0, 0, 0}
2477 MODULE_DEVICE_TABLE(pci
, savagefb_devices
);
2479 static struct pci_driver savagefb_driver
= {
2481 .id_table
= savagefb_devices
,
2482 .probe
= savagefb_probe
,
2483 .suspend
= savagefb_suspend
,
2484 .resume
= savagefb_resume
,
2485 .remove
= __devexit_p(savagefb_remove
)
2488 /* **************************** exit-time only **************************** */
2490 static void __exit
savage_done (void)
2493 pci_unregister_driver (&savagefb_driver
);
2497 /* ************************* init in-kernel code ************************** */
2499 static int __init
savagefb_setup(char *options
)
2504 if (!options
|| !*options
)
2507 while ((this_opt
= strsep(&options
, ",")) != NULL
) {
2508 mode_option
= this_opt
;
2510 #endif /* !MODULE */
2514 static int __init
savagefb_init(void)
2518 DBG("savagefb_init");
2520 if (fb_get_options("savagefb", &option
))
2523 savagefb_setup(option
);
2524 return pci_register_driver (&savagefb_driver
);
2528 module_init(savagefb_init
);
2529 module_exit(savage_done
);
2531 module_param(mode_option
, charp
, 0);
2532 MODULE_PARM_DESC(mode_option
, "Specify initial video mode");