include/asm-x86/system_64.h

   1 #ifndef __ASM_SYSTEM_H
   2 #define __ASM_SYSTEM_H
   3
   4 #include <linux/kernel.h>
   5 #include <asm/segment.h>
   6 #include <asm/cmpxchg.h>
   7
   8 #ifdef __KERNEL__
   9
  10 #define __SAVE(reg,offset) "movq %%" #reg ",(14-" #offset ")*8(%%rsp)\n\t"
  11 #define __RESTORE(reg,offset) "movq (14-" #offset ")*8(%%rsp),%%" #reg "\n\t"
  12
  13 /* frame pointer must be last for get_wchan */
  14 #define SAVE_CONTEXT    "pushf ; pushq %%rbp ; movq %%rsi,%%rbp\n\t"
  15 #define RESTORE_CONTEXT "movq %%rbp,%%rsi ; popq %%rbp ; popf\t"
  16
  17 #define __EXTRA_CLOBBER  \
  18         ,"rcx","rbx","rdx","r8","r9","r10","r11","r12","r13","r14","r15"
  19
  20 /* Save restore flags to clear handle leaking NT */
  21 #define switch_to(prev,next,last) \
  22         asm volatile(SAVE_CONTEXT                                                   \
  23                      "movq %%rsp,%P[threadrsp](%[prev])\n\t" /* save RSP */       \
  24                      "movq %P[threadrsp](%[next]),%%rsp\n\t" /* restore RSP */    \
  25                      "call __switch_to\n\t"                                       \
  26                      ".globl thread_return\n"                                   \
  27                      "thread_return:\n\t"                                           \
  28                      "movq %%gs:%P[pda_pcurrent],%%rsi\n\t"                       \
  29                      "movq %P[thread_info](%%rsi),%%r8\n\t"                       \
  30                      LOCK_PREFIX "btr  %[tif_fork],%P[ti_flags](%%r8)\n\t"        \
  31                      "movq %%rax,%%rdi\n\t"                                       \
  32                      "jc   ret_from_fork\n\t"                                     \
  33                      RESTORE_CONTEXT                                                \
  34                      : "=a" (last)                                                \
  35                      : [next] "S" (next), [prev] "D" (prev),                      \
  36                        [threadrsp] "i" (offsetof(struct task_struct, thread.rsp)), \
  37                        [ti_flags] "i" (offsetof(struct thread_info, flags)),\
  38                        [tif_fork] "i" (TIF_FORK),                         \
  39                        [thread_info] "i" (offsetof(struct task_struct, stack)), \
  40                        [pda_pcurrent] "i" (offsetof(struct x8664_pda, pcurrent))   \
  41                      : "memory", "cc" __EXTRA_CLOBBER)
  42
  43 extern void load_gs_index(unsigned);
  44
  45 /*
  46  * Load a segment. Fall back on loading the zero
  47  * segment if something goes wrong..
  48  */
  49 #define loadsegment(seg,value)  \
  50         asm volatile("\n"                       \
  51                 "1:\t"                          \
  52                 "movl %k0,%%" #seg "\n"         \
  53                 "2:\n"                          \
  54                 ".section .fixup,\"ax\"\n"      \
  55                 "3:\t"                          \
  56                 "movl %1,%%" #seg "\n\t"        \
  57                 "jmp 2b\n"                      \
  58                 ".previous\n"                   \
  59                 ".section __ex_table,\"a\"\n\t" \
  60                 ".align 8\n\t"                  \
  61                 ".quad 1b,3b\n"                 \
  62                 ".previous"                     \
  63                 : :"r" (value), "r" (0))
  64
  65 /*
  66  * Clear and set 'TS' bit respectively
  67  */
  68 #define clts() __asm__ __volatile__ ("clts")
  69
  70 static inline unsigned long read_cr0(void)
  71 {
  72         unsigned long cr0;
  73         asm volatile("movq %%cr0,%0" : "=r" (cr0));
  74         return cr0;
  75 }
  76
  77 static inline void write_cr0(unsigned long val)
  78 {
  79         asm volatile("movq %0,%%cr0" :: "r" (val));
  80 }
  81
  82 static inline unsigned long read_cr2(void)
  83 {
  84         unsigned long cr2;
  85         asm volatile("movq %%cr2,%0" : "=r" (cr2));
  86         return cr2;
  87 }
  88
  89 static inline void write_cr2(unsigned long val)
  90 {
  91         asm volatile("movq %0,%%cr2" :: "r" (val));
  92 }
  93
  94 static inline unsigned long read_cr3(void)
  95 {
  96         unsigned long cr3;
  97         asm volatile("movq %%cr3,%0" : "=r" (cr3));
  98         return cr3;
  99 }
 100
 101 static inline void write_cr3(unsigned long val)
 102 {
 103         asm volatile("movq %0,%%cr3" :: "r" (val) : "memory");
 104 }
 105
 106 static inline unsigned long read_cr4(void)
 107 {
 108         unsigned long cr4;
 109         asm volatile("movq %%cr4,%0" : "=r" (cr4));
 110         return cr4;
 111 }
 112
 113 static inline void write_cr4(unsigned long val)
 114 {
 115         asm volatile("movq %0,%%cr4" :: "r" (val) : "memory");
 116 }
 117
 118 static inline unsigned long read_cr8(void)
 119 {
 120         unsigned long cr8;
 121         asm volatile("movq %%cr8,%0" : "=r" (cr8));
 122         return cr8;
 123 }
 124
 125 static inline void write_cr8(unsigned long val)
 126 {
 127         asm volatile("movq %0,%%cr8" :: "r" (val) : "memory");
 128 }
 129
 130 #define stts() write_cr0(8 | read_cr0())
 131
 132 #define wbinvd() \
 133         __asm__ __volatile__ ("wbinvd": : :"memory")
 134
 135 #endif  /* __KERNEL__ */
 136
 137 static inline void clflush(volatile void *__p)
 138 {
 139         asm volatile("clflush %0" : "+m" (*(char __force *)__p));
 140 }
 141
 142 #define nop() __asm__ __volatile__ ("nop")
 143
 144 #ifdef CONFIG_SMP
 145 #define smp_mb()        mb()
 146 #define smp_rmb()       barrier()
 147 #define smp_wmb()       barrier()
 148 #define smp_read_barrier_depends()      do {} while(0)
 149 #else
 150 #define smp_mb()        barrier()
 151 #define smp_rmb()       barrier()
 152 #define smp_wmb()       barrier()
 153 #define smp_read_barrier_depends()      do {} while(0)
 154 #endif
 155
 156
 157 /*
 158  * Force strict CPU ordering.
 159  * And yes, this is required on UP too when we're talking
 160  * to devices.
 161  */
 162 #define mb()    asm volatile("mfence":::"memory")
 163 #define rmb()   asm volatile("lfence":::"memory")
 164 #define wmb()   asm volatile("sfence" ::: "memory")
 165
 166 #define read_barrier_depends()  do {} while(0)
 167 #define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
 168
 169 #define warn_if_not_ulong(x) do { unsigned long foo; (void) (&(x) == &foo); } while (0)
 170
 171 #include <linux/irqflags.h>
 172
 173 void cpu_idle_wait(void);
 174
 175 extern unsigned long arch_align_stack(unsigned long sp);
 176 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
 177
 178 #endif