include/asm-powerpc/pgtable-ppc32.h

   1 #ifndef _ASM_POWERPC_PGTABLE_PPC32_H
   2 #define _ASM_POWERPC_PGTABLE_PPC32_H
   3
   4 #include <asm-generic/pgtable-nopmd.h>
   5
   6 #ifndef __ASSEMBLY__
   7 #include <linux/sched.h>
   8 #include <linux/threads.h>
   9 #include <asm/io.h>                     /* For sub-arch specific PPC_PIN_SIZE */
  10
  11 extern unsigned long va_to_phys(unsigned long address);
  12 extern pte_t *va_to_pte(unsigned long address);
  13 extern unsigned long ioremap_bot, ioremap_base;
  14
  15 #ifdef CONFIG_44x
  16 extern int icache_44x_need_flush;
  17 #endif
  18
  19 #endif /* __ASSEMBLY__ */
  20
  21 /*
  22  * The PowerPC MMU uses a hash table containing PTEs, together with
  23  * a set of 16 segment registers (on 32-bit implementations), to define
  24  * the virtual to physical address mapping.
  25  *
  26  * We use the hash table as an extended TLB, i.e. a cache of currently
  27  * active mappings.  We maintain a two-level page table tree, much
  28  * like that used by the i386, for the sake of the Linux memory
  29  * management code.  Low-level assembler code in hashtable.S
  30  * (procedure hash_page) is responsible for extracting ptes from the
  31  * tree and putting them into the hash table when necessary, and
  32  * updating the accessed and modified bits in the page table tree.
  33  */
  34
  35 /*
  36  * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
  37  * We also use the two level tables, but we can put the real bits in them
  38  * needed for the TLB and tablewalk.  These definitions require Mx_CTR.PPM = 0,
  39  * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1.  The level 2 descriptor has
  40  * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
  41  * based upon user/super access.  The TLB does not have accessed nor write
  42  * protect.  We assume that if the TLB get loaded with an entry it is
  43  * accessed, and overload the changed bit for write protect.  We use
  44  * two bits in the software pte that are supposed to be set to zero in
  45  * the TLB entry (24 and 25) for these indicators.  Although the level 1
  46  * descriptor contains the guarded and writethrough/copyback bits, we can
  47  * set these at the page level since they get copied from the Mx_TWC
  48  * register when the TLB entry is loaded.  We will use bit 27 for guard, since
  49  * that is where it exists in the MD_TWC, and bit 26 for writethrough.
  50  * These will get masked from the level 2 descriptor at TLB load time, and
  51  * copied to the MD_TWC before it gets loaded.
  52  * Large page sizes added.  We currently support two sizes, 4K and 8M.
  53  * This also allows a TLB hander optimization because we can directly
  54  * load the PMD into MD_TWC.  The 8M pages are only used for kernel
  55  * mapping of well known areas.  The PMD (PGD) entries contain control
  56  * flags in addition to the address, so care must be taken that the
  57  * software no longer assumes these are only pointers.
  58  */
  59
  60 /*
  61  * At present, all PowerPC 400-class processors share a similar TLB
  62  * architecture. The instruction and data sides share a unified,
  63  * 64-entry, fully-associative TLB which is maintained totally under
  64  * software control. In addition, the instruction side has a
  65  * hardware-managed, 4-entry, fully-associative TLB which serves as a
  66  * first level to the shared TLB. These two TLBs are known as the UTLB
  67  * and ITLB, respectively (see "mmu.h" for definitions).
  68  */
  69
  70 /*
  71  * The normal case is that PTEs are 32-bits and we have a 1-page
  72  * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages.  -- paulus
  73  *
  74  * For any >32-bit physical address platform, we can use the following
  75  * two level page table layout where the pgdir is 8KB and the MS 13 bits
  76  * are an index to the second level table.  The combined pgdir/pmd first
  77  * level has 2048 entries and the second level has 512 64-bit PTE entries.
  78  * -Matt
  79  */
  80 /* PGDIR_SHIFT determines what a top-level page table entry can map */
  81 #define PGDIR_SHIFT     (PAGE_SHIFT + PTE_SHIFT)
  82 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
  83 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
  84
  85 /*
  86  * entries per page directory level: our page-table tree is two-level, so
  87  * we don't really have any PMD directory.
  88  */
  89 #define PTRS_PER_PTE    (1 << PTE_SHIFT)
  90 #define PTRS_PER_PMD    1
  91 #define PTRS_PER_PGD    (1 << (32 - PGDIR_SHIFT))
  92
  93 #define USER_PTRS_PER_PGD       (TASK_SIZE / PGDIR_SIZE)
  94 #define FIRST_USER_ADDRESS      0
  95
  96 #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
  97 #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
  98
  99 #define pte_ERROR(e) \
 100         printk("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
 101                 (unsigned long long)pte_val(e))
 102 #define pgd_ERROR(e) \
 103         printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
 104
 105 /*
 106  * Just any arbitrary offset to the start of the vmalloc VM area: the
 107  * current 64MB value just means that there will be a 64MB "hole" after the
 108  * physical memory until the kernel virtual memory starts.  That means that
 109  * any out-of-bounds memory accesses will hopefully be caught.
 110  * The vmalloc() routines leaves a hole of 4kB between each vmalloced
 111  * area for the same reason. ;)
 112  *
 113  * We no longer map larger than phys RAM with the BATs so we don't have
 114  * to worry about the VMALLOC_OFFSET causing problems.  We do have to worry
 115  * about clashes between our early calls to ioremap() that start growing down
 116  * from ioremap_base being run into the VM area allocations (growing upwards
 117  * from VMALLOC_START).  For this reason we have ioremap_bot to check when
 118  * we actually run into our mappings setup in the early boot with the VM
 119  * system.  This really does become a problem for machines with good amounts
 120  * of RAM.  -- Cort
 121  */
 122 #define VMALLOC_OFFSET (0x1000000) /* 16M */
 123 #ifdef PPC_PIN_SIZE
 124 #define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
 125 #else
 126 #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
 127 #endif
 128 #define VMALLOC_END     ioremap_bot
 129
 130 /*
 131  * Bits in a linux-style PTE.  These match the bits in the
 132  * (hardware-defined) PowerPC PTE as closely as possible.
 133  */
 134
 135 #if defined(CONFIG_40x)
 136
 137 /* There are several potential gotchas here.  The 40x hardware TLBLO
 138    field looks like this:
 139
 140    0  1  2  3  4  ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
 141    RPN.....................  0  0 EX WR ZSEL.......  W  I  M  G
 142
 143    Where possible we make the Linux PTE bits match up with this
 144
 145    - bits 20 and 21 must be cleared, because we use 4k pages (40x can
 146      support down to 1k pages), this is done in the TLBMiss exception
 147      handler.
 148    - We use only zones 0 (for kernel pages) and 1 (for user pages)
 149      of the 16 available.  Bit 24-26 of the TLB are cleared in the TLB
 150      miss handler.  Bit 27 is PAGE_USER, thus selecting the correct
 151      zone.
 152    - PRESENT *must* be in the bottom two bits because swap cache
 153      entries use the top 30 bits.  Because 40x doesn't support SMP
 154      anyway, M is irrelevant so we borrow it for PAGE_PRESENT.  Bit 30
 155      is cleared in the TLB miss handler before the TLB entry is loaded.
 156    - All other bits of the PTE are loaded into TLBLO without
 157      modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
 158      software PTE bits.  We actually use use bits 21, 24, 25, and
 159      30 respectively for the software bits: ACCESSED, DIRTY, RW, and
 160      PRESENT.
 161 */
 162
 163 /* Definitions for 40x embedded chips. */
 164 #define _PAGE_GUARDED   0x001   /* G: page is guarded from prefetch */
 165 #define _PAGE_FILE      0x001   /* when !present: nonlinear file mapping */
 166 #define _PAGE_PRESENT   0x002   /* software: PTE contains a translation */
 167 #define _PAGE_NO_CACHE  0x004   /* I: caching is inhibited */
 168 #define _PAGE_WRITETHRU 0x008   /* W: caching is write-through */
 169 #define _PAGE_USER      0x010   /* matches one of the zone permission bits */
 170 #define _PAGE_RW        0x040   /* software: Writes permitted */
 171 #define _PAGE_DIRTY     0x080   /* software: dirty page */
 172 #define _PAGE_HWWRITE   0x100   /* hardware: Dirty & RW, set in exception */
 173 #define _PAGE_HWEXEC    0x200   /* hardware: EX permission */
 174 #define _PAGE_ACCESSED  0x400   /* software: R: page referenced */
 175
 176 #define _PMD_PRESENT    0x400   /* PMD points to page of PTEs */
 177 #define _PMD_BAD        0x802
 178 #define _PMD_SIZE       0x0e0   /* size field, != 0 for large-page PMD entry */
 179 #define _PMD_SIZE_4M    0x0c0
 180 #define _PMD_SIZE_16M   0x0e0
 181 #define PMD_PAGE_SIZE(pmdval)   (1024 << (((pmdval) & _PMD_SIZE) >> 4))
 182
 183 #elif defined(CONFIG_44x)
 184 /*
 185  * Definitions for PPC440
 186  *
 187  * Because of the 3 word TLB entries to support 36-bit addressing,
 188  * the attribute are difficult to map in such a fashion that they
 189  * are easily loaded during exception processing.  I decided to
 190  * organize the entry so the ERPN is the only portion in the
 191  * upper word of the PTE and the attribute bits below are packed
 192  * in as sensibly as they can be in the area below a 4KB page size
 193  * oriented RPN.  This at least makes it easy to load the RPN and
 194  * ERPN fields in the TLB. -Matt
 195  *
 196  * Note that these bits preclude future use of a page size
 197  * less than 4KB.
 198  *
 199  *
 200  * PPC 440 core has following TLB attribute fields;
 201  *
 202  *   TLB1:
 203  *   0  1  2  3  4  ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
 204  *   RPN.................................  -  -  -  -  -  - ERPN.......
 205  *
 206  *   TLB2:
 207  *   0  1  2  3  4  ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
 208  *   -  -  -  -  -    - U0 U1 U2 U3 W  I  M  G  E   - UX UW UR SX SW SR
 209  *
 210  * There are some constrains and options, to decide mapping software bits
 211  * into TLB entry.
 212  *
 213  *   - PRESENT *must* be in the bottom three bits because swap cache
 214  *     entries use the top 29 bits for TLB2.
 215  *
 216  *   - FILE *must* be in the bottom three bits because swap cache
 217  *     entries use the top 29 bits for TLB2.
 218  *
 219  *   - CACHE COHERENT bit (M) has no effect on PPC440 core, because it
 220  *     doesn't support SMP. So we can use this as software bit, like
 221  *     DIRTY.
 222  *
 223  * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
 224  * for memory protection related functions (see PTE structure in
 225  * include/asm-ppc/mmu.h).  The _PAGE_XXX definitions in this file map to the
 226  * above bits.  Note that the bit values are CPU specific, not architecture
 227  * specific.
 228  *
 229  * The kernel PTE entry holds an arch-dependent swp_entry structure under
 230  * certain situations. In other words, in such situations some portion of
 231  * the PTE bits are used as a swp_entry. In the PPC implementation, the
 232  * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still
 233  * hold protection values. That means the three protection bits are
 234  * reserved for both PTE and SWAP entry at the most significant three
 235  * LSBs.
 236  *
 237  * There are three protection bits available for SWAP entry:
 238  *      _PAGE_PRESENT
 239  *      _PAGE_FILE
 240  *      _PAGE_HASHPTE (if HW has)
 241  *
 242  * So those three bits have to be inside of 0-2nd LSB of PTE.
 243  *
 244  */
 245
 246 #define _PAGE_PRESENT   0x00000001              /* S: PTE valid */
 247 #define _PAGE_RW        0x00000002              /* S: Write permission */
 248 #define _PAGE_FILE      0x00000004              /* S: nonlinear file mapping */
 249 #define _PAGE_ACCESSED  0x00000008              /* S: Page referenced */
 250 #define _PAGE_HWWRITE   0x00000010              /* H: Dirty & RW */
 251 #define _PAGE_HWEXEC    0x00000020              /* H: Execute permission */
 252 #define _PAGE_USER      0x00000040              /* S: User page */
 253 #define _PAGE_ENDIAN    0x00000080              /* H: E bit */
 254 #define _PAGE_GUARDED   0x00000100              /* H: G bit */
 255 #define _PAGE_DIRTY     0x00000200              /* S: Page dirty */
 256 #define _PAGE_NO_CACHE  0x00000400              /* H: I bit */
 257 #define _PAGE_WRITETHRU 0x00000800              /* H: W bit */
 258
 259 /* TODO: Add large page lowmem mapping support */
 260 #define _PMD_PRESENT    0
 261 #define _PMD_PRESENT_MASK (PAGE_MASK)
 262 #define _PMD_BAD        (~PAGE_MASK)
 263
 264 /* ERPN in a PTE never gets cleared, ignore it */
 265 #define _PTE_NONE_MASK  0xffffffff00000000ULL
 266
 267 #elif defined(CONFIG_FSL_BOOKE)
 268 /*
 269    MMU Assist Register 3:
 270
 271    32 33 34 35 36  ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
 272    RPN......................  0  0 U0 U1 U2 U3 UX SX UW SW UR SR
 273
 274    - PRESENT *must* be in the bottom three bits because swap cache
 275      entries use the top 29 bits.
 276
 277    - FILE *must* be in the bottom three bits because swap cache
 278      entries use the top 29 bits.
 279 */
 280
 281 /* Definitions for FSL Book-E Cores */
 282 #define _PAGE_PRESENT   0x00001 /* S: PTE contains a translation */
 283 #define _PAGE_USER      0x00002 /* S: User page (maps to UR) */
 284 #define _PAGE_FILE      0x00002 /* S: when !present: nonlinear file mapping */
 285 #define _PAGE_ACCESSED  0x00004 /* S: Page referenced */
 286 #define _PAGE_HWWRITE   0x00008 /* H: Dirty & RW, set in exception */
 287 #define _PAGE_RW        0x00010 /* S: Write permission */
 288 #define _PAGE_HWEXEC    0x00020 /* H: UX permission */
 289
 290 #define _PAGE_ENDIAN    0x00040 /* H: E bit */
 291 #define _PAGE_GUARDED   0x00080 /* H: G bit */
 292 #define _PAGE_COHERENT  0x00100 /* H: M bit */
 293 #define _PAGE_NO_CACHE  0x00200 /* H: I bit */
 294 #define _PAGE_WRITETHRU 0x00400 /* H: W bit */
 295
 296 #ifdef CONFIG_PTE_64BIT
 297 #define _PAGE_DIRTY     0x08000 /* S: Page dirty */
 298
 299 /* ERPN in a PTE never gets cleared, ignore it */
 300 #define _PTE_NONE_MASK  0xffffffffffff0000ULL
 301 #else
 302 #define _PAGE_DIRTY     0x00800 /* S: Page dirty */
 303 #endif
 304
 305 #define _PMD_PRESENT    0
 306 #define _PMD_PRESENT_MASK (PAGE_MASK)
 307 #define _PMD_BAD        (~PAGE_MASK)
 308
 309 #elif defined(CONFIG_8xx)
 310 /* Definitions for 8xx embedded chips. */
 311 #define _PAGE_PRESENT   0x0001  /* Page is valid */
 312 #define _PAGE_FILE      0x0002  /* when !present: nonlinear file mapping */
 313 #define _PAGE_NO_CACHE  0x0002  /* I: cache inhibit */
 314 #define _PAGE_SHARED    0x0004  /* No ASID (context) compare */
 315
 316 /* These five software bits must be masked out when the entry is loaded
 317  * into the TLB.
 318  */
 319 #define _PAGE_EXEC      0x0008  /* software: i-cache coherency required */
 320 #define _PAGE_GUARDED   0x0010  /* software: guarded access */
 321 #define _PAGE_DIRTY     0x0020  /* software: page changed */
 322 #define _PAGE_RW        0x0040  /* software: user write access allowed */
 323 #define _PAGE_ACCESSED  0x0080  /* software: page referenced */
 324
 325 /* Setting any bits in the nibble with the follow two controls will
 326  * require a TLB exception handler change.  It is assumed unused bits
 327  * are always zero.
 328  */
 329 #define _PAGE_HWWRITE   0x0100  /* h/w write enable: never set in Linux PTE */
 330 #define _PAGE_USER      0x0800  /* One of the PP bits, the other is USER&~RW */
 331
 332 #define _PMD_PRESENT    0x0001
 333 #define _PMD_BAD        0x0ff0
 334 #define _PMD_PAGE_MASK  0x000c
 335 #define _PMD_PAGE_8M    0x000c
 336
 337 /*
 338  * The 8xx TLB miss handler allegedly sets _PAGE_ACCESSED in the PTE
 339  * for an address even if _PAGE_PRESENT is not set, as a performance
 340  * optimization.  This is a bug if you ever want to use swap unless
 341  * _PAGE_ACCESSED is 2, which it isn't, or unless you have 8xx-specific
 342  * definitions for __swp_entry etc. below, which would be gross.
 343  *  -- paulus
 344  */
 345 #define _PTE_NONE_MASK _PAGE_ACCESSED
 346
 347 #else /* CONFIG_6xx */
 348 /* Definitions for 60x, 740/750, etc. */
 349 #define _PAGE_PRESENT   0x001   /* software: pte contains a translation */
 350 #define _PAGE_HASHPTE   0x002   /* hash_page has made an HPTE for this pte */
 351 #define _PAGE_FILE      0x004   /* when !present: nonlinear file mapping */
 352 #define _PAGE_USER      0x004   /* usermode access allowed */
 353 #define _PAGE_GUARDED   0x008   /* G: prohibit speculative access */
 354 #define _PAGE_COHERENT  0x010   /* M: enforce memory coherence (SMP systems) */
 355 #define _PAGE_NO_CACHE  0x020   /* I: cache inhibit */
 356 #define _PAGE_WRITETHRU 0x040   /* W: cache write-through */
 357 #define _PAGE_DIRTY     0x080   /* C: page changed */
 358 #define _PAGE_ACCESSED  0x100   /* R: page referenced */
 359 #define _PAGE_EXEC      0x200   /* software: i-cache coherency required */
 360 #define _PAGE_RW        0x400   /* software: user write access allowed */
 361
 362 #define _PTE_NONE_MASK  _PAGE_HASHPTE
 363
 364 #define _PMD_PRESENT    0
 365 #define _PMD_PRESENT_MASK (PAGE_MASK)
 366 #define _PMD_BAD        (~PAGE_MASK)
 367 #endif
 368
 369 /*
 370  * Some bits are only used on some cpu families...
 371  */
 372 #ifndef _PAGE_HASHPTE
 373 #define _PAGE_HASHPTE   0
 374 #endif
 375 #ifndef _PTE_NONE_MASK
 376 #define _PTE_NONE_MASK 0
 377 #endif
 378 #ifndef _PAGE_SHARED
 379 #define _PAGE_SHARED    0
 380 #endif
 381 #ifndef _PAGE_HWWRITE
 382 #define _PAGE_HWWRITE   0
 383 #endif
 384 #ifndef _PAGE_HWEXEC
 385 #define _PAGE_HWEXEC    0
 386 #endif
 387 #ifndef _PAGE_EXEC
 388 #define _PAGE_EXEC      0
 389 #endif
 390 #ifndef _PMD_PRESENT_MASK
 391 #define _PMD_PRESENT_MASK       _PMD_PRESENT
 392 #endif
 393 #ifndef _PMD_SIZE
 394 #define _PMD_SIZE       0
 395 #define PMD_PAGE_SIZE(pmd)      bad_call_to_PMD_PAGE_SIZE()
 396 #endif
 397
 398 #define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
 399
 400 /*
 401  * Note: the _PAGE_COHERENT bit automatically gets set in the hardware
 402  * PTE if CONFIG_SMP is defined (hash_page does this); there is no need
 403  * to have it in the Linux PTE, and in fact the bit could be reused for
 404  * another purpose.  -- paulus.
 405  */
 406
 407 #ifdef CONFIG_44x
 408 #define _PAGE_BASE      (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_GUARDED)
 409 #else
 410 #define _PAGE_BASE      (_PAGE_PRESENT | _PAGE_ACCESSED)
 411 #endif
 412 #define _PAGE_WRENABLE  (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE)
 413 #define _PAGE_KERNEL    (_PAGE_BASE | _PAGE_SHARED | _PAGE_WRENABLE)
 414
 415 #ifdef CONFIG_PPC_STD_MMU
 416 /* On standard PPC MMU, no user access implies kernel read/write access,
 417  * so to write-protect kernel memory we must turn on user access */
 418 #define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED | _PAGE_USER)
 419 #else
 420 #define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED)
 421 #endif
 422
 423 #define _PAGE_IO        (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED)
 424 #define _PAGE_RAM       (_PAGE_KERNEL | _PAGE_HWEXEC)
 425
 426 #if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH)
 427 /* We want the debuggers to be able to set breakpoints anywhere, so
 428  * don't write protect the kernel text */
 429 #define _PAGE_RAM_TEXT  _PAGE_RAM
 430 #else
 431 #define _PAGE_RAM_TEXT  (_PAGE_KERNEL_RO | _PAGE_HWEXEC)
 432 #endif
 433
 434 #define PAGE_NONE       __pgprot(_PAGE_BASE)
 435 #define PAGE_READONLY   __pgprot(_PAGE_BASE | _PAGE_USER)
 436 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
 437 #define PAGE_SHARED     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
 438 #define PAGE_SHARED_X   __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
 439 #define PAGE_COPY       __pgprot(_PAGE_BASE | _PAGE_USER)
 440 #define PAGE_COPY_X     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
 441
 442 #define PAGE_KERNEL             __pgprot(_PAGE_RAM)
 443 #define PAGE_KERNEL_NOCACHE     __pgprot(_PAGE_IO)
 444
 445 /*
 446  * The PowerPC can only do execute protection on a segment (256MB) basis,
 447  * not on a page basis.  So we consider execute permission the same as read.
 448  * Also, write permissions imply read permissions.
 449  * This is the closest we can get..
 450  */
 451 #define __P000  PAGE_NONE
 452 #define __P001  PAGE_READONLY_X
 453 #define __P010  PAGE_COPY
 454 #define __P011  PAGE_COPY_X
 455 #define __P100  PAGE_READONLY
 456 #define __P101  PAGE_READONLY_X
 457 #define __P110  PAGE_COPY
 458 #define __P111  PAGE_COPY_X
 459
 460 #define __S000  PAGE_NONE
 461 #define __S001  PAGE_READONLY_X
 462 #define __S010  PAGE_SHARED
 463 #define __S011  PAGE_SHARED_X
 464 #define __S100  PAGE_READONLY
 465 #define __S101  PAGE_READONLY_X
 466 #define __S110  PAGE_SHARED
 467 #define __S111  PAGE_SHARED_X
 468
 469 #ifndef __ASSEMBLY__
 470 /* Make sure we get a link error if PMD_PAGE_SIZE is ever called on a
 471  * kernel without large page PMD support */
 472 extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
 473
 474 /*
 475  * Conversions between PTE values and page frame numbers.
 476  */
 477
 478 /* in some case we want to additionaly adjust where the pfn is in the pte to
 479  * allow room for more flags */
 480 #if defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
 481 #define PFN_SHIFT_OFFSET        (PAGE_SHIFT + 8)
 482 #else
 483 #define PFN_SHIFT_OFFSET        (PAGE_SHIFT)
 484 #endif
 485
 486 #define pte_pfn(x)              (pte_val(x) >> PFN_SHIFT_OFFSET)
 487 #define pte_page(x)             pfn_to_page(pte_pfn(x))
 488
 489 #define pfn_pte(pfn, prot)      __pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) |\
 490                                         pgprot_val(prot))
 491 #define mk_pte(page, prot)      pfn_pte(page_to_pfn(page), prot)
 492 #endif /* __ASSEMBLY__ */
 493
 494 #define pte_none(pte)           ((pte_val(pte) & ~_PTE_NONE_MASK) == 0)
 495 #define pte_present(pte)        (pte_val(pte) & _PAGE_PRESENT)
 496 #define pte_clear(mm,addr,ptep) do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0)
 497
 498 #define pmd_none(pmd)           (!pmd_val(pmd))
 499 #define pmd_bad(pmd)            (pmd_val(pmd) & _PMD_BAD)
 500 #define pmd_present(pmd)        (pmd_val(pmd) & _PMD_PRESENT_MASK)
 501 #define pmd_clear(pmdp)         do { pmd_val(*(pmdp)) = 0; } while (0)
 502
 503 #ifndef __ASSEMBLY__
 504 /*
 505  * The following only work if pte_present() is true.
 506  * Undefined behaviour if not..
 507  */
 508 static inline int pte_write(pte_t pte)          { return pte_val(pte) & _PAGE_RW; }
 509 static inline int pte_dirty(pte_t pte)          { return pte_val(pte) & _PAGE_DIRTY; }
 510 static inline int pte_young(pte_t pte)          { return pte_val(pte) & _PAGE_ACCESSED; }
 511 static inline int pte_file(pte_t pte)           { return pte_val(pte) & _PAGE_FILE; }
 512
 513 static inline void pte_uncache(pte_t pte)       { pte_val(pte) |= _PAGE_NO_CACHE; }
 514 static inline void pte_cache(pte_t pte)         { pte_val(pte) &= ~_PAGE_NO_CACHE; }
 515
 516 static inline pte_t pte_wrprotect(pte_t pte) {
 517         pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
 518 static inline pte_t pte_mkclean(pte_t pte) {
 519         pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
 520 static inline pte_t pte_mkold(pte_t pte) {
 521         pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
 522
 523 static inline pte_t pte_mkwrite(pte_t pte) {
 524         pte_val(pte) |= _PAGE_RW; return pte; }
 525 static inline pte_t pte_mkdirty(pte_t pte) {
 526         pte_val(pte) |= _PAGE_DIRTY; return pte; }
 527 static inline pte_t pte_mkyoung(pte_t pte) {
 528         pte_val(pte) |= _PAGE_ACCESSED; return pte; }
 529
 530 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 531 {
 532         pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
 533         return pte;
 534 }
 535
 536 /*
 537  * When flushing the tlb entry for a page, we also need to flush the hash
 538  * table entry.  flush_hash_pages is assembler (for speed) in hashtable.S.
 539  */
 540 extern int flush_hash_pages(unsigned context, unsigned long va,
 541                             unsigned long pmdval, int count);
 542
 543 /* Add an HPTE to the hash table */
 544 extern void add_hash_page(unsigned context, unsigned long va,
 545                           unsigned long pmdval);
 546
 547 /*
 548  * Atomic PTE updates.
 549  *
 550  * pte_update clears and sets bit atomically, and returns
 551  * the old pte value.  In the 64-bit PTE case we lock around the
 552  * low PTE word since we expect ALL flag bits to be there
 553  */
 554 #ifndef CONFIG_PTE_64BIT
 555 static inline unsigned long pte_update(pte_t *p, unsigned long clr,
 556                                        unsigned long set)
 557 {
 558         unsigned long old, tmp;
 559
 560         __asm__ __volatile__("\
 561 1:      lwarx   %0,0,%3\n\
 562         andc    %1,%0,%4\n\
 563         or      %1,%1,%5\n"
 564         PPC405_ERR77(0,%3)
 565 "       stwcx.  %1,0,%3\n\
 566         bne-    1b"
 567         : "=&r" (old), "=&r" (tmp), "=m" (*p)
 568         : "r" (p), "r" (clr), "r" (set), "m" (*p)
 569         : "cc" );
 570 #ifdef CONFIG_44x
 571         if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC))
 572                 icache_44x_need_flush = 1;
 573 #endif
 574         return old;
 575 }
 576 #else
 577 static inline unsigned long long pte_update(pte_t *p, unsigned long clr,
 578                                        unsigned long set)
 579 {
 580         unsigned long long old;
 581         unsigned long tmp;
 582
 583         __asm__ __volatile__("\
 584 1:      lwarx   %L0,0,%4\n\
 585         lwzx    %0,0,%3\n\
 586         andc    %1,%L0,%5\n\
 587         or      %1,%1,%6\n"
 588         PPC405_ERR77(0,%3)
 589 "       stwcx.  %1,0,%4\n\
 590         bne-    1b"
 591         : "=&r" (old), "=&r" (tmp), "=m" (*p)
 592         : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
 593         : "cc" );
 594 #ifdef CONFIG_44x
 595         if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC))
 596                 icache_44x_need_flush = 1;
 597 #endif
 598         return old;
 599 }
 600 #endif
 601
 602 /*
 603  * set_pte stores a linux PTE into the linux page table.
 604  * On machines which use an MMU hash table we avoid changing the
 605  * _PAGE_HASHPTE bit.
 606  */
 607 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
 608                               pte_t *ptep, pte_t pte)
 609 {
 610 #if _PAGE_HASHPTE != 0
 611         pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) & ~_PAGE_HASHPTE);
 612 #else
 613         *ptep = pte;
 614 #endif
 615 }
 616
 617 /*
 618  * 2.6 calles this without flushing the TLB entry, this is wrong
 619  * for our hash-based implementation, we fix that up here
 620  */
 621 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 622 static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
 623 {
 624         unsigned long old;
 625         old = pte_update(ptep, _PAGE_ACCESSED, 0);
 626 #if _PAGE_HASHPTE != 0
 627         if (old & _PAGE_HASHPTE) {
 628                 unsigned long ptephys = __pa(ptep) & PAGE_MASK;
 629                 flush_hash_pages(context, addr, ptephys, 1);
 630         }
 631 #endif
 632         return (old & _PAGE_ACCESSED) != 0;
 633 }
 634 #define ptep_test_and_clear_young(__vma, __addr, __ptep) \
 635         __ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)
 636
 637 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 638 static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
 639                                        pte_t *ptep)
 640 {
 641         return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
 642 }
 643
 644 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
 645 static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
 646                                       pte_t *ptep)
 647 {
 648         pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
 649 }
 650
 651 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
 652 static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
 653 {
 654         unsigned long bits = pte_val(entry) &
 655                 (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW);
 656         pte_update(ptep, 0, bits);
 657 }
 658
 659 #define  ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
 660 ({                                                                         \
 661         int __changed = !pte_same(*(__ptep), __entry);                     \
 662         if (__changed) {                                                   \
 663                 __ptep_set_access_flags(__ptep, __entry, __dirty);         \
 664                 flush_tlb_page_nohash(__vma, __address);                   \
 665         }                                                                  \
 666         __changed;                                                         \
 667 })
 668
 669 /*
 670  * Macro to mark a page protection value as "uncacheable".
 671  */
 672 #define pgprot_noncached(prot)  (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
 673
 674 struct file;
 675 extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
 676                                      unsigned long size, pgprot_t vma_prot);
 677 #define __HAVE_PHYS_MEM_ACCESS_PROT
 678
 679 #define __HAVE_ARCH_PTE_SAME
 680 #define pte_same(A,B)   (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
 681
 682 /*
 683  * Note that on Book E processors, the pmd contains the kernel virtual
 684  * (lowmem) address of the pte page.  The physical address is less useful
 685  * because everything runs with translation enabled (even the TLB miss
 686  * handler).  On everything else the pmd contains the physical address
 687  * of the pte page.  -- paulus
 688  */
 689 #ifndef CONFIG_BOOKE
 690 #define pmd_page_vaddr(pmd)     \
 691         ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
 692 #define pmd_page(pmd)           \
 693         (mem_map + (pmd_val(pmd) >> PAGE_SHIFT))
 694 #else
 695 #define pmd_page_vaddr(pmd)     \
 696         ((unsigned long) (pmd_val(pmd) & PAGE_MASK))
 697 #define pmd_page(pmd)           \
 698         (mem_map + (__pa(pmd_val(pmd)) >> PAGE_SHIFT))
 699 #endif
 700
 701 /* to find an entry in a kernel page-table-directory */
 702 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 703
 704 /* to find an entry in a page-table-directory */
 705 #define pgd_index(address)       ((address) >> PGDIR_SHIFT)
 706 #define pgd_offset(mm, address)  ((mm)->pgd + pgd_index(address))
 707
 708 /* Find an entry in the third-level page table.. */
 709 #define pte_index(address)              \
 710         (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 711 #define pte_offset_kernel(dir, addr)    \
 712         ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
 713 #define pte_offset_map(dir, addr)               \
 714         ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE0) + pte_index(addr))
 715 #define pte_offset_map_nested(dir, addr)        \
 716         ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE1) + pte_index(addr))
 717
 718 #define pte_unmap(pte)          kunmap_atomic(pte, KM_PTE0)
 719 #define pte_unmap_nested(pte)   kunmap_atomic(pte, KM_PTE1)
 720
 721 /*
 722  * Encode and decode a swap entry.
 723  * Note that the bits we use in a PTE for representing a swap entry
 724  * must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the
 725  *_PAGE_HASHPTE bit (if used).  -- paulus
 726  */
 727 #define __swp_type(entry)               ((entry).val & 0x1f)
 728 #define __swp_offset(entry)             ((entry).val >> 5)
 729 #define __swp_entry(type, offset)       ((swp_entry_t) { (type) | ((offset) << 5) })
 730 #define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) >> 3 })
 731 #define __swp_entry_to_pte(x)           ((pte_t) { (x).val << 3 })
 732
 733 /* Encode and decode a nonlinear file mapping entry */
 734 #define PTE_FILE_MAX_BITS       29
 735 #define pte_to_pgoff(pte)       (pte_val(pte) >> 3)
 736 #define pgoff_to_pte(off)       ((pte_t) { ((off) << 3) | _PAGE_FILE })
 737
 738 /*
 739  * No page table caches to initialise
 740  */
 741 #define pgtable_cache_init()    do { } while (0)
 742
 743 extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep,
 744                       pmd_t **pmdp);
 745
 746 #endif /* !__ASSEMBLY__ */
 747
 748 #endif /* _ASM_POWERPC_PGTABLE_PPC32_H */