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[XFS] move freeing the mount structure from xfs_mount_free into the callers
[linux-2.6/mini2440.git] / drivers / ata / pata_icside.c
blob64a711776c453b51e4c5be2f01bddcfbfb1fe0f9
1 #include <linux/kernel.h>
2 #include <linux/module.h>
3 #include <linux/init.h>
4 #include <linux/blkdev.h>
5 #include <scsi/scsi_host.h>
6 #include <linux/ata.h>
7 #include <linux/libata.h>
8
9 #include <asm/dma.h>
10 #include <asm/ecard.h>
11
12 #define DRV_NAME "pata_icside"
13
14 #define ICS_IDENT_OFFSET 0x2280
15
16 #define ICS_ARCIN_V5_INTRSTAT 0x0000
17 #define ICS_ARCIN_V5_INTROFFSET 0x0004
18
19 #define ICS_ARCIN_V6_INTROFFSET_1 0x2200
20 #define ICS_ARCIN_V6_INTRSTAT_1 0x2290
21 #define ICS_ARCIN_V6_INTROFFSET_2 0x3200
22 #define ICS_ARCIN_V6_INTRSTAT_2 0x3290
23
24 struct portinfo {
25 unsigned int dataoffset;
26 unsigned int ctrloffset;
27 unsigned int stepping;
28 };
29
30 static const struct portinfo pata_icside_portinfo_v5 = {
31 .dataoffset = 0x2800,
32 .ctrloffset = 0x2b80,
33 .stepping = 6,
34 };
35
36 static const struct portinfo pata_icside_portinfo_v6_1 = {
37 .dataoffset = 0x2000,
38 .ctrloffset = 0x2380,
39 .stepping = 6,
40 };
41
42 static const struct portinfo pata_icside_portinfo_v6_2 = {
43 .dataoffset = 0x3000,
44 .ctrloffset = 0x3380,
45 .stepping = 6,
46 };
47
48 #define PATA_ICSIDE_MAX_SG 128
49
50 struct pata_icside_state {
51 void __iomem *irq_port;
52 void __iomem *ioc_base;
53 unsigned int type;
54 unsigned int dma;
55 struct {
56 u8 port_sel;
57 u8 disabled;
58 unsigned int speed[ATA_MAX_DEVICES];
59 } port[2];
60 struct scatterlist sg[PATA_ICSIDE_MAX_SG];
61 };
62
63 struct pata_icside_info {
64 struct pata_icside_state *state;
65 struct expansion_card *ec;
66 void __iomem *base;
67 void __iomem *irqaddr;
68 unsigned int irqmask;
69 const expansioncard_ops_t *irqops;
70 unsigned int mwdma_mask;
71 unsigned int nr_ports;
72 const struct portinfo *port[2];
73 };
74
75 #define ICS_TYPE_A3IN 0
76 #define ICS_TYPE_A3USER 1
77 #define ICS_TYPE_V6 3
78 #define ICS_TYPE_V5 15
79 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
80
81 /* ---------------- Version 5 PCB Support Functions --------------------- */
82 /* Prototype: pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
83 * Purpose : enable interrupts from card
84 */
85 static void pata_icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
86 {
87 struct pata_icside_state *state = ec->irq_data;
88
89 writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
90 }
91
92 /* Prototype: pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
93 * Purpose : disable interrupts from card
94 */
95 static void pata_icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
96 {
97 struct pata_icside_state *state = ec->irq_data;
98
99 readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
100 }
101
102 static const expansioncard_ops_t pata_icside_ops_arcin_v5 = {
103 .irqenable = pata_icside_irqenable_arcin_v5,
104 .irqdisable = pata_icside_irqdisable_arcin_v5,
105 };
106
107
108 /* ---------------- Version 6 PCB Support Functions --------------------- */
109 /* Prototype: pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
110 * Purpose : enable interrupts from card
111 */
112 static void pata_icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
113 {
114 struct pata_icside_state *state = ec->irq_data;
115 void __iomem *base = state->irq_port;
116
117 if (!state->port[0].disabled)
118 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
119 if (!state->port[1].disabled)
120 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
121 }
122
123 /* Prototype: pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
124 * Purpose : disable interrupts from card
125 */
126 static void pata_icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
127 {
128 struct pata_icside_state *state = ec->irq_data;
129
130 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
131 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
132 }
133
134 /* Prototype: pata_icside_irqprobe(struct expansion_card *ec)
135 * Purpose : detect an active interrupt from card
136 */
137 static int pata_icside_irqpending_arcin_v6(struct expansion_card *ec)
138 {
139 struct pata_icside_state *state = ec->irq_data;
140
141 return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
142 readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
143 }
144
145 static const expansioncard_ops_t pata_icside_ops_arcin_v6 = {
146 .irqenable = pata_icside_irqenable_arcin_v6,
147 .irqdisable = pata_icside_irqdisable_arcin_v6,
148 .irqpending = pata_icside_irqpending_arcin_v6,
149 };
150
151
152 /*
153 * SG-DMA support.
154 *
155 * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
156 * There is only one DMA controller per card, which means that only
157 * one drive can be accessed at one time. NOTE! We do not enforce that
158 * here, but we rely on the main IDE driver spotting that both
159 * interfaces use the same IRQ, which should guarantee this.
160 */
161
162 /*
163 * Configure the IOMD to give the appropriate timings for the transfer
164 * mode being requested. We take the advice of the ATA standards, and
165 * calculate the cycle time based on the transfer mode, and the EIDE
166 * MW DMA specs that the drive provides in the IDENTIFY command.
167 *
168 * We have the following IOMD DMA modes to choose from:
169 *
170 * Type Active Recovery Cycle
171 * A 250 (250) 312 (550) 562 (800)
172 * B 187 (200) 250 (550) 437 (750)
173 * C 125 (125) 125 (375) 250 (500)
174 * D 62 (50) 125 (375) 187 (425)
175 *
176 * (figures in brackets are actual measured timings on DIOR/DIOW)
177 *
178 * However, we also need to take care of the read/write active and
179 * recovery timings:
180 *
181 * Read Write
182 * Mode Active -- Recovery -- Cycle IOMD type
183 * MW0 215 50 215 480 A
184 * MW1 80 50 50 150 C
185 * MW2 70 25 25 120 C
186 */
187 static void pata_icside_set_dmamode(struct ata_port *ap, struct ata_device *adev)
188 {
189 struct pata_icside_state *state = ap->host->private_data;
190 struct ata_timing t;
191 unsigned int cycle;
192 char iomd_type;
193
194 /*
195 * DMA is based on a 16MHz clock
196 */
197 if (ata_timing_compute(adev, adev->dma_mode, &t, 1000, 1))
198 return;
199
200 /*
201 * Choose the IOMD cycle timing which ensure that the interface
202 * satisfies the measured active, recovery and cycle times.
203 */
204 if (t.active <= 50 && t.recover <= 375 && t.cycle <= 425)
205 iomd_type = 'D', cycle = 187;
206 else if (t.active <= 125 && t.recover <= 375 && t.cycle <= 500)
207 iomd_type = 'C', cycle = 250;
208 else if (t.active <= 200 && t.recover <= 550 && t.cycle <= 750)
209 iomd_type = 'B', cycle = 437;
210 else
211 iomd_type = 'A', cycle = 562;
212
213 ata_dev_printk(adev, KERN_INFO, "timings: act %dns rec %dns cyc %dns (%c)\n",
214 t.active, t.recover, t.cycle, iomd_type);
215
216 state->port[ap->port_no].speed[adev->devno] = cycle;
217 }
218
219 static void pata_icside_bmdma_setup(struct ata_queued_cmd *qc)
220 {
221 struct ata_port *ap = qc->ap;
222 struct pata_icside_state *state = ap->host->private_data;
223 struct scatterlist *sg, *rsg = state->sg;
224 unsigned int write = qc->tf.flags & ATA_TFLAG_WRITE;
225
226 /*
227 * We are simplex; BUG if we try to fiddle with DMA
228 * while it's active.
229 */
230 BUG_ON(dma_channel_active(state->dma));
231
232 /*
233 * Copy ATAs scattered sg list into a contiguous array of sg
234 */
235 ata_for_each_sg(sg, qc) {
236 memcpy(rsg, sg, sizeof(*sg));
237 rsg++;
238 }
239
240 /*
241 * Route the DMA signals to the correct interface
242 */
243 writeb(state->port[ap->port_no].port_sel, state->ioc_base);
244
245 set_dma_speed(state->dma, state->port[ap->port_no].speed[qc->dev->devno]);
246 set_dma_sg(state->dma, state->sg, rsg - state->sg);
247 set_dma_mode(state->dma, write ? DMA_MODE_WRITE : DMA_MODE_READ);
248
249 /* issue r/w command */
250 ap->ops->exec_command(ap, &qc->tf);
251 }
252
253 static void pata_icside_bmdma_start(struct ata_queued_cmd *qc)
254 {
255 struct ata_port *ap = qc->ap;
256 struct pata_icside_state *state = ap->host->private_data;
257
258 BUG_ON(dma_channel_active(state->dma));
259 enable_dma(state->dma);
260 }
261
262 static void pata_icside_bmdma_stop(struct ata_queued_cmd *qc)
263 {
264 struct ata_port *ap = qc->ap;
265 struct pata_icside_state *state = ap->host->private_data;
266
267 disable_dma(state->dma);
268
269 /* see ata_bmdma_stop */
270 ata_altstatus(ap);
271 }
272
273 static u8 pata_icside_bmdma_status(struct ata_port *ap)
274 {
275 struct pata_icside_state *state = ap->host->private_data;
276 void __iomem *irq_port;
277
278 irq_port = state->irq_port + (ap->port_no ? ICS_ARCIN_V6_INTRSTAT_2 :
279 ICS_ARCIN_V6_INTRSTAT_1);
280
281 return readb(irq_port) & 1 ? ATA_DMA_INTR : 0;
282 }
283
284 static int icside_dma_init(struct pata_icside_info *info)
285 {
286 struct pata_icside_state *state = info->state;
287 struct expansion_card *ec = info->ec;
288 int i;
289
290 for (i = 0; i < ATA_MAX_DEVICES; i++) {
291 state->port[0].speed[i] = 480;
292 state->port[1].speed[i] = 480;
293 }
294
295 if (ec->dma != NO_DMA && !request_dma(ec->dma, DRV_NAME)) {
296 state->dma = ec->dma;
297 info->mwdma_mask = 0x07; /* MW0..2 */
298 }
299
300 return 0;
301 }
302
303
304 static int pata_icside_port_start(struct ata_port *ap)
305 {
306 /* No PRD to alloc */
307 return ata_pad_alloc(ap, ap->dev);
308 }
309
310 static struct scsi_host_template pata_icside_sht = {
311 .module = THIS_MODULE,
312 .name = DRV_NAME,
313 .ioctl = ata_scsi_ioctl,
314 .queuecommand = ata_scsi_queuecmd,
315 .can_queue = ATA_DEF_QUEUE,
316 .this_id = ATA_SHT_THIS_ID,
317 .sg_tablesize = PATA_ICSIDE_MAX_SG,
318 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
319 .emulated = ATA_SHT_EMULATED,
320 .use_clustering = ATA_SHT_USE_CLUSTERING,
321 .proc_name = DRV_NAME,
322 .dma_boundary = ~0, /* no dma boundaries */
323 .slave_configure = ata_scsi_slave_config,
324 .slave_destroy = ata_scsi_slave_destroy,
325 .bios_param = ata_std_bios_param,
326 };
327
328 /* wish this was exported from libata-core */
329 static void ata_dummy_noret(struct ata_port *port)
330 {
331 }
332
333 static void pata_icside_postreset(struct ata_port *ap, unsigned int *classes)
334 {
335 struct pata_icside_state *state = ap->host->private_data;
336
337 if (classes[0] != ATA_DEV_NONE || classes[1] != ATA_DEV_NONE)
338 return ata_std_postreset(ap, classes);
339
340 state->port[ap->port_no].disabled = 1;
341
342 if (state->type == ICS_TYPE_V6) {
343 /*
344 * Disable interrupts from this port, otherwise we
345 * receive spurious interrupts from the floating
346 * interrupt line.
347 */
348 void __iomem *irq_port = state->irq_port +
349 (ap->port_no ? ICS_ARCIN_V6_INTROFFSET_2 : ICS_ARCIN_V6_INTROFFSET_1);
350 readb(irq_port);
351 }
352 }
353
354 static void pata_icside_error_handler(struct ata_port *ap)
355 {
356 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, NULL,
357 pata_icside_postreset);
358 }
359
360 static u8 pata_icside_irq_ack(struct ata_port *ap, unsigned int chk_drq)
361 {
362 unsigned int bits = chk_drq ? ATA_BUSY | ATA_DRQ : ATA_BUSY;
363 u8 status;
364
365 status = ata_busy_wait(ap, bits, 1000);
366 if (status & bits)
367 if (ata_msg_err(ap))
368 printk(KERN_ERR "abnormal status 0x%X\n", status);
369
370 if (ata_msg_intr(ap))
371 printk(KERN_INFO "%s: irq ack: drv_stat 0x%X\n",
372 __FUNCTION__, status);
373
374 return status;
375 }
376
377 static struct ata_port_operations pata_icside_port_ops = {
378 .port_disable = ata_port_disable,
379
380 .set_dmamode = pata_icside_set_dmamode,
381
382 .tf_load = ata_tf_load,
383 .tf_read = ata_tf_read,
384 .exec_command = ata_exec_command,
385 .check_status = ata_check_status,
386 .dev_select = ata_std_dev_select,
387
388 .cable_detect = ata_cable_40wire,
389
390 .bmdma_setup = pata_icside_bmdma_setup,
391 .bmdma_start = pata_icside_bmdma_start,
392
393 .data_xfer = ata_data_xfer_noirq,
394
395 /* no need to build any PRD tables for DMA */
396 .qc_prep = ata_noop_qc_prep,
397 .qc_issue = ata_qc_issue_prot,
398
399 .freeze = ata_bmdma_freeze,
400 .thaw = ata_bmdma_thaw,
401 .error_handler = pata_icside_error_handler,
402 .post_internal_cmd = pata_icside_bmdma_stop,
403
404 .irq_clear = ata_dummy_noret,
405 .irq_on = ata_irq_on,
406 .irq_ack = pata_icside_irq_ack,
407
408 .port_start = pata_icside_port_start,
409
410 .bmdma_stop = pata_icside_bmdma_stop,
411 .bmdma_status = pata_icside_bmdma_status,
412 };
413
414 static void __devinit
415 pata_icside_setup_ioaddr(struct ata_ioports *ioaddr, void __iomem *base,
416 const struct portinfo *info)
417 {
418 void __iomem *cmd = base + info->dataoffset;
419
420 ioaddr->cmd_addr = cmd;
421 ioaddr->data_addr = cmd + (ATA_REG_DATA << info->stepping);
422 ioaddr->error_addr = cmd + (ATA_REG_ERR << info->stepping);
423 ioaddr->feature_addr = cmd + (ATA_REG_FEATURE << info->stepping);
424 ioaddr->nsect_addr = cmd + (ATA_REG_NSECT << info->stepping);
425 ioaddr->lbal_addr = cmd + (ATA_REG_LBAL << info->stepping);
426 ioaddr->lbam_addr = cmd + (ATA_REG_LBAM << info->stepping);
427 ioaddr->lbah_addr = cmd + (ATA_REG_LBAH << info->stepping);
428 ioaddr->device_addr = cmd + (ATA_REG_DEVICE << info->stepping);
429 ioaddr->status_addr = cmd + (ATA_REG_STATUS << info->stepping);
430 ioaddr->command_addr = cmd + (ATA_REG_CMD << info->stepping);
431
432 ioaddr->ctl_addr = base + info->ctrloffset;
433 ioaddr->altstatus_addr = ioaddr->ctl_addr;
434 }
435
436 static int __devinit pata_icside_register_v5(struct pata_icside_info *info)
437 {
438 struct pata_icside_state *state = info->state;
439 void __iomem *base;
440
441 base = ecardm_iomap(info->ec, ECARD_RES_MEMC, 0, 0);
442 if (!base)
443 return -ENOMEM;
444
445 state->irq_port = base;
446
447 info->base = base;
448 info->irqaddr = base + ICS_ARCIN_V5_INTRSTAT;
449 info->irqmask = 1;
450 info->irqops = &pata_icside_ops_arcin_v5;
451 info->nr_ports = 1;
452 info->port[0] = &pata_icside_portinfo_v5;
453
454 return 0;
455 }
456
457 static int __devinit pata_icside_register_v6(struct pata_icside_info *info)
458 {
459 struct pata_icside_state *state = info->state;
460 struct expansion_card *ec = info->ec;
461 void __iomem *ioc_base, *easi_base;
462 unsigned int sel = 0;
463
464 ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
465 if (!ioc_base)
466 return -ENOMEM;
467
468 easi_base = ioc_base;
469
470 if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
471 easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
472 if (!easi_base)
473 return -ENOMEM;
474
475 /*
476 * Enable access to the EASI region.
477 */
478 sel = 1 << 5;
479 }
480
481 writeb(sel, ioc_base);
482
483 state->irq_port = easi_base;
484 state->ioc_base = ioc_base;
485 state->port[0].port_sel = sel;
486 state->port[1].port_sel = sel | 1;
487
488 info->base = easi_base;
489 info->irqops = &pata_icside_ops_arcin_v6;
490 info->nr_ports = 2;
491 info->port[0] = &pata_icside_portinfo_v6_1;
492 info->port[1] = &pata_icside_portinfo_v6_2;
493
494 return icside_dma_init(info);
495 }
496
497 static int __devinit pata_icside_add_ports(struct pata_icside_info *info)
498 {
499 struct expansion_card *ec = info->ec;
500 struct ata_host *host;
501 int i;
502
503 if (info->irqaddr) {
504 ec->irqaddr = info->irqaddr;
505 ec->irqmask = info->irqmask;
506 }
507 if (info->irqops)
508 ecard_setirq(ec, info->irqops, info->state);
509
510 /*
511 * Be on the safe side - disable interrupts
512 */
513 ec->ops->irqdisable(ec, ec->irq);
514
515 host = ata_host_alloc(&ec->dev, info->nr_ports);
516 if (!host)
517 return -ENOMEM;
518
519 host->private_data = info->state;
520 host->flags = ATA_HOST_SIMPLEX;
521
522 for (i = 0; i < info->nr_ports; i++) {
523 struct ata_port *ap = host->ports[i];
524
525 ap->pio_mask = 0x1f;
526 ap->mwdma_mask = info->mwdma_mask;
527 ap->flags |= ATA_FLAG_SLAVE_POSS;
528 ap->ops = &pata_icside_port_ops;
529
530 pata_icside_setup_ioaddr(&ap->ioaddr, info->base, info->port[i]);
531 }
532
533 return ata_host_activate(host, ec->irq, ata_interrupt, 0,
534 &pata_icside_sht);
535 }
536
537 static int __devinit
538 pata_icside_probe(struct expansion_card *ec, const struct ecard_id *id)
539 {
540 struct pata_icside_state *state;
541 struct pata_icside_info info;
542 void __iomem *idmem;
543 int ret;
544
545 ret = ecard_request_resources(ec);
546 if (ret)
547 goto out;
548
549 state = devm_kzalloc(&ec->dev, sizeof(*state), GFP_KERNEL);
550 if (!state) {
551 ret = -ENOMEM;
552 goto release;
553 }
554
555 state->type = ICS_TYPE_NOTYPE;
556 state->dma = NO_DMA;
557
558 idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
559 if (idmem) {
560 unsigned int type;
561
562 type = readb(idmem + ICS_IDENT_OFFSET) & 1;
563 type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
564 type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
565 type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
566 ecardm_iounmap(ec, idmem);
567
568 state->type = type;
569 }
570
571 memset(&info, 0, sizeof(info));
572 info.state = state;
573 info.ec = ec;
574
575 switch (state->type) {
576 case ICS_TYPE_A3IN:
577 dev_warn(&ec->dev, "A3IN unsupported\n");
578 ret = -ENODEV;
579 break;
580
581 case ICS_TYPE_A3USER:
582 dev_warn(&ec->dev, "A3USER unsupported\n");
583 ret = -ENODEV;
584 break;
585
586 case ICS_TYPE_V5:
587 ret = pata_icside_register_v5(&info);
588 break;
589
590 case ICS_TYPE_V6:
591 ret = pata_icside_register_v6(&info);
592 break;
593
594 default:
595 dev_warn(&ec->dev, "unknown interface type\n");
596 ret = -ENODEV;
597 break;
598 }
599
600 if (ret == 0)
601 ret = pata_icside_add_ports(&info);
602
603 if (ret == 0)
604 goto out;
605
606 release:
607 ecard_release_resources(ec);
608 out:
609 return ret;
610 }
611
612 static void pata_icside_shutdown(struct expansion_card *ec)
613 {
614 struct ata_host *host = ecard_get_drvdata(ec);
615 unsigned long flags;
616
617 /*
618 * Disable interrupts from this card. We need to do
619 * this before disabling EASI since we may be accessing
620 * this register via that region.
621 */
622 local_irq_save(flags);
623 ec->ops->irqdisable(ec, ec->irq);
624 local_irq_restore(flags);
625
626 /*
627 * Reset the ROM pointer so that we can read the ROM
628 * after a soft reboot. This also disables access to
629 * the IDE taskfile via the EASI region.
630 */
631 if (host) {
632 struct pata_icside_state *state = host->private_data;
633 if (state->ioc_base)
634 writeb(0, state->ioc_base);
635 }
636 }
637
638 static void __devexit pata_icside_remove(struct expansion_card *ec)
639 {
640 struct ata_host *host = ecard_get_drvdata(ec);
641 struct pata_icside_state *state = host->private_data;
642
643 ata_host_detach(host);
644
645 pata_icside_shutdown(ec);
646
647 /*
648 * don't NULL out the drvdata - devres/libata wants it
649 * to free the ata_host structure.
650 */
651 if (state->dma != NO_DMA)
652 free_dma(state->dma);
653
654 ecard_release_resources(ec);
655 }
656
657 static const struct ecard_id pata_icside_ids[] = {
658 { MANU_ICS, PROD_ICS_IDE },
659 { MANU_ICS2, PROD_ICS2_IDE },
660 { 0xffff, 0xffff }
661 };
662
663 static struct ecard_driver pata_icside_driver = {
664 .probe = pata_icside_probe,
665 .remove = __devexit_p(pata_icside_remove),
666 .shutdown = pata_icside_shutdown,
667 .id_table = pata_icside_ids,
668 .drv = {
669 .name = DRV_NAME,
670 },
671 };
672
673 static int __init pata_icside_init(void)
674 {
675 return ecard_register_driver(&pata_icside_driver);
676 }
677
678 static void __exit pata_icside_exit(void)
679 {
680 ecard_remove_driver(&pata_icside_driver);
681 }
682
683 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
684 MODULE_LICENSE("GPL");
685 MODULE_DESCRIPTION("ICS PATA driver");
686
687 module_init(pata_icside_init);
688 module_exit(pata_icside_exit);
Support for the Chinese Samsung S3C2440 based development boards