drivers/ide/pci/cy82c693.c

   1 /*
   2  *  Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
   3  *  Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator
   4  *
   5  * CYPRESS CY82C693 chipset IDE controller
   6  *
   7  * The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
   8  * Writing the driver was quite simple, since most of the job is
   9  * done by the generic pci-ide support.
  10  * The hard part was finding the CY82C693's datasheet on Cypress's
  11  * web page :-(. But Altavista solved this problem :-).
  12  *
  13  *
  14  * Notes:
  15  * - I recently got a 16.8G IBM DTTA, so I was able to test it with
  16  *   a large and fast disk - the results look great, so I'd say the
  17  *   driver is working fine :-)
  18  *   hdparm -t reports 8.17 MB/sec at about 6% CPU usage for the DTTA
  19  * - this is my first linux driver, so there's probably a lot  of room
  20  *   for optimizations and bug fixing, so feel free to do it.
  21  * - if using PIO mode it's a good idea to set the PIO mode and
  22  *   32-bit I/O support (if possible), e.g. hdparm -p2 -c1 /dev/hda
  23  * - I had some problems with my IBM DHEA with PIO modes < 2
  24  *   (lost interrupts) ?????
  25  * - first tests with DMA look okay, they seem to work, but there is a
  26  *   problem with sound - the BusMaster IDE TimeOut should fixed this
  27  *
  28  * Ancient History:
  29  * AMH@1999-08-24: v0.34 init_cy82c693_chip moved to pci_init_cy82c693
  30  * ASK@1999-01-23: v0.33 made a few minor code clean ups
  31  *                       removed DMA clock speed setting by default
  32  *                       added boot message
  33  * ASK@1998-11-01: v0.32 added support to set BusMaster IDE TimeOut
  34  *                       added support to set DMA Controller Clock Speed
  35  * ASK@1998-10-31: v0.31 fixed problem with setting to high DMA modes
  36  *                       on some drives.
  37  * ASK@1998-10-29: v0.3 added support to set DMA modes
  38  * ASK@1998-10-28: v0.2 added support to set PIO modes
  39  * ASK@1998-10-27: v0.1 first version - chipset detection
  40  *
  41  */
  42
  43 #include <linux/module.h>
  44 #include <linux/types.h>
  45 #include <linux/pci.h>
  46 #include <linux/ide.h>
  47 #include <linux/init.h>
  48
  49 #include <asm/io.h>
  50
  51 #define DRV_NAME "cy82c693"
  52
  53 /* the current version */
  54 #define CY82_VERSION    "CY82C693U driver v0.34 99-13-12 Andreas S. Krebs (akrebs@altavista.net)"
  55
  56 /*
  57  *      The following are used to debug the driver.
  58  */
  59 #define CY82C693_DEBUG_LOGS     0
  60 #define CY82C693_DEBUG_INFO     0
  61
  62 /* define CY82C693_SETDMA_CLOCK to set DMA Controller Clock Speed to ATCLK */
  63 #undef CY82C693_SETDMA_CLOCK
  64
  65 /*
  66  *      NOTE: the value for busmaster timeout is tricky and I got it by
  67  *      trial and error!  By using a to low value will cause DMA timeouts
  68  *      and drop IDE performance, and by using a to high value will cause
  69  *      audio playback to scatter.
  70  *      If you know a better value or how to calc it, please let me know.
  71  */
  72
  73 /* twice the value written in cy82c693ub datasheet */
  74 #define BUSMASTER_TIMEOUT       0x50
  75 /*
  76  * the value above was tested on my machine and it seems to work okay
  77  */
  78
  79 /* here are the offset definitions for the registers */
  80 #define CY82_IDE_CMDREG         0x04
  81 #define CY82_IDE_ADDRSETUP      0x48
  82 #define CY82_IDE_MASTER_IOR     0x4C
  83 #define CY82_IDE_MASTER_IOW     0x4D
  84 #define CY82_IDE_SLAVE_IOR      0x4E
  85 #define CY82_IDE_SLAVE_IOW      0x4F
  86 #define CY82_IDE_MASTER_8BIT    0x50
  87 #define CY82_IDE_SLAVE_8BIT     0x51
  88
  89 #define CY82_INDEX_PORT         0x22
  90 #define CY82_DATA_PORT          0x23
  91
  92 #define CY82_INDEX_CTRLREG1     0x01
  93 #define CY82_INDEX_CHANNEL0     0x30
  94 #define CY82_INDEX_CHANNEL1     0x31
  95 #define CY82_INDEX_TIMEOUT      0x32
  96
  97 /* the min and max PCI bus speed in MHz - from datasheet */
  98 #define CY82C963_MIN_BUS_SPEED  25
  99 #define CY82C963_MAX_BUS_SPEED  33
 100
 101 /* the struct for the PIO mode timings */
 102 typedef struct pio_clocks_s {
 103         u8      address_time;   /* Address setup (clocks) */
 104         u8      time_16r;       /* clocks for 16bit IOR (0xF0=Active/data, 0x0F=Recovery) */
 105         u8      time_16w;       /* clocks for 16bit IOW (0xF0=Active/data, 0x0F=Recovery) */
 106         u8      time_8;         /* clocks for 8bit (0xF0=Active/data, 0x0F=Recovery) */
 107 } pio_clocks_t;
 108
 109 /*
 110  * calc clocks using bus_speed
 111  * returns (rounded up) time in bus clocks for time in ns
 112  */
 113 static int calc_clk(int time, int bus_speed)
 114 {
 115         int clocks;
 116
 117         clocks = (time*bus_speed+999)/1000 - 1;
 118
 119         if (clocks < 0)
 120                 clocks = 0;
 121
 122         if (clocks > 0x0F)
 123                 clocks = 0x0F;
 124
 125         return clocks;
 126 }
 127
 128 /*
 129  * compute the values for the clock registers for PIO
 130  * mode and pci_clk [MHz] speed
 131  *
 132  * NOTE: for mode 0,1 and 2 drives 8-bit IDE command control registers are used
 133  *       for mode 3 and 4 drives 8 and 16-bit timings are the same
 134  *
 135  */
 136 static void compute_clocks(u8 pio, pio_clocks_t *p_pclk)
 137 {
 138         struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio);
 139         int clk1, clk2;
 140         int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
 141
 142         /* we don't check against CY82C693's min and max speed,
 143          * so you can play with the idebus=xx parameter
 144          */
 145
 146         /* let's calc the address setup time clocks */
 147         p_pclk->address_time = (u8)calc_clk(t->setup, bus_speed);
 148
 149         /* let's calc the active and recovery time clocks */
 150         clk1 = calc_clk(t->active, bus_speed);
 151
 152         /* calc recovery timing */
 153         clk2 = t->cycle - t->active - t->setup;
 154
 155         clk2 = calc_clk(clk2, bus_speed);
 156
 157         clk1 = (clk1<<4)|clk2;  /* combine active and recovery clocks */
 158
 159         /* note: we use the same values for 16bit IOR and IOW
 160          *      those are all the same, since I don't have other
 161          *      timings than those from ide-lib.c
 162          */
 163
 164         p_pclk->time_16r = (u8)clk1;
 165         p_pclk->time_16w = (u8)clk1;
 166
 167         /* what are good values for 8bit ?? */
 168         p_pclk->time_8 = (u8)clk1;
 169 }
 170
 171 /*
 172  * set DMA mode a specific channel for CY82C693
 173  */
 174
 175 static void cy82c693_set_dma_mode(ide_drive_t *drive, const u8 mode)
 176 {
 177         ide_hwif_t *hwif = drive->hwif;
 178         u8 single = (mode & 0x10) >> 4, index = 0, data = 0;
 179
 180         index = hwif->channel ? CY82_INDEX_CHANNEL1 : CY82_INDEX_CHANNEL0;
 181
 182 #if CY82C693_DEBUG_LOGS
 183         /* for debug let's show the previous values */
 184
 185         outb(index, CY82_INDEX_PORT);
 186         data = inb(CY82_DATA_PORT);
 187
 188         printk(KERN_INFO "%s (ch=%d, dev=%d): DMA mode is %d (single=%d)\n",
 189                 drive->name, HWIF(drive)->channel, drive->select.b.unit,
 190                 (data&0x3), ((data>>2)&1));
 191 #endif /* CY82C693_DEBUG_LOGS */
 192
 193         data = (mode & 3) | (single << 2);
 194
 195         outb(index, CY82_INDEX_PORT);
 196         outb(data, CY82_DATA_PORT);
 197
 198 #if CY82C693_DEBUG_INFO
 199         printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n",
 200                 drive->name, HWIF(drive)->channel, drive->select.b.unit,
 201                 mode & 3, single);
 202 #endif /* CY82C693_DEBUG_INFO */
 203
 204         /*
 205          * note: below we set the value for Bus Master IDE TimeOut Register
 206          * I'm not absolutly sure what this does, but it solved my problem
 207          * with IDE DMA and sound, so I now can play sound and work with
 208          * my IDE driver at the same time :-)
 209          *
 210          * If you know the correct (best) value for this register please
 211          * let me know - ASK
 212          */
 213
 214         data = BUSMASTER_TIMEOUT;
 215         outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
 216         outb(data, CY82_DATA_PORT);
 217
 218 #if CY82C693_DEBUG_INFO
 219         printk(KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n",
 220                 drive->name, data);
 221 #endif /* CY82C693_DEBUG_INFO */
 222 }
 223
 224 static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio)
 225 {
 226         ide_hwif_t *hwif = HWIF(drive);
 227         struct pci_dev *dev = to_pci_dev(hwif->dev);
 228         pio_clocks_t pclk;
 229         unsigned int addrCtrl;
 230
 231         /* select primary or secondary channel */
 232         if (hwif->index > 0) {  /* drive is on the secondary channel */
 233                 dev = pci_get_slot(dev->bus, dev->devfn+1);
 234                 if (!dev) {
 235                         printk(KERN_ERR "%s: tune_drive: "
 236                                 "Cannot find secondary interface!\n",
 237                                 drive->name);
 238                         return;
 239                 }
 240         }
 241
 242 #if CY82C693_DEBUG_LOGS
 243         /* for debug let's show the register values */
 244
 245         if (drive->select.b.unit == 0) {
 246                 /*
 247                  * get master drive registers
 248                  * address setup control register
 249                  * is 32 bit !!!
 250                  */
 251                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 252                 addrCtrl &= 0x0F;
 253
 254                 /* now let's get the remaining registers */
 255                 pci_read_config_byte(dev, CY82_IDE_MASTER_IOR, &pclk.time_16r);
 256                 pci_read_config_byte(dev, CY82_IDE_MASTER_IOW, &pclk.time_16w);
 257                 pci_read_config_byte(dev, CY82_IDE_MASTER_8BIT, &pclk.time_8);
 258         } else {
 259                 /*
 260                  * set slave drive registers
 261                  * address setup control register
 262                  * is 32 bit !!!
 263                  */
 264                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 265
 266                 addrCtrl &= 0xF0;
 267                 addrCtrl >>= 4;
 268
 269                 /* now let's get the remaining registers */
 270                 pci_read_config_byte(dev, CY82_IDE_SLAVE_IOR, &pclk.time_16r);
 271                 pci_read_config_byte(dev, CY82_IDE_SLAVE_IOW, &pclk.time_16w);
 272                 pci_read_config_byte(dev, CY82_IDE_SLAVE_8BIT, &pclk.time_8);
 273         }
 274
 275         printk(KERN_INFO "%s (ch=%d, dev=%d): PIO timing is "
 276                 "(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
 277                 drive->name, hwif->channel, drive->select.b.unit,
 278                 addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
 279 #endif /* CY82C693_DEBUG_LOGS */
 280
 281         /* let's calc the values for this PIO mode */
 282         compute_clocks(pio, &pclk);
 283
 284         /* now let's write  the clocks registers */
 285         if (drive->select.b.unit == 0) {
 286                 /*
 287                  * set master drive
 288                  * address setup control register
 289                  * is 32 bit !!!
 290                  */
 291                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 292
 293                 addrCtrl &= (~0xF);
 294                 addrCtrl |= (unsigned int)pclk.address_time;
 295                 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
 296
 297                 /* now let's set the remaining registers */
 298                 pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r);
 299                 pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w);
 300                 pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8);
 301
 302                 addrCtrl &= 0xF;
 303         } else {
 304                 /*
 305                  * set slave drive
 306                  * address setup control register
 307                  * is 32 bit !!!
 308                  */
 309                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 310
 311                 addrCtrl &= (~0xF0);
 312                 addrCtrl |= ((unsigned int)pclk.address_time<<4);
 313                 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
 314
 315                 /* now let's set the remaining registers */
 316                 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r);
 317                 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w);
 318                 pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8);
 319
 320                 addrCtrl >>= 4;
 321                 addrCtrl &= 0xF;
 322         }
 323
 324 #if CY82C693_DEBUG_INFO
 325         printk(KERN_INFO "%s (ch=%d, dev=%d): set PIO timing to "
 326                 "(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
 327                 drive->name, hwif->channel, drive->select.b.unit,
 328                 addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
 329 #endif /* CY82C693_DEBUG_INFO */
 330 }
 331
 332 /*
 333  * this function is called during init and is used to setup the cy82c693 chip
 334  */
 335 static unsigned int __devinit init_chipset_cy82c693(struct pci_dev *dev)
 336 {
 337         if (PCI_FUNC(dev->devfn) != 1)
 338                 return 0;
 339
 340 #ifdef CY82C693_SETDMA_CLOCK
 341         u8 data = 0;
 342 #endif /* CY82C693_SETDMA_CLOCK */
 343
 344         /* write info about this verion of the driver */
 345         printk(KERN_INFO CY82_VERSION "\n");
 346
 347 #ifdef CY82C693_SETDMA_CLOCK
 348        /* okay let's set the DMA clock speed */
 349
 350         outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
 351         data = inb(CY82_DATA_PORT);
 352
 353 #if CY82C693_DEBUG_INFO
 354         printk(KERN_INFO DRV_NAME ": Peripheral Configuration Register: 0x%X\n",
 355                 data);
 356 #endif /* CY82C693_DEBUG_INFO */
 357
 358         /*
 359          * for some reason sometimes the DMA controller
 360          * speed is set to ATCLK/2 ???? - we fix this here
 361          *
 362          * note: i don't know what causes this strange behaviour,
 363          *       but even changing the dma speed doesn't solve it :-(
 364          *       the ide performance is still only half the normal speed
 365          *
 366          *       if anybody knows what goes wrong with my machine, please
 367          *       let me know - ASK
 368          */
 369
 370         data |= 0x03;
 371
 372         outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
 373         outb(data, CY82_DATA_PORT);
 374
 375 #if CY82C693_DEBUG_INFO
 376         printk(KERN_INFO ": New Peripheral Configuration Register: 0x%X\n",
 377                 data);
 378 #endif /* CY82C693_DEBUG_INFO */
 379
 380 #endif /* CY82C693_SETDMA_CLOCK */
 381         return 0;
 382 }
 383
 384 static void __devinit init_iops_cy82c693(ide_hwif_t *hwif)
 385 {
 386         static ide_hwif_t *primary;
 387         struct pci_dev *dev = to_pci_dev(hwif->dev);
 388
 389         if (PCI_FUNC(dev->devfn) == 1)
 390                 primary = hwif;
 391         else {
 392                 hwif->mate = primary;
 393                 hwif->channel = 1;
 394         }
 395 }
 396
 397 static const struct ide_port_ops cy82c693_port_ops = {
 398         .set_pio_mode           = cy82c693_set_pio_mode,
 399         .set_dma_mode           = cy82c693_set_dma_mode,
 400 };
 401
 402 static const struct ide_port_info cy82c693_chipset __devinitdata = {
 403         .name           = DRV_NAME,
 404         .init_chipset   = init_chipset_cy82c693,
 405         .init_iops      = init_iops_cy82c693,
 406         .port_ops       = &cy82c693_port_ops,
 407         .chipset        = ide_cy82c693,
 408         .host_flags     = IDE_HFLAG_SINGLE,
 409         .pio_mask       = ATA_PIO4,
 410         .swdma_mask     = ATA_SWDMA2,
 411         .mwdma_mask     = ATA_MWDMA2,
 412 };
 413
 414 static int __devinit cy82c693_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 415 {
 416         struct pci_dev *dev2;
 417         int ret = -ENODEV;
 418
 419         /* CY82C693 is more than only a IDE controller.
 420            Function 1 is primary IDE channel, function 2 - secondary. */
 421         if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE &&
 422             PCI_FUNC(dev->devfn) == 1) {
 423                 dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
 424                 ret = ide_pci_init_two(dev, dev2, &cy82c693_chipset, NULL);
 425                 if (ret)
 426                         pci_dev_put(dev2);
 427         }
 428         return ret;
 429 }
 430
 431 static void __devexit cy82c693_remove(struct pci_dev *dev)
 432 {
 433         struct ide_host *host = pci_get_drvdata(dev);
 434         struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
 435
 436         ide_pci_remove(dev);
 437         pci_dev_put(dev2);
 438 }
 439
 440 static const struct pci_device_id cy82c693_pci_tbl[] = {
 441         { PCI_VDEVICE(CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693), 0 },
 442         { 0, },
 443 };
 444 MODULE_DEVICE_TABLE(pci, cy82c693_pci_tbl);
 445
 446 static struct pci_driver driver = {
 447         .name           = "Cypress_IDE",
 448         .id_table       = cy82c693_pci_tbl,
 449         .probe          = cy82c693_init_one,
 450         .remove         = cy82c693_remove,
 451 };
 452
 453 static int __init cy82c693_ide_init(void)
 454 {
 455         return ide_pci_register_driver(&driver);
 456 }
 457
 458 static void __exit cy82c693_ide_exit(void)
 459 {
 460         pci_unregister_driver(&driver);
 461 }
 462
 463 module_init(cy82c693_ide_init);
 464 module_exit(cy82c693_ide_exit);
 465
 466 MODULE_AUTHOR("Andreas Krebs, Andre Hedrick");
 467 MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE");
 468 MODULE_LICENSE("GPL");