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[PATCH] shpchp: Cleanup interrupt polling timer
[linux-2.6/mini2440.git] / drivers / pci / hotplug / shpchp_hpc.c
blob3a8186c405f10f59ea7a7e769c15ad905a84f016
1 /*
2 * Standard PCI Hot Plug Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
8 *
9 * All rights reserved.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
20 * details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
27 *
28 */
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/interrupt.h>
35
36 #include "shpchp.h"
37
38 #ifdef DEBUG
39 #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */
40 #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */
41 #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */
42 #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */
43 #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)
44 #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)
45 /* Redefine this flagword to set debug level */
46 #define DEBUG_LEVEL DBG_K_STANDARD
47
48 #define DEFINE_DBG_BUFFER char __dbg_str_buf[256];
49
50 #define DBG_PRINT( dbg_flags, args... ) \
51 do { \
52 if ( DEBUG_LEVEL & ( dbg_flags ) ) \
53 { \
54 int len; \
55 len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \
56 __FILE__, __LINE__, __FUNCTION__ ); \
57 sprintf( __dbg_str_buf + len, args ); \
58 printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \
59 } \
60 } while (0)
61
62 #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");
63 #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");
64 #else
65 #define DEFINE_DBG_BUFFER
66 #define DBG_ENTER_ROUTINE
67 #define DBG_LEAVE_ROUTINE
68 #endif /* DEBUG */
69
70 /* Slot Available Register I field definition */
71 #define SLOT_33MHZ 0x0000001f
72 #define SLOT_66MHZ_PCIX 0x00001f00
73 #define SLOT_100MHZ_PCIX 0x001f0000
74 #define SLOT_133MHZ_PCIX 0x1f000000
75
76 /* Slot Available Register II field definition */
77 #define SLOT_66MHZ 0x0000001f
78 #define SLOT_66MHZ_PCIX_266 0x00000f00
79 #define SLOT_100MHZ_PCIX_266 0x0000f000
80 #define SLOT_133MHZ_PCIX_266 0x000f0000
81 #define SLOT_66MHZ_PCIX_533 0x00f00000
82 #define SLOT_100MHZ_PCIX_533 0x0f000000
83 #define SLOT_133MHZ_PCIX_533 0xf0000000
84
85 /* Slot Configuration */
86 #define SLOT_NUM 0x0000001F
87 #define FIRST_DEV_NUM 0x00001F00
88 #define PSN 0x07FF0000
89 #define UPDOWN 0x20000000
90 #define MRLSENSOR 0x40000000
91 #define ATTN_BUTTON 0x80000000
92
93 /*
94 * Interrupt Locator Register definitions
95 */
96 #define CMD_INTR_PENDING (1 << 0)
97 #define SLOT_INTR_PENDING(i) (1 << (i + 1))
98
99 /*
100 * Controller SERR-INT Register
101 */
102 #define GLOBAL_INTR_MASK (1 << 0)
103 #define GLOBAL_SERR_MASK (1 << 1)
104 #define COMMAND_INTR_MASK (1 << 2)
105 #define ARBITER_SERR_MASK (1 << 3)
106 #define COMMAND_DETECTED (1 << 16)
107 #define ARBITER_DETECTED (1 << 17)
108 #define SERR_INTR_RSVDZ_MASK 0xfffc0000
109
110 /*
111 * Logical Slot Register definitions
112 */
113 #define SLOT_REG(i) (SLOT1 + (4 * i))
114
115 #define SLOT_STATE_SHIFT (0)
116 #define SLOT_STATE_MASK (3 << 0)
117 #define SLOT_STATE_PWRONLY (1)
118 #define SLOT_STATE_ENABLED (2)
119 #define SLOT_STATE_DISABLED (3)
120 #define PWR_LED_STATE_SHIFT (2)
121 #define PWR_LED_STATE_MASK (3 << 2)
122 #define ATN_LED_STATE_SHIFT (4)
123 #define ATN_LED_STATE_MASK (3 << 4)
124 #define ATN_LED_STATE_ON (1)
125 #define ATN_LED_STATE_BLINK (2)
126 #define ATN_LED_STATE_OFF (3)
127 #define POWER_FAULT (1 << 6)
128 #define ATN_BUTTON (1 << 7)
129 #define MRL_SENSOR (1 << 8)
130 #define MHZ66_CAP (1 << 9)
131 #define PRSNT_SHIFT (10)
132 #define PRSNT_MASK (3 << 10)
133 #define PCIX_CAP_SHIFT (12)
134 #define PCIX_CAP_MASK_PI1 (3 << 12)
135 #define PCIX_CAP_MASK_PI2 (7 << 12)
136 #define PRSNT_CHANGE_DETECTED (1 << 16)
137 #define ISO_PFAULT_DETECTED (1 << 17)
138 #define BUTTON_PRESS_DETECTED (1 << 18)
139 #define MRL_CHANGE_DETECTED (1 << 19)
140 #define CON_PFAULT_DETECTED (1 << 20)
141 #define PRSNT_CHANGE_INTR_MASK (1 << 24)
142 #define ISO_PFAULT_INTR_MASK (1 << 25)
143 #define BUTTON_PRESS_INTR_MASK (1 << 26)
144 #define MRL_CHANGE_INTR_MASK (1 << 27)
145 #define CON_PFAULT_INTR_MASK (1 << 28)
146 #define MRL_CHANGE_SERR_MASK (1 << 29)
147 #define CON_PFAULT_SERR_MASK (1 << 30)
148 #define SLOT_REG_RSVDZ_MASK (1 << 15) | (7 << 21)
149
150 /*
151 * SHPC Command Code definitnions
152 *
153 * Slot Operation 00h - 3Fh
154 * Set Bus Segment Speed/Mode A 40h - 47h
155 * Power-Only All Slots 48h
156 * Enable All Slots 49h
157 * Set Bus Segment Speed/Mode B (PI=2) 50h - 5Fh
158 * Reserved Command Codes 60h - BFh
159 * Vendor Specific Commands C0h - FFh
160 */
161 #define SET_SLOT_PWR 0x01 /* Slot Operation */
162 #define SET_SLOT_ENABLE 0x02
163 #define SET_SLOT_DISABLE 0x03
164 #define SET_PWR_ON 0x04
165 #define SET_PWR_BLINK 0x08
166 #define SET_PWR_OFF 0x0c
167 #define SET_ATTN_ON 0x10
168 #define SET_ATTN_BLINK 0x20
169 #define SET_ATTN_OFF 0x30
170 #define SETA_PCI_33MHZ 0x40 /* Set Bus Segment Speed/Mode A */
171 #define SETA_PCI_66MHZ 0x41
172 #define SETA_PCIX_66MHZ 0x42
173 #define SETA_PCIX_100MHZ 0x43
174 #define SETA_PCIX_133MHZ 0x44
175 #define SETA_RESERVED1 0x45
176 #define SETA_RESERVED2 0x46
177 #define SETA_RESERVED3 0x47
178 #define SET_PWR_ONLY_ALL 0x48 /* Power-Only All Slots */
179 #define SET_ENABLE_ALL 0x49 /* Enable All Slots */
180 #define SETB_PCI_33MHZ 0x50 /* Set Bus Segment Speed/Mode B */
181 #define SETB_PCI_66MHZ 0x51
182 #define SETB_PCIX_66MHZ_PM 0x52
183 #define SETB_PCIX_100MHZ_PM 0x53
184 #define SETB_PCIX_133MHZ_PM 0x54
185 #define SETB_PCIX_66MHZ_EM 0x55
186 #define SETB_PCIX_100MHZ_EM 0x56
187 #define SETB_PCIX_133MHZ_EM 0x57
188 #define SETB_PCIX_66MHZ_266 0x58
189 #define SETB_PCIX_100MHZ_266 0x59
190 #define SETB_PCIX_133MHZ_266 0x5a
191 #define SETB_PCIX_66MHZ_533 0x5b
192 #define SETB_PCIX_100MHZ_533 0x5c
193 #define SETB_PCIX_133MHZ_533 0x5d
194 #define SETB_RESERVED1 0x5e
195 #define SETB_RESERVED2 0x5f
196
197 /*
198 * SHPC controller command error code
199 */
200 #define SWITCH_OPEN 0x1
201 #define INVALID_CMD 0x2
202 #define INVALID_SPEED_MODE 0x4
203
204 /*
205 * For accessing SHPC Working Register Set via PCI Configuration Space
206 */
207 #define DWORD_SELECT 0x2
208 #define DWORD_DATA 0x4
209
210 /* Field Offset in Logical Slot Register - byte boundary */
211 #define SLOT_EVENT_LATCH 0x2
212 #define SLOT_SERR_INT_MASK 0x3
213
214 static spinlock_t hpc_event_lock;
215
216 DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */
217 static struct php_ctlr_state_s *php_ctlr_list_head; /* HPC state linked list */
218 static int ctlr_seq_num = 0; /* Controller sequenc # */
219 static spinlock_t list_lock;
220
221 static atomic_t shpchp_num_controllers = ATOMIC_INIT(0);
222
223 static irqreturn_t shpc_isr(int irq, void *dev_id, struct pt_regs *regs);
224 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int sec);
225 static int hpc_check_cmd_status(struct controller *ctrl);
226
227 static inline u8 shpc_readb(struct controller *ctrl, int reg)
228 {
229 return readb(ctrl->hpc_ctlr_handle->creg + reg);
230 }
231
232 static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val)
233 {
234 writeb(val, ctrl->hpc_ctlr_handle->creg + reg);
235 }
236
237 static inline u16 shpc_readw(struct controller *ctrl, int reg)
238 {
239 return readw(ctrl->hpc_ctlr_handle->creg + reg);
240 }
241
242 static inline void shpc_writew(struct controller *ctrl, int reg, u16 val)
243 {
244 writew(val, ctrl->hpc_ctlr_handle->creg + reg);
245 }
246
247 static inline u32 shpc_readl(struct controller *ctrl, int reg)
248 {
249 return readl(ctrl->hpc_ctlr_handle->creg + reg);
250 }
251
252 static inline void shpc_writel(struct controller *ctrl, int reg, u32 val)
253 {
254 writel(val, ctrl->hpc_ctlr_handle->creg + reg);
255 }
256
257 static inline int shpc_indirect_read(struct controller *ctrl, int index,
258 u32 *value)
259 {
260 int rc;
261 u32 cap_offset = ctrl->cap_offset;
262 struct pci_dev *pdev = ctrl->pci_dev;
263
264 rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index);
265 if (rc)
266 return rc;
267 return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value);
268 }
269
270 /*
271 * This is the interrupt polling timeout function.
272 */
273 static void int_poll_timeout(unsigned long lphp_ctlr)
274 {
275 struct php_ctlr_state_s *php_ctlr =
276 (struct php_ctlr_state_s *)lphp_ctlr;
277
278 DBG_ENTER_ROUTINE
279
280 /* Poll for interrupt events. regs == NULL => polling */
281 shpc_isr(0, php_ctlr->callback_instance_id, NULL);
282
283 init_timer(&php_ctlr->int_poll_timer);
284 if (!shpchp_poll_time)
285 shpchp_poll_time = 2; /* default polling interval is 2 sec */
286
287 start_int_poll_timer(php_ctlr, shpchp_poll_time);
288
289 DBG_LEAVE_ROUTINE
290 }
291
292 /*
293 * This function starts the interrupt polling timer.
294 */
295 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int sec)
296 {
297 /* Clamp to sane value */
298 if ((sec <= 0) || (sec > 60))
299 sec = 2;
300
301 php_ctlr->int_poll_timer.function = &int_poll_timeout;
302 php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr;
303 php_ctlr->int_poll_timer.expires = jiffies + sec * HZ;
304 add_timer(&php_ctlr->int_poll_timer);
305 }
306
307 static inline int shpc_wait_cmd(struct controller *ctrl)
308 {
309 int retval = 0;
310 unsigned int timeout_msec = shpchp_poll_mode ? 2000 : 1000;
311 unsigned long timeout = msecs_to_jiffies(timeout_msec);
312 int rc = wait_event_interruptible_timeout(ctrl->queue,
313 !ctrl->cmd_busy, timeout);
314 if (!rc) {
315 retval = -EIO;
316 err("Command not completed in %d msec\n", timeout_msec);
317 } else if (rc < 0) {
318 retval = -EINTR;
319 info("Command was interrupted by a signal\n");
320 }
321 ctrl->cmd_busy = 0;
322
323 return retval;
324 }
325
326 static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
327 {
328 struct controller *ctrl = slot->ctrl;
329 u16 cmd_status;
330 int retval = 0;
331 u16 temp_word;
332 int i;
333
334 DBG_ENTER_ROUTINE
335
336 mutex_lock(&slot->ctrl->cmd_lock);
337
338 for (i = 0; i < 10; i++) {
339 cmd_status = shpc_readw(ctrl, CMD_STATUS);
340
341 if (!(cmd_status & 0x1))
342 break;
343 /* Check every 0.1 sec for a total of 1 sec*/
344 msleep(100);
345 }
346
347 cmd_status = shpc_readw(ctrl, CMD_STATUS);
348
349 if (cmd_status & 0x1) {
350 /* After 1 sec and and the controller is still busy */
351 err("%s : Controller is still busy after 1 sec.\n", __FUNCTION__);
352 retval = -EBUSY;
353 goto out;
354 }
355
356 ++t_slot;
357 temp_word = (t_slot << 8) | (cmd & 0xFF);
358 dbg("%s: t_slot %x cmd %x\n", __FUNCTION__, t_slot, cmd);
359
360 /* To make sure the Controller Busy bit is 0 before we send out the
361 * command.
362 */
363 slot->ctrl->cmd_busy = 1;
364 shpc_writew(ctrl, CMD, temp_word);
365
366 /*
367 * Wait for command completion.
368 */
369 retval = shpc_wait_cmd(slot->ctrl);
370 if (retval)
371 goto out;
372
373 cmd_status = hpc_check_cmd_status(slot->ctrl);
374 if (cmd_status) {
375 err("%s: Failed to issued command 0x%x (error code = %d)\n",
376 __FUNCTION__, cmd, cmd_status);
377 retval = -EIO;
378 }
379 out:
380 mutex_unlock(&slot->ctrl->cmd_lock);
381
382 DBG_LEAVE_ROUTINE
383 return retval;
384 }
385
386 static int hpc_check_cmd_status(struct controller *ctrl)
387 {
388 u16 cmd_status;
389 int retval = 0;
390
391 DBG_ENTER_ROUTINE
392
393 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;
394
395 switch (cmd_status >> 1) {
396 case 0:
397 retval = 0;
398 break;
399 case 1:
400 retval = SWITCH_OPEN;
401 err("%s: Switch opened!\n", __FUNCTION__);
402 break;
403 case 2:
404 retval = INVALID_CMD;
405 err("%s: Invalid HPC command!\n", __FUNCTION__);
406 break;
407 case 4:
408 retval = INVALID_SPEED_MODE;
409 err("%s: Invalid bus speed/mode!\n", __FUNCTION__);
410 break;
411 default:
412 retval = cmd_status;
413 }
414
415 DBG_LEAVE_ROUTINE
416 return retval;
417 }
418
419
420 static int hpc_get_attention_status(struct slot *slot, u8 *status)
421 {
422 struct controller *ctrl = slot->ctrl;
423 u32 slot_reg;
424 u8 state;
425
426 DBG_ENTER_ROUTINE
427
428 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
429 state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT;
430
431 switch (state) {
432 case ATN_LED_STATE_ON:
433 *status = 1; /* On */
434 break;
435 case ATN_LED_STATE_BLINK:
436 *status = 2; /* Blink */
437 break;
438 case ATN_LED_STATE_OFF:
439 *status = 0; /* Off */
440 break;
441 default:
442 *status = 0xFF; /* Reserved */
443 break;
444 }
445
446 DBG_LEAVE_ROUTINE
447 return 0;
448 }
449
450 static int hpc_get_power_status(struct slot * slot, u8 *status)
451 {
452 struct controller *ctrl = slot->ctrl;
453 u32 slot_reg;
454 u8 state;
455
456 DBG_ENTER_ROUTINE
457
458 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
459 state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT;
460
461 switch (state) {
462 case SLOT_STATE_PWRONLY:
463 *status = 2; /* Powered only */
464 break;
465 case SLOT_STATE_ENABLED:
466 *status = 1; /* Enabled */
467 break;
468 case SLOT_STATE_DISABLED:
469 *status = 0; /* Disabled */
470 break;
471 default:
472 *status = 0xFF; /* Reserved */
473 break;
474 }
475
476 DBG_LEAVE_ROUTINE
477 return 0;
478 }
479
480
481 static int hpc_get_latch_status(struct slot *slot, u8 *status)
482 {
483 struct controller *ctrl = slot->ctrl;
484 u32 slot_reg;
485
486 DBG_ENTER_ROUTINE
487
488 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
489 *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */
490
491 DBG_LEAVE_ROUTINE
492 return 0;
493 }
494
495 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
496 {
497 struct controller *ctrl = slot->ctrl;
498 u32 slot_reg;
499 u8 state;
500
501 DBG_ENTER_ROUTINE
502
503 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
504 state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT;
505 *status = (state != 0x3) ? 1 : 0;
506
507 DBG_LEAVE_ROUTINE
508 return 0;
509 }
510
511 static int hpc_get_prog_int(struct slot *slot, u8 *prog_int)
512 {
513 struct controller *ctrl = slot->ctrl;
514
515 DBG_ENTER_ROUTINE
516
517 *prog_int = shpc_readb(ctrl, PROG_INTERFACE);
518
519 DBG_LEAVE_ROUTINE
520 return 0;
521 }
522
523 static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
524 {
525 int retval = 0;
526 struct controller *ctrl = slot->ctrl;
527 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
528 u8 m66_cap = !!(slot_reg & MHZ66_CAP);
529 u8 pi, pcix_cap;
530
531 DBG_ENTER_ROUTINE
532
533 if ((retval = hpc_get_prog_int(slot, &pi)))
534 return retval;
535
536 switch (pi) {
537 case 1:
538 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT;
539 break;
540 case 2:
541 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT;
542 break;
543 default:
544 return -ENODEV;
545 }
546
547 dbg("%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",
548 __FUNCTION__, slot_reg, pcix_cap, m66_cap);
549
550 switch (pcix_cap) {
551 case 0x0:
552 *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
553 break;
554 case 0x1:
555 *value = PCI_SPEED_66MHz_PCIX;
556 break;
557 case 0x3:
558 *value = PCI_SPEED_133MHz_PCIX;
559 break;
560 case 0x4:
561 *value = PCI_SPEED_133MHz_PCIX_266;
562 break;
563 case 0x5:
564 *value = PCI_SPEED_133MHz_PCIX_533;
565 break;
566 case 0x2:
567 default:
568 *value = PCI_SPEED_UNKNOWN;
569 retval = -ENODEV;
570 break;
571 }
572
573 dbg("Adapter speed = %d\n", *value);
574 DBG_LEAVE_ROUTINE
575 return retval;
576 }
577
578 static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
579 {
580 struct controller *ctrl = slot->ctrl;
581 u16 sec_bus_status;
582 u8 pi;
583 int retval = 0;
584
585 DBG_ENTER_ROUTINE
586
587 pi = shpc_readb(ctrl, PROG_INTERFACE);
588 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG);
589
590 if (pi == 2) {
591 *mode = (sec_bus_status & 0x0100) >> 8;
592 } else {
593 retval = -1;
594 }
595
596 dbg("Mode 1 ECC cap = %d\n", *mode);
597
598 DBG_LEAVE_ROUTINE
599 return retval;
600 }
601
602 static int hpc_query_power_fault(struct slot * slot)
603 {
604 struct controller *ctrl = slot->ctrl;
605 u32 slot_reg;
606
607 DBG_ENTER_ROUTINE
608
609 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
610
611 DBG_LEAVE_ROUTINE
612 /* Note: Logic 0 => fault */
613 return !(slot_reg & POWER_FAULT);
614 }
615
616 static int hpc_set_attention_status(struct slot *slot, u8 value)
617 {
618 u8 slot_cmd = 0;
619
620 switch (value) {
621 case 0 :
622 slot_cmd = SET_ATTN_OFF; /* OFF */
623 break;
624 case 1:
625 slot_cmd = SET_ATTN_ON; /* ON */
626 break;
627 case 2:
628 slot_cmd = SET_ATTN_BLINK; /* BLINK */
629 break;
630 default:
631 return -1;
632 }
633
634 return shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
635 }
636
637
638 static void hpc_set_green_led_on(struct slot *slot)
639 {
640 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON);
641 }
642
643 static void hpc_set_green_led_off(struct slot *slot)
644 {
645 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF);
646 }
647
648 static void hpc_set_green_led_blink(struct slot *slot)
649 {
650 shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK);
651 }
652
653 int shpc_get_ctlr_slot_config(struct controller *ctrl,
654 int *num_ctlr_slots, /* number of slots in this HPC */
655 int *first_device_num, /* PCI dev num of the first slot in this SHPC */
656 int *physical_slot_num, /* phy slot num of the first slot in this SHPC */
657 int *updown, /* physical_slot_num increament: 1 or -1 */
658 int *flags)
659 {
660 u32 slot_config;
661
662 DBG_ENTER_ROUTINE
663
664 slot_config = shpc_readl(ctrl, SLOT_CONFIG);
665 *first_device_num = (slot_config & FIRST_DEV_NUM) >> 8;
666 *num_ctlr_slots = slot_config & SLOT_NUM;
667 *physical_slot_num = (slot_config & PSN) >> 16;
668 *updown = ((slot_config & UPDOWN) >> 29) ? 1 : -1;
669
670 dbg("%s: physical_slot_num = %x\n", __FUNCTION__, *physical_slot_num);
671
672 DBG_LEAVE_ROUTINE
673 return 0;
674 }
675
676 static void hpc_release_ctlr(struct controller *ctrl)
677 {
678 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
679 struct php_ctlr_state_s *p, *p_prev;
680 int i;
681 u32 slot_reg, serr_int;
682
683 DBG_ENTER_ROUTINE
684
685 /*
686 * Mask event interrupts and SERRs of all slots
687 */
688 for (i = 0; i < ctrl->num_slots; i++) {
689 slot_reg = shpc_readl(ctrl, SLOT_REG(i));
690 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
691 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
692 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
693 CON_PFAULT_SERR_MASK);
694 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
695 shpc_writel(ctrl, SLOT_REG(i), slot_reg);
696 }
697
698 cleanup_slots(ctrl);
699
700 /*
701 * Mask SERR and System Interrut generation
702 */
703 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
704 serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
705 COMMAND_INTR_MASK | ARBITER_SERR_MASK);
706 serr_int &= ~SERR_INTR_RSVDZ_MASK;
707 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
708
709 if (shpchp_poll_mode) {
710 del_timer(&php_ctlr->int_poll_timer);
711 } else {
712 if (php_ctlr->irq) {
713 free_irq(php_ctlr->irq, ctrl);
714 php_ctlr->irq = 0;
715 pci_disable_msi(php_ctlr->pci_dev);
716 }
717 }
718
719 if (php_ctlr->pci_dev) {
720 iounmap(php_ctlr->creg);
721 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
722 php_ctlr->pci_dev = NULL;
723 }
724
725 spin_lock(&list_lock);
726 p = php_ctlr_list_head;
727 p_prev = NULL;
728 while (p) {
729 if (p == php_ctlr) {
730 if (p_prev)
731 p_prev->pnext = p->pnext;
732 else
733 php_ctlr_list_head = p->pnext;
734 break;
735 } else {
736 p_prev = p;
737 p = p->pnext;
738 }
739 }
740 spin_unlock(&list_lock);
741
742 kfree(php_ctlr);
743
744 /*
745 * If this is the last controller to be released, destroy the
746 * shpchpd work queue
747 */
748 if (atomic_dec_and_test(&shpchp_num_controllers))
749 destroy_workqueue(shpchp_wq);
750
751 DBG_LEAVE_ROUTINE
752
753 }
754
755 static int hpc_power_on_slot(struct slot * slot)
756 {
757 int retval;
758
759 DBG_ENTER_ROUTINE
760
761 retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR);
762 if (retval) {
763 err("%s: Write command failed!\n", __FUNCTION__);
764 return retval;
765 }
766
767 DBG_LEAVE_ROUTINE
768
769 return 0;
770 }
771
772 static int hpc_slot_enable(struct slot * slot)
773 {
774 int retval;
775
776 DBG_ENTER_ROUTINE
777
778 /* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */
779 retval = shpc_write_cmd(slot, slot->hp_slot,
780 SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF);
781 if (retval) {
782 err("%s: Write command failed!\n", __FUNCTION__);
783 return retval;
784 }
785
786 DBG_LEAVE_ROUTINE
787 return 0;
788 }
789
790 static int hpc_slot_disable(struct slot * slot)
791 {
792 int retval;
793
794 DBG_ENTER_ROUTINE
795
796 /* Slot - Disable, Power Indicator - Off, Attention Indicator - On */
797 retval = shpc_write_cmd(slot, slot->hp_slot,
798 SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON);
799 if (retval) {
800 err("%s: Write command failed!\n", __FUNCTION__);
801 return retval;
802 }
803
804 DBG_LEAVE_ROUTINE
805 return 0;
806 }
807
808 static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value)
809 {
810 int retval;
811 struct controller *ctrl = slot->ctrl;
812 u8 pi, cmd;
813
814 DBG_ENTER_ROUTINE
815
816 pi = shpc_readb(ctrl, PROG_INTERFACE);
817 if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX))
818 return -EINVAL;
819
820 switch (value) {
821 case PCI_SPEED_33MHz:
822 cmd = SETA_PCI_33MHZ;
823 break;
824 case PCI_SPEED_66MHz:
825 cmd = SETA_PCI_66MHZ;
826 break;
827 case PCI_SPEED_66MHz_PCIX:
828 cmd = SETA_PCIX_66MHZ;
829 break;
830 case PCI_SPEED_100MHz_PCIX:
831 cmd = SETA_PCIX_100MHZ;
832 break;
833 case PCI_SPEED_133MHz_PCIX:
834 cmd = SETA_PCIX_133MHZ;
835 break;
836 case PCI_SPEED_66MHz_PCIX_ECC:
837 cmd = SETB_PCIX_66MHZ_EM;
838 break;
839 case PCI_SPEED_100MHz_PCIX_ECC:
840 cmd = SETB_PCIX_100MHZ_EM;
841 break;
842 case PCI_SPEED_133MHz_PCIX_ECC:
843 cmd = SETB_PCIX_133MHZ_EM;
844 break;
845 case PCI_SPEED_66MHz_PCIX_266:
846 cmd = SETB_PCIX_66MHZ_266;
847 break;
848 case PCI_SPEED_100MHz_PCIX_266:
849 cmd = SETB_PCIX_100MHZ_266;
850 break;
851 case PCI_SPEED_133MHz_PCIX_266:
852 cmd = SETB_PCIX_133MHZ_266;
853 break;
854 case PCI_SPEED_66MHz_PCIX_533:
855 cmd = SETB_PCIX_66MHZ_533;
856 break;
857 case PCI_SPEED_100MHz_PCIX_533:
858 cmd = SETB_PCIX_100MHZ_533;
859 break;
860 case PCI_SPEED_133MHz_PCIX_533:
861 cmd = SETB_PCIX_133MHZ_533;
862 break;
863 default:
864 return -EINVAL;
865 }
866
867 retval = shpc_write_cmd(slot, 0, cmd);
868 if (retval)
869 err("%s: Write command failed!\n", __FUNCTION__);
870
871 DBG_LEAVE_ROUTINE
872 return retval;
873 }
874
875 static irqreturn_t shpc_isr(int irq, void *dev_id, struct pt_regs *regs)
876 {
877 struct controller *ctrl = (struct controller *)dev_id;
878 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
879 u32 serr_int, slot_reg, intr_loc, intr_loc2;
880 int hp_slot;
881
882 /* Check to see if it was our interrupt */
883 intr_loc = shpc_readl(ctrl, INTR_LOC);
884 if (!intr_loc)
885 return IRQ_NONE;
886
887 dbg("%s: intr_loc = %x\n",__FUNCTION__, intr_loc);
888
889 if(!shpchp_poll_mode) {
890 /*
891 * Mask Global Interrupt Mask - see implementation
892 * note on p. 139 of SHPC spec rev 1.0
893 */
894 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
895 serr_int |= GLOBAL_INTR_MASK;
896 serr_int &= ~SERR_INTR_RSVDZ_MASK;
897 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
898
899 intr_loc2 = shpc_readl(ctrl, INTR_LOC);
900 dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2);
901 }
902
903 if (intr_loc & CMD_INTR_PENDING) {
904 /*
905 * Command Complete Interrupt Pending
906 * RO only - clear by writing 1 to the Command Completion
907 * Detect bit in Controller SERR-INT register
908 */
909 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
910 serr_int &= ~SERR_INTR_RSVDZ_MASK;
911 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
912
913 ctrl->cmd_busy = 0;
914 wake_up_interruptible(&ctrl->queue);
915 }
916
917 if (!(intr_loc & ~CMD_INTR_PENDING))
918 goto out;
919
920 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
921 /* To find out which slot has interrupt pending */
922 if (!(intr_loc & SLOT_INTR_PENDING(hp_slot)))
923 continue;
924
925 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
926 dbg("%s: Slot %x with intr, slot register = %x\n",
927 __FUNCTION__, hp_slot, slot_reg);
928
929 if (slot_reg & MRL_CHANGE_DETECTED)
930 php_ctlr->switch_change_callback(
931 hp_slot, php_ctlr->callback_instance_id);
932
933 if (slot_reg & BUTTON_PRESS_DETECTED)
934 php_ctlr->attention_button_callback(
935 hp_slot, php_ctlr->callback_instance_id);
936
937 if (slot_reg & PRSNT_CHANGE_DETECTED)
938 php_ctlr->presence_change_callback(
939 hp_slot , php_ctlr->callback_instance_id);
940
941 if (slot_reg & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED))
942 php_ctlr->power_fault_callback(
943 hp_slot, php_ctlr->callback_instance_id);
944
945 /* Clear all slot events */
946 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
947 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
948 }
949 out:
950 if (!shpchp_poll_mode) {
951 /* Unmask Global Interrupt Mask */
952 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
953 serr_int &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK);
954 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
955 }
956
957 return IRQ_HANDLED;
958 }
959
960 static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value)
961 {
962 int retval = 0;
963 struct controller *ctrl = slot->ctrl;
964 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
965 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
966 u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1);
967 u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2);
968
969 DBG_ENTER_ROUTINE
970
971 if (pi == 2) {
972 if (slot_avail2 & SLOT_133MHZ_PCIX_533)
973 bus_speed = PCI_SPEED_133MHz_PCIX_533;
974 else if (slot_avail2 & SLOT_100MHZ_PCIX_533)
975 bus_speed = PCI_SPEED_100MHz_PCIX_533;
976 else if (slot_avail2 & SLOT_66MHZ_PCIX_533)
977 bus_speed = PCI_SPEED_66MHz_PCIX_533;
978 else if (slot_avail2 & SLOT_133MHZ_PCIX_266)
979 bus_speed = PCI_SPEED_133MHz_PCIX_266;
980 else if (slot_avail2 & SLOT_100MHZ_PCIX_266)
981 bus_speed = PCI_SPEED_100MHz_PCIX_266;
982 else if (slot_avail2 & SLOT_66MHZ_PCIX_266)
983 bus_speed = PCI_SPEED_66MHz_PCIX_266;
984 }
985
986 if (bus_speed == PCI_SPEED_UNKNOWN) {
987 if (slot_avail1 & SLOT_133MHZ_PCIX)
988 bus_speed = PCI_SPEED_133MHz_PCIX;
989 else if (slot_avail1 & SLOT_100MHZ_PCIX)
990 bus_speed = PCI_SPEED_100MHz_PCIX;
991 else if (slot_avail1 & SLOT_66MHZ_PCIX)
992 bus_speed = PCI_SPEED_66MHz_PCIX;
993 else if (slot_avail2 & SLOT_66MHZ)
994 bus_speed = PCI_SPEED_66MHz;
995 else if (slot_avail1 & SLOT_33MHZ)
996 bus_speed = PCI_SPEED_33MHz;
997 else
998 retval = -ENODEV;
999 }
1000
1001 *value = bus_speed;
1002 dbg("Max bus speed = %d\n", bus_speed);
1003 DBG_LEAVE_ROUTINE
1004 return retval;
1005 }
1006
1007 static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value)
1008 {
1009 int retval = 0;
1010 struct controller *ctrl = slot->ctrl;
1011 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
1012 u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG);
1013 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
1014 u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7);
1015
1016 DBG_ENTER_ROUTINE
1017
1018 if ((pi == 1) && (speed_mode > 4)) {
1019 *value = PCI_SPEED_UNKNOWN;
1020 return -ENODEV;
1021 }
1022
1023 switch (speed_mode) {
1024 case 0x0:
1025 *value = PCI_SPEED_33MHz;
1026 break;
1027 case 0x1:
1028 *value = PCI_SPEED_66MHz;
1029 break;
1030 case 0x2:
1031 *value = PCI_SPEED_66MHz_PCIX;
1032 break;
1033 case 0x3:
1034 *value = PCI_SPEED_100MHz_PCIX;
1035 break;
1036 case 0x4:
1037 *value = PCI_SPEED_133MHz_PCIX;
1038 break;
1039 case 0x5:
1040 *value = PCI_SPEED_66MHz_PCIX_ECC;
1041 break;
1042 case 0x6:
1043 *value = PCI_SPEED_100MHz_PCIX_ECC;
1044 break;
1045 case 0x7:
1046 *value = PCI_SPEED_133MHz_PCIX_ECC;
1047 break;
1048 case 0x8:
1049 *value = PCI_SPEED_66MHz_PCIX_266;
1050 break;
1051 case 0x9:
1052 *value = PCI_SPEED_100MHz_PCIX_266;
1053 break;
1054 case 0xa:
1055 *value = PCI_SPEED_133MHz_PCIX_266;
1056 break;
1057 case 0xb:
1058 *value = PCI_SPEED_66MHz_PCIX_533;
1059 break;
1060 case 0xc:
1061 *value = PCI_SPEED_100MHz_PCIX_533;
1062 break;
1063 case 0xd:
1064 *value = PCI_SPEED_133MHz_PCIX_533;
1065 break;
1066 default:
1067 *value = PCI_SPEED_UNKNOWN;
1068 retval = -ENODEV;
1069 break;
1070 }
1071
1072 dbg("Current bus speed = %d\n", bus_speed);
1073 DBG_LEAVE_ROUTINE
1074 return retval;
1075 }
1076
1077 static struct hpc_ops shpchp_hpc_ops = {
1078 .power_on_slot = hpc_power_on_slot,
1079 .slot_enable = hpc_slot_enable,
1080 .slot_disable = hpc_slot_disable,
1081 .set_bus_speed_mode = hpc_set_bus_speed_mode,
1082 .set_attention_status = hpc_set_attention_status,
1083 .get_power_status = hpc_get_power_status,
1084 .get_attention_status = hpc_get_attention_status,
1085 .get_latch_status = hpc_get_latch_status,
1086 .get_adapter_status = hpc_get_adapter_status,
1087
1088 .get_max_bus_speed = hpc_get_max_bus_speed,
1089 .get_cur_bus_speed = hpc_get_cur_bus_speed,
1090 .get_adapter_speed = hpc_get_adapter_speed,
1091 .get_mode1_ECC_cap = hpc_get_mode1_ECC_cap,
1092 .get_prog_int = hpc_get_prog_int,
1093
1094 .query_power_fault = hpc_query_power_fault,
1095 .green_led_on = hpc_set_green_led_on,
1096 .green_led_off = hpc_set_green_led_off,
1097 .green_led_blink = hpc_set_green_led_blink,
1098
1099 .release_ctlr = hpc_release_ctlr,
1100 };
1101
1102 int shpc_init(struct controller * ctrl, struct pci_dev * pdev)
1103 {
1104 struct php_ctlr_state_s *php_ctlr, *p;
1105 void *instance_id = ctrl;
1106 int rc, num_slots = 0;
1107 u8 hp_slot;
1108 static int first = 1;
1109 u32 shpc_base_offset;
1110 u32 tempdword, slot_reg, slot_config;
1111 u8 i;
1112
1113 DBG_ENTER_ROUTINE
1114
1115 ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */
1116
1117 spin_lock_init(&list_lock);
1118 php_ctlr = kzalloc(sizeof(*php_ctlr), GFP_KERNEL);
1119
1120 if (!php_ctlr) { /* allocate controller state data */
1121 err("%s: HPC controller memory allocation error!\n", __FUNCTION__);
1122 goto abort;
1123 }
1124
1125 php_ctlr->pci_dev = pdev; /* save pci_dev in context */
1126
1127 if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device ==
1128 PCI_DEVICE_ID_AMD_GOLAM_7450)) {
1129 /* amd shpc driver doesn't use Base Offset; assume 0 */
1130 ctrl->mmio_base = pci_resource_start(pdev, 0);
1131 ctrl->mmio_size = pci_resource_len(pdev, 0);
1132 } else {
1133 ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC);
1134 if (!ctrl->cap_offset) {
1135 err("%s : cap_offset == 0\n", __FUNCTION__);
1136 goto abort_free_ctlr;
1137 }
1138 dbg("%s: cap_offset = %x\n", __FUNCTION__, ctrl->cap_offset);
1139
1140 rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset);
1141 if (rc) {
1142 err("%s: cannot read base_offset\n", __FUNCTION__);
1143 goto abort_free_ctlr;
1144 }
1145
1146 rc = shpc_indirect_read(ctrl, 3, &tempdword);
1147 if (rc) {
1148 err("%s: cannot read slot config\n", __FUNCTION__);
1149 goto abort_free_ctlr;
1150 }
1151 num_slots = tempdword & SLOT_NUM;
1152 dbg("%s: num_slots (indirect) %x\n", __FUNCTION__, num_slots);
1153
1154 for (i = 0; i < 9 + num_slots; i++) {
1155 rc = shpc_indirect_read(ctrl, i, &tempdword);
1156 if (rc) {
1157 err("%s: cannot read creg (index = %d)\n",
1158 __FUNCTION__, i);
1159 goto abort_free_ctlr;
1160 }
1161 dbg("%s: offset %d: value %x\n", __FUNCTION__,i,
1162 tempdword);
1163 }
1164
1165 ctrl->mmio_base =
1166 pci_resource_start(pdev, 0) + shpc_base_offset;
1167 ctrl->mmio_size = 0x24 + 0x4 * num_slots;
1168 }
1169
1170 if (first) {
1171 spin_lock_init(&hpc_event_lock);
1172 first = 0;
1173 }
1174
1175 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, pdev->subsystem_vendor,
1176 pdev->subsystem_device);
1177
1178 if (pci_enable_device(pdev))
1179 goto abort_free_ctlr;
1180
1181 if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {
1182 err("%s: cannot reserve MMIO region\n", __FUNCTION__);
1183 goto abort_free_ctlr;
1184 }
1185
1186 php_ctlr->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);
1187 if (!php_ctlr->creg) {
1188 err("%s: cannot remap MMIO region %lx @ %lx\n", __FUNCTION__,
1189 ctrl->mmio_size, ctrl->mmio_base);
1190 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
1191 goto abort_free_ctlr;
1192 }
1193 dbg("%s: php_ctlr->creg %p\n", __FUNCTION__, php_ctlr->creg);
1194
1195 mutex_init(&ctrl->crit_sect);
1196 mutex_init(&ctrl->cmd_lock);
1197
1198 /* Setup wait queue */
1199 init_waitqueue_head(&ctrl->queue);
1200
1201 /* Find the IRQ */
1202 php_ctlr->irq = pdev->irq;
1203 php_ctlr->attention_button_callback = shpchp_handle_attention_button,
1204 php_ctlr->switch_change_callback = shpchp_handle_switch_change;
1205 php_ctlr->presence_change_callback = shpchp_handle_presence_change;
1206 php_ctlr->power_fault_callback = shpchp_handle_power_fault;
1207 php_ctlr->callback_instance_id = instance_id;
1208
1209 ctrl->hpc_ctlr_handle = php_ctlr;
1210 ctrl->hpc_ops = &shpchp_hpc_ops;
1211
1212 /* Return PCI Controller Info */
1213 slot_config = shpc_readl(ctrl, SLOT_CONFIG);
1214 php_ctlr->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8;
1215 php_ctlr->num_slots = slot_config & SLOT_NUM;
1216 dbg("%s: slot_device_offset %x\n", __FUNCTION__, php_ctlr->slot_device_offset);
1217 dbg("%s: num_slots %x\n", __FUNCTION__, php_ctlr->num_slots);
1218
1219 /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */
1220 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1221 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1222 tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
1223 COMMAND_INTR_MASK | ARBITER_SERR_MASK);
1224 tempdword &= ~SERR_INTR_RSVDZ_MASK;
1225 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1226 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1227 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1228
1229 /* Mask the MRL sensor SERR Mask of individual slot in
1230 * Slot SERR-INT Mask & clear all the existing event if any
1231 */
1232 for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) {
1233 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1234 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
1235 hp_slot, slot_reg);
1236 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1237 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
1238 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
1239 CON_PFAULT_SERR_MASK);
1240 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
1241 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1242 }
1243
1244 if (shpchp_poll_mode) {/* Install interrupt polling code */
1245 /* Install and start the interrupt polling timer */
1246 init_timer(&php_ctlr->int_poll_timer);
1247 start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */
1248 } else {
1249 /* Installs the interrupt handler */
1250 rc = pci_enable_msi(pdev);
1251 if (rc) {
1252 info("Can't get msi for the hotplug controller\n");
1253 info("Use INTx for the hotplug controller\n");
1254 } else
1255 php_ctlr->irq = pdev->irq;
1256
1257 rc = request_irq(php_ctlr->irq, shpc_isr, SA_SHIRQ, MY_NAME, (void *) ctrl);
1258 dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc);
1259 if (rc) {
1260 err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq);
1261 goto abort_free_ctlr;
1262 }
1263 }
1264 dbg("%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", __FUNCTION__,
1265 pdev->bus->number, PCI_SLOT(pdev->devfn),
1266 PCI_FUNC(pdev->devfn), pdev->irq);
1267 get_hp_hw_control_from_firmware(pdev);
1268
1269 /* Add this HPC instance into the HPC list */
1270 spin_lock(&list_lock);
1271 if (php_ctlr_list_head == 0) {
1272 php_ctlr_list_head = php_ctlr;
1273 p = php_ctlr_list_head;
1274 p->pnext = NULL;
1275 } else {
1276 p = php_ctlr_list_head;
1277
1278 while (p->pnext)
1279 p = p->pnext;
1280
1281 p->pnext = php_ctlr;
1282 }
1283 spin_unlock(&list_lock);
1284
1285 ctlr_seq_num++;
1286
1287 /*
1288 * If this is the first controller to be initialized,
1289 * initialize the shpchpd work queue
1290 */
1291 if (atomic_add_return(1, &shpchp_num_controllers) == 1) {
1292 shpchp_wq = create_singlethread_workqueue("shpchpd");
1293 if (!shpchp_wq)
1294 return -ENOMEM;
1295 }
1296
1297 /*
1298 * Unmask all event interrupts of all slots
1299 */
1300 for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) {
1301 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1302 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
1303 hp_slot, slot_reg);
1304 slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1305 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
1306 CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK);
1307 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1308 }
1309 if (!shpchp_poll_mode) {
1310 /* Unmask all general input interrupts and SERR */
1311 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1312 tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK |
1313 SERR_INTR_RSVDZ_MASK);
1314 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1315 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1316 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1317 }
1318
1319 DBG_LEAVE_ROUTINE
1320 return 0;
1321
1322 /* We end up here for the many possible ways to fail this API. */
1323 abort_free_ctlr:
1324 kfree(php_ctlr);
1325 abort:
1326 DBG_LEAVE_ROUTINE
1327 return -1;
1328 }
Support for the Chinese Samsung S3C2440 based development boards