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USB: serial: remove CONFIG_USB_DEBUG from sierra and option drivers
[linux-2.6/mini2440.git] / drivers / net / sh_eth.c
blob25e62cf58d3ac98e3cab012b1999f9b7a8711dfd
1 /*
2 * SuperH Ethernet device driver
3 *
4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
5 * Copyright (C) 2008 Renesas Solutions Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 */
22
23 #include <linux/version.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/etherdevice.h>
27 #include <linux/delay.h>
28 #include <linux/platform_device.h>
29 #include <linux/mdio-bitbang.h>
30 #include <linux/netdevice.h>
31 #include <linux/phy.h>
32 #include <linux/cache.h>
33 #include <linux/io.h>
34
35 #include "sh_eth.h"
36
37 /* CPU <-> EDMAC endian convert */
38 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
39 {
40 switch (mdp->edmac_endian) {
41 case EDMAC_LITTLE_ENDIAN:
42 return cpu_to_le32(x);
43 case EDMAC_BIG_ENDIAN:
44 return cpu_to_be32(x);
45 }
46 return x;
47 }
48
49 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
50 {
51 switch (mdp->edmac_endian) {
52 case EDMAC_LITTLE_ENDIAN:
53 return le32_to_cpu(x);
54 case EDMAC_BIG_ENDIAN:
55 return be32_to_cpu(x);
56 }
57 return x;
58 }
59
60 /*
61 * Program the hardware MAC address from dev->dev_addr.
62 */
63 static void update_mac_address(struct net_device *ndev)
64 {
65 u32 ioaddr = ndev->base_addr;
66
67 ctrl_outl((ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
68 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]),
69 ioaddr + MAHR);
70 ctrl_outl((ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]),
71 ioaddr + MALR);
72 }
73
74 /*
75 * Get MAC address from SuperH MAC address register
76 *
77 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
78 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
79 * When you want use this device, you must set MAC address in bootloader.
80 *
81 */
82 static void read_mac_address(struct net_device *ndev)
83 {
84 u32 ioaddr = ndev->base_addr;
85
86 ndev->dev_addr[0] = (ctrl_inl(ioaddr + MAHR) >> 24);
87 ndev->dev_addr[1] = (ctrl_inl(ioaddr + MAHR) >> 16) & 0xFF;
88 ndev->dev_addr[2] = (ctrl_inl(ioaddr + MAHR) >> 8) & 0xFF;
89 ndev->dev_addr[3] = (ctrl_inl(ioaddr + MAHR) & 0xFF);
90 ndev->dev_addr[4] = (ctrl_inl(ioaddr + MALR) >> 8) & 0xFF;
91 ndev->dev_addr[5] = (ctrl_inl(ioaddr + MALR) & 0xFF);
92 }
93
94 struct bb_info {
95 struct mdiobb_ctrl ctrl;
96 u32 addr;
97 u32 mmd_msk;/* MMD */
98 u32 mdo_msk;
99 u32 mdi_msk;
100 u32 mdc_msk;
101 };
102
103 /* PHY bit set */
104 static void bb_set(u32 addr, u32 msk)
105 {
106 ctrl_outl(ctrl_inl(addr) | msk, addr);
107 }
108
109 /* PHY bit clear */
110 static void bb_clr(u32 addr, u32 msk)
111 {
112 ctrl_outl((ctrl_inl(addr) & ~msk), addr);
113 }
114
115 /* PHY bit read */
116 static int bb_read(u32 addr, u32 msk)
117 {
118 return (ctrl_inl(addr) & msk) != 0;
119 }
120
121 /* Data I/O pin control */
122 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
123 {
124 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
125 if (bit)
126 bb_set(bitbang->addr, bitbang->mmd_msk);
127 else
128 bb_clr(bitbang->addr, bitbang->mmd_msk);
129 }
130
131 /* Set bit data*/
132 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
133 {
134 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
135
136 if (bit)
137 bb_set(bitbang->addr, bitbang->mdo_msk);
138 else
139 bb_clr(bitbang->addr, bitbang->mdo_msk);
140 }
141
142 /* Get bit data*/
143 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
144 {
145 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
146 return bb_read(bitbang->addr, bitbang->mdi_msk);
147 }
148
149 /* MDC pin control */
150 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
151 {
152 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
153
154 if (bit)
155 bb_set(bitbang->addr, bitbang->mdc_msk);
156 else
157 bb_clr(bitbang->addr, bitbang->mdc_msk);
158 }
159
160 /* mdio bus control struct */
161 static struct mdiobb_ops bb_ops = {
162 .owner = THIS_MODULE,
163 .set_mdc = sh_mdc_ctrl,
164 .set_mdio_dir = sh_mmd_ctrl,
165 .set_mdio_data = sh_set_mdio,
166 .get_mdio_data = sh_get_mdio,
167 };
168
169 /* Chip Reset */
170 static void sh_eth_reset(struct net_device *ndev)
171 {
172 u32 ioaddr = ndev->base_addr;
173
174 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
175 int cnt = 100;
176
177 ctrl_outl(EDSR_ENALL, ioaddr + EDSR);
178 ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR);
179 while (cnt > 0) {
180 if (!(ctrl_inl(ioaddr + EDMR) & 0x3))
181 break;
182 mdelay(1);
183 cnt--;
184 }
185 if (cnt < 0)
186 printk(KERN_ERR "Device reset fail\n");
187
188 /* Table Init */
189 ctrl_outl(0x0, ioaddr + TDLAR);
190 ctrl_outl(0x0, ioaddr + TDFAR);
191 ctrl_outl(0x0, ioaddr + TDFXR);
192 ctrl_outl(0x0, ioaddr + TDFFR);
193 ctrl_outl(0x0, ioaddr + RDLAR);
194 ctrl_outl(0x0, ioaddr + RDFAR);
195 ctrl_outl(0x0, ioaddr + RDFXR);
196 ctrl_outl(0x0, ioaddr + RDFFR);
197 #else
198 ctrl_outl(ctrl_inl(ioaddr + EDMR) | EDMR_SRST, ioaddr + EDMR);
199 mdelay(3);
200 ctrl_outl(ctrl_inl(ioaddr + EDMR) & ~EDMR_SRST, ioaddr + EDMR);
201 #endif
202 }
203
204 /* free skb and descriptor buffer */
205 static void sh_eth_ring_free(struct net_device *ndev)
206 {
207 struct sh_eth_private *mdp = netdev_priv(ndev);
208 int i;
209
210 /* Free Rx skb ringbuffer */
211 if (mdp->rx_skbuff) {
212 for (i = 0; i < RX_RING_SIZE; i++) {
213 if (mdp->rx_skbuff[i])
214 dev_kfree_skb(mdp->rx_skbuff[i]);
215 }
216 }
217 kfree(mdp->rx_skbuff);
218
219 /* Free Tx skb ringbuffer */
220 if (mdp->tx_skbuff) {
221 for (i = 0; i < TX_RING_SIZE; i++) {
222 if (mdp->tx_skbuff[i])
223 dev_kfree_skb(mdp->tx_skbuff[i]);
224 }
225 }
226 kfree(mdp->tx_skbuff);
227 }
228
229 /* format skb and descriptor buffer */
230 static void sh_eth_ring_format(struct net_device *ndev)
231 {
232 u32 ioaddr = ndev->base_addr, reserve = 0;
233 struct sh_eth_private *mdp = netdev_priv(ndev);
234 int i;
235 struct sk_buff *skb;
236 struct sh_eth_rxdesc *rxdesc = NULL;
237 struct sh_eth_txdesc *txdesc = NULL;
238 int rx_ringsize = sizeof(*rxdesc) * RX_RING_SIZE;
239 int tx_ringsize = sizeof(*txdesc) * TX_RING_SIZE;
240
241 mdp->cur_rx = mdp->cur_tx = 0;
242 mdp->dirty_rx = mdp->dirty_tx = 0;
243
244 memset(mdp->rx_ring, 0, rx_ringsize);
245
246 /* build Rx ring buffer */
247 for (i = 0; i < RX_RING_SIZE; i++) {
248 /* skb */
249 mdp->rx_skbuff[i] = NULL;
250 skb = dev_alloc_skb(mdp->rx_buf_sz);
251 mdp->rx_skbuff[i] = skb;
252 if (skb == NULL)
253 break;
254 skb->dev = ndev; /* Mark as being used by this device. */
255 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
256 reserve = SH7763_SKB_ALIGN
257 - ((uint32_t)skb->data & (SH7763_SKB_ALIGN-1));
258 if (reserve)
259 skb_reserve(skb, reserve);
260 #else
261 skb_reserve(skb, RX_OFFSET);
262 #endif
263 /* RX descriptor */
264 rxdesc = &mdp->rx_ring[i];
265 rxdesc->addr = (u32)skb->data & ~0x3UL;
266 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
267
268 /* The size of the buffer is 16 byte boundary. */
269 rxdesc->buffer_length = (mdp->rx_buf_sz + 16) & ~0x0F;
270 /* Rx descriptor address set */
271 if (i == 0) {
272 ctrl_outl((u32)rxdesc, ioaddr + RDLAR);
273 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
274 ctrl_outl((u32)rxdesc, ioaddr + RDFAR);
275 #endif
276 }
277 }
278
279 /* Rx descriptor address set */
280 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
281 ctrl_outl((u32)rxdesc, ioaddr + RDFXR);
282 ctrl_outl(0x1, ioaddr + RDFFR);
283 #endif
284
285 mdp->dirty_rx = (u32) (i - RX_RING_SIZE);
286
287 /* Mark the last entry as wrapping the ring. */
288 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
289
290 memset(mdp->tx_ring, 0, tx_ringsize);
291
292 /* build Tx ring buffer */
293 for (i = 0; i < TX_RING_SIZE; i++) {
294 mdp->tx_skbuff[i] = NULL;
295 txdesc = &mdp->tx_ring[i];
296 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
297 txdesc->buffer_length = 0;
298 if (i == 0) {
299 /* Tx descriptor address set */
300 ctrl_outl((u32)txdesc, ioaddr + TDLAR);
301 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
302 ctrl_outl((u32)txdesc, ioaddr + TDFAR);
303 #endif
304 }
305 }
306
307 /* Tx descriptor address set */
308 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
309 ctrl_outl((u32)txdesc, ioaddr + TDFXR);
310 ctrl_outl(0x1, ioaddr + TDFFR);
311 #endif
312
313 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
314 }
315
316 /* Get skb and descriptor buffer */
317 static int sh_eth_ring_init(struct net_device *ndev)
318 {
319 struct sh_eth_private *mdp = netdev_priv(ndev);
320 int rx_ringsize, tx_ringsize, ret = 0;
321
322 /*
323 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
324 * card needs room to do 8 byte alignment, +2 so we can reserve
325 * the first 2 bytes, and +16 gets room for the status word from the
326 * card.
327 */
328 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
329 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
330
331 /* Allocate RX and TX skb rings */
332 mdp->rx_skbuff = kmalloc(sizeof(*mdp->rx_skbuff) * RX_RING_SIZE,
333 GFP_KERNEL);
334 if (!mdp->rx_skbuff) {
335 printk(KERN_ERR "%s: Cannot allocate Rx skb\n", ndev->name);
336 ret = -ENOMEM;
337 return ret;
338 }
339
340 mdp->tx_skbuff = kmalloc(sizeof(*mdp->tx_skbuff) * TX_RING_SIZE,
341 GFP_KERNEL);
342 if (!mdp->tx_skbuff) {
343 printk(KERN_ERR "%s: Cannot allocate Tx skb\n", ndev->name);
344 ret = -ENOMEM;
345 goto skb_ring_free;
346 }
347
348 /* Allocate all Rx descriptors. */
349 rx_ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
350 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
351 GFP_KERNEL);
352
353 if (!mdp->rx_ring) {
354 printk(KERN_ERR "%s: Cannot allocate Rx Ring (size %d bytes)\n",
355 ndev->name, rx_ringsize);
356 ret = -ENOMEM;
357 goto desc_ring_free;
358 }
359
360 mdp->dirty_rx = 0;
361
362 /* Allocate all Tx descriptors. */
363 tx_ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
364 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
365 GFP_KERNEL);
366 if (!mdp->tx_ring) {
367 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
368 ndev->name, tx_ringsize);
369 ret = -ENOMEM;
370 goto desc_ring_free;
371 }
372 return ret;
373
374 desc_ring_free:
375 /* free DMA buffer */
376 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
377
378 skb_ring_free:
379 /* Free Rx and Tx skb ring buffer */
380 sh_eth_ring_free(ndev);
381
382 return ret;
383 }
384
385 static int sh_eth_dev_init(struct net_device *ndev)
386 {
387 int ret = 0;
388 struct sh_eth_private *mdp = netdev_priv(ndev);
389 u32 ioaddr = ndev->base_addr;
390 u_int32_t rx_int_var, tx_int_var;
391 u32 val;
392
393 /* Soft Reset */
394 sh_eth_reset(ndev);
395
396 /* Descriptor format */
397 sh_eth_ring_format(ndev);
398 ctrl_outl(RPADIR_INIT, ioaddr + RPADIR);
399
400 /* all sh_eth int mask */
401 ctrl_outl(0, ioaddr + EESIPR);
402
403 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
404 ctrl_outl(EDMR_EL, ioaddr + EDMR);
405 #else
406 ctrl_outl(0, ioaddr + EDMR); /* Endian change */
407 #endif
408
409 /* FIFO size set */
410 ctrl_outl((FIFO_SIZE_T | FIFO_SIZE_R), ioaddr + FDR);
411 ctrl_outl(0, ioaddr + TFTR);
412
413 /* Frame recv control */
414 ctrl_outl(0, ioaddr + RMCR);
415
416 rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5;
417 tx_int_var = mdp->tx_int_var = DESC_I_TINT2;
418 ctrl_outl(rx_int_var | tx_int_var, ioaddr + TRSCER);
419
420 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
421 /* Burst sycle set */
422 ctrl_outl(0x800, ioaddr + BCULR);
423 #endif
424
425 ctrl_outl((FIFO_F_D_RFF | FIFO_F_D_RFD), ioaddr + FCFTR);
426
427 #if !defined(CONFIG_CPU_SUBTYPE_SH7763)
428 ctrl_outl(0, ioaddr + TRIMD);
429 #endif
430
431 /* Recv frame limit set register */
432 ctrl_outl(RFLR_VALUE, ioaddr + RFLR);
433
434 ctrl_outl(ctrl_inl(ioaddr + EESR), ioaddr + EESR);
435 ctrl_outl((DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff), ioaddr + EESIPR);
436
437 /* PAUSE Prohibition */
438 val = (ctrl_inl(ioaddr + ECMR) & ECMR_DM) |
439 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
440
441 ctrl_outl(val, ioaddr + ECMR);
442
443 /* E-MAC Status Register clear */
444 ctrl_outl(ECSR_INIT, ioaddr + ECSR);
445
446 /* E-MAC Interrupt Enable register */
447 ctrl_outl(ECSIPR_INIT, ioaddr + ECSIPR);
448
449 /* Set MAC address */
450 update_mac_address(ndev);
451
452 /* mask reset */
453 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7763)
454 ctrl_outl(APR_AP, ioaddr + APR);
455 ctrl_outl(MPR_MP, ioaddr + MPR);
456 ctrl_outl(TPAUSER_UNLIMITED, ioaddr + TPAUSER);
457 #endif
458 #if defined(CONFIG_CPU_SUBTYPE_SH7710)
459 ctrl_outl(BCFR_UNLIMITED, ioaddr + BCFR);
460 #endif
461
462 /* Setting the Rx mode will start the Rx process. */
463 ctrl_outl(EDRRR_R, ioaddr + EDRRR);
464
465 netif_start_queue(ndev);
466
467 return ret;
468 }
469
470 /* free Tx skb function */
471 static int sh_eth_txfree(struct net_device *ndev)
472 {
473 struct sh_eth_private *mdp = netdev_priv(ndev);
474 struct sh_eth_txdesc *txdesc;
475 int freeNum = 0;
476 int entry = 0;
477
478 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
479 entry = mdp->dirty_tx % TX_RING_SIZE;
480 txdesc = &mdp->tx_ring[entry];
481 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
482 break;
483 /* Free the original skb. */
484 if (mdp->tx_skbuff[entry]) {
485 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
486 mdp->tx_skbuff[entry] = NULL;
487 freeNum++;
488 }
489 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
490 if (entry >= TX_RING_SIZE - 1)
491 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
492
493 mdp->stats.tx_packets++;
494 mdp->stats.tx_bytes += txdesc->buffer_length;
495 }
496 return freeNum;
497 }
498
499 /* Packet receive function */
500 static int sh_eth_rx(struct net_device *ndev)
501 {
502 struct sh_eth_private *mdp = netdev_priv(ndev);
503 struct sh_eth_rxdesc *rxdesc;
504
505 int entry = mdp->cur_rx % RX_RING_SIZE;
506 int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx;
507 struct sk_buff *skb;
508 u16 pkt_len = 0;
509 u32 desc_status, reserve = 0;
510
511 rxdesc = &mdp->rx_ring[entry];
512 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
513 desc_status = edmac_to_cpu(mdp, rxdesc->status);
514 pkt_len = rxdesc->frame_length;
515
516 if (--boguscnt < 0)
517 break;
518
519 if (!(desc_status & RDFEND))
520 mdp->stats.rx_length_errors++;
521
522 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
523 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
524 mdp->stats.rx_errors++;
525 if (desc_status & RD_RFS1)
526 mdp->stats.rx_crc_errors++;
527 if (desc_status & RD_RFS2)
528 mdp->stats.rx_frame_errors++;
529 if (desc_status & RD_RFS3)
530 mdp->stats.rx_length_errors++;
531 if (desc_status & RD_RFS4)
532 mdp->stats.rx_length_errors++;
533 if (desc_status & RD_RFS6)
534 mdp->stats.rx_missed_errors++;
535 if (desc_status & RD_RFS10)
536 mdp->stats.rx_over_errors++;
537 } else {
538 swaps((char *)(rxdesc->addr & ~0x3), pkt_len + 2);
539 skb = mdp->rx_skbuff[entry];
540 mdp->rx_skbuff[entry] = NULL;
541 skb_put(skb, pkt_len);
542 skb->protocol = eth_type_trans(skb, ndev);
543 netif_rx(skb);
544 ndev->last_rx = jiffies;
545 mdp->stats.rx_packets++;
546 mdp->stats.rx_bytes += pkt_len;
547 }
548 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
549 entry = (++mdp->cur_rx) % RX_RING_SIZE;
550 }
551
552 /* Refill the Rx ring buffers. */
553 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
554 entry = mdp->dirty_rx % RX_RING_SIZE;
555 rxdesc = &mdp->rx_ring[entry];
556 /* The size of the buffer is 16 byte boundary. */
557 rxdesc->buffer_length = (mdp->rx_buf_sz + 16) & ~0x0F;
558
559 if (mdp->rx_skbuff[entry] == NULL) {
560 skb = dev_alloc_skb(mdp->rx_buf_sz);
561 mdp->rx_skbuff[entry] = skb;
562 if (skb == NULL)
563 break; /* Better luck next round. */
564 skb->dev = ndev;
565 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
566 reserve = SH7763_SKB_ALIGN
567 - ((uint32_t)skb->data & (SH7763_SKB_ALIGN-1));
568 if (reserve)
569 skb_reserve(skb, reserve);
570 #else
571 skb_reserve(skb, RX_OFFSET);
572 #endif
573 skb->ip_summed = CHECKSUM_NONE;
574 rxdesc->addr = (u32)skb->data & ~0x3UL;
575 }
576 if (entry >= RX_RING_SIZE - 1)
577 rxdesc->status |=
578 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
579 else
580 rxdesc->status |=
581 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
582 }
583
584 /* Restart Rx engine if stopped. */
585 /* If we don't need to check status, don't. -KDU */
586 if (!(ctrl_inl(ndev->base_addr + EDRRR) & EDRRR_R))
587 ctrl_outl(EDRRR_R, ndev->base_addr + EDRRR);
588
589 return 0;
590 }
591
592 /* error control function */
593 static void sh_eth_error(struct net_device *ndev, int intr_status)
594 {
595 struct sh_eth_private *mdp = netdev_priv(ndev);
596 u32 ioaddr = ndev->base_addr;
597 u32 felic_stat;
598
599 if (intr_status & EESR_ECI) {
600 felic_stat = ctrl_inl(ioaddr + ECSR);
601 ctrl_outl(felic_stat, ioaddr + ECSR); /* clear int */
602 if (felic_stat & ECSR_ICD)
603 mdp->stats.tx_carrier_errors++;
604 if (felic_stat & ECSR_LCHNG) {
605 /* Link Changed */
606 u32 link_stat = (ctrl_inl(ioaddr + PSR));
607 if (!(link_stat & PHY_ST_LINK)) {
608 /* Link Down : disable tx and rx */
609 ctrl_outl(ctrl_inl(ioaddr + ECMR) &
610 ~(ECMR_RE | ECMR_TE), ioaddr + ECMR);
611 } else {
612 /* Link Up */
613 ctrl_outl(ctrl_inl(ioaddr + EESIPR) &
614 ~DMAC_M_ECI, ioaddr + EESIPR);
615 /*clear int */
616 ctrl_outl(ctrl_inl(ioaddr + ECSR),
617 ioaddr + ECSR);
618 ctrl_outl(ctrl_inl(ioaddr + EESIPR) |
619 DMAC_M_ECI, ioaddr + EESIPR);
620 /* enable tx and rx */
621 ctrl_outl(ctrl_inl(ioaddr + ECMR) |
622 (ECMR_RE | ECMR_TE), ioaddr + ECMR);
623 }
624 }
625 }
626
627 if (intr_status & EESR_TWB) {
628 /* Write buck end. unused write back interrupt */
629 if (intr_status & EESR_TABT) /* Transmit Abort int */
630 mdp->stats.tx_aborted_errors++;
631 }
632
633 if (intr_status & EESR_RABT) {
634 /* Receive Abort int */
635 if (intr_status & EESR_RFRMER) {
636 /* Receive Frame Overflow int */
637 mdp->stats.rx_frame_errors++;
638 printk(KERN_ERR "Receive Frame Overflow\n");
639 }
640 }
641 #if !defined(CONFIG_CPU_SUBTYPE_SH7763)
642 if (intr_status & EESR_ADE) {
643 if (intr_status & EESR_TDE) {
644 if (intr_status & EESR_TFE)
645 mdp->stats.tx_fifo_errors++;
646 }
647 }
648 #endif
649
650 if (intr_status & EESR_RDE) {
651 /* Receive Descriptor Empty int */
652 mdp->stats.rx_over_errors++;
653
654 if (ctrl_inl(ioaddr + EDRRR) ^ EDRRR_R)
655 ctrl_outl(EDRRR_R, ioaddr + EDRRR);
656 printk(KERN_ERR "Receive Descriptor Empty\n");
657 }
658 if (intr_status & EESR_RFE) {
659 /* Receive FIFO Overflow int */
660 mdp->stats.rx_fifo_errors++;
661 printk(KERN_ERR "Receive FIFO Overflow\n");
662 }
663 if (intr_status & (EESR_TWB | EESR_TABT |
664 #if !defined(CONFIG_CPU_SUBTYPE_SH7763)
665 EESR_ADE |
666 #endif
667 EESR_TDE | EESR_TFE)) {
668 /* Tx error */
669 u32 edtrr = ctrl_inl(ndev->base_addr + EDTRR);
670 /* dmesg */
671 printk(KERN_ERR "%s:TX error. status=%8.8x cur_tx=%8.8x ",
672 ndev->name, intr_status, mdp->cur_tx);
673 printk(KERN_ERR "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
674 mdp->dirty_tx, (u32) ndev->state, edtrr);
675 /* dirty buffer free */
676 sh_eth_txfree(ndev);
677
678 /* SH7712 BUG */
679 if (edtrr ^ EDTRR_TRNS) {
680 /* tx dma start */
681 ctrl_outl(EDTRR_TRNS, ndev->base_addr + EDTRR);
682 }
683 /* wakeup */
684 netif_wake_queue(ndev);
685 }
686 }
687
688 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
689 {
690 struct net_device *ndev = netdev;
691 struct sh_eth_private *mdp = netdev_priv(ndev);
692 u32 ioaddr, boguscnt = RX_RING_SIZE;
693 u32 intr_status = 0;
694
695 ioaddr = ndev->base_addr;
696 spin_lock(&mdp->lock);
697
698 /* Get interrpt stat */
699 intr_status = ctrl_inl(ioaddr + EESR);
700 /* Clear interrupt */
701 ctrl_outl(intr_status, ioaddr + EESR);
702
703 if (intr_status & (EESR_FRC | /* Frame recv*/
704 EESR_RMAF | /* Multi cast address recv*/
705 EESR_RRF | /* Bit frame recv */
706 EESR_RTLF | /* Long frame recv*/
707 EESR_RTSF | /* short frame recv */
708 EESR_PRE | /* PHY-LSI recv error */
709 EESR_CERF)){ /* recv frame CRC error */
710 sh_eth_rx(ndev);
711 }
712
713 /* Tx Check */
714 if (intr_status & TX_CHECK) {
715 sh_eth_txfree(ndev);
716 netif_wake_queue(ndev);
717 }
718
719 if (intr_status & EESR_ERR_CHECK)
720 sh_eth_error(ndev, intr_status);
721
722 if (--boguscnt < 0) {
723 printk(KERN_WARNING
724 "%s: Too much work at interrupt, status=0x%4.4x.\n",
725 ndev->name, intr_status);
726 }
727
728 spin_unlock(&mdp->lock);
729
730 return IRQ_HANDLED;
731 }
732
733 static void sh_eth_timer(unsigned long data)
734 {
735 struct net_device *ndev = (struct net_device *)data;
736 struct sh_eth_private *mdp = netdev_priv(ndev);
737
738 mod_timer(&mdp->timer, jiffies + (10 * HZ));
739 }
740
741 /* PHY state control function */
742 static void sh_eth_adjust_link(struct net_device *ndev)
743 {
744 struct sh_eth_private *mdp = netdev_priv(ndev);
745 struct phy_device *phydev = mdp->phydev;
746 u32 ioaddr = ndev->base_addr;
747 int new_state = 0;
748
749 if (phydev->link != PHY_DOWN) {
750 if (phydev->duplex != mdp->duplex) {
751 new_state = 1;
752 mdp->duplex = phydev->duplex;
753 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
754 if (mdp->duplex) { /* FULL */
755 ctrl_outl(ctrl_inl(ioaddr + ECMR) | ECMR_DM,
756 ioaddr + ECMR);
757 } else { /* Half */
758 ctrl_outl(ctrl_inl(ioaddr + ECMR) & ~ECMR_DM,
759 ioaddr + ECMR);
760 }
761 #endif
762 }
763
764 if (phydev->speed != mdp->speed) {
765 new_state = 1;
766 mdp->speed = phydev->speed;
767 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
768 switch (mdp->speed) {
769 case 10: /* 10BASE */
770 ctrl_outl(GECMR_10, ioaddr + GECMR); break;
771 case 100:/* 100BASE */
772 ctrl_outl(GECMR_100, ioaddr + GECMR); break;
773 case 1000: /* 1000BASE */
774 ctrl_outl(GECMR_1000, ioaddr + GECMR); break;
775 default:
776 break;
777 }
778 #endif
779 }
780 if (mdp->link == PHY_DOWN) {
781 ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_TXF)
782 | ECMR_DM, ioaddr + ECMR);
783 new_state = 1;
784 mdp->link = phydev->link;
785 }
786 } else if (mdp->link) {
787 new_state = 1;
788 mdp->link = PHY_DOWN;
789 mdp->speed = 0;
790 mdp->duplex = -1;
791 }
792
793 if (new_state)
794 phy_print_status(phydev);
795 }
796
797 /* PHY init function */
798 static int sh_eth_phy_init(struct net_device *ndev)
799 {
800 struct sh_eth_private *mdp = netdev_priv(ndev);
801 char phy_id[BUS_ID_SIZE];
802 struct phy_device *phydev = NULL;
803
804 snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT,
805 mdp->mii_bus->id , mdp->phy_id);
806
807 mdp->link = PHY_DOWN;
808 mdp->speed = 0;
809 mdp->duplex = -1;
810
811 /* Try connect to PHY */
812 phydev = phy_connect(ndev, phy_id, &sh_eth_adjust_link,
813 0, PHY_INTERFACE_MODE_MII);
814 if (IS_ERR(phydev)) {
815 dev_err(&ndev->dev, "phy_connect failed\n");
816 return PTR_ERR(phydev);
817 }
818 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
819 phydev->addr, phydev->drv->name);
820
821 mdp->phydev = phydev;
822
823 return 0;
824 }
825
826 /* PHY control start function */
827 static int sh_eth_phy_start(struct net_device *ndev)
828 {
829 struct sh_eth_private *mdp = netdev_priv(ndev);
830 int ret;
831
832 ret = sh_eth_phy_init(ndev);
833 if (ret)
834 return ret;
835
836 /* reset phy - this also wakes it from PDOWN */
837 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
838 phy_start(mdp->phydev);
839
840 return 0;
841 }
842
843 /* network device open function */
844 static int sh_eth_open(struct net_device *ndev)
845 {
846 int ret = 0;
847 struct sh_eth_private *mdp = netdev_priv(ndev);
848
849 ret = request_irq(ndev->irq, &sh_eth_interrupt, 0, ndev->name, ndev);
850 if (ret) {
851 printk(KERN_ERR "Can not assign IRQ number to %s\n", CARDNAME);
852 return ret;
853 }
854
855 /* Descriptor set */
856 ret = sh_eth_ring_init(ndev);
857 if (ret)
858 goto out_free_irq;
859
860 /* device init */
861 ret = sh_eth_dev_init(ndev);
862 if (ret)
863 goto out_free_irq;
864
865 /* PHY control start*/
866 ret = sh_eth_phy_start(ndev);
867 if (ret)
868 goto out_free_irq;
869
870 /* Set the timer to check for link beat. */
871 init_timer(&mdp->timer);
872 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
873 setup_timer(&mdp->timer, sh_eth_timer, (unsigned long)ndev);
874
875 return ret;
876
877 out_free_irq:
878 free_irq(ndev->irq, ndev);
879 return ret;
880 }
881
882 /* Timeout function */
883 static void sh_eth_tx_timeout(struct net_device *ndev)
884 {
885 struct sh_eth_private *mdp = netdev_priv(ndev);
886 u32 ioaddr = ndev->base_addr;
887 struct sh_eth_rxdesc *rxdesc;
888 int i;
889
890 netif_stop_queue(ndev);
891
892 /* worning message out. */
893 printk(KERN_WARNING "%s: transmit timed out, status %8.8x,"
894 " resetting...\n", ndev->name, (int)ctrl_inl(ioaddr + EESR));
895
896 /* tx_errors count up */
897 mdp->stats.tx_errors++;
898
899 /* timer off */
900 del_timer_sync(&mdp->timer);
901
902 /* Free all the skbuffs in the Rx queue. */
903 for (i = 0; i < RX_RING_SIZE; i++) {
904 rxdesc = &mdp->rx_ring[i];
905 rxdesc->status = 0;
906 rxdesc->addr = 0xBADF00D0;
907 if (mdp->rx_skbuff[i])
908 dev_kfree_skb(mdp->rx_skbuff[i]);
909 mdp->rx_skbuff[i] = NULL;
910 }
911 for (i = 0; i < TX_RING_SIZE; i++) {
912 if (mdp->tx_skbuff[i])
913 dev_kfree_skb(mdp->tx_skbuff[i]);
914 mdp->tx_skbuff[i] = NULL;
915 }
916
917 /* device init */
918 sh_eth_dev_init(ndev);
919
920 /* timer on */
921 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
922 add_timer(&mdp->timer);
923 }
924
925 /* Packet transmit function */
926 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
927 {
928 struct sh_eth_private *mdp = netdev_priv(ndev);
929 struct sh_eth_txdesc *txdesc;
930 u32 entry;
931 int flags;
932
933 spin_lock_irqsave(&mdp->lock, flags);
934 if ((mdp->cur_tx - mdp->dirty_tx) >= (TX_RING_SIZE - 4)) {
935 if (!sh_eth_txfree(ndev)) {
936 netif_stop_queue(ndev);
937 spin_unlock_irqrestore(&mdp->lock, flags);
938 return 1;
939 }
940 }
941 spin_unlock_irqrestore(&mdp->lock, flags);
942
943 entry = mdp->cur_tx % TX_RING_SIZE;
944 mdp->tx_skbuff[entry] = skb;
945 txdesc = &mdp->tx_ring[entry];
946 txdesc->addr = (u32)(skb->data);
947 /* soft swap. */
948 swaps((char *)(txdesc->addr & ~0x3), skb->len + 2);
949 /* write back */
950 __flush_purge_region(skb->data, skb->len);
951 if (skb->len < ETHERSMALL)
952 txdesc->buffer_length = ETHERSMALL;
953 else
954 txdesc->buffer_length = skb->len;
955
956 if (entry >= TX_RING_SIZE - 1)
957 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
958 else
959 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
960
961 mdp->cur_tx++;
962
963 if (!(ctrl_inl(ndev->base_addr + EDTRR) & EDTRR_TRNS))
964 ctrl_outl(EDTRR_TRNS, ndev->base_addr + EDTRR);
965
966 ndev->trans_start = jiffies;
967
968 return 0;
969 }
970
971 /* device close function */
972 static int sh_eth_close(struct net_device *ndev)
973 {
974 struct sh_eth_private *mdp = netdev_priv(ndev);
975 u32 ioaddr = ndev->base_addr;
976 int ringsize;
977
978 netif_stop_queue(ndev);
979
980 /* Disable interrupts by clearing the interrupt mask. */
981 ctrl_outl(0x0000, ioaddr + EESIPR);
982
983 /* Stop the chip's Tx and Rx processes. */
984 ctrl_outl(0, ioaddr + EDTRR);
985 ctrl_outl(0, ioaddr + EDRRR);
986
987 /* PHY Disconnect */
988 if (mdp->phydev) {
989 phy_stop(mdp->phydev);
990 phy_disconnect(mdp->phydev);
991 }
992
993 free_irq(ndev->irq, ndev);
994
995 del_timer_sync(&mdp->timer);
996
997 /* Free all the skbuffs in the Rx queue. */
998 sh_eth_ring_free(ndev);
999
1000 /* free DMA buffer */
1001 ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
1002 dma_free_coherent(NULL, ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1003
1004 /* free DMA buffer */
1005 ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
1006 dma_free_coherent(NULL, ringsize, mdp->tx_ring, mdp->tx_desc_dma);
1007
1008 return 0;
1009 }
1010
1011 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
1012 {
1013 struct sh_eth_private *mdp = netdev_priv(ndev);
1014 u32 ioaddr = ndev->base_addr;
1015
1016 mdp->stats.tx_dropped += ctrl_inl(ioaddr + TROCR);
1017 ctrl_outl(0, ioaddr + TROCR); /* (write clear) */
1018 mdp->stats.collisions += ctrl_inl(ioaddr + CDCR);
1019 ctrl_outl(0, ioaddr + CDCR); /* (write clear) */
1020 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + LCCR);
1021 ctrl_outl(0, ioaddr + LCCR); /* (write clear) */
1022 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
1023 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CERCR);/* CERCR */
1024 ctrl_outl(0, ioaddr + CERCR); /* (write clear) */
1025 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CEECR);/* CEECR */
1026 ctrl_outl(0, ioaddr + CEECR); /* (write clear) */
1027 #else
1028 mdp->stats.tx_carrier_errors += ctrl_inl(ioaddr + CNDCR);
1029 ctrl_outl(0, ioaddr + CNDCR); /* (write clear) */
1030 #endif
1031 return &mdp->stats;
1032 }
1033
1034 /* ioctl to device funciotn*/
1035 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
1036 int cmd)
1037 {
1038 struct sh_eth_private *mdp = netdev_priv(ndev);
1039 struct phy_device *phydev = mdp->phydev;
1040
1041 if (!netif_running(ndev))
1042 return -EINVAL;
1043
1044 if (!phydev)
1045 return -ENODEV;
1046
1047 return phy_mii_ioctl(phydev, if_mii(rq), cmd);
1048 }
1049
1050
1051 /* Multicast reception directions set */
1052 static void sh_eth_set_multicast_list(struct net_device *ndev)
1053 {
1054 u32 ioaddr = ndev->base_addr;
1055
1056 if (ndev->flags & IFF_PROMISC) {
1057 /* Set promiscuous. */
1058 ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_MCT) | ECMR_PRM,
1059 ioaddr + ECMR);
1060 } else {
1061 /* Normal, unicast/broadcast-only mode. */
1062 ctrl_outl((ctrl_inl(ioaddr + ECMR) & ~ECMR_PRM) | ECMR_MCT,
1063 ioaddr + ECMR);
1064 }
1065 }
1066
1067 /* SuperH's TSU register init function */
1068 static void sh_eth_tsu_init(u32 ioaddr)
1069 {
1070 ctrl_outl(0, ioaddr + TSU_FWEN0); /* Disable forward(0->1) */
1071 ctrl_outl(0, ioaddr + TSU_FWEN1); /* Disable forward(1->0) */
1072 ctrl_outl(0, ioaddr + TSU_FCM); /* forward fifo 3k-3k */
1073 ctrl_outl(0xc, ioaddr + TSU_BSYSL0);
1074 ctrl_outl(0xc, ioaddr + TSU_BSYSL1);
1075 ctrl_outl(0, ioaddr + TSU_PRISL0);
1076 ctrl_outl(0, ioaddr + TSU_PRISL1);
1077 ctrl_outl(0, ioaddr + TSU_FWSL0);
1078 ctrl_outl(0, ioaddr + TSU_FWSL1);
1079 ctrl_outl(TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, ioaddr + TSU_FWSLC);
1080 #if defined(CONFIG_CPU_SUBTYPE_SH7763)
1081 ctrl_outl(0, ioaddr + TSU_QTAG0); /* Disable QTAG(0->1) */
1082 ctrl_outl(0, ioaddr + TSU_QTAG1); /* Disable QTAG(1->0) */
1083 #else
1084 ctrl_outl(0, ioaddr + TSU_QTAGM0); /* Disable QTAG(0->1) */
1085 ctrl_outl(0, ioaddr + TSU_QTAGM1); /* Disable QTAG(1->0) */
1086 #endif
1087 ctrl_outl(0, ioaddr + TSU_FWSR); /* all interrupt status clear */
1088 ctrl_outl(0, ioaddr + TSU_FWINMK); /* Disable all interrupt */
1089 ctrl_outl(0, ioaddr + TSU_TEN); /* Disable all CAM entry */
1090 ctrl_outl(0, ioaddr + TSU_POST1); /* Disable CAM entry [ 0- 7] */
1091 ctrl_outl(0, ioaddr + TSU_POST2); /* Disable CAM entry [ 8-15] */
1092 ctrl_outl(0, ioaddr + TSU_POST3); /* Disable CAM entry [16-23] */
1093 ctrl_outl(0, ioaddr + TSU_POST4); /* Disable CAM entry [24-31] */
1094 }
1095
1096 /* MDIO bus release function */
1097 static int sh_mdio_release(struct net_device *ndev)
1098 {
1099 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
1100
1101 /* unregister mdio bus */
1102 mdiobus_unregister(bus);
1103
1104 /* remove mdio bus info from net_device */
1105 dev_set_drvdata(&ndev->dev, NULL);
1106
1107 /* free bitbang info */
1108 free_mdio_bitbang(bus);
1109
1110 return 0;
1111 }
1112
1113 /* MDIO bus init function */
1114 static int sh_mdio_init(struct net_device *ndev, int id)
1115 {
1116 int ret, i;
1117 struct bb_info *bitbang;
1118 struct sh_eth_private *mdp = netdev_priv(ndev);
1119
1120 /* create bit control struct for PHY */
1121 bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
1122 if (!bitbang) {
1123 ret = -ENOMEM;
1124 goto out;
1125 }
1126
1127 /* bitbang init */
1128 bitbang->addr = ndev->base_addr + PIR;
1129 bitbang->mdi_msk = 0x08;
1130 bitbang->mdo_msk = 0x04;
1131 bitbang->mmd_msk = 0x02;/* MMD */
1132 bitbang->mdc_msk = 0x01;
1133 bitbang->ctrl.ops = &bb_ops;
1134
1135 /* MII contorller setting */
1136 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
1137 if (!mdp->mii_bus) {
1138 ret = -ENOMEM;
1139 goto out_free_bitbang;
1140 }
1141
1142 /* Hook up MII support for ethtool */
1143 mdp->mii_bus->name = "sh_mii";
1144 mdp->mii_bus->dev = &ndev->dev;
1145 mdp->mii_bus->id[0] = id;
1146
1147 /* PHY IRQ */
1148 mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1149 if (!mdp->mii_bus->irq) {
1150 ret = -ENOMEM;
1151 goto out_free_bus;
1152 }
1153
1154 for (i = 0; i < PHY_MAX_ADDR; i++)
1155 mdp->mii_bus->irq[i] = PHY_POLL;
1156
1157 /* regist mdio bus */
1158 ret = mdiobus_register(mdp->mii_bus);
1159 if (ret)
1160 goto out_free_irq;
1161
1162 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
1163
1164 return 0;
1165
1166 out_free_irq:
1167 kfree(mdp->mii_bus->irq);
1168
1169 out_free_bus:
1170 kfree(mdp->mii_bus);
1171
1172 out_free_bitbang:
1173 kfree(bitbang);
1174
1175 out:
1176 return ret;
1177 }
1178
1179 static int sh_eth_drv_probe(struct platform_device *pdev)
1180 {
1181 int ret, i, devno = 0;
1182 struct resource *res;
1183 struct net_device *ndev = NULL;
1184 struct sh_eth_private *mdp;
1185 struct sh_eth_plat_data *pd;
1186
1187 /* get base addr */
1188 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1189 if (unlikely(res == NULL)) {
1190 dev_err(&pdev->dev, "invalid resource\n");
1191 ret = -EINVAL;
1192 goto out;
1193 }
1194
1195 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
1196 if (!ndev) {
1197 printk(KERN_ERR "%s: could not allocate device.\n", CARDNAME);
1198 ret = -ENOMEM;
1199 goto out;
1200 }
1201
1202 /* The sh Ether-specific entries in the device structure. */
1203 ndev->base_addr = res->start;
1204 devno = pdev->id;
1205 if (devno < 0)
1206 devno = 0;
1207
1208 ndev->dma = -1;
1209 ndev->irq = platform_get_irq(pdev, 0);
1210 if (ndev->irq < 0) {
1211 ret = -ENODEV;
1212 goto out_release;
1213 }
1214
1215 SET_NETDEV_DEV(ndev, &pdev->dev);
1216
1217 /* Fill in the fields of the device structure with ethernet values. */
1218 ether_setup(ndev);
1219
1220 mdp = netdev_priv(ndev);
1221 spin_lock_init(&mdp->lock);
1222
1223 pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data);
1224 /* get PHY ID */
1225 mdp->phy_id = pd->phy;
1226 /* EDMAC endian */
1227 mdp->edmac_endian = pd->edmac_endian;
1228
1229 /* set function */
1230 ndev->open = sh_eth_open;
1231 ndev->hard_start_xmit = sh_eth_start_xmit;
1232 ndev->stop = sh_eth_close;
1233 ndev->get_stats = sh_eth_get_stats;
1234 ndev->set_multicast_list = sh_eth_set_multicast_list;
1235 ndev->do_ioctl = sh_eth_do_ioctl;
1236 ndev->tx_timeout = sh_eth_tx_timeout;
1237 ndev->watchdog_timeo = TX_TIMEOUT;
1238
1239 mdp->post_rx = POST_RX >> (devno << 1);
1240 mdp->post_fw = POST_FW >> (devno << 1);
1241
1242 /* read and set MAC address */
1243 read_mac_address(ndev);
1244
1245 /* First device only init */
1246 if (!devno) {
1247 #if defined(ARSTR)
1248 /* reset device */
1249 ctrl_outl(ARSTR_ARSTR, ARSTR);
1250 mdelay(1);
1251 #endif
1252
1253 #if defined(SH_TSU_ADDR)
1254 /* TSU init (Init only)*/
1255 sh_eth_tsu_init(SH_TSU_ADDR);
1256 #endif
1257 }
1258
1259 /* network device register */
1260 ret = register_netdev(ndev);
1261 if (ret)
1262 goto out_release;
1263
1264 /* mdio bus init */
1265 ret = sh_mdio_init(ndev, pdev->id);
1266 if (ret)
1267 goto out_unregister;
1268
1269 /* pritnt device infomation */
1270 printk(KERN_INFO "%s: %s at 0x%x, ",
1271 ndev->name, CARDNAME, (u32) ndev->base_addr);
1272
1273 for (i = 0; i < 5; i++)
1274 printk("%02X:", ndev->dev_addr[i]);
1275 printk("%02X, IRQ %d.\n", ndev->dev_addr[i], ndev->irq);
1276
1277 platform_set_drvdata(pdev, ndev);
1278
1279 return ret;
1280
1281 out_unregister:
1282 unregister_netdev(ndev);
1283
1284 out_release:
1285 /* net_dev free */
1286 if (ndev)
1287 free_netdev(ndev);
1288
1289 out:
1290 return ret;
1291 }
1292
1293 static int sh_eth_drv_remove(struct platform_device *pdev)
1294 {
1295 struct net_device *ndev = platform_get_drvdata(pdev);
1296
1297 sh_mdio_release(ndev);
1298 unregister_netdev(ndev);
1299 flush_scheduled_work();
1300
1301 free_netdev(ndev);
1302 platform_set_drvdata(pdev, NULL);
1303
1304 return 0;
1305 }
1306
1307 static struct platform_driver sh_eth_driver = {
1308 .probe = sh_eth_drv_probe,
1309 .remove = sh_eth_drv_remove,
1310 .driver = {
1311 .name = CARDNAME,
1312 },
1313 };
1314
1315 static int __init sh_eth_init(void)
1316 {
1317 return platform_driver_register(&sh_eth_driver);
1318 }
1319
1320 static void __exit sh_eth_cleanup(void)
1321 {
1322 platform_driver_unregister(&sh_eth_driver);
1323 }
1324
1325 module_init(sh_eth_init);
1326 module_exit(sh_eth_cleanup);
1327
1328 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
1329 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
1330 MODULE_LICENSE("GPL v2");
Support for the Chinese Samsung S3C2440 based development boards