drivers/video/aty/radeonfb.h

   1 #ifndef __RADEONFB_H__
   2 #define __RADEONFB_H__
   3
   4 #ifdef CONFIG_FB_RADEON_DEBUG
   5 #define DEBUG           1
   6 #endif
   7
   8 #include <linux/module.h>
   9 #include <linux/kernel.h>
  10 #include <linux/sched.h>
  11 #include <linux/delay.h>
  12 #include <linux/pci.h>
  13 #include <linux/fb.h>
  14
  15
  16 #ifdef CONFIG_FB_RADEON_I2C
  17 #include <linux/i2c.h>
  18 #include <linux/i2c-algo-bit.h>
  19 #endif
  20
  21 #include <asm/io.h>
  22
  23 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
  24 #include <asm/prom.h>
  25 #endif
  26
  27 #include <video/radeon.h>
  28
  29 /***************************************************************
  30  * Most of the definitions here are adapted right from XFree86 *
  31  ***************************************************************/
  32
  33
  34 /*
  35  * Chip families. Must fit in the low 16 bits of a long word
  36  */
  37 enum radeon_family {
  38         CHIP_FAMILY_UNKNOW,
  39         CHIP_FAMILY_LEGACY,
  40         CHIP_FAMILY_RADEON,
  41         CHIP_FAMILY_RV100,
  42         CHIP_FAMILY_RS100,    /* U1 (IGP320M) or A3 (IGP320)*/
  43         CHIP_FAMILY_RV200,
  44         CHIP_FAMILY_RS200,    /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350),
  45                                  RS250 (IGP 7000) */
  46         CHIP_FAMILY_R200,
  47         CHIP_FAMILY_RV250,
  48         CHIP_FAMILY_RS300,    /* Radeon 9000 IGP */
  49         CHIP_FAMILY_RV280,
  50         CHIP_FAMILY_R300,
  51         CHIP_FAMILY_R350,
  52         CHIP_FAMILY_RV350,
  53         CHIP_FAMILY_RV380,    /* RV370/RV380/M22/M24 */
  54         CHIP_FAMILY_R420,     /* R420/R423/M18 */
  55         CHIP_FAMILY_RC410,
  56         CHIP_FAMILY_RS400,
  57         CHIP_FAMILY_RS480,
  58         CHIP_FAMILY_LAST,
  59 };
  60
  61 #define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100)  || \
  62                                  ((rinfo)->family == CHIP_FAMILY_RV200)  || \
  63                                  ((rinfo)->family == CHIP_FAMILY_RS100)  || \
  64                                  ((rinfo)->family == CHIP_FAMILY_RS200)  || \
  65                                  ((rinfo)->family == CHIP_FAMILY_RV250)  || \
  66                                  ((rinfo)->family == CHIP_FAMILY_RV280)  || \
  67                                  ((rinfo)->family == CHIP_FAMILY_RS300))
  68
  69
  70 #define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300)  || \
  71                                 ((rinfo)->family == CHIP_FAMILY_RV350) || \
  72                                 ((rinfo)->family == CHIP_FAMILY_R350)  || \
  73                                 ((rinfo)->family == CHIP_FAMILY_RV380) || \
  74                                 ((rinfo)->family == CHIP_FAMILY_R420)  || \
  75                                ((rinfo)->family == CHIP_FAMILY_RC410) || \
  76                                ((rinfo)->family == CHIP_FAMILY_RS480))
  77
  78 /*
  79  * Chip flags
  80  */
  81 enum radeon_chip_flags {
  82         CHIP_FAMILY_MASK        = 0x0000ffffUL,
  83         CHIP_FLAGS_MASK         = 0xffff0000UL,
  84         CHIP_IS_MOBILITY        = 0x00010000UL,
  85         CHIP_IS_IGP             = 0x00020000UL,
  86         CHIP_HAS_CRTC2          = 0x00040000UL,
  87 };
  88
  89 /*
  90  * Errata workarounds
  91  */
  92 enum radeon_errata {
  93         CHIP_ERRATA_R300_CG             = 0x00000001,
  94         CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
  95         CHIP_ERRATA_PLL_DELAY           = 0x00000004,
  96 };
  97
  98
  99 /*
 100  * Monitor types
 101  */
 102 enum radeon_montype {
 103         MT_NONE = 0,
 104         MT_CRT,         /* CRT */
 105         MT_LCD,         /* LCD */
 106         MT_DFP,         /* DVI */
 107         MT_CTV,         /* composite TV */
 108         MT_STV          /* S-Video out */
 109 };
 110
 111 /*
 112  * DDC i2c ports
 113  */
 114 enum ddc_type {
 115         ddc_none,
 116         ddc_monid,
 117         ddc_dvi,
 118         ddc_vga,
 119         ddc_crt2,
 120 };
 121
 122 /*
 123  * Connector types
 124  */
 125 enum conn_type {
 126         conn_none,
 127         conn_proprietary,
 128         conn_crt,
 129         conn_DVI_I,
 130         conn_DVI_D,
 131 };
 132
 133
 134 /*
 135  * PLL infos
 136  */
 137 struct pll_info {
 138         int ppll_max;
 139         int ppll_min;
 140         int sclk, mclk;
 141         int ref_div;
 142         int ref_clk;
 143 };
 144
 145
 146 /*
 147  * This structure contains the various registers manipulated by this
 148  * driver for setting or restoring a mode. It's mostly copied from
 149  * XFree's RADEONSaveRec structure. A few chip settings might still be
 150  * tweaked without beeing reflected or saved in these registers though
 151  */
 152 struct radeon_regs {
 153         /* Common registers */
 154         u32             ovr_clr;
 155         u32             ovr_wid_left_right;
 156         u32             ovr_wid_top_bottom;
 157         u32             ov0_scale_cntl;
 158         u32             mpp_tb_config;
 159         u32             mpp_gp_config;
 160         u32             subpic_cntl;
 161         u32             viph_control;
 162         u32             i2c_cntl_1;
 163         u32             gen_int_cntl;
 164         u32             cap0_trig_cntl;
 165         u32             cap1_trig_cntl;
 166         u32             bus_cntl;
 167         u32             surface_cntl;
 168         u32             bios_5_scratch;
 169
 170         /* Other registers to save for VT switches or driver load/unload */
 171         u32             dp_datatype;
 172         u32             rbbm_soft_reset;
 173         u32             clock_cntl_index;
 174         u32             amcgpio_en_reg;
 175         u32             amcgpio_mask;
 176
 177         /* Surface/tiling registers */
 178         u32             surf_lower_bound[8];
 179         u32             surf_upper_bound[8];
 180         u32             surf_info[8];
 181
 182         /* CRTC registers */
 183         u32             crtc_gen_cntl;
 184         u32             crtc_ext_cntl;
 185         u32             dac_cntl;
 186         u32             crtc_h_total_disp;
 187         u32             crtc_h_sync_strt_wid;
 188         u32             crtc_v_total_disp;
 189         u32             crtc_v_sync_strt_wid;
 190         u32             crtc_offset;
 191         u32             crtc_offset_cntl;
 192         u32             crtc_pitch;
 193         u32             disp_merge_cntl;
 194         u32             grph_buffer_cntl;
 195         u32             crtc_more_cntl;
 196
 197         /* CRTC2 registers */
 198         u32             crtc2_gen_cntl;
 199         u32             dac2_cntl;
 200         u32             disp_output_cntl;
 201         u32             disp_hw_debug;
 202         u32             disp2_merge_cntl;
 203         u32             grph2_buffer_cntl;
 204         u32             crtc2_h_total_disp;
 205         u32             crtc2_h_sync_strt_wid;
 206         u32             crtc2_v_total_disp;
 207         u32             crtc2_v_sync_strt_wid;
 208         u32             crtc2_offset;
 209         u32             crtc2_offset_cntl;
 210         u32             crtc2_pitch;
 211
 212         /* Flat panel regs */
 213         u32             fp_crtc_h_total_disp;
 214         u32             fp_crtc_v_total_disp;
 215         u32             fp_gen_cntl;
 216         u32             fp2_gen_cntl;
 217         u32             fp_h_sync_strt_wid;
 218         u32             fp2_h_sync_strt_wid;
 219         u32             fp_horz_stretch;
 220         u32             fp_panel_cntl;
 221         u32             fp_v_sync_strt_wid;
 222         u32             fp2_v_sync_strt_wid;
 223         u32             fp_vert_stretch;
 224         u32             lvds_gen_cntl;
 225         u32             lvds_pll_cntl;
 226         u32             tmds_crc;
 227         u32             tmds_transmitter_cntl;
 228
 229         /* Computed values for PLL */
 230         u32             dot_clock_freq;
 231         int             feedback_div;
 232         int             post_div;
 233
 234         /* PLL registers */
 235         u32             ppll_div_3;
 236         u32             ppll_ref_div;
 237         u32             vclk_ecp_cntl;
 238         u32             clk_cntl_index;
 239
 240         /* Computed values for PLL2 */
 241         u32             dot_clock_freq_2;
 242         int             feedback_div_2;
 243         int             post_div_2;
 244
 245         /* PLL2 registers */
 246         u32             p2pll_ref_div;
 247         u32             p2pll_div_0;
 248         u32             htotal_cntl2;
 249
 250         /* Palette */
 251         int             palette_valid;
 252 };
 253
 254 struct panel_info {
 255         int xres, yres;
 256         int valid;
 257         int clock;
 258         int hOver_plus, hSync_width, hblank;
 259         int vOver_plus, vSync_width, vblank;
 260         int hAct_high, vAct_high, interlaced;
 261         int pwr_delay;
 262         int use_bios_dividers;
 263         int ref_divider;
 264         int post_divider;
 265         int fbk_divider;
 266 };
 267
 268 struct radeonfb_info;
 269
 270 #ifdef CONFIG_FB_RADEON_I2C
 271 struct radeon_i2c_chan {
 272         struct radeonfb_info            *rinfo;
 273         u32                             ddc_reg;
 274         struct i2c_adapter              adapter;
 275         struct i2c_algo_bit_data        algo;
 276 };
 277 #endif
 278
 279 enum radeon_pm_mode {
 280         radeon_pm_none  = 0,            /* Nothing supported */
 281         radeon_pm_d2    = 0x00000001,   /* Can do D2 state */
 282         radeon_pm_off   = 0x00000002,   /* Can resume from D3 cold */
 283 };
 284
 285 typedef void (*reinit_function_ptr)(struct radeonfb_info *rinfo);
 286
 287 struct radeonfb_info {
 288         struct fb_info          *info;
 289
 290         struct radeon_regs      state;
 291         struct radeon_regs      init_state;
 292
 293         char                    name[50];
 294
 295         unsigned long           mmio_base_phys;
 296         unsigned long           fb_base_phys;
 297
 298         void __iomem            *mmio_base;
 299         void __iomem            *fb_base;
 300
 301         unsigned long           fb_local_base;
 302
 303         struct pci_dev          *pdev;
 304 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
 305         struct device_node      *of_node;
 306 #endif
 307
 308         void __iomem            *bios_seg;
 309         int                     fp_bios_start;
 310
 311         u32                     pseudo_palette[16];
 312         struct { u8 red, green, blue, pad; }
 313                                 palette[256];
 314
 315         int                     chipset;
 316         u8                      family;
 317         u8                      rev;
 318         unsigned int            errata;
 319         unsigned long           video_ram;
 320         unsigned long           mapped_vram;
 321         int                     vram_width;
 322         int                     vram_ddr;
 323
 324         int                     pitch, bpp, depth;
 325
 326         int                     has_CRTC2;
 327         int                     is_mobility;
 328         int                     is_IGP;
 329         int                     reversed_DAC;
 330         int                     reversed_TMDS;
 331         struct panel_info       panel_info;
 332         int                     mon1_type;
 333         u8                      *mon1_EDID;
 334         struct fb_videomode     *mon1_modedb;
 335         int                     mon1_dbsize;
 336         int                     mon2_type;
 337         u8                      *mon2_EDID;
 338
 339         /* accel bits */
 340         u32                     dp_gui_mc_base;
 341         u32                     dp_gui_mc_cache;
 342         u32                     dp_cntl_cache;
 343         u32                     dp_brush_fg_cache;
 344         u32                     dp_brush_bg_cache;
 345         u32                     dp_src_fg_cache;
 346         u32                     dp_src_bg_cache;
 347         u32                     fifo_free;
 348
 349         struct pll_info         pll;
 350
 351         int                     mtrr_hdl;
 352
 353         int                     pm_reg;
 354         u32                     save_regs[100];
 355         int                     asleep;
 356         int                     lock_blank;
 357         int                     dynclk;
 358         int                     no_schedule;
 359         int                     gfx_mode;
 360         enum radeon_pm_mode     pm_mode;
 361         reinit_function_ptr     reinit_func;
 362
 363         /* Lock on register access */
 364         spinlock_t              reg_lock;
 365
 366         /* Timer used for delayed LVDS operations */
 367         struct timer_list       lvds_timer;
 368         u32                     pending_lvds_gen_cntl;
 369
 370 #ifdef CONFIG_FB_RADEON_I2C
 371         struct radeon_i2c_chan  i2c[4];
 372 #endif
 373
 374         u32                     cfg_save[64];
 375 };
 376
 377
 378 #define PRIMARY_MONITOR(rinfo)  (rinfo->mon1_type)
 379
 380
 381 /*
 382  * IO macros
 383  */
 384
 385 /* Note about this function: we have some rare cases where we must not schedule,
 386  * this typically happen with our special "wake up early" hook which allows us to
 387  * wake up the graphic chip (and thus get the console back) before everything else
 388  * on some machines that support that mechanism. At this point, interrupts are off
 389  * and scheduling is not permitted
 390  */
 391 static inline void _radeon_msleep(struct radeonfb_info *rinfo, unsigned long ms)
 392 {
 393         if (rinfo->no_schedule || oops_in_progress)
 394                 mdelay(ms);
 395         else
 396                 msleep(ms);
 397 }
 398
 399
 400 #define INREG8(addr)            readb((rinfo->mmio_base)+addr)
 401 #define OUTREG8(addr,val)       writeb(val, (rinfo->mmio_base)+addr)
 402 #define INREG16(addr)           readw((rinfo->mmio_base)+addr)
 403 #define OUTREG16(addr,val)      writew(val, (rinfo->mmio_base)+addr)
 404
 405 #ifdef CONFIG_PPC
 406 #define INREG(addr)             ({ eieio(); ld_le32(rinfo->mmio_base+(addr)); })
 407 #define OUTREG(addr,val)        do { eieio(); st_le32(rinfo->mmio_base+(addr),(val)); } while(0)
 408 #else
 409 #define INREG(addr)             readl((rinfo->mmio_base)+addr)
 410 #define OUTREG(addr,val)        writel(val, (rinfo->mmio_base)+addr)
 411 #endif
 412
 413 static inline void _OUTREGP(struct radeonfb_info *rinfo, u32 addr,
 414                        u32 val, u32 mask)
 415 {
 416         unsigned long flags;
 417         unsigned int tmp;
 418
 419         spin_lock_irqsave(&rinfo->reg_lock, flags);
 420         tmp = INREG(addr);
 421         tmp &= (mask);
 422         tmp |= (val);
 423         OUTREG(addr, tmp);
 424         spin_unlock_irqrestore(&rinfo->reg_lock, flags);
 425 }
 426
 427 #define OUTREGP(addr,val,mask)  _OUTREGP(rinfo, addr, val,mask)
 428
 429 /*
 430  * Note about PLL register accesses:
 431  *
 432  * I have removed the spinlock on them on purpose. The driver now
 433  * expects that it will only manipulate the PLL registers in normal
 434  * task environment, where radeon_msleep() will be called, protected
 435  * by a semaphore (currently the console semaphore) so that no conflict
 436  * will happen on the PLL register index.
 437  *
 438  * With the latest changes to the VT layer, this is guaranteed for all
 439  * calls except the actual drawing/blits which aren't supposed to use
 440  * the PLL registers anyway
 441  *
 442  * This is very important for the workarounds to work properly. The only
 443  * possible exception to this rule is the call to unblank(), which may
 444  * be done at irq time if an oops is in progress.
 445  */
 446 static inline void radeon_pll_errata_after_index(struct radeonfb_info *rinfo)
 447 {
 448         if (!(rinfo->errata & CHIP_ERRATA_PLL_DUMMYREADS))
 449                 return;
 450
 451         (void)INREG(CLOCK_CNTL_DATA);
 452         (void)INREG(CRTC_GEN_CNTL);
 453 }
 454
 455 static inline void radeon_pll_errata_after_data(struct radeonfb_info *rinfo)
 456 {
 457         if (rinfo->errata & CHIP_ERRATA_PLL_DELAY) {
 458                 /* we can't deal with posted writes here ... */
 459                 _radeon_msleep(rinfo, 5);
 460         }
 461         if (rinfo->errata & CHIP_ERRATA_R300_CG) {
 462                 u32 save, tmp;
 463                 save = INREG(CLOCK_CNTL_INDEX);
 464                 tmp = save & ~(0x3f | PLL_WR_EN);
 465                 OUTREG(CLOCK_CNTL_INDEX, tmp);
 466                 tmp = INREG(CLOCK_CNTL_DATA);
 467                 OUTREG(CLOCK_CNTL_INDEX, save);
 468         }
 469 }
 470
 471 static inline u32 __INPLL(struct radeonfb_info *rinfo, u32 addr)
 472 {
 473         u32 data;
 474
 475         OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
 476         radeon_pll_errata_after_index(rinfo);
 477         data = INREG(CLOCK_CNTL_DATA);
 478         radeon_pll_errata_after_data(rinfo);
 479         return data;
 480 }
 481
 482 static inline void __OUTPLL(struct radeonfb_info *rinfo, unsigned int index,
 483                             u32 val)
 484 {
 485
 486         OUTREG8(CLOCK_CNTL_INDEX, (index & 0x0000003f) | 0x00000080);
 487         radeon_pll_errata_after_index(rinfo);
 488         OUTREG(CLOCK_CNTL_DATA, val);
 489         radeon_pll_errata_after_data(rinfo);
 490 }
 491
 492
 493 static inline void __OUTPLLP(struct radeonfb_info *rinfo, unsigned int index,
 494                              u32 val, u32 mask)
 495 {
 496         unsigned int tmp;
 497
 498         tmp  = __INPLL(rinfo, index);
 499         tmp &= (mask);
 500         tmp |= (val);
 501         __OUTPLL(rinfo, index, tmp);
 502 }
 503
 504
 505 #define INPLL(addr)                     __INPLL(rinfo, addr)
 506 #define OUTPLL(index, val)              __OUTPLL(rinfo, index, val)
 507 #define OUTPLLP(index, val, mask)       __OUTPLLP(rinfo, index, val, mask)
 508
 509
 510 #define BIOS_IN8(v)     (readb(rinfo->bios_seg + (v)))
 511 #define BIOS_IN16(v)    (readb(rinfo->bios_seg + (v)) | \
 512                           (readb(rinfo->bios_seg + (v) + 1) << 8))
 513 #define BIOS_IN32(v)    (readb(rinfo->bios_seg + (v)) | \
 514                           (readb(rinfo->bios_seg + (v) + 1) << 8) | \
 515                           (readb(rinfo->bios_seg + (v) + 2) << 16) | \
 516                           (readb(rinfo->bios_seg + (v) + 3) << 24))
 517
 518 /*
 519  * Inline utilities
 520  */
 521 static inline int round_div(int num, int den)
 522 {
 523         return (num + (den / 2)) / den;
 524 }
 525
 526 static inline int var_to_depth(const struct fb_var_screeninfo *var)
 527 {
 528         if (var->bits_per_pixel != 16)
 529                 return var->bits_per_pixel;
 530         return (var->green.length == 5) ? 15 : 16;
 531 }
 532
 533 static inline u32 radeon_get_dstbpp(u16 depth)
 534 {
 535         switch (depth) {
 536         case 8:
 537                 return DST_8BPP;
 538         case 15:
 539                 return DST_15BPP;
 540         case 16:
 541                 return DST_16BPP;
 542         case 32:
 543                 return DST_32BPP;
 544         default:
 545                 return 0;
 546         }
 547 }
 548
 549 /*
 550  * 2D Engine helper routines
 551  */
 552
 553 extern void radeon_fifo_update_and_wait(struct radeonfb_info *rinfo, int entries);
 554
 555 static inline void radeon_engine_flush (struct radeonfb_info *rinfo)
 556 {
 557         int i;
 558
 559         /* Initiate flush */
 560         OUTREGP(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
 561                 ~RB2D_DC_FLUSH_ALL);
 562
 563         /* Ensure FIFO is empty, ie, make sure the flush commands
 564          * has reached the cache
 565          */
 566         radeon_fifo_update_and_wait(rinfo, 64);
 567
 568         /* Wait for the flush to complete */
 569         for (i=0; i < 2000000; i++) {
 570                 if (!(INREG(DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
 571                         return;
 572                 udelay(1);
 573         }
 574         printk(KERN_ERR "radeonfb: Flush Timeout !\n");
 575 }
 576
 577
 578 static inline void radeon_engine_idle(struct radeonfb_info *rinfo)
 579 {
 580         int i;
 581
 582         /* ensure FIFO is empty before waiting for idle */
 583         radeon_fifo_update_and_wait (rinfo, 64);
 584
 585         for (i=0; i<2000000; i++) {
 586                 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
 587                         radeon_engine_flush (rinfo);
 588                         return;
 589                 }
 590                 udelay(1);
 591         }
 592         printk(KERN_ERR "radeonfb: Idle Timeout !\n");
 593 }
 594
 595
 596 #define radeon_msleep(ms)               _radeon_msleep(rinfo,ms)
 597
 598
 599 /* I2C Functions */
 600 extern void radeon_create_i2c_busses(struct radeonfb_info *rinfo);
 601 extern void radeon_delete_i2c_busses(struct radeonfb_info *rinfo);
 602 extern int radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int conn, u8 **out_edid);
 603
 604 /* PM Functions */
 605 extern int radeonfb_pci_suspend(struct pci_dev *pdev, pm_message_t state);
 606 extern int radeonfb_pci_resume(struct pci_dev *pdev);
 607 extern void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlist, int force_sleep);
 608 extern void radeonfb_pm_exit(struct radeonfb_info *rinfo);
 609
 610 /* Monitor probe functions */
 611 extern void radeon_probe_screens(struct radeonfb_info *rinfo,
 612                                  const char *monitor_layout, int ignore_edid);
 613 extern void radeon_check_modes(struct radeonfb_info *rinfo, const char *mode_option);
 614 extern int radeon_match_mode(struct radeonfb_info *rinfo,
 615                              struct fb_var_screeninfo *dest,
 616                              const struct fb_var_screeninfo *src);
 617
 618 /* Accel functions */
 619 extern void radeonfb_fillrect(struct fb_info *info, const struct fb_fillrect *region);
 620 extern void radeonfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
 621 extern void radeonfb_imageblit(struct fb_info *p, const struct fb_image *image);
 622 extern int radeonfb_sync(struct fb_info *info);
 623 extern void radeonfb_engine_init (struct radeonfb_info *rinfo);
 624 extern void radeonfb_engine_reset(struct radeonfb_info *rinfo);
 625 extern void radeon_fixup_mem_offset(struct radeonfb_info *rinfo);
 626
 627 /* Other functions */
 628 extern int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch);
 629 extern void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
 630                                int reg_only);
 631
 632 /* Backlight functions */
 633 #ifdef CONFIG_FB_RADEON_BACKLIGHT
 634 extern void radeonfb_bl_init(struct radeonfb_info *rinfo);
 635 extern void radeonfb_bl_exit(struct radeonfb_info *rinfo);
 636 #else
 637 static inline void radeonfb_bl_init(struct radeonfb_info *rinfo) {}
 638 static inline void radeonfb_bl_exit(struct radeonfb_info *rinfo) {}
 639 #endif
 640
 641 extern int accel_cexp;
 642
 643 #endif /* __RADEONFB_H__ */