1 /* -*- mode: c; c-basic-offset: 8 -*- */
3 /* Copyright (C) 1999,2001
5 * Author: J.E.J.Bottomley@HansenPartnership.com
7 * linux/arch/i386/kernel/voyager_smp.c
9 * This file provides all the same external entries as smp.c but uses
10 * the voyager hal to provide the functionality
12 #include <linux/config.h>
13 #include <linux/module.h>
15 #include <linux/kernel_stat.h>
16 #include <linux/delay.h>
17 #include <linux/mc146818rtc.h>
18 #include <linux/cache.h>
19 #include <linux/interrupt.h>
20 #include <linux/smp_lock.h>
21 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <linux/bootmem.h>
24 #include <linux/completion.h>
26 #include <asm/voyager.h>
29 #include <asm/pgalloc.h>
30 #include <asm/tlbflush.h>
31 #include <asm/arch_hooks.h>
33 #include <linux/irq.h>
35 /* TLB state -- visible externally, indexed physically */
36 DEFINE_PER_CPU(struct tlb_state
, cpu_tlbstate
) ____cacheline_aligned
= { &init_mm
, 0 };
38 /* CPU IRQ affinity -- set to all ones initially */
39 static unsigned long cpu_irq_affinity
[NR_CPUS
] __cacheline_aligned
= { [0 ... NR_CPUS
-1] = ~0UL };
41 /* per CPU data structure (for /proc/cpuinfo et al), visible externally
42 * indexed physically */
43 struct cpuinfo_x86 cpu_data
[NR_CPUS
] __cacheline_aligned
;
44 EXPORT_SYMBOL(cpu_data
);
46 /* physical ID of the CPU used to boot the system */
47 unsigned char boot_cpu_id
;
49 /* The memory line addresses for the Quad CPIs */
50 struct voyager_qic_cpi
*voyager_quad_cpi_addr
[NR_CPUS
] __cacheline_aligned
;
52 /* The masks for the Extended VIC processors, filled in by cat_init */
53 __u32 voyager_extended_vic_processors
= 0;
55 /* Masks for the extended Quad processors which cannot be VIC booted */
56 __u32 voyager_allowed_boot_processors
= 0;
58 /* The mask for the Quad Processors (both extended and non-extended) */
59 __u32 voyager_quad_processors
= 0;
61 /* Total count of live CPUs, used in process.c to display
62 * the CPU information and in irq.c for the per CPU irq
63 * activity count. Finally exported by i386_ksyms.c */
64 static int voyager_extended_cpus
= 1;
66 /* Have we found an SMP box - used by time.c to do the profiling
67 interrupt for timeslicing; do not set to 1 until the per CPU timer
68 interrupt is active */
69 int smp_found_config
= 0;
71 /* Used for the invalidate map that's also checked in the spinlock */
72 static volatile unsigned long smp_invalidate_needed
;
74 /* Bitmask of currently online CPUs - used by setup.c for
75 /proc/cpuinfo, visible externally but still physical */
76 cpumask_t cpu_online_map
= CPU_MASK_NONE
;
77 EXPORT_SYMBOL(cpu_online_map
);
79 /* Bitmask of CPUs present in the system - exported by i386_syms.c, used
80 * by scheduler but indexed physically */
81 cpumask_t phys_cpu_present_map
= CPU_MASK_NONE
;
84 /* The internal functions */
85 static void send_CPI(__u32 cpuset
, __u8 cpi
);
86 static void ack_CPI(__u8 cpi
);
87 static int ack_QIC_CPI(__u8 cpi
);
88 static void ack_special_QIC_CPI(__u8 cpi
);
89 static void ack_VIC_CPI(__u8 cpi
);
90 static void send_CPI_allbutself(__u8 cpi
);
91 static void enable_vic_irq(unsigned int irq
);
92 static void disable_vic_irq(unsigned int irq
);
93 static unsigned int startup_vic_irq(unsigned int irq
);
94 static void enable_local_vic_irq(unsigned int irq
);
95 static void disable_local_vic_irq(unsigned int irq
);
96 static void before_handle_vic_irq(unsigned int irq
);
97 static void after_handle_vic_irq(unsigned int irq
);
98 static void set_vic_irq_affinity(unsigned int irq
, cpumask_t mask
);
99 static void ack_vic_irq(unsigned int irq
);
100 static void vic_enable_cpi(void);
101 static void do_boot_cpu(__u8 cpuid
);
102 static void do_quad_bootstrap(void);
104 int hard_smp_processor_id(void);
106 /* Inline functions */
108 send_one_QIC_CPI(__u8 cpu
, __u8 cpi
)
110 voyager_quad_cpi_addr
[cpu
]->qic_cpi
[cpi
].cpi
=
111 (smp_processor_id() << 16) + cpi
;
115 send_QIC_CPI(__u32 cpuset
, __u8 cpi
)
119 for_each_online_cpu(cpu
) {
120 if(cpuset
& (1<<cpu
)) {
122 if(!cpu_isset(cpu
, cpu_online_map
))
123 VDEBUG(("CPU%d sending cpi %d to CPU%d not in cpu_online_map\n", hard_smp_processor_id(), cpi
, cpu
));
125 send_one_QIC_CPI(cpu
, cpi
- QIC_CPI_OFFSET
);
131 wrapper_smp_local_timer_interrupt(struct pt_regs
*regs
)
134 smp_local_timer_interrupt(regs
);
139 send_one_CPI(__u8 cpu
, __u8 cpi
)
141 if(voyager_quad_processors
& (1<<cpu
))
142 send_one_QIC_CPI(cpu
, cpi
- QIC_CPI_OFFSET
);
144 send_CPI(1<<cpu
, cpi
);
148 send_CPI_allbutself(__u8 cpi
)
150 __u8 cpu
= smp_processor_id();
151 __u32 mask
= cpus_addr(cpu_online_map
)[0] & ~(1 << cpu
);
158 __u8 cpumask
= inb(VIC_PROC_WHO_AM_I
);
159 return ((cpumask
& QUAD_IDENTIFIER
) == QUAD_IDENTIFIER
);
163 is_cpu_extended(void)
165 __u8 cpu
= hard_smp_processor_id();
167 return(voyager_extended_vic_processors
& (1<<cpu
));
171 is_cpu_vic_boot(void)
173 __u8 cpu
= hard_smp_processor_id();
175 return(voyager_extended_vic_processors
176 & voyager_allowed_boot_processors
& (1<<cpu
));
184 case VIC_CPU_BOOT_CPI
:
185 if(is_cpu_quad() && !is_cpu_vic_boot())
192 /* These are slightly strange. Even on the Quad card,
193 * They are vectored as VIC CPIs */
195 ack_special_QIC_CPI(cpi
);
200 printk("VOYAGER ERROR: CPI%d is in common CPI code\n", cpi
);
205 /* local variables */
207 /* The VIC IRQ descriptors -- these look almost identical to the
208 * 8259 IRQs except that masks and things must be kept per processor
210 static struct hw_interrupt_type vic_irq_type
= {
211 .typename
= "VIC-level",
212 .startup
= startup_vic_irq
,
213 .shutdown
= disable_vic_irq
,
214 .enable
= enable_vic_irq
,
215 .disable
= disable_vic_irq
,
216 .ack
= before_handle_vic_irq
,
217 .end
= after_handle_vic_irq
,
218 .set_affinity
= set_vic_irq_affinity
,
221 /* used to count up as CPUs are brought on line (starts at 0) */
222 static int cpucount
= 0;
224 /* steal a page from the bottom of memory for the trampoline and
225 * squirrel its address away here. This will be in kernel virtual
227 static __u32 trampoline_base
;
229 /* The per cpu profile stuff - used in smp_local_timer_interrupt */
230 static DEFINE_PER_CPU(int, prof_multiplier
) = 1;
231 static DEFINE_PER_CPU(int, prof_old_multiplier
) = 1;
232 static DEFINE_PER_CPU(int, prof_counter
) = 1;
234 /* the map used to check if a CPU has booted */
235 static __u32 cpu_booted_map
;
237 /* the synchronize flag used to hold all secondary CPUs spinning in
238 * a tight loop until the boot sequence is ready for them */
239 static cpumask_t smp_commenced_mask
= CPU_MASK_NONE
;
241 /* This is for the new dynamic CPU boot code */
242 cpumask_t cpu_callin_map
= CPU_MASK_NONE
;
243 cpumask_t cpu_callout_map
= CPU_MASK_NONE
;
244 EXPORT_SYMBOL(cpu_callout_map
);
246 /* The per processor IRQ masks (these are usually kept in sync) */
247 static __u16 vic_irq_mask
[NR_CPUS
] __cacheline_aligned
;
249 /* the list of IRQs to be enabled by the VIC_ENABLE_IRQ_CPI */
250 static __u16 vic_irq_enable_mask
[NR_CPUS
] __cacheline_aligned
= { 0 };
252 /* Lock for enable/disable of VIC interrupts */
253 static __cacheline_aligned
DEFINE_SPINLOCK(vic_irq_lock
);
255 /* The boot processor is correctly set up in PC mode when it
256 * comes up, but the secondaries need their master/slave 8259
257 * pairs initializing correctly */
259 /* Interrupt counters (per cpu) and total - used to try to
260 * even up the interrupt handling routines */
261 static long vic_intr_total
= 0;
262 static long vic_intr_count
[NR_CPUS
] __cacheline_aligned
= { 0 };
263 static unsigned long vic_tick
[NR_CPUS
] __cacheline_aligned
= { 0 };
265 /* Since we can only use CPI0, we fake all the other CPIs */
266 static unsigned long vic_cpi_mailbox
[NR_CPUS
] __cacheline_aligned
;
268 /* debugging routine to read the isr of the cpu's pic */
275 isr
= inb(0xa0) << 8;
286 /* not a quad, no setup */
289 outb(QIC_DEFAULT_MASK0
, QIC_MASK_REGISTER0
);
290 outb(QIC_CPI_ENABLE
, QIC_MASK_REGISTER1
);
292 if(is_cpu_extended()) {
293 /* the QIC duplicate of the VIC base register */
294 outb(VIC_DEFAULT_CPI_BASE
, QIC_VIC_CPI_BASE_REGISTER
);
295 outb(QIC_DEFAULT_CPI_BASE
, QIC_CPI_BASE_REGISTER
);
297 /* FIXME: should set up the QIC timer and memory parity
298 * error vectors here */
305 outb(1, VIC_REDIRECT_REGISTER_1
);
306 /* clear the claim registers for dynamic routing */
307 outb(0, VIC_CLAIM_REGISTER_0
);
308 outb(0, VIC_CLAIM_REGISTER_1
);
310 outb(0, VIC_PRIORITY_REGISTER
);
311 /* Set the Primary and Secondary Microchannel vector
312 * bases to be the same as the ordinary interrupts
314 * FIXME: This would be more efficient using separate
316 outb(FIRST_EXTERNAL_VECTOR
, VIC_PRIMARY_MC_BASE
);
317 outb(FIRST_EXTERNAL_VECTOR
, VIC_SECONDARY_MC_BASE
);
318 /* Now initiallise the master PIC belonging to this CPU by
319 * sending the four ICWs */
321 /* ICW1: level triggered, ICW4 needed */
324 /* ICW2: vector base */
325 outb(FIRST_EXTERNAL_VECTOR
, 0x21);
327 /* ICW3: slave at line 2 */
330 /* ICW4: 8086 mode */
333 /* now the same for the slave PIC */
335 /* ICW1: level trigger, ICW4 needed */
338 /* ICW2: slave vector base */
339 outb(FIRST_EXTERNAL_VECTOR
+ 8, 0xA1);
344 /* ICW4: 8086 mode */
349 do_quad_bootstrap(void)
351 if(is_cpu_quad() && is_cpu_vic_boot()) {
354 __u8 cpuid
= hard_smp_processor_id();
356 local_irq_save(flags
);
358 for(i
= 0; i
<4; i
++) {
359 /* FIXME: this would be >>3 &0x7 on the 32 way */
360 if(((cpuid
>> 2) & 0x03) == i
)
361 /* don't lower our own mask! */
364 /* masquerade as local Quad CPU */
365 outb(QIC_CPUID_ENABLE
| i
, QIC_PROCESSOR_ID
);
366 /* enable the startup CPI */
367 outb(QIC_BOOT_CPI_MASK
, QIC_MASK_REGISTER1
);
369 outb(0, QIC_PROCESSOR_ID
);
371 local_irq_restore(flags
);
376 /* Set up all the basic stuff: read the SMP config and make all the
377 * SMP information reflect only the boot cpu. All others will be
378 * brought on-line later. */
380 find_smp_config(void)
384 boot_cpu_id
= hard_smp_processor_id();
386 printk("VOYAGER SMP: Boot cpu is %d\n", boot_cpu_id
);
388 /* initialize the CPU structures (moved from smp_boot_cpus) */
389 for(i
=0; i
<NR_CPUS
; i
++) {
390 cpu_irq_affinity
[i
] = ~0;
392 cpu_online_map
= cpumask_of_cpu(boot_cpu_id
);
394 /* The boot CPU must be extended */
395 voyager_extended_vic_processors
= 1<<boot_cpu_id
;
396 /* initially, all of the first 8 cpu's can boot */
397 voyager_allowed_boot_processors
= 0xff;
398 /* set up everything for just this CPU, we can alter
399 * this as we start the other CPUs later */
400 /* now get the CPU disposition from the extended CMOS */
401 cpus_addr(phys_cpu_present_map
)[0] = voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK
);
402 cpus_addr(phys_cpu_present_map
)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK
+ 1) << 8;
403 cpus_addr(phys_cpu_present_map
)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK
+ 2) << 16;
404 cpus_addr(phys_cpu_present_map
)[0] |= voyager_extended_cmos_read(VOYAGER_PROCESSOR_PRESENT_MASK
+ 3) << 24;
405 printk("VOYAGER SMP: phys_cpu_present_map = 0x%lx\n", cpus_addr(phys_cpu_present_map
)[0]);
406 /* Here we set up the VIC to enable SMP */
407 /* enable the CPIs by writing the base vector to their register */
408 outb(VIC_DEFAULT_CPI_BASE
, VIC_CPI_BASE_REGISTER
);
409 outb(1, VIC_REDIRECT_REGISTER_1
);
410 /* set the claim registers for static routing --- Boot CPU gets
411 * all interrupts untill all other CPUs started */
412 outb(0xff, VIC_CLAIM_REGISTER_0
);
413 outb(0xff, VIC_CLAIM_REGISTER_1
);
414 /* Set the Primary and Secondary Microchannel vector
415 * bases to be the same as the ordinary interrupts
417 * FIXME: This would be more efficient using separate
419 outb(FIRST_EXTERNAL_VECTOR
, VIC_PRIMARY_MC_BASE
);
420 outb(FIRST_EXTERNAL_VECTOR
, VIC_SECONDARY_MC_BASE
);
422 /* Finally tell the firmware that we're driving */
423 outb(inb(VOYAGER_SUS_IN_CONTROL_PORT
) | VOYAGER_IN_CONTROL_FLAG
,
424 VOYAGER_SUS_IN_CONTROL_PORT
);
426 current_thread_info()->cpu
= boot_cpu_id
;
430 * The bootstrap kernel entry code has set these up. Save them
431 * for a given CPU, id is physical */
433 smp_store_cpu_info(int id
)
435 struct cpuinfo_x86
*c
=&cpu_data
[id
];
442 /* set up the trampoline and return the physical address of the code */
444 setup_trampoline(void)
446 /* these two are global symbols in trampoline.S */
447 extern __u8 trampoline_end
[];
448 extern __u8 trampoline_data
[];
450 memcpy((__u8
*)trampoline_base
, trampoline_data
,
451 trampoline_end
- trampoline_data
);
452 return virt_to_phys((__u8
*)trampoline_base
);
455 /* Routine initially called when a non-boot CPU is brought online */
457 start_secondary(void *unused
)
459 __u8 cpuid
= hard_smp_processor_id();
460 /* external functions not defined in the headers */
461 extern void calibrate_delay(void);
465 /* OK, we're in the routine */
466 ack_CPI(VIC_CPU_BOOT_CPI
);
468 /* setup the 8259 master slave pair belonging to this CPU ---
469 * we won't actually receive any until the boot CPU
470 * relinquishes it's static routing mask */
475 if(is_cpu_quad() && !is_cpu_vic_boot()) {
476 /* clear the boot CPI */
479 dummy
= voyager_quad_cpi_addr
[cpuid
]->qic_cpi
[VIC_CPU_BOOT_CPI
].cpi
;
480 printk("read dummy %d\n", dummy
);
483 /* lower the mask to receive CPIs */
486 VDEBUG(("VOYAGER SMP: CPU%d, stack at about %p\n", cpuid
, &cpuid
));
488 /* enable interrupts */
491 /* get our bogomips */
494 /* save our processor parameters */
495 smp_store_cpu_info(cpuid
);
497 /* if we're a quad, we may need to bootstrap other CPUs */
500 /* FIXME: this is rather a poor hack to prevent the CPU
501 * activating softirqs while it's supposed to be waiting for
502 * permission to proceed. Without this, the new per CPU stuff
503 * in the softirqs will fail */
505 cpu_set(cpuid
, cpu_callin_map
);
507 /* signal that we're done */
510 while (!cpu_isset(cpuid
, smp_commenced_mask
))
516 cpu_set(cpuid
, cpu_online_map
);
522 /* Routine to kick start the given CPU and wait for it to report ready
523 * (or timeout in startup). When this routine returns, the requested
524 * CPU is either fully running and configured or known to be dead.
526 * We call this routine sequentially 1 CPU at a time, so no need for
530 do_boot_cpu(__u8 cpu
)
532 struct task_struct
*idle
;
535 int quad_boot
= (1<<cpu
) & voyager_quad_processors
536 & ~( voyager_extended_vic_processors
537 & voyager_allowed_boot_processors
);
539 /* For the 486, we can't use the 4Mb page table trick, so
540 * must map a region of memory */
543 unsigned long *page_table_copies
= (unsigned long *)
544 __get_free_page(GFP_KERNEL
);
546 pgd_t orig_swapper_pg_dir0
;
548 /* This is an area in head.S which was used to set up the
549 * initial kernel stack. We need to alter this to give the
550 * booting CPU a new stack (taken from its idle process) */
555 /* This is the format of the CPI IDT gate (in real mode) which
556 * we're hijacking to boot the CPU */
565 __u32
*hijack_vector
;
566 __u32 start_phys_address
= setup_trampoline();
568 /* There's a clever trick to this: The linux trampoline is
569 * compiled to begin at absolute location zero, so make the
570 * address zero but have the data segment selector compensate
571 * for the actual address */
572 hijack_source
.idt
.Offset
= start_phys_address
& 0x000F;
573 hijack_source
.idt
.Segment
= (start_phys_address
>> 4) & 0xFFFF;
576 idle
= fork_idle(cpu
);
578 panic("failed fork for CPU%d", cpu
);
579 idle
->thread
.eip
= (unsigned long) start_secondary
;
580 /* init_tasks (in sched.c) is indexed logically */
581 stack_start
.esp
= (void *) idle
->thread
.esp
;
585 /* Note: Don't modify initial ss override */
586 VDEBUG(("VOYAGER SMP: Booting CPU%d at 0x%lx[%x:%x], stack %p\n", cpu
,
587 (unsigned long)hijack_source
.val
, hijack_source
.idt
.Segment
,
588 hijack_source
.idt
.Offset
, stack_start
.esp
));
589 /* set the original swapper_pg_dir[0] to map 0 to 4Mb transparently
590 * (so that the booting CPU can find start_32 */
591 orig_swapper_pg_dir0
= swapper_pg_dir
[0];
593 if(page_table_copies
== NULL
)
594 panic("No free memory for 486 page tables\n");
595 for(i
= 0; i
< PAGE_SIZE
/sizeof(unsigned long); i
++)
596 page_table_copies
[i
] = (i
* PAGE_SIZE
)
597 | _PAGE_RW
| _PAGE_USER
| _PAGE_PRESENT
;
599 ((unsigned long *)swapper_pg_dir
)[0] =
600 ((virt_to_phys(page_table_copies
)) & PAGE_MASK
)
601 | _PAGE_RW
| _PAGE_USER
| _PAGE_PRESENT
;
603 ((unsigned long *)swapper_pg_dir
)[0] =
604 (virt_to_phys(pg0
) & PAGE_MASK
)
605 | _PAGE_RW
| _PAGE_USER
| _PAGE_PRESENT
;
609 printk("CPU %d: non extended Quad boot\n", cpu
);
610 hijack_vector
= (__u32
*)phys_to_virt((VIC_CPU_BOOT_CPI
+ QIC_DEFAULT_CPI_BASE
)*4);
611 *hijack_vector
= hijack_source
.val
;
613 printk("CPU%d: extended VIC boot\n", cpu
);
614 hijack_vector
= (__u32
*)phys_to_virt((VIC_CPU_BOOT_CPI
+ VIC_DEFAULT_CPI_BASE
)*4);
615 *hijack_vector
= hijack_source
.val
;
616 /* VIC errata, may also receive interrupt at this address */
617 hijack_vector
= (__u32
*)phys_to_virt((VIC_CPU_BOOT_ERRATA_CPI
+ VIC_DEFAULT_CPI_BASE
)*4);
618 *hijack_vector
= hijack_source
.val
;
620 /* All non-boot CPUs start with interrupts fully masked. Need
621 * to lower the mask of the CPI we're about to send. We do
622 * this in the VIC by masquerading as the processor we're
623 * about to boot and lowering its interrupt mask */
624 local_irq_save(flags
);
626 send_one_QIC_CPI(cpu
, VIC_CPU_BOOT_CPI
);
628 outb(VIC_CPU_MASQUERADE_ENABLE
| cpu
, VIC_PROCESSOR_ID
);
629 /* here we're altering registers belonging to `cpu' */
631 outb(VIC_BOOT_INTERRUPT_MASK
, 0x21);
632 /* now go back to our original identity */
633 outb(boot_cpu_id
, VIC_PROCESSOR_ID
);
635 /* and boot the CPU */
637 send_CPI((1<<cpu
), VIC_CPU_BOOT_CPI
);
640 local_irq_restore(flags
);
642 /* now wait for it to become ready (or timeout) */
643 for(timeout
= 0; timeout
< 50000; timeout
++) {
648 /* reset the page table */
649 swapper_pg_dir
[0] = orig_swapper_pg_dir0
;
652 free_page((unsigned long)page_table_copies
);
655 if (cpu_booted_map
) {
656 VDEBUG(("CPU%d: Booted successfully, back in CPU %d\n",
657 cpu
, smp_processor_id()));
659 printk("CPU%d: ", cpu
);
660 print_cpu_info(&cpu_data
[cpu
]);
662 cpu_set(cpu
, cpu_callout_map
);
665 printk("CPU%d FAILED TO BOOT: ", cpu
);
666 if (*((volatile unsigned char *)phys_to_virt(start_phys_address
))==0xA5)
669 printk("Not responding.\n");
680 /* CAT BUS initialisation must be done after the memory */
681 /* FIXME: The L4 has a catbus too, it just needs to be
682 * accessed in a totally different way */
683 if(voyager_level
== 5) {
686 /* now that the cat has probed the Voyager System Bus, sanity
687 * check the cpu map */
688 if( ((voyager_quad_processors
| voyager_extended_vic_processors
)
689 & cpus_addr(phys_cpu_present_map
)[0]) != cpus_addr(phys_cpu_present_map
)[0]) {
691 printk("\n\n***WARNING*** Sanity check of CPU present map FAILED\n");
693 } else if(voyager_level
== 4)
694 voyager_extended_vic_processors
= cpus_addr(phys_cpu_present_map
)[0];
696 /* this sets up the idle task to run on the current cpu */
697 voyager_extended_cpus
= 1;
698 /* Remove the global_irq_holder setting, it triggers a BUG() on
699 * schedule at the moment */
700 //global_irq_holder = boot_cpu_id;
702 /* FIXME: Need to do something about this but currently only works
703 * on CPUs with a tsc which none of mine have.
704 smp_tune_scheduling();
706 smp_store_cpu_info(boot_cpu_id
);
707 printk("CPU%d: ", boot_cpu_id
);
708 print_cpu_info(&cpu_data
[boot_cpu_id
]);
711 /* booting on a Quad CPU */
712 printk("VOYAGER SMP: Boot CPU is Quad\n");
717 /* enable our own CPIs */
720 cpu_set(boot_cpu_id
, cpu_online_map
);
721 cpu_set(boot_cpu_id
, cpu_callout_map
);
723 /* loop over all the extended VIC CPUs and boot them. The
724 * Quad CPUs must be bootstrapped by their extended VIC cpu */
725 for(i
= 0; i
< NR_CPUS
; i
++) {
726 if(i
== boot_cpu_id
|| !cpu_isset(i
, phys_cpu_present_map
))
729 /* This udelay seems to be needed for the Quad boots
730 * don't remove unless you know what you're doing */
733 /* we could compute the total bogomips here, but why bother?,
734 * Code added from smpboot.c */
736 unsigned long bogosum
= 0;
737 for (i
= 0; i
< NR_CPUS
; i
++)
738 if (cpu_isset(i
, cpu_online_map
))
739 bogosum
+= cpu_data
[i
].loops_per_jiffy
;
740 printk(KERN_INFO
"Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
743 (bogosum
/(5000/HZ
))%100);
745 voyager_extended_cpus
= hweight32(voyager_extended_vic_processors
);
746 printk("VOYAGER: Extended (interrupt handling CPUs): %d, non-extended: %d\n", voyager_extended_cpus
, num_booting_cpus() - voyager_extended_cpus
);
747 /* that's it, switch to symmetric mode */
748 outb(0, VIC_PRIORITY_REGISTER
);
749 outb(0, VIC_CLAIM_REGISTER_0
);
750 outb(0, VIC_CLAIM_REGISTER_1
);
752 VDEBUG(("VOYAGER SMP: Booted with %d CPUs\n", num_booting_cpus()));
755 /* Reload the secondary CPUs task structure (this function does not
758 initialize_secondary(void)
762 set_current(hard_get_current());
766 * We don't actually need to load the full TSS,
767 * basically just the stack pointer and the eip.
774 :"r" (current
->thread
.esp
),"r" (current
->thread
.eip
));
777 /* handle a Voyager SYS_INT -- If we don't, the base board will
780 * System interrupts occur because some problem was detected on the
781 * various busses. To find out what you have to probe all the
782 * hardware via the CAT bus. FIXME: At the moment we do nothing. */
784 smp_vic_sys_interrupt(struct pt_regs
*regs
)
786 ack_CPI(VIC_SYS_INT
);
787 printk("Voyager SYSTEM INTERRUPT\n");
790 /* Handle a voyager CMN_INT; These interrupts occur either because of
791 * a system status change or because a single bit memory error
792 * occurred. FIXME: At the moment, ignore all this. */
794 smp_vic_cmn_interrupt(struct pt_regs
*regs
)
796 static __u8 in_cmn_int
= 0;
797 static DEFINE_SPINLOCK(cmn_int_lock
);
799 /* common ints are broadcast, so make sure we only do this once */
800 _raw_spin_lock(&cmn_int_lock
);
805 _raw_spin_unlock(&cmn_int_lock
);
807 VDEBUG(("Voyager COMMON INTERRUPT\n"));
809 if(voyager_level
== 5)
810 voyager_cat_do_common_interrupt();
812 _raw_spin_lock(&cmn_int_lock
);
815 _raw_spin_unlock(&cmn_int_lock
);
816 ack_CPI(VIC_CMN_INT
);
820 * Reschedule call back. Nothing to do, all the work is done
821 * automatically when we return from the interrupt. */
823 smp_reschedule_interrupt(void)
828 static struct mm_struct
* flush_mm
;
829 static unsigned long flush_va
;
830 static DEFINE_SPINLOCK(tlbstate_lock
);
831 #define FLUSH_ALL 0xffffffff
834 * We cannot call mmdrop() because we are in interrupt context,
835 * instead update mm->cpu_vm_mask.
837 * We need to reload %cr3 since the page tables may be going
838 * away from under us..
841 leave_mm (unsigned long cpu
)
843 if (per_cpu(cpu_tlbstate
, cpu
).state
== TLBSTATE_OK
)
845 cpu_clear(cpu
, per_cpu(cpu_tlbstate
, cpu
).active_mm
->cpu_vm_mask
);
846 load_cr3(swapper_pg_dir
);
851 * Invalidate call-back
854 smp_invalidate_interrupt(void)
856 __u8 cpu
= smp_processor_id();
858 if (!test_bit(cpu
, &smp_invalidate_needed
))
860 /* This will flood messages. Don't uncomment unless you see
861 * Problems with cross cpu invalidation
862 VDEBUG(("VOYAGER SMP: CPU%d received INVALIDATE_CPI\n",
863 smp_processor_id()));
866 if (flush_mm
== per_cpu(cpu_tlbstate
, cpu
).active_mm
) {
867 if (per_cpu(cpu_tlbstate
, cpu
).state
== TLBSTATE_OK
) {
868 if (flush_va
== FLUSH_ALL
)
871 __flush_tlb_one(flush_va
);
875 smp_mb__before_clear_bit();
876 clear_bit(cpu
, &smp_invalidate_needed
);
877 smp_mb__after_clear_bit();
880 /* All the new flush operations for 2.4 */
883 /* This routine is called with a physical cpu mask */
885 flush_tlb_others (unsigned long cpumask
, struct mm_struct
*mm
,
892 if ((cpumask
& cpus_addr(cpu_online_map
)[0]) != cpumask
)
894 if (cpumask
& (1 << smp_processor_id()))
899 spin_lock(&tlbstate_lock
);
903 atomic_set_mask(cpumask
, &smp_invalidate_needed
);
905 * We have to send the CPI only to
908 send_CPI(cpumask
, VIC_INVALIDATE_CPI
);
910 while (smp_invalidate_needed
) {
913 printk("***WARNING*** Stuck doing invalidate CPI (CPU%d)\n", smp_processor_id());
918 /* Uncomment only to debug invalidation problems
919 VDEBUG(("VOYAGER SMP: Completed invalidate CPI (CPU%d)\n", cpu));
924 spin_unlock(&tlbstate_lock
);
928 flush_tlb_current_task(void)
930 struct mm_struct
*mm
= current
->mm
;
931 unsigned long cpu_mask
;
935 cpu_mask
= cpus_addr(mm
->cpu_vm_mask
)[0] & ~(1 << smp_processor_id());
938 flush_tlb_others(cpu_mask
, mm
, FLUSH_ALL
);
945 flush_tlb_mm (struct mm_struct
* mm
)
947 unsigned long cpu_mask
;
951 cpu_mask
= cpus_addr(mm
->cpu_vm_mask
)[0] & ~(1 << smp_processor_id());
953 if (current
->active_mm
== mm
) {
957 leave_mm(smp_processor_id());
960 flush_tlb_others(cpu_mask
, mm
, FLUSH_ALL
);
965 void flush_tlb_page(struct vm_area_struct
* vma
, unsigned long va
)
967 struct mm_struct
*mm
= vma
->vm_mm
;
968 unsigned long cpu_mask
;
972 cpu_mask
= cpus_addr(mm
->cpu_vm_mask
)[0] & ~(1 << smp_processor_id());
973 if (current
->active_mm
== mm
) {
977 leave_mm(smp_processor_id());
981 flush_tlb_others(cpu_mask
, mm
, va
);
985 EXPORT_SYMBOL(flush_tlb_page
);
987 /* enable the requested IRQs */
989 smp_enable_irq_interrupt(void)
992 __u8 cpu
= get_cpu();
994 VDEBUG(("VOYAGER SMP: CPU%d enabling irq mask 0x%x\n", cpu
,
995 vic_irq_enable_mask
[cpu
]));
997 spin_lock(&vic_irq_lock
);
998 for(irq
= 0; irq
< 16; irq
++) {
999 if(vic_irq_enable_mask
[cpu
] & (1<<irq
))
1000 enable_local_vic_irq(irq
);
1002 vic_irq_enable_mask
[cpu
] = 0;
1003 spin_unlock(&vic_irq_lock
);
1005 put_cpu_no_resched();
1009 * CPU halt call-back
1012 smp_stop_cpu_function(void *dummy
)
1014 VDEBUG(("VOYAGER SMP: CPU%d is STOPPING\n", smp_processor_id()));
1015 cpu_clear(smp_processor_id(), cpu_online_map
);
1016 local_irq_disable();
1021 static DEFINE_SPINLOCK(call_lock
);
1023 struct call_data_struct
{
1024 void (*func
) (void *info
);
1026 volatile unsigned long started
;
1027 volatile unsigned long finished
;
1031 static struct call_data_struct
* call_data
;
1033 /* execute a thread on a new CPU. The function to be called must be
1034 * previously set up. This is used to schedule a function for
1035 * execution on all CPU's - set up the function then broadcast a
1036 * function_interrupt CPI to come here on each CPU */
1038 smp_call_function_interrupt(void)
1040 void (*func
) (void *info
) = call_data
->func
;
1041 void *info
= call_data
->info
;
1042 /* must take copy of wait because call_data may be replaced
1043 * unless the function is waiting for us to finish */
1044 int wait
= call_data
->wait
;
1045 __u8 cpu
= smp_processor_id();
1048 * Notify initiating CPU that I've grabbed the data and am
1049 * about to execute the function
1052 if(!test_and_clear_bit(cpu
, &call_data
->started
)) {
1053 /* If the bit wasn't set, this could be a replay */
1054 printk(KERN_WARNING
"VOYAGER SMP: CPU %d received call funtion with no call pending\n", cpu
);
1058 * At this point the info structure may be out of scope unless wait==1
1065 clear_bit(cpu
, &call_data
->finished
);
1069 /* Call this function on all CPUs using the function_interrupt above
1070 <func> The function to run. This must be fast and non-blocking.
1071 <info> An arbitrary pointer to pass to the function.
1072 <retry> If true, keep retrying until ready.
1073 <wait> If true, wait until function has completed on other CPUs.
1074 [RETURNS] 0 on success, else a negative status code. Does not return until
1075 remote CPUs are nearly ready to execute <<func>> or are or have executed.
1078 smp_call_function (void (*func
) (void *info
), void *info
, int retry
,
1081 struct call_data_struct data
;
1082 __u32 mask
= cpus_addr(cpu_online_map
)[0];
1084 mask
&= ~(1<<smp_processor_id());
1089 /* Can deadlock when called with interrupts disabled */
1090 WARN_ON(irqs_disabled());
1094 data
.started
= mask
;
1097 data
.finished
= mask
;
1099 spin_lock(&call_lock
);
1102 /* Send a message to all other CPUs and wait for them to respond */
1103 send_CPI_allbutself(VIC_CALL_FUNCTION_CPI
);
1105 /* Wait for response */
1106 while (data
.started
)
1110 while (data
.finished
)
1113 spin_unlock(&call_lock
);
1117 EXPORT_SYMBOL(smp_call_function
);
1119 /* Sorry about the name. In an APIC based system, the APICs
1120 * themselves are programmed to send a timer interrupt. This is used
1121 * by linux to reschedule the processor. Voyager doesn't have this,
1122 * so we use the system clock to interrupt one processor, which in
1123 * turn, broadcasts a timer CPI to all the others --- we receive that
1124 * CPI here. We don't use this actually for counting so losing
1125 * ticks doesn't matter
1127 * FIXME: For those CPU's which actually have a local APIC, we could
1128 * try to use it to trigger this interrupt instead of having to
1129 * broadcast the timer tick. Unfortunately, all my pentium DYADs have
1130 * no local APIC, so I can't do this
1132 * This function is currently a placeholder and is unused in the code */
1134 smp_apic_timer_interrupt(struct pt_regs
*regs
)
1136 wrapper_smp_local_timer_interrupt(regs
);
1139 /* All of the QUAD interrupt GATES */
1141 smp_qic_timer_interrupt(struct pt_regs
*regs
)
1143 ack_QIC_CPI(QIC_TIMER_CPI
);
1144 wrapper_smp_local_timer_interrupt(regs
);
1148 smp_qic_invalidate_interrupt(struct pt_regs
*regs
)
1150 ack_QIC_CPI(QIC_INVALIDATE_CPI
);
1151 smp_invalidate_interrupt();
1155 smp_qic_reschedule_interrupt(struct pt_regs
*regs
)
1157 ack_QIC_CPI(QIC_RESCHEDULE_CPI
);
1158 smp_reschedule_interrupt();
1162 smp_qic_enable_irq_interrupt(struct pt_regs
*regs
)
1164 ack_QIC_CPI(QIC_ENABLE_IRQ_CPI
);
1165 smp_enable_irq_interrupt();
1169 smp_qic_call_function_interrupt(struct pt_regs
*regs
)
1171 ack_QIC_CPI(QIC_CALL_FUNCTION_CPI
);
1172 smp_call_function_interrupt();
1176 smp_vic_cpi_interrupt(struct pt_regs
*regs
)
1178 __u8 cpu
= smp_processor_id();
1181 ack_QIC_CPI(VIC_CPI_LEVEL0
);
1183 ack_VIC_CPI(VIC_CPI_LEVEL0
);
1185 if(test_and_clear_bit(VIC_TIMER_CPI
, &vic_cpi_mailbox
[cpu
]))
1186 wrapper_smp_local_timer_interrupt(regs
);
1187 if(test_and_clear_bit(VIC_INVALIDATE_CPI
, &vic_cpi_mailbox
[cpu
]))
1188 smp_invalidate_interrupt();
1189 if(test_and_clear_bit(VIC_RESCHEDULE_CPI
, &vic_cpi_mailbox
[cpu
]))
1190 smp_reschedule_interrupt();
1191 if(test_and_clear_bit(VIC_ENABLE_IRQ_CPI
, &vic_cpi_mailbox
[cpu
]))
1192 smp_enable_irq_interrupt();
1193 if(test_and_clear_bit(VIC_CALL_FUNCTION_CPI
, &vic_cpi_mailbox
[cpu
]))
1194 smp_call_function_interrupt();
1198 do_flush_tlb_all(void* info
)
1200 unsigned long cpu
= smp_processor_id();
1203 if (per_cpu(cpu_tlbstate
, cpu
).state
== TLBSTATE_LAZY
)
1208 /* flush the TLB of every active CPU in the system */
1212 on_each_cpu(do_flush_tlb_all
, 0, 1, 1);
1215 /* used to set up the trampoline for other CPUs when the memory manager
1218 smp_alloc_memory(void)
1220 trampoline_base
= (__u32
)alloc_bootmem_low_pages(PAGE_SIZE
);
1221 if(__pa(trampoline_base
) >= 0x93000)
1225 /* send a reschedule CPI to one CPU by physical CPU number*/
1227 smp_send_reschedule(int cpu
)
1229 send_one_CPI(cpu
, VIC_RESCHEDULE_CPI
);
1234 hard_smp_processor_id(void)
1237 __u8 cpumask
= inb(VIC_PROC_WHO_AM_I
);
1238 if((cpumask
& QUAD_IDENTIFIER
) == QUAD_IDENTIFIER
)
1239 return cpumask
& 0x1F;
1241 for(i
= 0; i
< 8; i
++) {
1242 if(cpumask
& (1<<i
))
1245 printk("** WARNING ** Illegal cpuid returned by VIC: %d", cpumask
);
1249 /* broadcast a halt to all other CPUs */
1253 smp_call_function(smp_stop_cpu_function
, NULL
, 1, 1);
1256 /* this function is triggered in time.c when a clock tick fires
1257 * we need to re-broadcast the tick to all CPUs */
1259 smp_vic_timer_interrupt(struct pt_regs
*regs
)
1261 send_CPI_allbutself(VIC_TIMER_CPI
);
1262 smp_local_timer_interrupt(regs
);
1265 /* local (per CPU) timer interrupt. It does both profiling and
1266 * process statistics/rescheduling.
1268 * We do profiling in every local tick, statistics/rescheduling
1269 * happen only every 'profiling multiplier' ticks. The default
1270 * multiplier is 1 and it can be changed by writing the new multiplier
1271 * value into /proc/profile.
1274 smp_local_timer_interrupt(struct pt_regs
* regs
)
1276 int cpu
= smp_processor_id();
1279 profile_tick(CPU_PROFILING
, regs
);
1280 if (--per_cpu(prof_counter
, cpu
) <= 0) {
1282 * The multiplier may have changed since the last time we got
1283 * to this point as a result of the user writing to
1284 * /proc/profile. In this case we need to adjust the APIC
1285 * timer accordingly.
1287 * Interrupts are already masked off at this point.
1289 per_cpu(prof_counter
,cpu
) = per_cpu(prof_multiplier
, cpu
);
1290 if (per_cpu(prof_counter
, cpu
) !=
1291 per_cpu(prof_old_multiplier
, cpu
)) {
1292 /* FIXME: need to update the vic timer tick here */
1293 per_cpu(prof_old_multiplier
, cpu
) =
1294 per_cpu(prof_counter
, cpu
);
1297 update_process_times(user_mode_vm(regs
));
1300 if( ((1<<cpu
) & voyager_extended_vic_processors
) == 0)
1301 /* only extended VIC processors participate in
1302 * interrupt distribution */
1306 * We take the 'long' return path, and there every subsystem
1307 * grabs the apropriate locks (kernel lock/ irq lock).
1309 * we might want to decouple profiling from the 'long path',
1310 * and do the profiling totally in assembly.
1312 * Currently this isn't too much of an issue (performance wise),
1313 * we can take more than 100K local irqs per second on a 100 MHz P5.
1316 if((++vic_tick
[cpu
] & 0x7) != 0)
1318 /* get here every 16 ticks (about every 1/6 of a second) */
1320 /* Change our priority to give someone else a chance at getting
1321 * the IRQ. The algorithm goes like this:
1323 * In the VIC, the dynamically routed interrupt is always
1324 * handled by the lowest priority eligible (i.e. receiving
1325 * interrupts) CPU. If >1 eligible CPUs are equal lowest, the
1326 * lowest processor number gets it.
1328 * The priority of a CPU is controlled by a special per-CPU
1329 * VIC priority register which is 3 bits wide 0 being lowest
1330 * and 7 highest priority..
1332 * Therefore we subtract the average number of interrupts from
1333 * the number we've fielded. If this number is negative, we
1334 * lower the activity count and if it is positive, we raise
1337 * I'm afraid this still leads to odd looking interrupt counts:
1338 * the totals are all roughly equal, but the individual ones
1339 * look rather skewed.
1341 * FIXME: This algorithm is total crap when mixed with SMP
1342 * affinity code since we now try to even up the interrupt
1343 * counts when an affinity binding is keeping them on a
1345 weight
= (vic_intr_count
[cpu
]*voyager_extended_cpus
1346 - vic_intr_total
) >> 4;
1353 outb((__u8
)weight
, VIC_PRIORITY_REGISTER
);
1355 #ifdef VOYAGER_DEBUG
1356 if((vic_tick
[cpu
] & 0xFFF) == 0) {
1357 /* print this message roughly every 25 secs */
1358 printk("VOYAGER SMP: vic_tick[%d] = %lu, weight = %ld\n",
1359 cpu
, vic_tick
[cpu
], weight
);
1364 /* setup the profiling timer */
1366 setup_profiling_timer(unsigned int multiplier
)
1374 * Set the new multiplier for each CPU. CPUs don't start using the
1375 * new values until the next timer interrupt in which they do process
1378 for (i
= 0; i
< NR_CPUS
; ++i
)
1379 per_cpu(prof_multiplier
, i
) = multiplier
;
1385 /* The CPIs are handled in the per cpu 8259s, so they must be
1386 * enabled to be received: FIX: enabling the CPIs in the early
1387 * boot sequence interferes with bug checking; enable them later
1389 #define VIC_SET_GATE(cpi, vector) \
1390 set_intr_gate((cpi) + VIC_DEFAULT_CPI_BASE, (vector))
1391 #define QIC_SET_GATE(cpi, vector) \
1392 set_intr_gate((cpi) + QIC_DEFAULT_CPI_BASE, (vector))
1399 /* initialize the per cpu irq mask to all disabled */
1400 for(i
= 0; i
< NR_CPUS
; i
++)
1401 vic_irq_mask
[i
] = 0xFFFF;
1403 VIC_SET_GATE(VIC_CPI_LEVEL0
, vic_cpi_interrupt
);
1405 VIC_SET_GATE(VIC_SYS_INT
, vic_sys_interrupt
);
1406 VIC_SET_GATE(VIC_CMN_INT
, vic_cmn_interrupt
);
1408 QIC_SET_GATE(QIC_TIMER_CPI
, qic_timer_interrupt
);
1409 QIC_SET_GATE(QIC_INVALIDATE_CPI
, qic_invalidate_interrupt
);
1410 QIC_SET_GATE(QIC_RESCHEDULE_CPI
, qic_reschedule_interrupt
);
1411 QIC_SET_GATE(QIC_ENABLE_IRQ_CPI
, qic_enable_irq_interrupt
);
1412 QIC_SET_GATE(QIC_CALL_FUNCTION_CPI
, qic_call_function_interrupt
);
1415 /* now put the VIC descriptor into the first 48 IRQs
1417 * This is for later: first 16 correspond to PC IRQs; next 16
1418 * are Primary MC IRQs and final 16 are Secondary MC IRQs */
1419 for(i
= 0; i
< 48; i
++)
1420 irq_desc
[i
].handler
= &vic_irq_type
;
1423 /* send a CPI at level cpi to a set of cpus in cpuset (set 1 bit per
1424 * processor to receive CPI */
1426 send_CPI(__u32 cpuset
, __u8 cpi
)
1429 __u32 quad_cpuset
= (cpuset
& voyager_quad_processors
);
1431 if(cpi
< VIC_START_FAKE_CPI
) {
1432 /* fake CPI are only used for booting, so send to the
1433 * extended quads as well---Quads must be VIC booted */
1434 outb((__u8
)(cpuset
), VIC_CPI_Registers
[cpi
]);
1438 send_QIC_CPI(quad_cpuset
, cpi
);
1439 cpuset
&= ~quad_cpuset
;
1440 cpuset
&= 0xff; /* only first 8 CPUs vaild for VIC CPI */
1443 for_each_online_cpu(cpu
) {
1444 if(cpuset
& (1<<cpu
))
1445 set_bit(cpi
, &vic_cpi_mailbox
[cpu
]);
1448 outb((__u8
)cpuset
, VIC_CPI_Registers
[VIC_CPI_LEVEL0
]);
1451 /* Acknowledge receipt of CPI in the QIC, clear in QIC hardware and
1452 * set the cache line to shared by reading it.
1454 * DON'T make this inline otherwise the cache line read will be
1458 ack_QIC_CPI(__u8 cpi
) {
1459 __u8 cpu
= hard_smp_processor_id();
1463 outb(1<<cpi
, QIC_INTERRUPT_CLEAR1
);
1464 return voyager_quad_cpi_addr
[cpu
]->qic_cpi
[cpi
].cpi
;
1468 ack_special_QIC_CPI(__u8 cpi
)
1472 outb(QIC_CMN_INT
, QIC_INTERRUPT_CLEAR0
);
1475 outb(QIC_SYS_INT
, QIC_INTERRUPT_CLEAR0
);
1478 /* also clear at the VIC, just in case (nop for non-extended proc) */
1482 /* Acknowledge receipt of CPI in the VIC (essentially an EOI) */
1484 ack_VIC_CPI(__u8 cpi
)
1486 #ifdef VOYAGER_DEBUG
1487 unsigned long flags
;
1489 __u8 cpu
= smp_processor_id();
1491 local_irq_save(flags
);
1492 isr
= vic_read_isr();
1493 if((isr
& (1<<(cpi
&7))) == 0) {
1494 printk("VOYAGER SMP: CPU%d lost CPI%d\n", cpu
, cpi
);
1497 /* send specific EOI; the two system interrupts have
1498 * bit 4 set for a separate vector but behave as the
1499 * corresponding 3 bit intr */
1500 outb_p(0x60|(cpi
& 7),0x20);
1502 #ifdef VOYAGER_DEBUG
1503 if((vic_read_isr() & (1<<(cpi
&7))) != 0) {
1504 printk("VOYAGER SMP: CPU%d still asserting CPI%d\n", cpu
, cpi
);
1506 local_irq_restore(flags
);
1510 /* cribbed with thanks from irq.c */
1511 #define __byte(x,y) (((unsigned char *)&(y))[x])
1512 #define cached_21(cpu) (__byte(0,vic_irq_mask[cpu]))
1513 #define cached_A1(cpu) (__byte(1,vic_irq_mask[cpu]))
1516 startup_vic_irq(unsigned int irq
)
1518 enable_vic_irq(irq
);
1523 /* The enable and disable routines. This is where we run into
1524 * conflicting architectural philosophy. Fundamentally, the voyager
1525 * architecture does not expect to have to disable interrupts globally
1526 * (the IRQ controllers belong to each CPU). The processor masquerade
1527 * which is used to start the system shouldn't be used in a running OS
1528 * since it will cause great confusion if two separate CPUs drive to
1529 * the same IRQ controller (I know, I've tried it).
1531 * The solution is a variant on the NCR lazy SPL design:
1533 * 1) To disable an interrupt, do nothing (other than set the
1534 * IRQ_DISABLED flag). This dares the interrupt actually to arrive.
1536 * 2) If the interrupt dares to come in, raise the local mask against
1537 * it (this will result in all the CPU masks being raised
1540 * 3) To enable the interrupt, lower the mask on the local CPU and
1541 * broadcast an Interrupt enable CPI which causes all other CPUs to
1542 * adjust their masks accordingly. */
1545 enable_vic_irq(unsigned int irq
)
1547 /* linux doesn't to processor-irq affinity, so enable on
1548 * all CPUs we know about */
1549 int cpu
= smp_processor_id(), real_cpu
;
1550 __u16 mask
= (1<<irq
);
1551 __u32 processorList
= 0;
1552 unsigned long flags
;
1554 VDEBUG(("VOYAGER: enable_vic_irq(%d) CPU%d affinity 0x%lx\n",
1555 irq
, cpu
, cpu_irq_affinity
[cpu
]));
1556 spin_lock_irqsave(&vic_irq_lock
, flags
);
1557 for_each_online_cpu(real_cpu
) {
1558 if(!(voyager_extended_vic_processors
& (1<<real_cpu
)))
1560 if(!(cpu_irq_affinity
[real_cpu
] & mask
)) {
1561 /* irq has no affinity for this CPU, ignore */
1564 if(real_cpu
== cpu
) {
1565 enable_local_vic_irq(irq
);
1567 else if(vic_irq_mask
[real_cpu
] & mask
) {
1568 vic_irq_enable_mask
[real_cpu
] |= mask
;
1569 processorList
|= (1<<real_cpu
);
1572 spin_unlock_irqrestore(&vic_irq_lock
, flags
);
1574 send_CPI(processorList
, VIC_ENABLE_IRQ_CPI
);
1578 disable_vic_irq(unsigned int irq
)
1580 /* lazy disable, do nothing */
1584 enable_local_vic_irq(unsigned int irq
)
1586 __u8 cpu
= smp_processor_id();
1587 __u16 mask
= ~(1 << irq
);
1588 __u16 old_mask
= vic_irq_mask
[cpu
];
1590 vic_irq_mask
[cpu
] &= mask
;
1591 if(vic_irq_mask
[cpu
] == old_mask
)
1594 VDEBUG(("VOYAGER DEBUG: Enabling irq %d in hardware on CPU %d\n",
1598 outb_p(cached_A1(cpu
),0xA1);
1602 outb_p(cached_21(cpu
),0x21);
1608 disable_local_vic_irq(unsigned int irq
)
1610 __u8 cpu
= smp_processor_id();
1611 __u16 mask
= (1 << irq
);
1612 __u16 old_mask
= vic_irq_mask
[cpu
];
1617 vic_irq_mask
[cpu
] |= mask
;
1618 if(old_mask
== vic_irq_mask
[cpu
])
1621 VDEBUG(("VOYAGER DEBUG: Disabling irq %d in hardware on CPU %d\n",
1625 outb_p(cached_A1(cpu
),0xA1);
1629 outb_p(cached_21(cpu
),0x21);
1634 /* The VIC is level triggered, so the ack can only be issued after the
1635 * interrupt completes. However, we do Voyager lazy interrupt
1636 * handling here: It is an extremely expensive operation to mask an
1637 * interrupt in the vic, so we merely set a flag (IRQ_DISABLED). If
1638 * this interrupt actually comes in, then we mask and ack here to push
1639 * the interrupt off to another CPU */
1641 before_handle_vic_irq(unsigned int irq
)
1643 irq_desc_t
*desc
= irq_desc
+ irq
;
1644 __u8 cpu
= smp_processor_id();
1646 _raw_spin_lock(&vic_irq_lock
);
1648 vic_intr_count
[cpu
]++;
1650 if(!(cpu_irq_affinity
[cpu
] & (1<<irq
))) {
1651 /* The irq is not in our affinity mask, push it off
1652 * onto another CPU */
1653 VDEBUG(("VOYAGER DEBUG: affinity triggered disable of irq %d on cpu %d\n",
1655 disable_local_vic_irq(irq
);
1656 /* set IRQ_INPROGRESS to prevent the handler in irq.c from
1657 * actually calling the interrupt routine */
1658 desc
->status
|= IRQ_REPLAY
| IRQ_INPROGRESS
;
1659 } else if(desc
->status
& IRQ_DISABLED
) {
1660 /* Damn, the interrupt actually arrived, do the lazy
1661 * disable thing. The interrupt routine in irq.c will
1662 * not handle a IRQ_DISABLED interrupt, so nothing more
1663 * need be done here */
1664 VDEBUG(("VOYAGER DEBUG: lazy disable of irq %d on CPU %d\n",
1666 disable_local_vic_irq(irq
);
1667 desc
->status
|= IRQ_REPLAY
;
1669 desc
->status
&= ~IRQ_REPLAY
;
1672 _raw_spin_unlock(&vic_irq_lock
);
1675 /* Finish the VIC interrupt: basically mask */
1677 after_handle_vic_irq(unsigned int irq
)
1679 irq_desc_t
*desc
= irq_desc
+ irq
;
1681 _raw_spin_lock(&vic_irq_lock
);
1683 unsigned int status
= desc
->status
& ~IRQ_INPROGRESS
;
1684 #ifdef VOYAGER_DEBUG
1688 desc
->status
= status
;
1689 if ((status
& IRQ_DISABLED
))
1690 disable_local_vic_irq(irq
);
1691 #ifdef VOYAGER_DEBUG
1692 /* DEBUG: before we ack, check what's in progress */
1693 isr
= vic_read_isr();
1694 if((isr
& (1<<irq
) && !(status
& IRQ_REPLAY
)) == 0) {
1696 __u8 cpu
= smp_processor_id();
1698 int mask
; /* Um... initialize me??? --RR */
1700 printk("VOYAGER SMP: CPU%d lost interrupt %d\n",
1702 for_each_cpu(real_cpu
, mask
) {
1704 outb(VIC_CPU_MASQUERADE_ENABLE
| real_cpu
,
1706 isr
= vic_read_isr();
1707 if(isr
& (1<<irq
)) {
1708 printk("VOYAGER SMP: CPU%d ack irq %d\n",
1712 outb(cpu
, VIC_PROCESSOR_ID
);
1715 #endif /* VOYAGER_DEBUG */
1716 /* as soon as we ack, the interrupt is eligible for
1717 * receipt by another CPU so everything must be in
1720 if(status
& IRQ_REPLAY
) {
1721 /* replay is set if we disable the interrupt
1722 * in the before_handle_vic_irq() routine, so
1723 * clear the in progress bit here to allow the
1724 * next CPU to handle this correctly */
1725 desc
->status
&= ~(IRQ_REPLAY
| IRQ_INPROGRESS
);
1727 #ifdef VOYAGER_DEBUG
1728 isr
= vic_read_isr();
1729 if((isr
& (1<<irq
)) != 0)
1730 printk("VOYAGER SMP: after_handle_vic_irq() after ack irq=%d, isr=0x%x\n",
1732 #endif /* VOYAGER_DEBUG */
1734 _raw_spin_unlock(&vic_irq_lock
);
1736 /* All code after this point is out of the main path - the IRQ
1737 * may be intercepted by another CPU if reasserted */
1741 /* Linux processor - interrupt affinity manipulations.
1743 * For each processor, we maintain a 32 bit irq affinity mask.
1744 * Initially it is set to all 1's so every processor accepts every
1745 * interrupt. In this call, we change the processor's affinity mask:
1747 * Change from enable to disable:
1749 * If the interrupt ever comes in to the processor, we will disable it
1750 * and ack it to push it off to another CPU, so just accept the mask here.
1752 * Change from disable to enable:
1754 * change the mask and then do an interrupt enable CPI to re-enable on
1755 * the selected processors */
1758 set_vic_irq_affinity(unsigned int irq
, cpumask_t mask
)
1760 /* Only extended processors handle interrupts */
1761 unsigned long real_mask
;
1762 unsigned long irq_mask
= 1 << irq
;
1765 real_mask
= cpus_addr(mask
)[0] & voyager_extended_vic_processors
;
1767 if(cpus_addr(mask
)[0] == 0)
1768 /* can't have no cpu's to accept the interrupt -- extremely
1769 * bad things will happen */
1773 /* can't change the affinity of the timer IRQ. This
1774 * is due to the constraint in the voyager
1775 * architecture that the CPI also comes in on and IRQ
1776 * line and we have chosen IRQ0 for this. If you
1777 * raise the mask on this interrupt, the processor
1778 * will no-longer be able to accept VIC CPIs */
1782 /* You can only have 32 interrupts in a voyager system
1783 * (and 32 only if you have a secondary microchannel
1787 for_each_online_cpu(cpu
) {
1788 unsigned long cpu_mask
= 1 << cpu
;
1790 if(cpu_mask
& real_mask
) {
1791 /* enable the interrupt for this cpu */
1792 cpu_irq_affinity
[cpu
] |= irq_mask
;
1794 /* disable the interrupt for this cpu */
1795 cpu_irq_affinity
[cpu
] &= ~irq_mask
;
1798 /* this is magic, we now have the correct affinity maps, so
1799 * enable the interrupt. This will send an enable CPI to
1800 * those cpu's who need to enable it in their local masks,
1801 * causing them to correct for the new affinity . If the
1802 * interrupt is currently globally disabled, it will simply be
1803 * disabled again as it comes in (voyager lazy disable). If
1804 * the affinity map is tightened to disable the interrupt on a
1805 * cpu, it will be pushed off when it comes in */
1806 enable_vic_irq(irq
);
1810 ack_vic_irq(unsigned int irq
)
1813 outb(0x62,0x20); /* Specific EOI to cascade */
1814 outb(0x60|(irq
& 7),0xA0);
1816 outb(0x60 | (irq
& 7),0x20);
1820 /* enable the CPIs. In the VIC, the CPIs are delivered by the 8259
1821 * but are not vectored by it. This means that the 8259 mask must be
1822 * lowered to receive them */
1824 vic_enable_cpi(void)
1826 __u8 cpu
= smp_processor_id();
1828 /* just take a copy of the current mask (nop for boot cpu) */
1829 vic_irq_mask
[cpu
] = vic_irq_mask
[boot_cpu_id
];
1831 enable_local_vic_irq(VIC_CPI_LEVEL0
);
1832 enable_local_vic_irq(VIC_CPI_LEVEL1
);
1833 /* for sys int and cmn int */
1834 enable_local_vic_irq(7);
1837 outb(QIC_DEFAULT_MASK0
, QIC_MASK_REGISTER0
);
1838 outb(QIC_CPI_ENABLE
, QIC_MASK_REGISTER1
);
1839 VDEBUG(("VOYAGER SMP: QIC ENABLE CPI: CPU%d: MASK 0x%x\n",
1840 cpu
, QIC_CPI_ENABLE
));
1843 VDEBUG(("VOYAGER SMP: ENABLE CPI: CPU%d: MASK 0x%x\n",
1844 cpu
, vic_irq_mask
[cpu
]));
1850 int old_cpu
= smp_processor_id(), cpu
;
1852 /* dump the interrupt masks of each processor */
1853 for_each_online_cpu(cpu
) {
1854 __u16 imr
, isr
, irr
;
1855 unsigned long flags
;
1857 local_irq_save(flags
);
1858 outb(VIC_CPU_MASQUERADE_ENABLE
| cpu
, VIC_PROCESSOR_ID
);
1859 imr
= (inb(0xa1) << 8) | inb(0x21);
1861 irr
= inb(0xa0) << 8;
1865 isr
= inb(0xa0) << 8;
1868 outb(old_cpu
, VIC_PROCESSOR_ID
);
1869 local_irq_restore(flags
);
1870 printk("\tCPU%d: mask=0x%x, IMR=0x%x, IRR=0x%x, ISR=0x%x\n",
1871 cpu
, vic_irq_mask
[cpu
], imr
, irr
, isr
);
1873 /* These lines are put in to try to unstick an un ack'd irq */
1876 for(irq
=0; irq
<16; irq
++) {
1877 if(isr
& (1<<irq
)) {
1878 printk("\tCPU%d: ack irq %d\n",
1880 local_irq_save(flags
);
1881 outb(VIC_CPU_MASQUERADE_ENABLE
| cpu
,
1884 outb(old_cpu
, VIC_PROCESSOR_ID
);
1885 local_irq_restore(flags
);
1894 smp_voyager_power_off(void *dummy
)
1896 if(smp_processor_id() == boot_cpu_id
)
1897 voyager_power_off();
1899 smp_stop_cpu_function(NULL
);
1903 smp_prepare_cpus(unsigned int max_cpus
)
1905 /* FIXME: ignore max_cpus for now */
1909 void __devinit
smp_prepare_boot_cpu(void)
1911 cpu_set(smp_processor_id(), cpu_online_map
);
1912 cpu_set(smp_processor_id(), cpu_callout_map
);
1916 __cpu_up(unsigned int cpu
)
1918 /* This only works at boot for x86. See "rewrite" above. */
1919 if (cpu_isset(cpu
, smp_commenced_mask
))
1922 /* In case one didn't come up */
1923 if (!cpu_isset(cpu
, cpu_callin_map
))
1925 /* Unleash the CPU! */
1926 cpu_set(cpu
, smp_commenced_mask
);
1927 while (!cpu_isset(cpu
, cpu_online_map
))
1933 smp_cpus_done(unsigned int max_cpus
)