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[SCSI] mvsas: remove execute permission from file
[linux-2.6/mini2440.git] / drivers / scsi / mvsas.c
blobd4a6ac3c9c4746155eca706225995344ff265e52
1 /*
2 mvsas.c - Marvell 88SE6440 SAS/SATA support
3
4 Copyright 2007 Red Hat, Inc.
5 Copyright 2008 Marvell. <kewei@marvell.com>
6
7 This program is free software; you can redistribute it and/or
8 modify it under the terms of the GNU General Public License as
9 published by the Free Software Foundation; either version 2,
10 or (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty
14 of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
15 See the GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public
18 License along with this program; see the file COPYING. If not,
19 write to the Free Software Foundation, 675 Mass Ave, Cambridge,
20 MA 02139, USA.
21
22 ---------------------------------------------------------------
23
24 Random notes:
25 * hardware supports controlling the endian-ness of data
26 structures. this permits elimination of all the le32_to_cpu()
27 and cpu_to_le32() conversions.
28
29 */
30
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/pci.h>
34 #include <linux/interrupt.h>
35 #include <linux/spinlock.h>
36 #include <linux/delay.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/ctype.h>
39 #include <scsi/libsas.h>
40 #include <asm/io.h>
41
42 #define DRV_NAME "mvsas"
43 #define DRV_VERSION "0.5"
44 #define _MV_DUMP 0
45 #define MVS_DISABLE_NVRAM
46 #define MVS_DISABLE_MSI
47
48 #define mr32(reg) readl(regs + MVS_##reg)
49 #define mw32(reg,val) writel((val), regs + MVS_##reg)
50 #define mw32_f(reg,val) do { \
51 writel((val), regs + MVS_##reg); \
52 readl(regs + MVS_##reg); \
53 } while (0)
54
55 #define MVS_ID_NOT_MAPPED 0xff
56 #define MVS_CHIP_SLOT_SZ (1U << mvi->chip->slot_width)
57
58 /* offset for D2H FIS in the Received FIS List Structure */
59 #define SATA_RECEIVED_D2H_FIS(reg_set) \
60 ((void *) mvi->rx_fis + 0x400 + 0x100 * reg_set + 0x40)
61 #define SATA_RECEIVED_PIO_FIS(reg_set) \
62 ((void *) mvi->rx_fis + 0x400 + 0x100 * reg_set + 0x20)
63 #define UNASSOC_D2H_FIS(id) \
64 ((void *) mvi->rx_fis + 0x100 * id)
65
66 #define for_each_phy(__lseq_mask, __mc, __lseq, __rest) \
67 for ((__mc) = (__lseq_mask), (__lseq) = 0; \
68 (__mc) != 0 && __rest; \
69 (++__lseq), (__mc) >>= 1)
70
71 /* driver compile-time configuration */
72 enum driver_configuration {
73 MVS_TX_RING_SZ = 1024, /* TX ring size (12-bit) */
74 MVS_RX_RING_SZ = 1024, /* RX ring size (12-bit) */
75 /* software requires power-of-2
76 ring size */
77
78 MVS_SLOTS = 512, /* command slots */
79 MVS_SLOT_BUF_SZ = 8192, /* cmd tbl + IU + status + PRD */
80 MVS_SSP_CMD_SZ = 64, /* SSP command table buffer size */
81 MVS_ATA_CMD_SZ = 96, /* SATA command table buffer size */
82 MVS_OAF_SZ = 64, /* Open address frame buffer size */
83
84 MVS_RX_FIS_COUNT = 17, /* Optional rx'd FISs (max 17) */
85
86 MVS_QUEUE_SIZE = 30, /* Support Queue depth */
87 };
88
89 /* unchangeable hardware details */
90 enum hardware_details {
91 MVS_MAX_PHYS = 8, /* max. possible phys */
92 MVS_MAX_PORTS = 8, /* max. possible ports */
93 MVS_RX_FISL_SZ = 0x400 + (MVS_RX_FIS_COUNT * 0x100),
94 };
95
96 /* peripheral registers (BAR2) */
97 enum peripheral_registers {
98 SPI_CTL = 0x10, /* EEPROM control */
99 SPI_CMD = 0x14, /* EEPROM command */
100 SPI_DATA = 0x18, /* EEPROM data */
101 };
102
103 enum peripheral_register_bits {
104 TWSI_RDY = (1U << 7), /* EEPROM interface ready */
105 TWSI_RD = (1U << 4), /* EEPROM read access */
106
107 SPI_ADDR_MASK = 0x3ffff, /* bits 17:0 */
108 };
109
110 /* enhanced mode registers (BAR4) */
111 enum hw_registers {
112 MVS_GBL_CTL = 0x04, /* global control */
113 MVS_GBL_INT_STAT = 0x08, /* global irq status */
114 MVS_GBL_PI = 0x0C, /* ports implemented bitmask */
115 MVS_GBL_PORT_TYPE = 0xa0, /* port type */
116
117 MVS_CTL = 0x100, /* SAS/SATA port configuration */
118 MVS_PCS = 0x104, /* SAS/SATA port control/status */
119 MVS_CMD_LIST_LO = 0x108, /* cmd list addr */
120 MVS_CMD_LIST_HI = 0x10C,
121 MVS_RX_FIS_LO = 0x110, /* RX FIS list addr */
122 MVS_RX_FIS_HI = 0x114,
123
124 MVS_TX_CFG = 0x120, /* TX configuration */
125 MVS_TX_LO = 0x124, /* TX (delivery) ring addr */
126 MVS_TX_HI = 0x128,
127
128 MVS_TX_PROD_IDX = 0x12C, /* TX producer pointer */
129 MVS_TX_CONS_IDX = 0x130, /* TX consumer pointer (RO) */
130 MVS_RX_CFG = 0x134, /* RX configuration */
131 MVS_RX_LO = 0x138, /* RX (completion) ring addr */
132 MVS_RX_HI = 0x13C,
133 MVS_RX_CONS_IDX = 0x140, /* RX consumer pointer (RO) */
134
135 MVS_INT_COAL = 0x148, /* Int coalescing config */
136 MVS_INT_COAL_TMOUT = 0x14C, /* Int coalescing timeout */
137 MVS_INT_STAT = 0x150, /* Central int status */
138 MVS_INT_MASK = 0x154, /* Central int enable */
139 MVS_INT_STAT_SRS = 0x158, /* SATA register set status */
140 MVS_INT_MASK_SRS = 0x15C,
141
142 /* ports 1-3 follow after this */
143 MVS_P0_INT_STAT = 0x160, /* port0 interrupt status */
144 MVS_P0_INT_MASK = 0x164, /* port0 interrupt mask */
145 MVS_P4_INT_STAT = 0x200, /* Port 4 interrupt status */
146 MVS_P4_INT_MASK = 0x204, /* Port 4 interrupt enable mask */
147
148 /* ports 1-3 follow after this */
149 MVS_P0_SER_CTLSTAT = 0x180, /* port0 serial control/status */
150 MVS_P4_SER_CTLSTAT = 0x220, /* port4 serial control/status */
151
152 MVS_CMD_ADDR = 0x1B8, /* Command register port (addr) */
153 MVS_CMD_DATA = 0x1BC, /* Command register port (data) */
154
155 /* ports 1-3 follow after this */
156 MVS_P0_CFG_ADDR = 0x1C0, /* port0 phy register address */
157 MVS_P0_CFG_DATA = 0x1C4, /* port0 phy register data */
158 MVS_P4_CFG_ADDR = 0x230, /* Port 4 config address */
159 MVS_P4_CFG_DATA = 0x234, /* Port 4 config data */
160
161 /* ports 1-3 follow after this */
162 MVS_P0_VSR_ADDR = 0x1E0, /* port0 VSR address */
163 MVS_P0_VSR_DATA = 0x1E4, /* port0 VSR data */
164 MVS_P4_VSR_ADDR = 0x250, /* port 4 VSR addr */
165 MVS_P4_VSR_DATA = 0x254, /* port 4 VSR data */
166 };
167
168 enum hw_register_bits {
169 /* MVS_GBL_CTL */
170 INT_EN = (1U << 1), /* Global int enable */
171 HBA_RST = (1U << 0), /* HBA reset */
172
173 /* MVS_GBL_INT_STAT */
174 INT_XOR = (1U << 4), /* XOR engine event */
175 INT_SAS_SATA = (1U << 0), /* SAS/SATA event */
176
177 /* MVS_GBL_PORT_TYPE */ /* shl for ports 1-3 */
178 SATA_TARGET = (1U << 16), /* port0 SATA target enable */
179 MODE_AUTO_DET_PORT7 = (1U << 15), /* port0 SAS/SATA autodetect */
180 MODE_AUTO_DET_PORT6 = (1U << 14),
181 MODE_AUTO_DET_PORT5 = (1U << 13),
182 MODE_AUTO_DET_PORT4 = (1U << 12),
183 MODE_AUTO_DET_PORT3 = (1U << 11),
184 MODE_AUTO_DET_PORT2 = (1U << 10),
185 MODE_AUTO_DET_PORT1 = (1U << 9),
186 MODE_AUTO_DET_PORT0 = (1U << 8),
187 MODE_AUTO_DET_EN = MODE_AUTO_DET_PORT0 | MODE_AUTO_DET_PORT1 |
188 MODE_AUTO_DET_PORT2 | MODE_AUTO_DET_PORT3 |
189 MODE_AUTO_DET_PORT4 | MODE_AUTO_DET_PORT5 |
190 MODE_AUTO_DET_PORT6 | MODE_AUTO_DET_PORT7,
191 MODE_SAS_PORT7_MASK = (1U << 7), /* port0 SAS(1), SATA(0) mode */
192 MODE_SAS_PORT6_MASK = (1U << 6),
193 MODE_SAS_PORT5_MASK = (1U << 5),
194 MODE_SAS_PORT4_MASK = (1U << 4),
195 MODE_SAS_PORT3_MASK = (1U << 3),
196 MODE_SAS_PORT2_MASK = (1U << 2),
197 MODE_SAS_PORT1_MASK = (1U << 1),
198 MODE_SAS_PORT0_MASK = (1U << 0),
199 MODE_SAS_SATA = MODE_SAS_PORT0_MASK | MODE_SAS_PORT1_MASK |
200 MODE_SAS_PORT2_MASK | MODE_SAS_PORT3_MASK |
201 MODE_SAS_PORT4_MASK | MODE_SAS_PORT5_MASK |
202 MODE_SAS_PORT6_MASK | MODE_SAS_PORT7_MASK,
203
204 /* SAS_MODE value may be
205 * dictated (in hw) by values
206 * of SATA_TARGET & AUTO_DET
207 */
208
209 /* MVS_TX_CFG */
210 TX_EN = (1U << 16), /* Enable TX */
211 TX_RING_SZ_MASK = 0xfff, /* TX ring size, bits 11:0 */
212
213 /* MVS_RX_CFG */
214 RX_EN = (1U << 16), /* Enable RX */
215 RX_RING_SZ_MASK = 0xfff, /* RX ring size, bits 11:0 */
216
217 /* MVS_INT_COAL */
218 COAL_EN = (1U << 16), /* Enable int coalescing */
219
220 /* MVS_INT_STAT, MVS_INT_MASK */
221 CINT_I2C = (1U << 31), /* I2C event */
222 CINT_SW0 = (1U << 30), /* software event 0 */
223 CINT_SW1 = (1U << 29), /* software event 1 */
224 CINT_PRD_BC = (1U << 28), /* PRD BC err for read cmd */
225 CINT_DMA_PCIE = (1U << 27), /* DMA to PCIE timeout */
226 CINT_MEM = (1U << 26), /* int mem parity err */
227 CINT_I2C_SLAVE = (1U << 25), /* slave I2C event */
228 CINT_SRS = (1U << 3), /* SRS event */
229 CINT_CI_STOP = (1U << 1), /* cmd issue stopped */
230 CINT_DONE = (1U << 0), /* cmd completion */
231
232 /* shl for ports 1-3 */
233 CINT_PORT_STOPPED = (1U << 16), /* port0 stopped */
234 CINT_PORT = (1U << 8), /* port0 event */
235 CINT_PORT_MASK_OFFSET = 8,
236 CINT_PORT_MASK = (0xFF << CINT_PORT_MASK_OFFSET),
237
238 /* TX (delivery) ring bits */
239 TXQ_CMD_SHIFT = 29,
240 TXQ_CMD_SSP = 1, /* SSP protocol */
241 TXQ_CMD_SMP = 2, /* SMP protocol */
242 TXQ_CMD_STP = 3, /* STP/SATA protocol */
243 TXQ_CMD_SSP_FREE_LIST = 4, /* add to SSP targ free list */
244 TXQ_CMD_SLOT_RESET = 7, /* reset command slot */
245 TXQ_MODE_I = (1U << 28), /* mode: 0=target,1=initiator */
246 TXQ_PRIO_HI = (1U << 27), /* priority: 0=normal, 1=high */
247 TXQ_SRS_SHIFT = 20, /* SATA register set */
248 TXQ_SRS_MASK = 0x7f,
249 TXQ_PHY_SHIFT = 12, /* PHY bitmap */
250 TXQ_PHY_MASK = 0xff,
251 TXQ_SLOT_MASK = 0xfff, /* slot number */
252
253 /* RX (completion) ring bits */
254 RXQ_GOOD = (1U << 23), /* Response good */
255 RXQ_SLOT_RESET = (1U << 21), /* Slot reset complete */
256 RXQ_CMD_RX = (1U << 20), /* target cmd received */
257 RXQ_ATTN = (1U << 19), /* attention */
258 RXQ_RSP = (1U << 18), /* response frame xfer'd */
259 RXQ_ERR = (1U << 17), /* err info rec xfer'd */
260 RXQ_DONE = (1U << 16), /* cmd complete */
261 RXQ_SLOT_MASK = 0xfff, /* slot number */
262
263 /* mvs_cmd_hdr bits */
264 MCH_PRD_LEN_SHIFT = 16, /* 16-bit PRD table len */
265 MCH_SSP_FR_TYPE_SHIFT = 13, /* SSP frame type */
266
267 /* SSP initiator only */
268 MCH_SSP_FR_CMD = 0x0, /* COMMAND frame */
269
270 /* SSP initiator or target */
271 MCH_SSP_FR_TASK = 0x1, /* TASK frame */
272
273 /* SSP target only */
274 MCH_SSP_FR_XFER_RDY = 0x4, /* XFER_RDY frame */
275 MCH_SSP_FR_RESP = 0x5, /* RESPONSE frame */
276 MCH_SSP_FR_READ = 0x6, /* Read DATA frame(s) */
277 MCH_SSP_FR_READ_RESP = 0x7, /* ditto, plus RESPONSE */
278
279 MCH_PASSTHRU = (1U << 12), /* pass-through (SSP) */
280 MCH_FBURST = (1U << 11), /* first burst (SSP) */
281 MCH_CHK_LEN = (1U << 10), /* chk xfer len (SSP) */
282 MCH_RETRY = (1U << 9), /* tport layer retry (SSP) */
283 MCH_PROTECTION = (1U << 8), /* protection info rec (SSP) */
284 MCH_RESET = (1U << 7), /* Reset (STP/SATA) */
285 MCH_FPDMA = (1U << 6), /* First party DMA (STP/SATA) */
286 MCH_ATAPI = (1U << 5), /* ATAPI (STP/SATA) */
287 MCH_BIST = (1U << 4), /* BIST activate (STP/SATA) */
288 MCH_PMP_MASK = 0xf, /* PMP from cmd FIS (STP/SATA)*/
289
290 CCTL_RST = (1U << 5), /* port logic reset */
291
292 /* 0(LSB first), 1(MSB first) */
293 CCTL_ENDIAN_DATA = (1U << 3), /* PRD data */
294 CCTL_ENDIAN_RSP = (1U << 2), /* response frame */
295 CCTL_ENDIAN_OPEN = (1U << 1), /* open address frame */
296 CCTL_ENDIAN_CMD = (1U << 0), /* command table */
297
298 /* MVS_Px_SER_CTLSTAT (per-phy control) */
299 PHY_SSP_RST = (1U << 3), /* reset SSP link layer */
300 PHY_BCAST_CHG = (1U << 2), /* broadcast(change) notif */
301 PHY_RST_HARD = (1U << 1), /* hard reset + phy reset */
302 PHY_RST = (1U << 0), /* phy reset */
303 PHY_MIN_SPP_PHYS_LINK_RATE_MASK = (0xF << 8),
304 PHY_MAX_SPP_PHYS_LINK_RATE_MASK = (0xF << 12),
305 PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET = (16),
306 PHY_NEG_SPP_PHYS_LINK_RATE_MASK =
307 (0xF << PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET),
308 PHY_READY_MASK = (1U << 20),
309
310 /* MVS_Px_INT_STAT, MVS_Px_INT_MASK (per-phy events) */
311 PHYEV_DEC_ERR = (1U << 24), /* Phy Decoding Error */
312 PHYEV_UNASSOC_FIS = (1U << 19), /* unassociated FIS rx'd */
313 PHYEV_AN = (1U << 18), /* SATA async notification */
314 PHYEV_BIST_ACT = (1U << 17), /* BIST activate FIS */
315 PHYEV_SIG_FIS = (1U << 16), /* signature FIS */
316 PHYEV_POOF = (1U << 12), /* phy ready from 1 -> 0 */
317 PHYEV_IU_BIG = (1U << 11), /* IU too long err */
318 PHYEV_IU_SMALL = (1U << 10), /* IU too short err */
319 PHYEV_UNK_TAG = (1U << 9), /* unknown tag */
320 PHYEV_BROAD_CH = (1U << 8), /* broadcast(CHANGE) */
321 PHYEV_COMWAKE = (1U << 7), /* COMWAKE rx'd */
322 PHYEV_PORT_SEL = (1U << 6), /* port selector present */
323 PHYEV_HARD_RST = (1U << 5), /* hard reset rx'd */
324 PHYEV_ID_TMOUT = (1U << 4), /* identify timeout */
325 PHYEV_ID_FAIL = (1U << 3), /* identify failed */
326 PHYEV_ID_DONE = (1U << 2), /* identify done */
327 PHYEV_HARD_RST_DONE = (1U << 1), /* hard reset done */
328 PHYEV_RDY_CH = (1U << 0), /* phy ready changed state */
329
330 /* MVS_PCS */
331 PCS_EN_SATA_REG_SHIFT = (16), /* Enable SATA Register Set */
332 PCS_EN_PORT_XMT_SHIFT = (12), /* Enable Port Transmit */
333 PCS_EN_PORT_XMT_SHIFT2 = (8), /* For 6480 */
334 PCS_SATA_RETRY = (1U << 8), /* retry ctl FIS on R_ERR */
335 PCS_RSP_RX_EN = (1U << 7), /* raw response rx */
336 PCS_SELF_CLEAR = (1U << 5), /* self-clearing int mode */
337 PCS_FIS_RX_EN = (1U << 4), /* FIS rx enable */
338 PCS_CMD_STOP_ERR = (1U << 3), /* cmd stop-on-err enable */
339 PCS_CMD_RST = (1U << 1), /* reset cmd issue */
340 PCS_CMD_EN = (1U << 0), /* enable cmd issue */
341
342 /* Port n Attached Device Info */
343 PORT_DEV_SSP_TRGT = (1U << 19),
344 PORT_DEV_SMP_TRGT = (1U << 18),
345 PORT_DEV_STP_TRGT = (1U << 17),
346 PORT_DEV_SSP_INIT = (1U << 11),
347 PORT_DEV_SMP_INIT = (1U << 10),
348 PORT_DEV_STP_INIT = (1U << 9),
349 PORT_PHY_ID_MASK = (0xFFU << 24),
350 PORT_DEV_TRGT_MASK = (0x7U << 17),
351 PORT_DEV_INIT_MASK = (0x7U << 9),
352 PORT_DEV_TYPE_MASK = (0x7U << 0),
353
354 /* Port n PHY Status */
355 PHY_RDY = (1U << 2),
356 PHY_DW_SYNC = (1U << 1),
357 PHY_OOB_DTCTD = (1U << 0),
358
359 /* VSR */
360 /* PHYMODE 6 (CDB) */
361 PHY_MODE6_DTL_SPEED = (1U << 27),
362 };
363
364 enum mvs_info_flags {
365 MVF_MSI = (1U << 0), /* MSI is enabled */
366 MVF_PHY_PWR_FIX = (1U << 1), /* bug workaround */
367 };
368
369 enum sas_cmd_port_registers {
370 CMD_CMRST_OOB_DET = 0x100, /* COMRESET OOB detect register */
371 CMD_CMWK_OOB_DET = 0x104, /* COMWAKE OOB detect register */
372 CMD_CMSAS_OOB_DET = 0x108, /* COMSAS OOB detect register */
373 CMD_BRST_OOB_DET = 0x10c, /* burst OOB detect register */
374 CMD_OOB_SPACE = 0x110, /* OOB space control register */
375 CMD_OOB_BURST = 0x114, /* OOB burst control register */
376 CMD_PHY_TIMER = 0x118, /* PHY timer control register */
377 CMD_PHY_CONFIG0 = 0x11c, /* PHY config register 0 */
378 CMD_PHY_CONFIG1 = 0x120, /* PHY config register 1 */
379 CMD_SAS_CTL0 = 0x124, /* SAS control register 0 */
380 CMD_SAS_CTL1 = 0x128, /* SAS control register 1 */
381 CMD_SAS_CTL2 = 0x12c, /* SAS control register 2 */
382 CMD_SAS_CTL3 = 0x130, /* SAS control register 3 */
383 CMD_ID_TEST = 0x134, /* ID test register */
384 CMD_PL_TIMER = 0x138, /* PL timer register */
385 CMD_WD_TIMER = 0x13c, /* WD timer register */
386 CMD_PORT_SEL_COUNT = 0x140, /* port selector count register */
387 CMD_APP_MEM_CTL = 0x144, /* Application Memory Control */
388 CMD_XOR_MEM_CTL = 0x148, /* XOR Block Memory Control */
389 CMD_DMA_MEM_CTL = 0x14c, /* DMA Block Memory Control */
390 CMD_PORT_MEM_CTL0 = 0x150, /* Port Memory Control 0 */
391 CMD_PORT_MEM_CTL1 = 0x154, /* Port Memory Control 1 */
392 CMD_SATA_PORT_MEM_CTL0 = 0x158, /* SATA Port Memory Control 0 */
393 CMD_SATA_PORT_MEM_CTL1 = 0x15c, /* SATA Port Memory Control 1 */
394 CMD_XOR_MEM_BIST_CTL = 0x160, /* XOR Memory BIST Control */
395 CMD_XOR_MEM_BIST_STAT = 0x164, /* XOR Memroy BIST Status */
396 CMD_DMA_MEM_BIST_CTL = 0x168, /* DMA Memory BIST Control */
397 CMD_DMA_MEM_BIST_STAT = 0x16c, /* DMA Memory BIST Status */
398 CMD_PORT_MEM_BIST_CTL = 0x170, /* Port Memory BIST Control */
399 CMD_PORT_MEM_BIST_STAT0 = 0x174, /* Port Memory BIST Status 0 */
400 CMD_PORT_MEM_BIST_STAT1 = 0x178, /* Port Memory BIST Status 1 */
401 CMD_STP_MEM_BIST_CTL = 0x17c, /* STP Memory BIST Control */
402 CMD_STP_MEM_BIST_STAT0 = 0x180, /* STP Memory BIST Status 0 */
403 CMD_STP_MEM_BIST_STAT1 = 0x184, /* STP Memory BIST Status 1 */
404 CMD_RESET_COUNT = 0x188, /* Reset Count */
405 CMD_MONTR_DATA_SEL = 0x18C, /* Monitor Data/Select */
406 CMD_PLL_PHY_CONFIG = 0x190, /* PLL/PHY Configuration */
407 CMD_PHY_CTL = 0x194, /* PHY Control and Status */
408 CMD_PHY_TEST_COUNT0 = 0x198, /* Phy Test Count 0 */
409 CMD_PHY_TEST_COUNT1 = 0x19C, /* Phy Test Count 1 */
410 CMD_PHY_TEST_COUNT2 = 0x1A0, /* Phy Test Count 2 */
411 CMD_APP_ERR_CONFIG = 0x1A4, /* Application Error Configuration */
412 CMD_PND_FIFO_CTL0 = 0x1A8, /* Pending FIFO Control 0 */
413 CMD_HOST_CTL = 0x1AC, /* Host Control Status */
414 CMD_HOST_WR_DATA = 0x1B0, /* Host Write Data */
415 CMD_HOST_RD_DATA = 0x1B4, /* Host Read Data */
416 CMD_PHY_MODE_21 = 0x1B8, /* Phy Mode 21 */
417 CMD_SL_MODE0 = 0x1BC, /* SL Mode 0 */
418 CMD_SL_MODE1 = 0x1C0, /* SL Mode 1 */
419 CMD_PND_FIFO_CTL1 = 0x1C4, /* Pending FIFO Control 1 */
420 };
421
422 /* SAS/SATA configuration port registers, aka phy registers */
423 enum sas_sata_config_port_regs {
424 PHYR_IDENTIFY = 0x00, /* info for IDENTIFY frame */
425 PHYR_ADDR_LO = 0x04, /* my SAS address (low) */
426 PHYR_ADDR_HI = 0x08, /* my SAS address (high) */
427 PHYR_ATT_DEV_INFO = 0x0C, /* attached device info */
428 PHYR_ATT_ADDR_LO = 0x10, /* attached dev SAS addr (low) */
429 PHYR_ATT_ADDR_HI = 0x14, /* attached dev SAS addr (high) */
430 PHYR_SATA_CTL = 0x18, /* SATA control */
431 PHYR_PHY_STAT = 0x1C, /* PHY status */
432 PHYR_SATA_SIG0 = 0x20, /*port SATA signature FIS(Byte 0-3) */
433 PHYR_SATA_SIG1 = 0x24, /*port SATA signature FIS(Byte 4-7) */
434 PHYR_SATA_SIG2 = 0x28, /*port SATA signature FIS(Byte 8-11) */
435 PHYR_SATA_SIG3 = 0x2c, /*port SATA signature FIS(Byte 12-15) */
436 PHYR_R_ERR_COUNT = 0x30, /* port R_ERR count register */
437 PHYR_CRC_ERR_COUNT = 0x34, /* port CRC error count register */
438 PHYR_WIDE_PORT = 0x38, /* wide port participating */
439 PHYR_CURRENT0 = 0x80, /* current connection info 0 */
440 PHYR_CURRENT1 = 0x84, /* current connection info 1 */
441 PHYR_CURRENT2 = 0x88, /* current connection info 2 */
442 };
443
444 /* SAS/SATA Vendor Specific Port Registers */
445 enum sas_sata_vsp_regs {
446 VSR_PHY_STAT = 0x00, /* Phy Status */
447 VSR_PHY_MODE1 = 0x01, /* phy tx */
448 VSR_PHY_MODE2 = 0x02, /* tx scc */
449 VSR_PHY_MODE3 = 0x03, /* pll */
450 VSR_PHY_MODE4 = 0x04, /* VCO */
451 VSR_PHY_MODE5 = 0x05, /* Rx */
452 VSR_PHY_MODE6 = 0x06, /* CDR */
453 VSR_PHY_MODE7 = 0x07, /* Impedance */
454 VSR_PHY_MODE8 = 0x08, /* Voltage */
455 VSR_PHY_MODE9 = 0x09, /* Test */
456 VSR_PHY_MODE10 = 0x0A, /* Power */
457 VSR_PHY_MODE11 = 0x0B, /* Phy Mode */
458 VSR_PHY_VS0 = 0x0C, /* Vednor Specific 0 */
459 VSR_PHY_VS1 = 0x0D, /* Vednor Specific 1 */
460 };
461
462 enum pci_cfg_registers {
463 PCR_PHY_CTL = 0x40,
464 PCR_PHY_CTL2 = 0x90,
465 PCR_DEV_CTRL = 0xE8,
466 };
467
468 enum pci_cfg_register_bits {
469 PCTL_PWR_ON = (0xFU << 24),
470 PCTL_OFF = (0xFU << 12),
471 PRD_REQ_SIZE = (0x4000),
472 PRD_REQ_MASK = (0x00007000),
473 };
474
475 enum nvram_layout_offsets {
476 NVR_SIG = 0x00, /* 0xAA, 0x55 */
477 NVR_SAS_ADDR = 0x02, /* 8-byte SAS address */
478 };
479
480 enum chip_flavors {
481 chip_6320,
482 chip_6440,
483 chip_6480,
484 };
485
486 enum port_type {
487 PORT_TYPE_SAS = (1L << 1),
488 PORT_TYPE_SATA = (1L << 0),
489 };
490
491 /* Command Table Format */
492 enum ct_format {
493 /* SSP */
494 SSP_F_H = 0x00,
495 SSP_F_IU = 0x18,
496 SSP_F_MAX = 0x4D,
497 /* STP */
498 STP_CMD_FIS = 0x00,
499 STP_ATAPI_CMD = 0x40,
500 STP_F_MAX = 0x10,
501 /* SMP */
502 SMP_F_T = 0x00,
503 SMP_F_DEP = 0x01,
504 SMP_F_MAX = 0x101,
505 };
506
507 enum status_buffer {
508 SB_EIR_OFF = 0x00, /* Error Information Record */
509 SB_RFB_OFF = 0x08, /* Response Frame Buffer */
510 SB_RFB_MAX = 0x400, /* RFB size*/
511 };
512
513 enum error_info_rec {
514 CMD_ISS_STPD = (1U << 31), /* Cmd Issue Stopped */
515 };
516
517 struct mvs_chip_info {
518 u32 n_phy;
519 u32 srs_sz;
520 u32 slot_width;
521 };
522
523 struct mvs_err_info {
524 __le32 flags;
525 __le32 flags2;
526 };
527
528 struct mvs_prd {
529 __le64 addr; /* 64-bit buffer address */
530 __le32 reserved;
531 __le32 len; /* 16-bit length */
532 };
533
534 struct mvs_cmd_hdr {
535 __le32 flags; /* PRD tbl len; SAS, SATA ctl */
536 __le32 lens; /* cmd, max resp frame len */
537 __le32 tags; /* targ port xfer tag; tag */
538 __le32 data_len; /* data xfer len */
539 __le64 cmd_tbl; /* command table address */
540 __le64 open_frame; /* open addr frame address */
541 __le64 status_buf; /* status buffer address */
542 __le64 prd_tbl; /* PRD tbl address */
543 __le32 reserved[4];
544 };
545
546 struct mvs_slot_info {
547 struct sas_task *task;
548 u32 n_elem;
549 u32 tx;
550
551 /* DMA buffer for storing cmd tbl, open addr frame, status buffer,
552 * and PRD table
553 */
554 void *buf;
555 dma_addr_t buf_dma;
556 #if _MV_DUMP
557 u32 cmd_size;
558 #endif
559
560 void *response;
561 };
562
563 struct mvs_port {
564 struct asd_sas_port sas_port;
565 u8 port_attached;
566 u8 taskfileset;
567 u8 wide_port_phymap;
568 };
569
570 struct mvs_phy {
571 struct mvs_port *port;
572 struct asd_sas_phy sas_phy;
573 struct sas_identify identify;
574 struct scsi_device *sdev;
575 u64 dev_sas_addr;
576 u64 att_dev_sas_addr;
577 u32 att_dev_info;
578 u32 dev_info;
579 u32 phy_type;
580 u32 phy_status;
581 u32 irq_status;
582 u32 frame_rcvd_size;
583 u8 frame_rcvd[32];
584 u8 phy_attached;
585 };
586
587 struct mvs_info {
588 unsigned long flags;
589
590 spinlock_t lock; /* host-wide lock */
591 struct pci_dev *pdev; /* our device */
592 void __iomem *regs; /* enhanced mode registers */
593 void __iomem *peri_regs; /* peripheral registers */
594
595 u8 sas_addr[SAS_ADDR_SIZE];
596 struct sas_ha_struct sas; /* SCSI/SAS glue */
597 struct Scsi_Host *shost;
598
599 __le32 *tx; /* TX (delivery) DMA ring */
600 dma_addr_t tx_dma;
601 u32 tx_prod; /* cached next-producer idx */
602
603 __le32 *rx; /* RX (completion) DMA ring */
604 dma_addr_t rx_dma;
605 u32 rx_cons; /* RX consumer idx */
606
607 __le32 *rx_fis; /* RX'd FIS area */
608 dma_addr_t rx_fis_dma;
609
610 struct mvs_cmd_hdr *slot; /* DMA command header slots */
611 dma_addr_t slot_dma;
612
613 const struct mvs_chip_info *chip;
614
615 unsigned long tags[MVS_SLOTS];
616 struct mvs_slot_info slot_info[MVS_SLOTS];
617 /* further per-slot information */
618 struct mvs_phy phy[MVS_MAX_PHYS];
619 struct mvs_port port[MVS_MAX_PHYS];
620
621 u32 can_queue; /* per adapter */
622 u32 tag_out; /*Get*/
623 u32 tag_in; /*Give*/
624 };
625
626 struct mvs_queue_task {
627 struct list_head list;
628
629 void *uldd_task;
630 };
631
632 static int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
633 void *funcdata);
634 static u32 mvs_read_phy_ctl(struct mvs_info *mvi, u32 port);
635 static void mvs_write_phy_ctl(struct mvs_info *mvi, u32 port, u32 val);
636 static u32 mvs_read_port_irq_stat(struct mvs_info *mvi, u32 port);
637 static void mvs_write_port_irq_stat(struct mvs_info *mvi, u32 port, u32 val);
638 static void mvs_write_port_irq_mask(struct mvs_info *mvi, u32 port, u32 val);
639 static u32 mvs_read_port_irq_mask(struct mvs_info *mvi, u32 port);
640
641 static u32 mvs_is_phy_ready(struct mvs_info *mvi, int i);
642 static void mvs_detect_porttype(struct mvs_info *mvi, int i);
643 static void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st);
644
645 static int mvs_scan_finished(struct Scsi_Host *, unsigned long);
646 static void mvs_scan_start(struct Scsi_Host *);
647 static int mvs_sas_slave_alloc(struct scsi_device *scsi_dev);
648
649 static struct scsi_transport_template *mvs_stt;
650
651 static const struct mvs_chip_info mvs_chips[] = {
652 [chip_6320] = { 2, 16, 9 },
653 [chip_6440] = { 4, 16, 9 },
654 [chip_6480] = { 8, 32, 10 },
655 };
656
657 static struct scsi_host_template mvs_sht = {
658 .module = THIS_MODULE,
659 .name = DRV_NAME,
660 .queuecommand = sas_queuecommand,
661 .target_alloc = sas_target_alloc,
662 .slave_configure = sas_slave_configure,
663 .slave_destroy = sas_slave_destroy,
664 .scan_finished = mvs_scan_finished,
665 .scan_start = mvs_scan_start,
666 .change_queue_depth = sas_change_queue_depth,
667 .change_queue_type = sas_change_queue_type,
668 .bios_param = sas_bios_param,
669 .can_queue = 1,
670 .cmd_per_lun = 1,
671 .this_id = -1,
672 .sg_tablesize = SG_ALL,
673 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
674 .use_clustering = ENABLE_CLUSTERING,
675 .eh_device_reset_handler = sas_eh_device_reset_handler,
676 .eh_bus_reset_handler = sas_eh_bus_reset_handler,
677 .slave_alloc = mvs_sas_slave_alloc,
678 .target_destroy = sas_target_destroy,
679 .ioctl = sas_ioctl,
680 };
681
682 static void mvs_hexdump(u32 size, u8 *data, u32 baseaddr)
683 {
684 u32 i;
685 u32 run;
686 u32 offset;
687
688 offset = 0;
689 while (size) {
690 printk("%08X : ", baseaddr + offset);
691 if (size >= 16)
692 run = 16;
693 else
694 run = size;
695 size -= run;
696 for (i = 0; i < 16; i++) {
697 if (i < run)
698 printk("%02X ", (u32)data[i]);
699 else
700 printk(" ");
701 }
702 printk(": ");
703 for (i = 0; i < run; i++)
704 printk("%c", isalnum(data[i]) ? data[i] : '.');
705 printk("\n");
706 data = &data[16];
707 offset += run;
708 }
709 printk("\n");
710 }
711
712 static void mvs_hba_sb_dump(struct mvs_info *mvi, u32 tag,
713 enum sas_protocol proto)
714 {
715 #if _MV_DUMP
716 u32 offset;
717 struct pci_dev *pdev = mvi->pdev;
718 struct mvs_slot_info *slot = &mvi->slot_info[tag];
719
720 offset = slot->cmd_size + MVS_OAF_SZ +
721 sizeof(struct mvs_prd) * slot->n_elem;
722 dev_printk(KERN_DEBUG, &pdev->dev, "+---->Status buffer[%d] :\n",
723 tag);
724 mvs_hexdump(32, (u8 *) slot->response,
725 (u32) slot->buf_dma + offset);
726 #endif
727 }
728
729 static void mvs_hba_memory_dump(struct mvs_info *mvi, u32 tag,
730 enum sas_protocol proto)
731 {
732 #if _MV_DUMP
733 u32 sz, w_ptr, r_ptr;
734 u64 addr;
735 void __iomem *regs = mvi->regs;
736 struct pci_dev *pdev = mvi->pdev;
737 struct mvs_slot_info *slot = &mvi->slot_info[tag];
738
739 /*Delivery Queue */
740 sz = mr32(TX_CFG) & TX_RING_SZ_MASK;
741 w_ptr = mr32(TX_PROD_IDX) & TX_RING_SZ_MASK;
742 r_ptr = mr32(TX_CONS_IDX) & TX_RING_SZ_MASK;
743 addr = mr32(TX_HI) << 16 << 16 | mr32(TX_LO);
744 dev_printk(KERN_DEBUG, &pdev->dev,
745 "Delivery Queue Size=%04d , WRT_PTR=%04X , RD_PTR=%04X\n",
746 sz, w_ptr, r_ptr);
747 dev_printk(KERN_DEBUG, &pdev->dev,
748 "Delivery Queue Base Address=0x%llX (PA)"
749 "(tx_dma=0x%llX), Entry=%04d\n",
750 addr, mvi->tx_dma, w_ptr);
751 mvs_hexdump(sizeof(u32), (u8 *)(&mvi->tx[mvi->tx_prod]),
752 (u32) mvi->tx_dma + sizeof(u32) * w_ptr);
753 /*Command List */
754 addr = mr32(CMD_LIST_HI) << 16 << 16 | mr32(CMD_LIST_LO);
755 dev_printk(KERN_DEBUG, &pdev->dev,
756 "Command List Base Address=0x%llX (PA)"
757 "(slot_dma=0x%llX), Header=%03d\n",
758 addr, mvi->slot_dma, tag);
759 dev_printk(KERN_DEBUG, &pdev->dev, "Command Header[%03d]:\n", tag);
760 /*mvs_cmd_hdr */
761 mvs_hexdump(sizeof(struct mvs_cmd_hdr), (u8 *)(&mvi->slot[tag]),
762 (u32) mvi->slot_dma + tag * sizeof(struct mvs_cmd_hdr));
763 /*1.command table area */
764 dev_printk(KERN_DEBUG, &pdev->dev, "+---->Command Table :\n");
765 mvs_hexdump(slot->cmd_size, (u8 *) slot->buf, (u32) slot->buf_dma);
766 /*2.open address frame area */
767 dev_printk(KERN_DEBUG, &pdev->dev, "+---->Open Address Frame :\n");
768 mvs_hexdump(MVS_OAF_SZ, (u8 *) slot->buf + slot->cmd_size,
769 (u32) slot->buf_dma + slot->cmd_size);
770 /*3.status buffer */
771 mvs_hba_sb_dump(mvi, tag, proto);
772 /*4.PRD table */
773 dev_printk(KERN_DEBUG, &pdev->dev, "+---->PRD table :\n");
774 mvs_hexdump(sizeof(struct mvs_prd) * slot->n_elem,
775 (u8 *) slot->buf + slot->cmd_size + MVS_OAF_SZ,
776 (u32) slot->buf_dma + slot->cmd_size + MVS_OAF_SZ);
777 #endif
778 }
779
780 static void mvs_hba_cq_dump(struct mvs_info *mvi)
781 {
782 #if _MV_DUMP
783 u64 addr;
784 void __iomem *regs = mvi->regs;
785 struct pci_dev *pdev = mvi->pdev;
786 u32 entry = mvi->rx_cons + 1;
787 u32 rx_desc = le32_to_cpu(mvi->rx[entry]);
788
789 /*Completion Queue */
790 addr = mr32(RX_HI) << 16 << 16 | mr32(RX_LO);
791 dev_printk(KERN_DEBUG, &pdev->dev, "Completion Task = 0x%08X\n",
792 (u32) mvi->slot_info[rx_desc & RXQ_SLOT_MASK].task);
793 dev_printk(KERN_DEBUG, &pdev->dev,
794 "Completion List Base Address=0x%llX (PA), "
795 "CQ_Entry=%04d, CQ_WP=0x%08X\n",
796 addr, entry - 1, mvi->rx[0]);
797 mvs_hexdump(sizeof(u32), (u8 *)(&rx_desc),
798 mvi->rx_dma + sizeof(u32) * entry);
799 #endif
800 }
801
802 static void mvs_hba_interrupt_enable(struct mvs_info *mvi)
803 {
804 void __iomem *regs = mvi->regs;
805 u32 tmp;
806
807 tmp = mr32(GBL_CTL);
808
809 mw32(GBL_CTL, tmp | INT_EN);
810 }
811
812 static void mvs_hba_interrupt_disable(struct mvs_info *mvi)
813 {
814 void __iomem *regs = mvi->regs;
815 u32 tmp;
816
817 tmp = mr32(GBL_CTL);
818
819 mw32(GBL_CTL, tmp & ~INT_EN);
820 }
821
822 static int mvs_int_rx(struct mvs_info *mvi, bool self_clear);
823
824 /* move to PCI layer or libata core? */
825 static int pci_go_64(struct pci_dev *pdev)
826 {
827 int rc;
828
829 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
830 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
831 if (rc) {
832 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
833 if (rc) {
834 dev_printk(KERN_ERR, &pdev->dev,
835 "64-bit DMA enable failed\n");
836 return rc;
837 }
838 }
839 } else {
840 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
841 if (rc) {
842 dev_printk(KERN_ERR, &pdev->dev,
843 "32-bit DMA enable failed\n");
844 return rc;
845 }
846 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
847 if (rc) {
848 dev_printk(KERN_ERR, &pdev->dev,
849 "32-bit consistent DMA enable failed\n");
850 return rc;
851 }
852 }
853
854 return rc;
855 }
856
857 static void mvs_tag_clear(struct mvs_info *mvi, u32 tag)
858 {
859 mvi->tag_in = (mvi->tag_in + 1) & (MVS_SLOTS - 1);
860 mvi->tags[mvi->tag_in] = tag;
861 }
862
863 static void mvs_tag_free(struct mvs_info *mvi, u32 tag)
864 {
865 mvi->tag_out = (mvi->tag_out - 1) & (MVS_SLOTS - 1);
866 }
867
868 static int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out)
869 {
870 if (mvi->tag_out != mvi->tag_in) {
871 *tag_out = mvi->tags[mvi->tag_out];
872 mvi->tag_out = (mvi->tag_out + 1) & (MVS_SLOTS - 1);
873 return 0;
874 }
875 return -EBUSY;
876 }
877
878 static void mvs_tag_init(struct mvs_info *mvi)
879 {
880 int i;
881 for (i = 0; i < MVS_SLOTS; ++i)
882 mvi->tags[i] = i;
883 mvi->tag_out = 0;
884 mvi->tag_in = MVS_SLOTS - 1;
885 }
886
887 #ifndef MVS_DISABLE_NVRAM
888 static int mvs_eep_read(void __iomem *regs, u32 addr, u32 *data)
889 {
890 int timeout = 1000;
891
892 if (addr & ~SPI_ADDR_MASK)
893 return -EINVAL;
894
895 writel(addr, regs + SPI_CMD);
896 writel(TWSI_RD, regs + SPI_CTL);
897
898 while (timeout-- > 0) {
899 if (readl(regs + SPI_CTL) & TWSI_RDY) {
900 *data = readl(regs + SPI_DATA);
901 return 0;
902 }
903
904 udelay(10);
905 }
906
907 return -EBUSY;
908 }
909
910 static int mvs_eep_read_buf(void __iomem *regs, u32 addr,
911 void *buf, u32 buflen)
912 {
913 u32 addr_end, tmp_addr, i, j;
914 u32 tmp = 0;
915 int rc;
916 u8 *tmp8, *buf8 = buf;
917
918 addr_end = addr + buflen;
919 tmp_addr = ALIGN(addr, 4);
920 if (addr > 0xff)
921 return -EINVAL;
922
923 j = addr & 0x3;
924 if (j) {
925 rc = mvs_eep_read(regs, tmp_addr, &tmp);
926 if (rc)
927 return rc;
928
929 tmp8 = (u8 *)&tmp;
930 for (i = j; i < 4; i++)
931 *buf8++ = tmp8[i];
932
933 tmp_addr += 4;
934 }
935
936 for (j = ALIGN(addr_end, 4); tmp_addr < j; tmp_addr += 4) {
937 rc = mvs_eep_read(regs, tmp_addr, &tmp);
938 if (rc)
939 return rc;
940
941 memcpy(buf8, &tmp, 4);
942 buf8 += 4;
943 }
944
945 if (tmp_addr < addr_end) {
946 rc = mvs_eep_read(regs, tmp_addr, &tmp);
947 if (rc)
948 return rc;
949
950 tmp8 = (u8 *)&tmp;
951 j = addr_end - tmp_addr;
952 for (i = 0; i < j; i++)
953 *buf8++ = tmp8[i];
954
955 tmp_addr += 4;
956 }
957
958 return 0;
959 }
960 #endif
961
962 static int mvs_nvram_read(struct mvs_info *mvi, u32 addr,
963 void *buf, u32 buflen)
964 {
965 #ifndef MVS_DISABLE_NVRAM
966 void __iomem *regs = mvi->regs;
967 int rc, i;
968 u32 sum;
969 u8 hdr[2], *tmp;
970 const char *msg;
971
972 rc = mvs_eep_read_buf(regs, addr, &hdr, 2);
973 if (rc) {
974 msg = "nvram hdr read failed";
975 goto err_out;
976 }
977 rc = mvs_eep_read_buf(regs, addr + 2, buf, buflen);
978 if (rc) {
979 msg = "nvram read failed";
980 goto err_out;
981 }
982
983 if (hdr[0] != 0x5A) {
984 /* entry id */
985 msg = "invalid nvram entry id";
986 rc = -ENOENT;
987 goto err_out;
988 }
989
990 tmp = buf;
991 sum = ((u32)hdr[0]) + ((u32)hdr[1]);
992 for (i = 0; i < buflen; i++)
993 sum += ((u32)tmp[i]);
994
995 if (sum) {
996 msg = "nvram checksum failure";
997 rc = -EILSEQ;
998 goto err_out;
999 }
1000
1001 return 0;
1002
1003 err_out:
1004 dev_printk(KERN_ERR, &mvi->pdev->dev, "%s", msg);
1005 return rc;
1006 #else
1007 /* FIXME , For SAS target mode */
1008 memcpy(buf, "\x00\x00\xab\x11\x30\x04\x05\x50", 8);
1009 return 0;
1010 #endif
1011 }
1012
1013 static void mvs_bytes_dmaed(struct mvs_info *mvi, int i)
1014 {
1015 struct mvs_phy *phy = &mvi->phy[i];
1016
1017 if (!phy->phy_attached)
1018 return;
1019
1020 if (phy->phy_type & PORT_TYPE_SAS) {
1021 struct sas_identify_frame *id;
1022
1023 id = (struct sas_identify_frame *)phy->frame_rcvd;
1024 id->dev_type = phy->identify.device_type;
1025 id->initiator_bits = SAS_PROTOCOL_ALL;
1026 id->target_bits = phy->identify.target_port_protocols;
1027 } else if (phy->phy_type & PORT_TYPE_SATA) {
1028 /* TODO */
1029 }
1030 mvi->sas.sas_phy[i]->frame_rcvd_size = phy->frame_rcvd_size;
1031 mvi->sas.notify_port_event(mvi->sas.sas_phy[i],
1032 PORTE_BYTES_DMAED);
1033 }
1034
1035 static int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time)
1036 {
1037 /* give the phy enabling interrupt event time to come in (1s
1038 * is empirically about all it takes) */
1039 if (time < HZ)
1040 return 0;
1041 /* Wait for discovery to finish */
1042 scsi_flush_work(shost);
1043 return 1;
1044 }
1045
1046 static void mvs_scan_start(struct Scsi_Host *shost)
1047 {
1048 int i;
1049 struct mvs_info *mvi = SHOST_TO_SAS_HA(shost)->lldd_ha;
1050
1051 for (i = 0; i < mvi->chip->n_phy; ++i) {
1052 mvs_bytes_dmaed(mvi, i);
1053 }
1054 }
1055
1056 static int mvs_sas_slave_alloc(struct scsi_device *scsi_dev)
1057 {
1058 int rc;
1059
1060 rc = sas_slave_alloc(scsi_dev);
1061
1062 return rc;
1063 }
1064
1065 static void mvs_int_port(struct mvs_info *mvi, int port_no, u32 events)
1066 {
1067 struct pci_dev *pdev = mvi->pdev;
1068 struct sas_ha_struct *sas_ha = &mvi->sas;
1069 struct mvs_phy *phy = &mvi->phy[port_no];
1070 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1071
1072 phy->irq_status = mvs_read_port_irq_stat(mvi, port_no);
1073 /*
1074 * events is port event now ,
1075 * we need check the interrupt status which belongs to per port.
1076 */
1077 dev_printk(KERN_DEBUG, &pdev->dev,
1078 "Port %d Event = %X\n",
1079 port_no, phy->irq_status);
1080
1081 if (phy->irq_status & (PHYEV_POOF | PHYEV_DEC_ERR)) {
1082 if (!mvs_is_phy_ready(mvi, port_no)) {
1083 sas_phy_disconnected(sas_phy);
1084 sas_ha->notify_phy_event(sas_phy, PHYE_LOSS_OF_SIGNAL);
1085 } else
1086 mvs_phy_control(sas_phy, PHY_FUNC_LINK_RESET, NULL);
1087 }
1088 if (!(phy->irq_status & PHYEV_DEC_ERR)) {
1089 if (phy->irq_status & PHYEV_COMWAKE) {
1090 u32 tmp = mvs_read_port_irq_mask(mvi, port_no);
1091 mvs_write_port_irq_mask(mvi, port_no,
1092 tmp | PHYEV_SIG_FIS);
1093 }
1094 if (phy->irq_status & (PHYEV_SIG_FIS | PHYEV_ID_DONE)) {
1095 phy->phy_status = mvs_is_phy_ready(mvi, port_no);
1096 if (phy->phy_status) {
1097 mvs_detect_porttype(mvi, port_no);
1098
1099 if (phy->phy_type & PORT_TYPE_SATA) {
1100 u32 tmp = mvs_read_port_irq_mask(mvi,
1101 port_no);
1102 tmp &= ~PHYEV_SIG_FIS;
1103 mvs_write_port_irq_mask(mvi,
1104 port_no, tmp);
1105 }
1106
1107 mvs_update_phyinfo(mvi, port_no, 0);
1108 sas_ha->notify_phy_event(sas_phy,
1109 PHYE_OOB_DONE);
1110 mvs_bytes_dmaed(mvi, port_no);
1111 } else {
1112 dev_printk(KERN_DEBUG, &pdev->dev,
1113 "plugin interrupt but phy is gone\n");
1114 mvs_phy_control(sas_phy, PHY_FUNC_LINK_RESET,
1115 NULL);
1116 }
1117 } else if (phy->irq_status & PHYEV_BROAD_CH)
1118 sas_ha->notify_port_event(sas_phy,
1119 PORTE_BROADCAST_RCVD);
1120 }
1121 mvs_write_port_irq_stat(mvi, port_no, phy->irq_status);
1122 }
1123
1124 static void mvs_int_sata(struct mvs_info *mvi)
1125 {
1126 /* FIXME */
1127 }
1128
1129 static void mvs_slot_free(struct mvs_info *mvi, struct sas_task *task,
1130 struct mvs_slot_info *slot, u32 slot_idx)
1131 {
1132 if (!sas_protocol_ata(task->task_proto))
1133 if (slot->n_elem)
1134 pci_unmap_sg(mvi->pdev, task->scatter,
1135 slot->n_elem, task->data_dir);
1136
1137 switch (task->task_proto) {
1138 case SAS_PROTOCOL_SMP:
1139 pci_unmap_sg(mvi->pdev, &task->smp_task.smp_resp, 1,
1140 PCI_DMA_FROMDEVICE);
1141 pci_unmap_sg(mvi->pdev, &task->smp_task.smp_req, 1,
1142 PCI_DMA_TODEVICE);
1143 break;
1144
1145 case SAS_PROTOCOL_SATA:
1146 case SAS_PROTOCOL_STP:
1147 case SAS_PROTOCOL_SSP:
1148 default:
1149 /* do nothing */
1150 break;
1151 }
1152
1153 slot->task = NULL;
1154 mvs_tag_clear(mvi, slot_idx);
1155 }
1156
1157 static void mvs_slot_err(struct mvs_info *mvi, struct sas_task *task,
1158 u32 slot_idx)
1159 {
1160 struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
1161 u64 err_dw0 = *(u32 *) slot->response;
1162 void __iomem *regs = mvi->regs;
1163 u32 tmp;
1164
1165 if (err_dw0 & CMD_ISS_STPD)
1166 if (sas_protocol_ata(task->task_proto)) {
1167 tmp = mr32(INT_STAT_SRS);
1168 mw32(INT_STAT_SRS, tmp & 0xFFFF);
1169 }
1170
1171 mvs_hba_sb_dump(mvi, slot_idx, task->task_proto);
1172 }
1173
1174 static int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc)
1175 {
1176 u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
1177 struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
1178 struct sas_task *task = slot->task;
1179 struct task_status_struct *tstat = &task->task_status;
1180 struct mvs_port *port = &mvi->port[task->dev->port->id];
1181 bool aborted;
1182 void *to;
1183
1184 spin_lock(&task->task_state_lock);
1185 aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
1186 if (!aborted) {
1187 task->task_state_flags &=
1188 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1189 task->task_state_flags |= SAS_TASK_STATE_DONE;
1190 }
1191 spin_unlock(&task->task_state_lock);
1192
1193 if (aborted)
1194 return -1;
1195
1196 memset(tstat, 0, sizeof(*tstat));
1197 tstat->resp = SAS_TASK_COMPLETE;
1198
1199
1200 if (unlikely(!port->port_attached)) {
1201 tstat->stat = SAS_PHY_DOWN;
1202 goto out;
1203 }
1204
1205 /* error info record present */
1206 if ((rx_desc & RXQ_ERR) && (*(u64 *) slot->response)) {
1207 tstat->stat = SAM_CHECK_COND;
1208 mvs_slot_err(mvi, task, slot_idx);
1209 goto out;
1210 }
1211
1212 switch (task->task_proto) {
1213 case SAS_PROTOCOL_SSP:
1214 /* hw says status == 0, datapres == 0 */
1215 if (rx_desc & RXQ_GOOD) {
1216 tstat->stat = SAM_GOOD;
1217 tstat->resp = SAS_TASK_COMPLETE;
1218 }
1219 /* response frame present */
1220 else if (rx_desc & RXQ_RSP) {
1221 struct ssp_response_iu *iu =
1222 slot->response + sizeof(struct mvs_err_info);
1223 sas_ssp_task_response(&mvi->pdev->dev, task, iu);
1224 }
1225
1226 /* should never happen? */
1227 else
1228 tstat->stat = SAM_CHECK_COND;
1229 break;
1230
1231 case SAS_PROTOCOL_SMP: {
1232 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1233 tstat->stat = SAM_GOOD;
1234 to = kmap_atomic(sg_page(sg_resp), KM_IRQ0);
1235 memcpy(to + sg_resp->offset,
1236 slot->response + sizeof(struct mvs_err_info),
1237 sg_dma_len(sg_resp));
1238 kunmap_atomic(to, KM_IRQ0);
1239 break;
1240 }
1241
1242 case SAS_PROTOCOL_SATA:
1243 case SAS_PROTOCOL_STP:
1244 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: {
1245 struct ata_task_resp *resp =
1246 (struct ata_task_resp *)tstat->buf;
1247
1248 if ((rx_desc & (RXQ_DONE | RXQ_ERR | RXQ_ATTN)) ==
1249 RXQ_DONE)
1250 tstat->stat = SAM_GOOD;
1251 else
1252 tstat->stat = SAM_CHECK_COND;
1253
1254 resp->frame_len = sizeof(struct dev_to_host_fis);
1255 memcpy(&resp->ending_fis[0],
1256 SATA_RECEIVED_D2H_FIS(port->taskfileset),
1257 sizeof(struct dev_to_host_fis));
1258 if (resp->ending_fis[2] & ATA_ERR)
1259 mvs_hexdump(16, resp->ending_fis, 0);
1260 break;
1261 }
1262
1263 default:
1264 tstat->stat = SAM_CHECK_COND;
1265 break;
1266 }
1267
1268 out:
1269 mvs_slot_free(mvi, task, slot, slot_idx);
1270 task->task_done(task);
1271 return tstat->stat;
1272 }
1273
1274 static void mvs_int_full(struct mvs_info *mvi)
1275 {
1276 void __iomem *regs = mvi->regs;
1277 u32 tmp, stat;
1278 int i;
1279
1280 stat = mr32(INT_STAT);
1281
1282 mvs_int_rx(mvi, false);
1283
1284 for (i = 0; i < MVS_MAX_PORTS; i++) {
1285 tmp = (stat >> i) & (CINT_PORT | CINT_PORT_STOPPED);
1286 if (tmp)
1287 mvs_int_port(mvi, i, tmp);
1288 }
1289
1290 if (stat & CINT_SRS)
1291 mvs_int_sata(mvi);
1292
1293 mw32(INT_STAT, stat);
1294 }
1295
1296 static int mvs_int_rx(struct mvs_info *mvi, bool self_clear)
1297 {
1298 void __iomem *regs = mvi->regs;
1299 u32 rx_prod_idx, rx_desc;
1300 bool attn = false;
1301 struct pci_dev *pdev = mvi->pdev;
1302
1303 /* the first dword in the RX ring is special: it contains
1304 * a mirror of the hardware's RX producer index, so that
1305 * we don't have to stall the CPU reading that register.
1306 * The actual RX ring is offset by one dword, due to this.
1307 */
1308 rx_prod_idx = mr32(RX_CONS_IDX) & RX_RING_SZ_MASK;
1309 if (rx_prod_idx == 0xfff) { /* h/w hasn't touched RX ring yet */
1310 mvi->rx_cons = 0xfff;
1311 return 0;
1312 }
1313
1314 /* The CMPL_Q may come late, read from register and try again
1315 * note: if coalescing is enabled,
1316 * it will need to read from register every time for sure
1317 */
1318 if (mvi->rx_cons == rx_prod_idx)
1319 return 0;
1320
1321 if (mvi->rx_cons == 0xfff)
1322 mvi->rx_cons = MVS_RX_RING_SZ - 1;
1323
1324 while (mvi->rx_cons != rx_prod_idx) {
1325
1326 /* increment our internal RX consumer pointer */
1327 mvi->rx_cons = (mvi->rx_cons + 1) & (MVS_RX_RING_SZ - 1);
1328
1329 rx_desc = le32_to_cpu(mvi->rx[mvi->rx_cons + 1]);
1330
1331 mvs_hba_cq_dump(mvi);
1332
1333 if (unlikely(rx_desc & RXQ_DONE))
1334 mvs_slot_complete(mvi, rx_desc);
1335 if (rx_desc & RXQ_ATTN) {
1336 attn = true;
1337 dev_printk(KERN_DEBUG, &pdev->dev, "ATTN %X\n",
1338 rx_desc);
1339 } else if (rx_desc & RXQ_ERR) {
1340 dev_printk(KERN_DEBUG, &pdev->dev, "RXQ_ERR %X\n",
1341 rx_desc);
1342 }
1343 }
1344
1345 if (attn && self_clear)
1346 mvs_int_full(mvi);
1347
1348 return 0;
1349 }
1350
1351 static irqreturn_t mvs_interrupt(int irq, void *opaque)
1352 {
1353 struct mvs_info *mvi = opaque;
1354 void __iomem *regs = mvi->regs;
1355 u32 stat;
1356
1357 stat = mr32(GBL_INT_STAT);
1358
1359 /* clear CMD_CMPLT ASAP */
1360 mw32_f(INT_STAT, CINT_DONE);
1361
1362 if (stat == 0 || stat == 0xffffffff)
1363 return IRQ_NONE;
1364
1365 spin_lock(&mvi->lock);
1366
1367 mvs_int_full(mvi);
1368
1369 spin_unlock(&mvi->lock);
1370
1371 return IRQ_HANDLED;
1372 }
1373
1374 #ifndef MVS_DISABLE_MSI
1375 static irqreturn_t mvs_msi_interrupt(int irq, void *opaque)
1376 {
1377 struct mvs_info *mvi = opaque;
1378
1379 spin_lock(&mvi->lock);
1380
1381 mvs_int_rx(mvi, true);
1382
1383 spin_unlock(&mvi->lock);
1384
1385 return IRQ_HANDLED;
1386 }
1387 #endif
1388
1389 struct mvs_task_exec_info {
1390 struct sas_task *task;
1391 struct mvs_cmd_hdr *hdr;
1392 struct mvs_port *port;
1393 u32 tag;
1394 int n_elem;
1395 };
1396
1397 static int mvs_task_prep_smp(struct mvs_info *mvi,
1398 struct mvs_task_exec_info *tei)
1399 {
1400 int elem, rc, i;
1401 struct sas_task *task = tei->task;
1402 struct mvs_cmd_hdr *hdr = tei->hdr;
1403 struct scatterlist *sg_req, *sg_resp;
1404 u32 req_len, resp_len, tag = tei->tag;
1405 void *buf_tmp;
1406 u8 *buf_oaf;
1407 dma_addr_t buf_tmp_dma;
1408 struct mvs_prd *buf_prd;
1409 struct scatterlist *sg;
1410 struct mvs_slot_info *slot = &mvi->slot_info[tag];
1411 struct asd_sas_port *sas_port = task->dev->port;
1412 u32 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
1413 #if _MV_DUMP
1414 u8 *buf_cmd;
1415 void *from;
1416 #endif
1417 /*
1418 * DMA-map SMP request, response buffers
1419 */
1420 sg_req = &task->smp_task.smp_req;
1421 elem = pci_map_sg(mvi->pdev, sg_req, 1, PCI_DMA_TODEVICE);
1422 if (!elem)
1423 return -ENOMEM;
1424 req_len = sg_dma_len(sg_req);
1425
1426 sg_resp = &task->smp_task.smp_resp;
1427 elem = pci_map_sg(mvi->pdev, sg_resp, 1, PCI_DMA_FROMDEVICE);
1428 if (!elem) {
1429 rc = -ENOMEM;
1430 goto err_out;
1431 }
1432 resp_len = sg_dma_len(sg_resp);
1433
1434 /* must be in dwords */
1435 if ((req_len & 0x3) || (resp_len & 0x3)) {
1436 rc = -EINVAL;
1437 goto err_out_2;
1438 }
1439
1440 /*
1441 * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
1442 */
1443
1444 /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ************** */
1445 buf_tmp = slot->buf;
1446 buf_tmp_dma = slot->buf_dma;
1447
1448 #if _MV_DUMP
1449 buf_cmd = buf_tmp;
1450 hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
1451 buf_tmp += req_len;
1452 buf_tmp_dma += req_len;
1453 slot->cmd_size = req_len;
1454 #else
1455 hdr->cmd_tbl = cpu_to_le64(sg_dma_address(sg_req));
1456 #endif
1457
1458 /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
1459 buf_oaf = buf_tmp;
1460 hdr->open_frame = cpu_to_le64(buf_tmp_dma);
1461
1462 buf_tmp += MVS_OAF_SZ;
1463 buf_tmp_dma += MVS_OAF_SZ;
1464
1465 /* region 3: PRD table ********************************************* */
1466 buf_prd = buf_tmp;
1467 if (tei->n_elem)
1468 hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
1469 else
1470 hdr->prd_tbl = 0;
1471
1472 i = sizeof(struct mvs_prd) * tei->n_elem;
1473 buf_tmp += i;
1474 buf_tmp_dma += i;
1475
1476 /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
1477 slot->response = buf_tmp;
1478 hdr->status_buf = cpu_to_le64(buf_tmp_dma);
1479
1480 /*
1481 * Fill in TX ring and command slot header
1482 */
1483 slot->tx = mvi->tx_prod;
1484 mvi->tx[mvi->tx_prod] = cpu_to_le32((TXQ_CMD_SMP << TXQ_CMD_SHIFT) |
1485 TXQ_MODE_I | tag |
1486 (sas_port->phy_mask << TXQ_PHY_SHIFT));
1487
1488 hdr->flags |= flags;
1489 hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | ((req_len - 4) / 4));
1490 hdr->tags = cpu_to_le32(tag);
1491 hdr->data_len = 0;
1492
1493 /* generate open address frame hdr (first 12 bytes) */
1494 buf_oaf[0] = (1 << 7) | (0 << 4) | 0x01; /* initiator, SMP, ftype 1h */
1495 buf_oaf[1] = task->dev->linkrate & 0xf;
1496 *(u16 *)(buf_oaf + 2) = 0xFFFF; /* SAS SPEC */
1497 memcpy(buf_oaf + 4, task->dev->sas_addr, SAS_ADDR_SIZE);
1498
1499 /* fill in PRD (scatter/gather) table, if any */
1500 for_each_sg(task->scatter, sg, tei->n_elem, i) {
1501 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
1502 buf_prd->len = cpu_to_le32(sg_dma_len(sg));
1503 buf_prd++;
1504 }
1505
1506 #if _MV_DUMP
1507 /* copy cmd table */
1508 from = kmap_atomic(sg_page(sg_req), KM_IRQ0);
1509 memcpy(buf_cmd, from + sg_req->offset, req_len);
1510 kunmap_atomic(from, KM_IRQ0);
1511 #endif
1512 return 0;
1513
1514 err_out_2:
1515 pci_unmap_sg(mvi->pdev, &tei->task->smp_task.smp_resp, 1,
1516 PCI_DMA_FROMDEVICE);
1517 err_out:
1518 pci_unmap_sg(mvi->pdev, &tei->task->smp_task.smp_req, 1,
1519 PCI_DMA_TODEVICE);
1520 return rc;
1521 }
1522
1523 static void mvs_free_reg_set(struct mvs_info *mvi, struct mvs_port *port)
1524 {
1525 void __iomem *regs = mvi->regs;
1526 u32 tmp, offs;
1527 u8 *tfs = &port->taskfileset;
1528
1529 if (*tfs == MVS_ID_NOT_MAPPED)
1530 return;
1531
1532 offs = 1U << ((*tfs & 0x0f) + PCS_EN_SATA_REG_SHIFT);
1533 if (*tfs < 16) {
1534 tmp = mr32(PCS);
1535 mw32(PCS, tmp & ~offs);
1536 } else {
1537 tmp = mr32(CTL);
1538 mw32(CTL, tmp & ~offs);
1539 }
1540
1541 tmp = mr32(INT_STAT_SRS) & (1U << *tfs);
1542 if (tmp)
1543 mw32(INT_STAT_SRS, tmp);
1544
1545 *tfs = MVS_ID_NOT_MAPPED;
1546 }
1547
1548 static u8 mvs_assign_reg_set(struct mvs_info *mvi, struct mvs_port *port)
1549 {
1550 int i;
1551 u32 tmp, offs;
1552 void __iomem *regs = mvi->regs;
1553
1554 if (port->taskfileset != MVS_ID_NOT_MAPPED)
1555 return 0;
1556
1557 tmp = mr32(PCS);
1558
1559 for (i = 0; i < mvi->chip->srs_sz; i++) {
1560 if (i == 16)
1561 tmp = mr32(CTL);
1562 offs = 1U << ((i & 0x0f) + PCS_EN_SATA_REG_SHIFT);
1563 if (!(tmp & offs)) {
1564 port->taskfileset = i;
1565
1566 if (i < 16)
1567 mw32(PCS, tmp | offs);
1568 else
1569 mw32(CTL, tmp | offs);
1570 tmp = mr32(INT_STAT_SRS) & (1U << i);
1571 if (tmp)
1572 mw32(INT_STAT_SRS, tmp);
1573 return 0;
1574 }
1575 }
1576 return MVS_ID_NOT_MAPPED;
1577 }
1578
1579 static u32 mvs_get_ncq_tag(struct sas_task *task)
1580 {
1581 u32 tag = 0;
1582 struct ata_queued_cmd *qc = task->uldd_task;
1583
1584 if (qc)
1585 tag = qc->tag;
1586
1587 return tag;
1588 }
1589
1590 static int mvs_task_prep_ata(struct mvs_info *mvi,
1591 struct mvs_task_exec_info *tei)
1592 {
1593 struct sas_task *task = tei->task;
1594 struct domain_device *dev = task->dev;
1595 struct mvs_cmd_hdr *hdr = tei->hdr;
1596 struct asd_sas_port *sas_port = dev->port;
1597 struct mvs_slot_info *slot;
1598 struct scatterlist *sg;
1599 struct mvs_prd *buf_prd;
1600 struct mvs_port *port = tei->port;
1601 u32 tag = tei->tag;
1602 u32 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
1603 void *buf_tmp;
1604 u8 *buf_cmd, *buf_oaf;
1605 dma_addr_t buf_tmp_dma;
1606 u32 i, req_len, resp_len;
1607 const u32 max_resp_len = SB_RFB_MAX;
1608
1609 if (mvs_assign_reg_set(mvi, port) == MVS_ID_NOT_MAPPED)
1610 return -EBUSY;
1611
1612 slot = &mvi->slot_info[tag];
1613 slot->tx = mvi->tx_prod;
1614 mvi->tx[mvi->tx_prod] = cpu_to_le32(TXQ_MODE_I | tag |
1615 (TXQ_CMD_STP << TXQ_CMD_SHIFT) |
1616 (sas_port->phy_mask << TXQ_PHY_SHIFT) |
1617 (port->taskfileset << TXQ_SRS_SHIFT));
1618
1619 if (task->ata_task.use_ncq)
1620 flags |= MCH_FPDMA;
1621 if (dev->sata_dev.command_set == ATAPI_COMMAND_SET) {
1622 if (task->ata_task.fis.command != ATA_CMD_ID_ATAPI)
1623 flags |= MCH_ATAPI;
1624 }
1625
1626 /* FIXME: fill in port multiplier number */
1627
1628 hdr->flags = cpu_to_le32(flags);
1629
1630 /* FIXME: the low order order 5 bits for the TAG if enable NCQ */
1631 if (task->ata_task.use_ncq) {
1632 hdr->tags = cpu_to_le32(mvs_get_ncq_tag(task));
1633 /*Fill in task file */
1634 task->ata_task.fis.sector_count = hdr->tags << 3;
1635 } else
1636 hdr->tags = cpu_to_le32(tag);
1637 hdr->data_len = cpu_to_le32(task->total_xfer_len);
1638
1639 /*
1640 * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
1641 */
1642
1643 /* region 1: command table area (MVS_ATA_CMD_SZ bytes) ************** */
1644 buf_cmd = buf_tmp = slot->buf;
1645 buf_tmp_dma = slot->buf_dma;
1646
1647 hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
1648
1649 buf_tmp += MVS_ATA_CMD_SZ;
1650 buf_tmp_dma += MVS_ATA_CMD_SZ;
1651 #if _MV_DUMP
1652 slot->cmd_size = MVS_ATA_CMD_SZ;
1653 #endif
1654
1655 /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
1656 /* used for STP. unused for SATA? */
1657 buf_oaf = buf_tmp;
1658 hdr->open_frame = cpu_to_le64(buf_tmp_dma);
1659
1660 buf_tmp += MVS_OAF_SZ;
1661 buf_tmp_dma += MVS_OAF_SZ;
1662
1663 /* region 3: PRD table ********************************************* */
1664 buf_prd = buf_tmp;
1665 if (tei->n_elem)
1666 hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
1667 else
1668 hdr->prd_tbl = 0;
1669
1670 i = sizeof(struct mvs_prd) * tei->n_elem;
1671 buf_tmp += i;
1672 buf_tmp_dma += i;
1673
1674 /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
1675 /* FIXME: probably unused, for SATA. kept here just in case
1676 * we get a STP/SATA error information record
1677 */
1678 slot->response = buf_tmp;
1679 hdr->status_buf = cpu_to_le64(buf_tmp_dma);
1680
1681 req_len = sizeof(struct host_to_dev_fis);
1682 resp_len = MVS_SLOT_BUF_SZ - MVS_ATA_CMD_SZ -
1683 sizeof(struct mvs_err_info) - i;
1684
1685 /* request, response lengths */
1686 resp_len = min(resp_len, max_resp_len);
1687 hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
1688
1689 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1690 /* fill in command FIS and ATAPI CDB */
1691 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1692 if (dev->sata_dev.command_set == ATAPI_COMMAND_SET)
1693 memcpy(buf_cmd + STP_ATAPI_CMD,
1694 task->ata_task.atapi_packet, 16);
1695
1696 /* generate open address frame hdr (first 12 bytes) */
1697 buf_oaf[0] = (1 << 7) | (2 << 4) | 0x1; /* initiator, STP, ftype 1h */
1698 buf_oaf[1] = task->dev->linkrate & 0xf;
1699 *(u16 *)(buf_oaf + 2) = cpu_to_be16(tag);
1700 memcpy(buf_oaf + 4, task->dev->sas_addr, SAS_ADDR_SIZE);
1701
1702 /* fill in PRD (scatter/gather) table, if any */
1703 for_each_sg(task->scatter, sg, tei->n_elem, i) {
1704 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
1705 buf_prd->len = cpu_to_le32(sg_dma_len(sg));
1706 buf_prd++;
1707 }
1708
1709 return 0;
1710 }
1711
1712 static int mvs_task_prep_ssp(struct mvs_info *mvi,
1713 struct mvs_task_exec_info *tei)
1714 {
1715 struct sas_task *task = tei->task;
1716 struct mvs_cmd_hdr *hdr = tei->hdr;
1717 struct mvs_port *port = tei->port;
1718 struct mvs_slot_info *slot;
1719 struct scatterlist *sg;
1720 struct mvs_prd *buf_prd;
1721 struct ssp_frame_hdr *ssp_hdr;
1722 void *buf_tmp;
1723 u8 *buf_cmd, *buf_oaf, fburst = 0;
1724 dma_addr_t buf_tmp_dma;
1725 u32 flags;
1726 u32 resp_len, req_len, i, tag = tei->tag;
1727 const u32 max_resp_len = SB_RFB_MAX;
1728
1729 slot = &mvi->slot_info[tag];
1730
1731 slot->tx = mvi->tx_prod;
1732 mvi->tx[mvi->tx_prod] = cpu_to_le32(TXQ_MODE_I | tag |
1733 (TXQ_CMD_SSP << TXQ_CMD_SHIFT) |
1734 (port->wide_port_phymap << TXQ_PHY_SHIFT));
1735
1736 flags = MCH_RETRY;
1737 if (task->ssp_task.enable_first_burst) {
1738 flags |= MCH_FBURST;
1739 fburst = (1 << 7);
1740 }
1741 hdr->flags = cpu_to_le32(flags |
1742 (tei->n_elem << MCH_PRD_LEN_SHIFT) |
1743 (MCH_SSP_FR_CMD << MCH_SSP_FR_TYPE_SHIFT));
1744
1745 hdr->tags = cpu_to_le32(tag);
1746 hdr->data_len = cpu_to_le32(task->total_xfer_len);
1747
1748 /*
1749 * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
1750 */
1751
1752 /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ************** */
1753 buf_cmd = buf_tmp = slot->buf;
1754 buf_tmp_dma = slot->buf_dma;
1755
1756 hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
1757
1758 buf_tmp += MVS_SSP_CMD_SZ;
1759 buf_tmp_dma += MVS_SSP_CMD_SZ;
1760 #if _MV_DUMP
1761 slot->cmd_size = MVS_SSP_CMD_SZ;
1762 #endif
1763
1764 /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
1765 buf_oaf = buf_tmp;
1766 hdr->open_frame = cpu_to_le64(buf_tmp_dma);
1767
1768 buf_tmp += MVS_OAF_SZ;
1769 buf_tmp_dma += MVS_OAF_SZ;
1770
1771 /* region 3: PRD table ********************************************* */
1772 buf_prd = buf_tmp;
1773 if (tei->n_elem)
1774 hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
1775 else
1776 hdr->prd_tbl = 0;
1777
1778 i = sizeof(struct mvs_prd) * tei->n_elem;
1779 buf_tmp += i;
1780 buf_tmp_dma += i;
1781
1782 /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
1783 slot->response = buf_tmp;
1784 hdr->status_buf = cpu_to_le64(buf_tmp_dma);
1785
1786 resp_len = MVS_SLOT_BUF_SZ - MVS_SSP_CMD_SZ - MVS_OAF_SZ -
1787 sizeof(struct mvs_err_info) - i;
1788 resp_len = min(resp_len, max_resp_len);
1789
1790 req_len = sizeof(struct ssp_frame_hdr) + 28;
1791
1792 /* request, response lengths */
1793 hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
1794
1795 /* generate open address frame hdr (first 12 bytes) */
1796 buf_oaf[0] = (1 << 7) | (1 << 4) | 0x1; /* initiator, SSP, ftype 1h */
1797 buf_oaf[1] = task->dev->linkrate & 0xf;
1798 *(u16 *)(buf_oaf + 2) = cpu_to_be16(tag);
1799 memcpy(buf_oaf + 4, task->dev->sas_addr, SAS_ADDR_SIZE);
1800
1801 /* fill in SSP frame header (Command Table.SSP frame header) */
1802 ssp_hdr = (struct ssp_frame_hdr *)buf_cmd;
1803 ssp_hdr->frame_type = SSP_COMMAND;
1804 memcpy(ssp_hdr->hashed_dest_addr, task->dev->hashed_sas_addr,
1805 HASHED_SAS_ADDR_SIZE);
1806 memcpy(ssp_hdr->hashed_src_addr,
1807 task->dev->port->ha->hashed_sas_addr, HASHED_SAS_ADDR_SIZE);
1808 ssp_hdr->tag = cpu_to_be16(tag);
1809
1810 /* fill in command frame IU */
1811 buf_cmd += sizeof(*ssp_hdr);
1812 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1813 buf_cmd[9] = fburst | task->ssp_task.task_attr |
1814 (task->ssp_task.task_prio << 3);
1815 memcpy(buf_cmd + 12, &task->ssp_task.cdb, 16);
1816
1817 /* fill in PRD (scatter/gather) table, if any */
1818 for_each_sg(task->scatter, sg, tei->n_elem, i) {
1819 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
1820 buf_prd->len = cpu_to_le32(sg_dma_len(sg));
1821 buf_prd++;
1822 }
1823
1824 return 0;
1825 }
1826
1827 static int mvs_task_exec(struct sas_task *task, const int num, gfp_t gfp_flags)
1828 {
1829 struct domain_device *dev = task->dev;
1830 struct mvs_info *mvi = dev->port->ha->lldd_ha;
1831 struct pci_dev *pdev = mvi->pdev;
1832 void __iomem *regs = mvi->regs;
1833 struct mvs_task_exec_info tei;
1834 struct sas_task *t = task;
1835 u32 tag = 0xdeadbeef, rc, n_elem = 0;
1836 unsigned long flags;
1837 u32 n = num, pass = 0;
1838
1839 spin_lock_irqsave(&mvi->lock, flags);
1840
1841 do {
1842 tei.port = &mvi->port[dev->port->id];
1843
1844 if (!tei.port->port_attached) {
1845 struct task_status_struct *ts = &t->task_status;
1846 ts->stat = SAS_PHY_DOWN;
1847 t->task_done(t);
1848 rc = 0;
1849 goto exec_exit;
1850 }
1851 if (!sas_protocol_ata(t->task_proto)) {
1852 if (t->num_scatter) {
1853 n_elem = pci_map_sg(mvi->pdev, t->scatter,
1854 t->num_scatter,
1855 t->data_dir);
1856 if (!n_elem) {
1857 rc = -ENOMEM;
1858 goto err_out;
1859 }
1860 }
1861 } else {
1862 n_elem = t->num_scatter;
1863 }
1864
1865 rc = mvs_tag_alloc(mvi, &tag);
1866 if (rc)
1867 goto err_out;
1868
1869 mvi->slot_info[tag].task = t;
1870 mvi->slot_info[tag].n_elem = n_elem;
1871 memset(mvi->slot_info[tag].buf, 0, MVS_SLOT_BUF_SZ);
1872 tei.task = t;
1873 tei.hdr = &mvi->slot[tag];
1874 tei.tag = tag;
1875 tei.n_elem = n_elem;
1876
1877 switch (t->task_proto) {
1878 case SAS_PROTOCOL_SMP:
1879 rc = mvs_task_prep_smp(mvi, &tei);
1880 break;
1881 case SAS_PROTOCOL_SSP:
1882 rc = mvs_task_prep_ssp(mvi, &tei);
1883 break;
1884 case SAS_PROTOCOL_SATA:
1885 case SAS_PROTOCOL_STP:
1886 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1887 rc = mvs_task_prep_ata(mvi, &tei);
1888 break;
1889 default:
1890 dev_printk(KERN_ERR, &pdev->dev,
1891 "unknown sas_task proto: 0x%x\n",
1892 t->task_proto);
1893 rc = -EINVAL;
1894 break;
1895 }
1896
1897 if (rc)
1898 goto err_out_tag;
1899
1900 /* TODO: select normal or high priority */
1901
1902 spin_lock(&t->task_state_lock);
1903 t->task_state_flags |= SAS_TASK_AT_INITIATOR;
1904 spin_unlock(&t->task_state_lock);
1905
1906 if (n == 1) {
1907 spin_unlock_irqrestore(&mvi->lock, flags);
1908 mw32(TX_PROD_IDX, mvi->tx_prod);
1909 }
1910 mvs_hba_memory_dump(mvi, tag, t->task_proto);
1911
1912 ++pass;
1913 mvi->tx_prod = (mvi->tx_prod + 1) & (MVS_CHIP_SLOT_SZ - 1);
1914
1915 if (n == 1)
1916 break;
1917
1918 t = list_entry(t->list.next, struct sas_task, list);
1919 } while (--n);
1920
1921 return 0;
1922
1923 err_out_tag:
1924 mvs_tag_free(mvi, tag);
1925 err_out:
1926 dev_printk(KERN_ERR, &pdev->dev, "mvsas exec failed[%d]!\n", rc);
1927 if (!sas_protocol_ata(t->task_proto))
1928 if (n_elem)
1929 pci_unmap_sg(mvi->pdev, t->scatter, n_elem,
1930 t->data_dir);
1931 exec_exit:
1932 if (pass)
1933 mw32(TX_PROD_IDX, (mvi->tx_prod - 1) & (MVS_CHIP_SLOT_SZ - 1));
1934 spin_unlock_irqrestore(&mvi->lock, flags);
1935 return rc;
1936 }
1937
1938 static int mvs_task_abort(struct sas_task *task)
1939 {
1940 int rc = 1;
1941 unsigned long flags;
1942 struct mvs_info *mvi = task->dev->port->ha->lldd_ha;
1943 struct pci_dev *pdev = mvi->pdev;
1944
1945 spin_lock_irqsave(&task->task_state_lock, flags);
1946 if (task->task_state_flags & SAS_TASK_STATE_DONE) {
1947 rc = TMF_RESP_FUNC_COMPLETE;
1948 goto out_done;
1949 }
1950 spin_unlock_irqrestore(&task->task_state_lock, flags);
1951
1952 /*FIXME*/
1953 rc = TMF_RESP_FUNC_COMPLETE;
1954
1955 switch (task->task_proto) {
1956 case SAS_PROTOCOL_SMP:
1957 dev_printk(KERN_DEBUG, &pdev->dev, "SMP Abort! ");
1958 break;
1959 case SAS_PROTOCOL_SSP:
1960 dev_printk(KERN_DEBUG, &pdev->dev, "SSP Abort! ");
1961 break;
1962 case SAS_PROTOCOL_SATA:
1963 case SAS_PROTOCOL_STP:
1964 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:{
1965 dev_printk(KERN_DEBUG, &pdev->dev, "STP Abort! "
1966 "Dump D2H FIS: \n");
1967 mvs_hexdump(sizeof(struct host_to_dev_fis),
1968 (void *)&task->ata_task.fis, 0);
1969 dev_printk(KERN_DEBUG, &pdev->dev, "Dump ATAPI Cmd : \n");
1970 mvs_hexdump(16, task->ata_task.atapi_packet, 0);
1971 break;
1972 }
1973 default:
1974 break;
1975 }
1976 out_done:
1977 return rc;
1978 }
1979
1980 static void mvs_free(struct mvs_info *mvi)
1981 {
1982 int i;
1983
1984 if (!mvi)
1985 return;
1986
1987 for (i = 0; i < MVS_SLOTS; i++) {
1988 struct mvs_slot_info *slot = &mvi->slot_info[i];
1989
1990 if (slot->buf)
1991 dma_free_coherent(&mvi->pdev->dev, MVS_SLOT_BUF_SZ,
1992 slot->buf, slot->buf_dma);
1993 }
1994
1995 if (mvi->tx)
1996 dma_free_coherent(&mvi->pdev->dev,
1997 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
1998 mvi->tx, mvi->tx_dma);
1999 if (mvi->rx_fis)
2000 dma_free_coherent(&mvi->pdev->dev, MVS_RX_FISL_SZ,
2001 mvi->rx_fis, mvi->rx_fis_dma);
2002 if (mvi->rx)
2003 dma_free_coherent(&mvi->pdev->dev,
2004 sizeof(*mvi->rx) * MVS_RX_RING_SZ,
2005 mvi->rx, mvi->rx_dma);
2006 if (mvi->slot)
2007 dma_free_coherent(&mvi->pdev->dev,
2008 sizeof(*mvi->slot) * MVS_SLOTS,
2009 mvi->slot, mvi->slot_dma);
2010 #ifdef MVS_ENABLE_PERI
2011 if (mvi->peri_regs)
2012 iounmap(mvi->peri_regs);
2013 #endif
2014 if (mvi->regs)
2015 iounmap(mvi->regs);
2016 if (mvi->shost)
2017 scsi_host_put(mvi->shost);
2018 kfree(mvi->sas.sas_port);
2019 kfree(mvi->sas.sas_phy);
2020 kfree(mvi);
2021 }
2022
2023 /* FIXME: locking? */
2024 static int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
2025 void *funcdata)
2026 {
2027 struct mvs_info *mvi = sas_phy->ha->lldd_ha;
2028 int rc = 0, phy_id = sas_phy->id;
2029 u32 tmp;
2030
2031 tmp = mvs_read_phy_ctl(mvi, phy_id);
2032
2033 switch (func) {
2034 case PHY_FUNC_SET_LINK_RATE:{
2035 struct sas_phy_linkrates *rates = funcdata;
2036 u32 lrmin = 0, lrmax = 0;
2037
2038 lrmin = (rates->minimum_linkrate << 8);
2039 lrmax = (rates->maximum_linkrate << 12);
2040
2041 if (lrmin) {
2042 tmp &= ~(0xf << 8);
2043 tmp |= lrmin;
2044 }
2045 if (lrmax) {
2046 tmp &= ~(0xf << 12);
2047 tmp |= lrmax;
2048 }
2049 mvs_write_phy_ctl(mvi, phy_id, tmp);
2050 break;
2051 }
2052
2053 case PHY_FUNC_HARD_RESET:
2054 if (tmp & PHY_RST_HARD)
2055 break;
2056 mvs_write_phy_ctl(mvi, phy_id, tmp | PHY_RST_HARD);
2057 break;
2058
2059 case PHY_FUNC_LINK_RESET:
2060 mvs_write_phy_ctl(mvi, phy_id, tmp | PHY_RST);
2061 break;
2062
2063 case PHY_FUNC_DISABLE:
2064 case PHY_FUNC_RELEASE_SPINUP_HOLD:
2065 default:
2066 rc = -EOPNOTSUPP;
2067 }
2068
2069 return rc;
2070 }
2071
2072 static void __devinit mvs_phy_init(struct mvs_info *mvi, int phy_id)
2073 {
2074 struct mvs_phy *phy = &mvi->phy[phy_id];
2075 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2076
2077 sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0;
2078 sas_phy->class = SAS;
2079 sas_phy->iproto = SAS_PROTOCOL_ALL;
2080 sas_phy->tproto = 0;
2081 sas_phy->type = PHY_TYPE_PHYSICAL;
2082 sas_phy->role = PHY_ROLE_INITIATOR;
2083 sas_phy->oob_mode = OOB_NOT_CONNECTED;
2084 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
2085
2086 sas_phy->id = phy_id;
2087 sas_phy->sas_addr = &mvi->sas_addr[0];
2088 sas_phy->frame_rcvd = &phy->frame_rcvd[0];
2089 sas_phy->ha = &mvi->sas;
2090 sas_phy->lldd_phy = phy;
2091 }
2092
2093 static struct mvs_info *__devinit mvs_alloc(struct pci_dev *pdev,
2094 const struct pci_device_id *ent)
2095 {
2096 struct mvs_info *mvi;
2097 unsigned long res_start, res_len, res_flag;
2098 struct asd_sas_phy **arr_phy;
2099 struct asd_sas_port **arr_port;
2100 const struct mvs_chip_info *chip = &mvs_chips[ent->driver_data];
2101 int i;
2102
2103 /*
2104 * alloc and init our per-HBA mvs_info struct
2105 */
2106
2107 mvi = kzalloc(sizeof(*mvi), GFP_KERNEL);
2108 if (!mvi)
2109 return NULL;
2110
2111 spin_lock_init(&mvi->lock);
2112 mvi->pdev = pdev;
2113 mvi->chip = chip;
2114
2115 if (pdev->device == 0x6440 && pdev->revision == 0)
2116 mvi->flags |= MVF_PHY_PWR_FIX;
2117
2118 /*
2119 * alloc and init SCSI, SAS glue
2120 */
2121
2122 mvi->shost = scsi_host_alloc(&mvs_sht, sizeof(void *));
2123 if (!mvi->shost)
2124 goto err_out;
2125
2126 arr_phy = kcalloc(MVS_MAX_PHYS, sizeof(void *), GFP_KERNEL);
2127 arr_port = kcalloc(MVS_MAX_PHYS, sizeof(void *), GFP_KERNEL);
2128 if (!arr_phy || !arr_port)
2129 goto err_out;
2130
2131 for (i = 0; i < MVS_MAX_PHYS; i++) {
2132 mvs_phy_init(mvi, i);
2133 arr_phy[i] = &mvi->phy[i].sas_phy;
2134 arr_port[i] = &mvi->port[i].sas_port;
2135 }
2136
2137 SHOST_TO_SAS_HA(mvi->shost) = &mvi->sas;
2138 mvi->shost->transportt = mvs_stt;
2139 mvi->shost->max_id = 21;
2140 mvi->shost->max_lun = ~0;
2141 mvi->shost->max_channel = 0;
2142 mvi->shost->max_cmd_len = 16;
2143
2144 mvi->sas.sas_ha_name = DRV_NAME;
2145 mvi->sas.dev = &pdev->dev;
2146 mvi->sas.lldd_module = THIS_MODULE;
2147 mvi->sas.sas_addr = &mvi->sas_addr[0];
2148 mvi->sas.sas_phy = arr_phy;
2149 mvi->sas.sas_port = arr_port;
2150 mvi->sas.num_phys = chip->n_phy;
2151 mvi->sas.lldd_max_execute_num = MVS_CHIP_SLOT_SZ - 1;
2152 mvi->sas.lldd_queue_size = MVS_QUEUE_SIZE;
2153 mvi->can_queue = (MVS_CHIP_SLOT_SZ >> 1) - 1;
2154 mvi->sas.lldd_ha = mvi;
2155 mvi->sas.core.shost = mvi->shost;
2156
2157 mvs_tag_init(mvi);
2158
2159 /*
2160 * ioremap main and peripheral registers
2161 */
2162
2163 #ifdef MVS_ENABLE_PERI
2164 res_start = pci_resource_start(pdev, 2);
2165 res_len = pci_resource_len(pdev, 2);
2166 if (!res_start || !res_len)
2167 goto err_out;
2168
2169 mvi->peri_regs = ioremap_nocache(res_start, res_len);
2170 if (!mvi->peri_regs)
2171 goto err_out;
2172 #endif
2173
2174 res_start = pci_resource_start(pdev, 4);
2175 res_len = pci_resource_len(pdev, 4);
2176 if (!res_start || !res_len)
2177 goto err_out;
2178
2179 res_flag = pci_resource_flags(pdev, 4);
2180 if (res_flag & IORESOURCE_CACHEABLE)
2181 mvi->regs = ioremap(res_start, res_len);
2182 else
2183 mvi->regs = ioremap_nocache(res_start, res_len);
2184
2185 if (!mvi->regs)
2186 goto err_out;
2187
2188 /*
2189 * alloc and init our DMA areas
2190 */
2191
2192 mvi->tx = dma_alloc_coherent(&pdev->dev,
2193 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
2194 &mvi->tx_dma, GFP_KERNEL);
2195 if (!mvi->tx)
2196 goto err_out;
2197 memset(mvi->tx, 0, sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ);
2198
2199 mvi->rx_fis = dma_alloc_coherent(&pdev->dev, MVS_RX_FISL_SZ,
2200 &mvi->rx_fis_dma, GFP_KERNEL);
2201 if (!mvi->rx_fis)
2202 goto err_out;
2203 memset(mvi->rx_fis, 0, MVS_RX_FISL_SZ);
2204
2205 mvi->rx = dma_alloc_coherent(&pdev->dev,
2206 sizeof(*mvi->rx) * MVS_RX_RING_SZ,
2207 &mvi->rx_dma, GFP_KERNEL);
2208 if (!mvi->rx)
2209 goto err_out;
2210 memset(mvi->rx, 0, sizeof(*mvi->rx) * MVS_RX_RING_SZ);
2211
2212 mvi->rx[0] = cpu_to_le32(0xfff);
2213 mvi->rx_cons = 0xfff;
2214
2215 mvi->slot = dma_alloc_coherent(&pdev->dev,
2216 sizeof(*mvi->slot) * MVS_SLOTS,
2217 &mvi->slot_dma, GFP_KERNEL);
2218 if (!mvi->slot)
2219 goto err_out;
2220 memset(mvi->slot, 0, sizeof(*mvi->slot) * MVS_SLOTS);
2221
2222 for (i = 0; i < MVS_SLOTS; i++) {
2223 struct mvs_slot_info *slot = &mvi->slot_info[i];
2224
2225 slot->buf = dma_alloc_coherent(&pdev->dev, MVS_SLOT_BUF_SZ,
2226 &slot->buf_dma, GFP_KERNEL);
2227 if (!slot->buf)
2228 goto err_out;
2229 memset(slot->buf, 0, MVS_SLOT_BUF_SZ);
2230 }
2231
2232 /* finally, read NVRAM to get our SAS address */
2233 if (mvs_nvram_read(mvi, NVR_SAS_ADDR, &mvi->sas_addr, 8))
2234 goto err_out;
2235 return mvi;
2236
2237 err_out:
2238 mvs_free(mvi);
2239 return NULL;
2240 }
2241
2242 static u32 mvs_cr32(void __iomem *regs, u32 addr)
2243 {
2244 mw32(CMD_ADDR, addr);
2245 return mr32(CMD_DATA);
2246 }
2247
2248 static void mvs_cw32(void __iomem *regs, u32 addr, u32 val)
2249 {
2250 mw32(CMD_ADDR, addr);
2251 mw32(CMD_DATA, val);
2252 }
2253
2254 static u32 mvs_read_phy_ctl(struct mvs_info *mvi, u32 port)
2255 {
2256 void __iomem *regs = mvi->regs;
2257 return (port < 4)?mr32(P0_SER_CTLSTAT + port * 4):
2258 mr32(P4_SER_CTLSTAT + (port - 4) * 4);
2259 }
2260
2261 static void mvs_write_phy_ctl(struct mvs_info *mvi, u32 port, u32 val)
2262 {
2263 void __iomem *regs = mvi->regs;
2264 if (port < 4)
2265 mw32(P0_SER_CTLSTAT + port * 4, val);
2266 else
2267 mw32(P4_SER_CTLSTAT + (port - 4) * 4, val);
2268 }
2269
2270 static u32 mvs_read_port(struct mvs_info *mvi, u32 off, u32 off2, u32 port)
2271 {
2272 void __iomem *regs = mvi->regs + off;
2273 void __iomem *regs2 = mvi->regs + off2;
2274 return (port < 4)?readl(regs + port * 8):
2275 readl(regs2 + (port - 4) * 8);
2276 }
2277
2278 static void mvs_write_port(struct mvs_info *mvi, u32 off, u32 off2,
2279 u32 port, u32 val)
2280 {
2281 void __iomem *regs = mvi->regs + off;
2282 void __iomem *regs2 = mvi->regs + off2;
2283 if (port < 4)
2284 writel(val, regs + port * 8);
2285 else
2286 writel(val, regs2 + (port - 4) * 8);
2287 }
2288
2289 static u32 mvs_read_port_cfg_data(struct mvs_info *mvi, u32 port)
2290 {
2291 return mvs_read_port(mvi, MVS_P0_CFG_DATA, MVS_P4_CFG_DATA, port);
2292 }
2293
2294 static void mvs_write_port_cfg_data(struct mvs_info *mvi, u32 port, u32 val)
2295 {
2296 mvs_write_port(mvi, MVS_P0_CFG_DATA, MVS_P4_CFG_DATA, port, val);
2297 }
2298
2299 static void mvs_write_port_cfg_addr(struct mvs_info *mvi, u32 port, u32 addr)
2300 {
2301 mvs_write_port(mvi, MVS_P0_CFG_ADDR, MVS_P4_CFG_ADDR, port, addr);
2302 }
2303
2304 static u32 mvs_read_port_vsr_data(struct mvs_info *mvi, u32 port)
2305 {
2306 return mvs_read_port(mvi, MVS_P0_VSR_DATA, MVS_P4_VSR_DATA, port);
2307 }
2308
2309 static void mvs_write_port_vsr_data(struct mvs_info *mvi, u32 port, u32 val)
2310 {
2311 mvs_write_port(mvi, MVS_P0_VSR_DATA, MVS_P4_VSR_DATA, port, val);
2312 }
2313
2314 static void mvs_write_port_vsr_addr(struct mvs_info *mvi, u32 port, u32 addr)
2315 {
2316 mvs_write_port(mvi, MVS_P0_VSR_ADDR, MVS_P4_VSR_ADDR, port, addr);
2317 }
2318
2319 static u32 mvs_read_port_irq_stat(struct mvs_info *mvi, u32 port)
2320 {
2321 return mvs_read_port(mvi, MVS_P0_INT_STAT, MVS_P4_INT_STAT, port);
2322 }
2323
2324 static void mvs_write_port_irq_stat(struct mvs_info *mvi, u32 port, u32 val)
2325 {
2326 mvs_write_port(mvi, MVS_P0_INT_STAT, MVS_P4_INT_STAT, port, val);
2327 }
2328
2329 static u32 mvs_read_port_irq_mask(struct mvs_info *mvi, u32 port)
2330 {
2331 return mvs_read_port(mvi, MVS_P0_INT_MASK, MVS_P4_INT_MASK, port);
2332 }
2333
2334 static void mvs_write_port_irq_mask(struct mvs_info *mvi, u32 port, u32 val)
2335 {
2336 mvs_write_port(mvi, MVS_P0_INT_MASK, MVS_P4_INT_MASK, port, val);
2337 }
2338
2339 static void __devinit mvs_phy_hacks(struct mvs_info *mvi)
2340 {
2341 void __iomem *regs = mvi->regs;
2342 u32 tmp;
2343
2344 /* workaround for SATA R-ERR, to ignore phy glitch */
2345 tmp = mvs_cr32(regs, CMD_PHY_TIMER);
2346 tmp &= ~(1 << 9);
2347 tmp |= (1 << 10);
2348 mvs_cw32(regs, CMD_PHY_TIMER, tmp);
2349
2350 /* enable retry 127 times */
2351 mvs_cw32(regs, CMD_SAS_CTL1, 0x7f7f);
2352
2353 /* extend open frame timeout to max */
2354 tmp = mvs_cr32(regs, CMD_SAS_CTL0);
2355 tmp &= ~0xffff;
2356 tmp |= 0x3fff;
2357 mvs_cw32(regs, CMD_SAS_CTL0, tmp);
2358
2359 /* workaround for WDTIMEOUT , set to 550 ms */
2360 mvs_cw32(regs, CMD_WD_TIMER, 0xffffff);
2361
2362 /* not to halt for different port op during wideport link change */
2363 mvs_cw32(regs, CMD_APP_ERR_CONFIG, 0xffefbf7d);
2364
2365 /* workaround for Seagate disk not-found OOB sequence, recv
2366 * COMINIT before sending out COMWAKE */
2367 tmp = mvs_cr32(regs, CMD_PHY_MODE_21);
2368 tmp &= 0x0000ffff;
2369 tmp |= 0x00fa0000;
2370 mvs_cw32(regs, CMD_PHY_MODE_21, tmp);
2371
2372 tmp = mvs_cr32(regs, CMD_PHY_TIMER);
2373 tmp &= 0x1fffffff;
2374 tmp |= (2U << 29); /* 8 ms retry */
2375 mvs_cw32(regs, CMD_PHY_TIMER, tmp);
2376
2377 /* TEST - for phy decoding error, adjust voltage levels */
2378 mw32(P0_VSR_ADDR + 0, 0x8);
2379 mw32(P0_VSR_DATA + 0, 0x2F0);
2380
2381 mw32(P0_VSR_ADDR + 8, 0x8);
2382 mw32(P0_VSR_DATA + 8, 0x2F0);
2383
2384 mw32(P0_VSR_ADDR + 16, 0x8);
2385 mw32(P0_VSR_DATA + 16, 0x2F0);
2386
2387 mw32(P0_VSR_ADDR + 24, 0x8);
2388 mw32(P0_VSR_DATA + 24, 0x2F0);
2389
2390 }
2391
2392 static void mvs_enable_xmt(struct mvs_info *mvi, int PhyId)
2393 {
2394 void __iomem *regs = mvi->regs;
2395 u32 tmp;
2396
2397 tmp = mr32(PCS);
2398 if (mvi->chip->n_phy <= 4)
2399 tmp |= 1 << (PhyId + PCS_EN_PORT_XMT_SHIFT);
2400 else
2401 tmp |= 1 << (PhyId + PCS_EN_PORT_XMT_SHIFT2);
2402 mw32(PCS, tmp);
2403 }
2404
2405 static void mvs_detect_porttype(struct mvs_info *mvi, int i)
2406 {
2407 void __iomem *regs = mvi->regs;
2408 u32 reg;
2409 struct mvs_phy *phy = &mvi->phy[i];
2410
2411 /* TODO check & save device type */
2412 reg = mr32(GBL_PORT_TYPE);
2413
2414 if (reg & MODE_SAS_SATA & (1 << i))
2415 phy->phy_type |= PORT_TYPE_SAS;
2416 else
2417 phy->phy_type |= PORT_TYPE_SATA;
2418 }
2419
2420 static void *mvs_get_d2h_reg(struct mvs_info *mvi, int i, void *buf)
2421 {
2422 u32 *s = (u32 *) buf;
2423
2424 if (!s)
2425 return NULL;
2426
2427 mvs_write_port_cfg_addr(mvi, i, PHYR_SATA_SIG3);
2428 s[3] = mvs_read_port_cfg_data(mvi, i);
2429
2430 mvs_write_port_cfg_addr(mvi, i, PHYR_SATA_SIG2);
2431 s[2] = mvs_read_port_cfg_data(mvi, i);
2432
2433 mvs_write_port_cfg_addr(mvi, i, PHYR_SATA_SIG1);
2434 s[1] = mvs_read_port_cfg_data(mvi, i);
2435
2436 mvs_write_port_cfg_addr(mvi, i, PHYR_SATA_SIG0);
2437 s[0] = mvs_read_port_cfg_data(mvi, i);
2438
2439 return (void *)s;
2440 }
2441
2442 static u32 mvs_is_sig_fis_received(u32 irq_status)
2443 {
2444 return irq_status & PHYEV_SIG_FIS;
2445 }
2446
2447 static void mvs_update_wideport(struct mvs_info *mvi, int i)
2448 {
2449 struct mvs_phy *phy = &mvi->phy[i];
2450 struct mvs_port *port = phy->port;
2451 int j, no;
2452
2453 for_each_phy(port->wide_port_phymap, no, j, mvi->chip->n_phy)
2454 if (no & 1) {
2455 mvs_write_port_cfg_addr(mvi, no, PHYR_WIDE_PORT);
2456 mvs_write_port_cfg_data(mvi, no,
2457 port->wide_port_phymap);
2458 } else {
2459 mvs_write_port_cfg_addr(mvi, no, PHYR_WIDE_PORT);
2460 mvs_write_port_cfg_data(mvi, no, 0);
2461 }
2462 }
2463
2464 static u32 mvs_is_phy_ready(struct mvs_info *mvi, int i)
2465 {
2466 u32 tmp;
2467 struct mvs_phy *phy = &mvi->phy[i];
2468 struct mvs_port *port;
2469
2470 tmp = mvs_read_phy_ctl(mvi, i);
2471
2472 if ((tmp & PHY_READY_MASK) && !(phy->irq_status & PHYEV_POOF)) {
2473 if (!phy->port)
2474 phy->phy_attached = 1;
2475 return tmp;
2476 }
2477
2478 port = phy->port;
2479 if (port) {
2480 if (phy->phy_type & PORT_TYPE_SAS) {
2481 port->wide_port_phymap &= ~(1U << i);
2482 if (!port->wide_port_phymap)
2483 port->port_attached = 0;
2484 mvs_update_wideport(mvi, i);
2485 } else if (phy->phy_type & PORT_TYPE_SATA)
2486 port->port_attached = 0;
2487 mvs_free_reg_set(mvi, phy->port);
2488 phy->port = NULL;
2489 phy->phy_attached = 0;
2490 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
2491 }
2492 return 0;
2493 }
2494
2495 static void mvs_update_phyinfo(struct mvs_info *mvi, int i,
2496 int get_st)
2497 {
2498 struct mvs_phy *phy = &mvi->phy[i];
2499 struct pci_dev *pdev = mvi->pdev;
2500 u32 tmp, j;
2501 u64 tmp64;
2502
2503 mvs_write_port_cfg_addr(mvi, i, PHYR_IDENTIFY);
2504 phy->dev_info = mvs_read_port_cfg_data(mvi, i);
2505
2506 mvs_write_port_cfg_addr(mvi, i, PHYR_ADDR_HI);
2507 phy->dev_sas_addr = (u64) mvs_read_port_cfg_data(mvi, i) << 32;
2508
2509 mvs_write_port_cfg_addr(mvi, i, PHYR_ADDR_LO);
2510 phy->dev_sas_addr |= mvs_read_port_cfg_data(mvi, i);
2511
2512 if (get_st) {
2513 phy->irq_status = mvs_read_port_irq_stat(mvi, i);
2514 phy->phy_status = mvs_is_phy_ready(mvi, i);
2515 }
2516
2517 if (phy->phy_status) {
2518 u32 phy_st;
2519 struct asd_sas_phy *sas_phy = mvi->sas.sas_phy[i];
2520
2521 mvs_write_port_cfg_addr(mvi, i, PHYR_PHY_STAT);
2522 phy_st = mvs_read_port_cfg_data(mvi, i);
2523
2524 sas_phy->linkrate =
2525 (phy->phy_status & PHY_NEG_SPP_PHYS_LINK_RATE_MASK) >>
2526 PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET;
2527
2528 /* Updated attached_sas_addr */
2529 mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_ADDR_HI);
2530 phy->att_dev_sas_addr =
2531 (u64) mvs_read_port_cfg_data(mvi, i) << 32;
2532
2533 mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_ADDR_LO);
2534 phy->att_dev_sas_addr |= mvs_read_port_cfg_data(mvi, i);
2535
2536 dev_printk(KERN_DEBUG, &pdev->dev,
2537 "phy[%d] Get Attached Address 0x%llX ,"
2538 " SAS Address 0x%llX\n",
2539 i, phy->att_dev_sas_addr, phy->dev_sas_addr);
2540 dev_printk(KERN_DEBUG, &pdev->dev,
2541 "Rate = %x , type = %d\n",
2542 sas_phy->linkrate, phy->phy_type);
2543
2544 #if 1
2545 /*
2546 * If the device is capable of supporting a wide port
2547 * on its phys, it may configure the phys as a wide port.
2548 */
2549 if (phy->phy_type & PORT_TYPE_SAS)
2550 for (j = 0; j < mvi->chip->n_phy && j != i; ++j) {
2551 if ((mvi->phy[j].phy_attached) &&
2552 (mvi->phy[j].phy_type & PORT_TYPE_SAS))
2553 if (phy->att_dev_sas_addr ==
2554 mvi->phy[j].att_dev_sas_addr - 1) {
2555 phy->att_dev_sas_addr =
2556 mvi->phy[j].att_dev_sas_addr;
2557 break;
2558 }
2559 }
2560
2561 #endif
2562
2563 tmp64 = cpu_to_be64(phy->att_dev_sas_addr);
2564 memcpy(sas_phy->attached_sas_addr, &tmp64, SAS_ADDR_SIZE);
2565
2566 if (phy->phy_type & PORT_TYPE_SAS) {
2567 mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_DEV_INFO);
2568 phy->att_dev_info = mvs_read_port_cfg_data(mvi, i);
2569 phy->identify.device_type =
2570 phy->att_dev_info & PORT_DEV_TYPE_MASK;
2571
2572 if (phy->identify.device_type == SAS_END_DEV)
2573 phy->identify.target_port_protocols =
2574 SAS_PROTOCOL_SSP;
2575 else if (phy->identify.device_type != NO_DEVICE)
2576 phy->identify.target_port_protocols =
2577 SAS_PROTOCOL_SMP;
2578 if (phy_st & PHY_OOB_DTCTD)
2579 sas_phy->oob_mode = SAS_OOB_MODE;
2580 phy->frame_rcvd_size =
2581 sizeof(struct sas_identify_frame);
2582 } else if (phy->phy_type & PORT_TYPE_SATA) {
2583 phy->identify.target_port_protocols = SAS_PROTOCOL_STP;
2584 if (mvs_is_sig_fis_received(phy->irq_status)) {
2585 if (phy_st & PHY_OOB_DTCTD)
2586 sas_phy->oob_mode = SATA_OOB_MODE;
2587 phy->frame_rcvd_size =
2588 sizeof(struct dev_to_host_fis);
2589 mvs_get_d2h_reg(mvi, i,
2590 (void *)sas_phy->frame_rcvd);
2591 } else {
2592 dev_printk(KERN_DEBUG, &pdev->dev,
2593 "No sig fis\n");
2594 }
2595 }
2596 /* workaround for HW phy decoding error on 1.5g disk drive */
2597 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE6);
2598 tmp = mvs_read_port_vsr_data(mvi, i);
2599 if (((phy->phy_status & PHY_NEG_SPP_PHYS_LINK_RATE_MASK) >>
2600 PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET) ==
2601 SAS_LINK_RATE_1_5_GBPS)
2602 tmp &= ~PHY_MODE6_DTL_SPEED;
2603 else
2604 tmp |= PHY_MODE6_DTL_SPEED;
2605 mvs_write_port_vsr_data(mvi, i, tmp);
2606
2607 }
2608 if (get_st)
2609 mvs_write_port_irq_stat(mvi, i, phy->irq_status);
2610 }
2611
2612 static void mvs_port_formed(struct asd_sas_phy *sas_phy)
2613 {
2614 struct sas_ha_struct *sas_ha = sas_phy->ha;
2615 struct mvs_info *mvi = sas_ha->lldd_ha;
2616 struct asd_sas_port *sas_port = sas_phy->port;
2617 struct mvs_phy *phy = sas_phy->lldd_phy;
2618 struct mvs_port *port = &mvi->port[sas_port->id];
2619 unsigned long flags;
2620
2621 spin_lock_irqsave(&mvi->lock, flags);
2622 port->port_attached = 1;
2623 phy->port = port;
2624 port->taskfileset = MVS_ID_NOT_MAPPED;
2625 if (phy->phy_type & PORT_TYPE_SAS) {
2626 port->wide_port_phymap = sas_port->phy_mask;
2627 mvs_update_wideport(mvi, sas_phy->id);
2628 }
2629 spin_unlock_irqrestore(&mvi->lock, flags);
2630 }
2631
2632 static int __devinit mvs_hw_init(struct mvs_info *mvi)
2633 {
2634 void __iomem *regs = mvi->regs;
2635 int i;
2636 u32 tmp, cctl;
2637
2638 /* make sure interrupts are masked immediately (paranoia) */
2639 mw32(GBL_CTL, 0);
2640 tmp = mr32(GBL_CTL);
2641
2642 /* Reset Controller */
2643 if (!(tmp & HBA_RST)) {
2644 if (mvi->flags & MVF_PHY_PWR_FIX) {
2645 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp);
2646 tmp &= ~PCTL_PWR_ON;
2647 tmp |= PCTL_OFF;
2648 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);
2649
2650 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp);
2651 tmp &= ~PCTL_PWR_ON;
2652 tmp |= PCTL_OFF;
2653 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);
2654 }
2655
2656 /* global reset, incl. COMRESET/H_RESET_N (self-clearing) */
2657 mw32_f(GBL_CTL, HBA_RST);
2658 }
2659
2660 /* wait for reset to finish; timeout is just a guess */
2661 i = 1000;
2662 while (i-- > 0) {
2663 msleep(10);
2664
2665 if (!(mr32(GBL_CTL) & HBA_RST))
2666 break;
2667 }
2668 if (mr32(GBL_CTL) & HBA_RST) {
2669 dev_printk(KERN_ERR, &mvi->pdev->dev, "HBA reset failed\n");
2670 return -EBUSY;
2671 }
2672
2673 /* Init Chip */
2674 /* make sure RST is set; HBA_RST /should/ have done that for us */
2675 cctl = mr32(CTL);
2676 if (cctl & CCTL_RST)
2677 cctl &= ~CCTL_RST;
2678 else
2679 mw32_f(CTL, cctl | CCTL_RST);
2680
2681 /* write to device control _AND_ device status register? - A.C. */
2682 pci_read_config_dword(mvi->pdev, PCR_DEV_CTRL, &tmp);
2683 tmp &= ~PRD_REQ_MASK;
2684 tmp |= PRD_REQ_SIZE;
2685 pci_write_config_dword(mvi->pdev, PCR_DEV_CTRL, tmp);
2686
2687 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp);
2688 tmp |= PCTL_PWR_ON;
2689 tmp &= ~PCTL_OFF;
2690 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);
2691
2692 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp);
2693 tmp |= PCTL_PWR_ON;
2694 tmp &= ~PCTL_OFF;
2695 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);
2696
2697 mw32_f(CTL, cctl);
2698
2699 /* reset control */
2700 mw32(PCS, 0); /*MVS_PCS */
2701
2702 mvs_phy_hacks(mvi);
2703
2704 mw32(CMD_LIST_LO, mvi->slot_dma);
2705 mw32(CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16);
2706
2707 mw32(RX_FIS_LO, mvi->rx_fis_dma);
2708 mw32(RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16);
2709
2710 mw32(TX_CFG, MVS_CHIP_SLOT_SZ);
2711 mw32(TX_LO, mvi->tx_dma);
2712 mw32(TX_HI, (mvi->tx_dma >> 16) >> 16);
2713
2714 mw32(RX_CFG, MVS_RX_RING_SZ);
2715 mw32(RX_LO, mvi->rx_dma);
2716 mw32(RX_HI, (mvi->rx_dma >> 16) >> 16);
2717
2718 /* enable auto port detection */
2719 mw32(GBL_PORT_TYPE, MODE_AUTO_DET_EN);
2720 msleep(100);
2721 /* init and reset phys */
2722 for (i = 0; i < mvi->chip->n_phy; i++) {
2723 /* FIXME: is this the correct dword order? */
2724 u32 lo = *((u32 *)&mvi->sas_addr[0]);
2725 u32 hi = *((u32 *)&mvi->sas_addr[4]);
2726
2727 mvs_detect_porttype(mvi, i);
2728
2729 /* set phy local SAS address */
2730 mvs_write_port_cfg_addr(mvi, i, PHYR_ADDR_LO);
2731 mvs_write_port_cfg_data(mvi, i, lo);
2732 mvs_write_port_cfg_addr(mvi, i, PHYR_ADDR_HI);
2733 mvs_write_port_cfg_data(mvi, i, hi);
2734
2735 /* reset phy */
2736 tmp = mvs_read_phy_ctl(mvi, i);
2737 tmp |= PHY_RST;
2738 mvs_write_phy_ctl(mvi, i, tmp);
2739 }
2740
2741 msleep(100);
2742
2743 for (i = 0; i < mvi->chip->n_phy; i++) {
2744 /* clear phy int status */
2745 tmp = mvs_read_port_irq_stat(mvi, i);
2746 tmp &= ~PHYEV_SIG_FIS;
2747 mvs_write_port_irq_stat(mvi, i, tmp);
2748
2749 /* set phy int mask */
2750 tmp = PHYEV_RDY_CH | PHYEV_BROAD_CH | PHYEV_UNASSOC_FIS |
2751 PHYEV_ID_DONE | PHYEV_DEC_ERR;
2752 mvs_write_port_irq_mask(mvi, i, tmp);
2753
2754 msleep(100);
2755 mvs_update_phyinfo(mvi, i, 1);
2756 mvs_enable_xmt(mvi, i);
2757 }
2758
2759 /* FIXME: update wide port bitmaps */
2760
2761 /* little endian for open address and command table, etc. */
2762 /* A.C.
2763 * it seems that ( from the spec ) turning on big-endian won't
2764 * do us any good on big-endian machines, need further confirmation
2765 */
2766 cctl = mr32(CTL);
2767 cctl |= CCTL_ENDIAN_CMD;
2768 cctl |= CCTL_ENDIAN_DATA;
2769 cctl &= ~CCTL_ENDIAN_OPEN;
2770 cctl |= CCTL_ENDIAN_RSP;
2771 mw32_f(CTL, cctl);
2772
2773 /* reset CMD queue */
2774 tmp = mr32(PCS);
2775 tmp |= PCS_CMD_RST;
2776 mw32(PCS, tmp);
2777 /* interrupt coalescing may cause missing HW interrput in some case,
2778 * and the max count is 0x1ff, while our max slot is 0x200,
2779 * it will make count 0.
2780 */
2781 tmp = 0;
2782 mw32(INT_COAL, tmp);
2783
2784 tmp = 0x100;
2785 mw32(INT_COAL_TMOUT, tmp);
2786
2787 /* ladies and gentlemen, start your engines */
2788 mw32(TX_CFG, 0);
2789 mw32(TX_CFG, MVS_CHIP_SLOT_SZ | TX_EN);
2790 mw32(RX_CFG, MVS_RX_RING_SZ | RX_EN);
2791 /* enable CMD/CMPL_Q/RESP mode */
2792 mw32(PCS, PCS_SATA_RETRY | PCS_FIS_RX_EN | PCS_CMD_EN);
2793
2794 /* re-enable interrupts globally */
2795 mvs_hba_interrupt_enable(mvi);
2796
2797 /* enable completion queue interrupt */
2798 tmp = (CINT_PORT_MASK | CINT_DONE | CINT_MEM);
2799 mw32(INT_MASK, tmp);
2800
2801 return 0;
2802 }
2803
2804 static void __devinit mvs_print_info(struct mvs_info *mvi)
2805 {
2806 struct pci_dev *pdev = mvi->pdev;
2807 static int printed_version;
2808
2809 if (!printed_version++)
2810 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
2811
2812 dev_printk(KERN_INFO, &pdev->dev, "%u phys, addr %llx\n",
2813 mvi->chip->n_phy, SAS_ADDR(mvi->sas_addr));
2814 }
2815
2816 static int __devinit mvs_pci_init(struct pci_dev *pdev,
2817 const struct pci_device_id *ent)
2818 {
2819 int rc;
2820 struct mvs_info *mvi;
2821 irq_handler_t irq_handler = mvs_interrupt;
2822
2823 rc = pci_enable_device(pdev);
2824 if (rc)
2825 return rc;
2826
2827 pci_set_master(pdev);
2828
2829 rc = pci_request_regions(pdev, DRV_NAME);
2830 if (rc)
2831 goto err_out_disable;
2832
2833 rc = pci_go_64(pdev);
2834 if (rc)
2835 goto err_out_regions;
2836
2837 mvi = mvs_alloc(pdev, ent);
2838 if (!mvi) {
2839 rc = -ENOMEM;
2840 goto err_out_regions;
2841 }
2842
2843 rc = mvs_hw_init(mvi);
2844 if (rc)
2845 goto err_out_mvi;
2846
2847 #ifndef MVS_DISABLE_MSI
2848 if (!pci_enable_msi(pdev)) {
2849 u32 tmp;
2850 void __iomem *regs = mvi->regs;
2851 mvi->flags |= MVF_MSI;
2852 irq_handler = mvs_msi_interrupt;
2853 tmp = mr32(PCS);
2854 mw32(PCS, tmp | PCS_SELF_CLEAR);
2855 }
2856 #endif
2857
2858 rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED, DRV_NAME, mvi);
2859 if (rc)
2860 goto err_out_msi;
2861
2862 rc = scsi_add_host(mvi->shost, &pdev->dev);
2863 if (rc)
2864 goto err_out_irq;
2865
2866 rc = sas_register_ha(&mvi->sas);
2867 if (rc)
2868 goto err_out_shost;
2869
2870 pci_set_drvdata(pdev, mvi);
2871
2872 mvs_print_info(mvi);
2873
2874 scsi_scan_host(mvi->shost);
2875
2876 return 0;
2877
2878 err_out_shost:
2879 scsi_remove_host(mvi->shost);
2880 err_out_irq:
2881 free_irq(pdev->irq, mvi);
2882 err_out_msi:
2883 if (mvi->flags |= MVF_MSI)
2884 pci_disable_msi(pdev);
2885 err_out_mvi:
2886 mvs_free(mvi);
2887 err_out_regions:
2888 pci_release_regions(pdev);
2889 err_out_disable:
2890 pci_disable_device(pdev);
2891 return rc;
2892 }
2893
2894 static void __devexit mvs_pci_remove(struct pci_dev *pdev)
2895 {
2896 struct mvs_info *mvi = pci_get_drvdata(pdev);
2897
2898 pci_set_drvdata(pdev, NULL);
2899
2900 if (mvi) {
2901 sas_unregister_ha(&mvi->sas);
2902 mvs_hba_interrupt_disable(mvi);
2903 sas_remove_host(mvi->shost);
2904 scsi_remove_host(mvi->shost);
2905
2906 free_irq(pdev->irq, mvi);
2907 if (mvi->flags & MVF_MSI)
2908 pci_disable_msi(pdev);
2909 mvs_free(mvi);
2910 pci_release_regions(pdev);
2911 }
2912 pci_disable_device(pdev);
2913 }
2914
2915 static struct sas_domain_function_template mvs_transport_ops = {
2916 .lldd_execute_task = mvs_task_exec,
2917 .lldd_control_phy = mvs_phy_control,
2918 .lldd_abort_task = mvs_task_abort,
2919 .lldd_port_formed = mvs_port_formed
2920 };
2921
2922 static struct pci_device_id __devinitdata mvs_pci_table[] = {
2923 { PCI_VDEVICE(MARVELL, 0x6320), chip_6320 },
2924 { PCI_VDEVICE(MARVELL, 0x6340), chip_6440 },
2925 { PCI_VDEVICE(MARVELL, 0x6440), chip_6440 },
2926 { PCI_VDEVICE(MARVELL, 0x6480), chip_6480 },
2927
2928 { } /* terminate list */
2929 };
2930
2931 static struct pci_driver mvs_pci_driver = {
2932 .name = DRV_NAME,
2933 .id_table = mvs_pci_table,
2934 .probe = mvs_pci_init,
2935 .remove = __devexit_p(mvs_pci_remove),
2936 };
2937
2938 static int __init mvs_init(void)
2939 {
2940 int rc;
2941
2942 mvs_stt = sas_domain_attach_transport(&mvs_transport_ops);
2943 if (!mvs_stt)
2944 return -ENOMEM;
2945
2946 rc = pci_register_driver(&mvs_pci_driver);
2947 if (rc)
2948 goto err_out;
2949
2950 return 0;
2951
2952 err_out:
2953 sas_release_transport(mvs_stt);
2954 return rc;
2955 }
2956
2957 static void __exit mvs_exit(void)
2958 {
2959 pci_unregister_driver(&mvs_pci_driver);
2960 sas_release_transport(mvs_stt);
2961 }
2962
2963 module_init(mvs_init);
2964 module_exit(mvs_exit);
2965
2966 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
2967 MODULE_DESCRIPTION("Marvell 88SE6440 SAS/SATA controller driver");
2968 MODULE_VERSION(DRV_VERSION);
2969 MODULE_LICENSE("GPL");
2970 MODULE_DEVICE_TABLE(pci, mvs_pci_table);
Support for the Chinese Samsung S3C2440 based development boards