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radeon: fix PCI bus mastering support enables.
[linux-2.6/mini2440.git] / drivers / gpu / drm / radeon / radeon_cp.c
blob59a2132a8f57a5e833b83011191de047dc9ec43e
1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
2 /*
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2007 Advanced Micro Devices, Inc.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 */
31
32 #include "drmP.h"
33 #include "drm.h"
34 #include "radeon_drm.h"
35 #include "radeon_drv.h"
36 #include "r300_reg.h"
37
38 #include "radeon_microcode.h"
39
40 #define RADEON_FIFO_DEBUG 0
41
42 static int radeon_do_cleanup_cp(struct drm_device * dev);
43 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
44
45 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
46 {
47 u32 ret;
48 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
49 ret = RADEON_READ(R520_MC_IND_DATA);
50 RADEON_WRITE(R520_MC_IND_INDEX, 0);
51 return ret;
52 }
53
54 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
55 {
56 u32 ret;
57 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
58 ret = RADEON_READ(RS480_NB_MC_DATA);
59 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
60 return ret;
61 }
62
63 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
64 {
65 u32 ret;
66 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
67 ret = RADEON_READ(RS690_MC_DATA);
68 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
69 return ret;
70 }
71
72 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
73 {
74 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
75 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
76 return RS690_READ_MCIND(dev_priv, addr);
77 else
78 return RS480_READ_MCIND(dev_priv, addr);
79 }
80
81 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
82 {
83
84 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
85 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
86 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
87 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
88 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
89 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
90 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
91 else
92 return RADEON_READ(RADEON_MC_FB_LOCATION);
93 }
94
95 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
96 {
97 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
98 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
99 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
100 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
101 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
102 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
103 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
104 else
105 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
106 }
107
108 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
109 {
110 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
111 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
112 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
113 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
114 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
115 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
116 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
117 else
118 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
119 }
120
121 static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
122 {
123 u32 agp_base_hi = upper_32_bits(agp_base);
124 u32 agp_base_lo = agp_base & 0xffffffff;
125
126 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
127 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
128 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
129 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
130 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
131 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
132 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
133 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
134 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
135 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
136 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
137 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
138 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
139 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
140 } else {
141 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
142 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
143 RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
144 }
145 }
146
147 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
148 {
149 drm_radeon_private_t *dev_priv = dev->dev_private;
150
151 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
152 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
153 }
154
155 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
156 {
157 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
158 return RADEON_READ(RADEON_PCIE_DATA);
159 }
160
161 #if RADEON_FIFO_DEBUG
162 static void radeon_status(drm_radeon_private_t * dev_priv)
163 {
164 printk("%s:\n", __func__);
165 printk("RBBM_STATUS = 0x%08x\n",
166 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
167 printk("CP_RB_RTPR = 0x%08x\n",
168 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
169 printk("CP_RB_WTPR = 0x%08x\n",
170 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
171 printk("AIC_CNTL = 0x%08x\n",
172 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
173 printk("AIC_STAT = 0x%08x\n",
174 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
175 printk("AIC_PT_BASE = 0x%08x\n",
176 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
177 printk("TLB_ADDR = 0x%08x\n",
178 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
179 printk("TLB_DATA = 0x%08x\n",
180 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
181 }
182 #endif
183
184 /* ================================================================
185 * Engine, FIFO control
186 */
187
188 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
189 {
190 u32 tmp;
191 int i;
192
193 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
194
195 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
196 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
197 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
198 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
199
200 for (i = 0; i < dev_priv->usec_timeout; i++) {
201 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
202 & RADEON_RB3D_DC_BUSY)) {
203 return 0;
204 }
205 DRM_UDELAY(1);
206 }
207 } else {
208 /* don't flush or purge cache here or lockup */
209 return 0;
210 }
211
212 #if RADEON_FIFO_DEBUG
213 DRM_ERROR("failed!\n");
214 radeon_status(dev_priv);
215 #endif
216 return -EBUSY;
217 }
218
219 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
220 {
221 int i;
222
223 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
224
225 for (i = 0; i < dev_priv->usec_timeout; i++) {
226 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
227 & RADEON_RBBM_FIFOCNT_MASK);
228 if (slots >= entries)
229 return 0;
230 DRM_UDELAY(1);
231 }
232 DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
233 RADEON_READ(RADEON_RBBM_STATUS),
234 RADEON_READ(R300_VAP_CNTL_STATUS));
235
236 #if RADEON_FIFO_DEBUG
237 DRM_ERROR("failed!\n");
238 radeon_status(dev_priv);
239 #endif
240 return -EBUSY;
241 }
242
243 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
244 {
245 int i, ret;
246
247 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
248
249 ret = radeon_do_wait_for_fifo(dev_priv, 64);
250 if (ret)
251 return ret;
252
253 for (i = 0; i < dev_priv->usec_timeout; i++) {
254 if (!(RADEON_READ(RADEON_RBBM_STATUS)
255 & RADEON_RBBM_ACTIVE)) {
256 radeon_do_pixcache_flush(dev_priv);
257 return 0;
258 }
259 DRM_UDELAY(1);
260 }
261 DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
262 RADEON_READ(RADEON_RBBM_STATUS),
263 RADEON_READ(R300_VAP_CNTL_STATUS));
264
265 #if RADEON_FIFO_DEBUG
266 DRM_ERROR("failed!\n");
267 radeon_status(dev_priv);
268 #endif
269 return -EBUSY;
270 }
271
272 static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
273 {
274 uint32_t gb_tile_config, gb_pipe_sel = 0;
275
276 /* RS4xx/RS6xx/R4xx/R5xx */
277 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
278 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
279 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
280 } else {
281 /* R3xx */
282 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
283 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
284 dev_priv->num_gb_pipes = 2;
285 } else {
286 /* R3Vxx */
287 dev_priv->num_gb_pipes = 1;
288 }
289 }
290 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
291
292 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
293
294 switch (dev_priv->num_gb_pipes) {
295 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
296 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
297 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
298 default:
299 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
300 }
301
302 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
303 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
304 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
305 }
306 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
307 radeon_do_wait_for_idle(dev_priv);
308 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
309 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
310 R300_DC_AUTOFLUSH_ENABLE |
311 R300_DC_DC_DISABLE_IGNORE_PE));
312
313
314 }
315
316 /* ================================================================
317 * CP control, initialization
318 */
319
320 /* Load the microcode for the CP */
321 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
322 {
323 int i;
324 DRM_DEBUG("\n");
325
326 radeon_do_wait_for_idle(dev_priv);
327
328 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
329 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
330 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
331 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
332 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
333 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
334 DRM_INFO("Loading R100 Microcode\n");
335 for (i = 0; i < 256; i++) {
336 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
337 R100_cp_microcode[i][1]);
338 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
339 R100_cp_microcode[i][0]);
340 }
341 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
342 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
343 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
344 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
345 DRM_INFO("Loading R200 Microcode\n");
346 for (i = 0; i < 256; i++) {
347 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
348 R200_cp_microcode[i][1]);
349 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
350 R200_cp_microcode[i][0]);
351 }
352 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
353 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
354 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
355 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
356 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
357 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
358 DRM_INFO("Loading R300 Microcode\n");
359 for (i = 0; i < 256; i++) {
360 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
361 R300_cp_microcode[i][1]);
362 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
363 R300_cp_microcode[i][0]);
364 }
365 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
366 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
367 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
368 DRM_INFO("Loading R400 Microcode\n");
369 for (i = 0; i < 256; i++) {
370 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
371 R420_cp_microcode[i][1]);
372 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
373 R420_cp_microcode[i][0]);
374 }
375 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
376 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
377 DRM_INFO("Loading RS690/RS740 Microcode\n");
378 for (i = 0; i < 256; i++) {
379 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
380 RS690_cp_microcode[i][1]);
381 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
382 RS690_cp_microcode[i][0]);
383 }
384 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
385 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
386 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
387 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
388 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
389 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
390 DRM_INFO("Loading R500 Microcode\n");
391 for (i = 0; i < 256; i++) {
392 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
393 R520_cp_microcode[i][1]);
394 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
395 R520_cp_microcode[i][0]);
396 }
397 }
398 }
399
400 /* Flush any pending commands to the CP. This should only be used just
401 * prior to a wait for idle, as it informs the engine that the command
402 * stream is ending.
403 */
404 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
405 {
406 DRM_DEBUG("\n");
407 #if 0
408 u32 tmp;
409
410 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
411 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
412 #endif
413 }
414
415 /* Wait for the CP to go idle.
416 */
417 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
418 {
419 RING_LOCALS;
420 DRM_DEBUG("\n");
421
422 BEGIN_RING(6);
423
424 RADEON_PURGE_CACHE();
425 RADEON_PURGE_ZCACHE();
426 RADEON_WAIT_UNTIL_IDLE();
427
428 ADVANCE_RING();
429 COMMIT_RING();
430
431 return radeon_do_wait_for_idle(dev_priv);
432 }
433
434 /* Start the Command Processor.
435 */
436 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
437 {
438 RING_LOCALS;
439 DRM_DEBUG("\n");
440
441 radeon_do_wait_for_idle(dev_priv);
442
443 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
444
445 dev_priv->cp_running = 1;
446
447 BEGIN_RING(8);
448 /* isync can only be written through cp on r5xx write it here */
449 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
450 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
451 RADEON_ISYNC_ANY3D_IDLE2D |
452 RADEON_ISYNC_WAIT_IDLEGUI |
453 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
454 RADEON_PURGE_CACHE();
455 RADEON_PURGE_ZCACHE();
456 RADEON_WAIT_UNTIL_IDLE();
457 ADVANCE_RING();
458 COMMIT_RING();
459
460 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
461 }
462
463 /* Reset the Command Processor. This will not flush any pending
464 * commands, so you must wait for the CP command stream to complete
465 * before calling this routine.
466 */
467 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
468 {
469 u32 cur_read_ptr;
470 DRM_DEBUG("\n");
471
472 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
473 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
474 SET_RING_HEAD(dev_priv, cur_read_ptr);
475 dev_priv->ring.tail = cur_read_ptr;
476 }
477
478 /* Stop the Command Processor. This will not flush any pending
479 * commands, so you must flush the command stream and wait for the CP
480 * to go idle before calling this routine.
481 */
482 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
483 {
484 DRM_DEBUG("\n");
485
486 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
487
488 dev_priv->cp_running = 0;
489 }
490
491 /* Reset the engine. This will stop the CP if it is running.
492 */
493 static int radeon_do_engine_reset(struct drm_device * dev)
494 {
495 drm_radeon_private_t *dev_priv = dev->dev_private;
496 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
497 DRM_DEBUG("\n");
498
499 radeon_do_pixcache_flush(dev_priv);
500
501 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
502 /* may need something similar for newer chips */
503 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
504 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
505
506 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
507 RADEON_FORCEON_MCLKA |
508 RADEON_FORCEON_MCLKB |
509 RADEON_FORCEON_YCLKA |
510 RADEON_FORCEON_YCLKB |
511 RADEON_FORCEON_MC |
512 RADEON_FORCEON_AIC));
513 }
514
515 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
516
517 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
518 RADEON_SOFT_RESET_CP |
519 RADEON_SOFT_RESET_HI |
520 RADEON_SOFT_RESET_SE |
521 RADEON_SOFT_RESET_RE |
522 RADEON_SOFT_RESET_PP |
523 RADEON_SOFT_RESET_E2 |
524 RADEON_SOFT_RESET_RB));
525 RADEON_READ(RADEON_RBBM_SOFT_RESET);
526 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
527 ~(RADEON_SOFT_RESET_CP |
528 RADEON_SOFT_RESET_HI |
529 RADEON_SOFT_RESET_SE |
530 RADEON_SOFT_RESET_RE |
531 RADEON_SOFT_RESET_PP |
532 RADEON_SOFT_RESET_E2 |
533 RADEON_SOFT_RESET_RB)));
534 RADEON_READ(RADEON_RBBM_SOFT_RESET);
535
536 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
537 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
538 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
539 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
540 }
541
542 /* setup the raster pipes */
543 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
544 radeon_init_pipes(dev_priv);
545
546 /* Reset the CP ring */
547 radeon_do_cp_reset(dev_priv);
548
549 /* The CP is no longer running after an engine reset */
550 dev_priv->cp_running = 0;
551
552 /* Reset any pending vertex, indirect buffers */
553 radeon_freelist_reset(dev);
554
555 return 0;
556 }
557
558 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
559 drm_radeon_private_t * dev_priv)
560 {
561 u32 ring_start, cur_read_ptr;
562 u32 tmp;
563
564 /* Initialize the memory controller. With new memory map, the fb location
565 * is not changed, it should have been properly initialized already. Part
566 * of the problem is that the code below is bogus, assuming the GART is
567 * always appended to the fb which is not necessarily the case
568 */
569 if (!dev_priv->new_memmap)
570 radeon_write_fb_location(dev_priv,
571 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
572 | (dev_priv->fb_location >> 16));
573
574 #if __OS_HAS_AGP
575 if (dev_priv->flags & RADEON_IS_AGP) {
576 radeon_write_agp_base(dev_priv, dev->agp->base);
577
578 radeon_write_agp_location(dev_priv,
579 (((dev_priv->gart_vm_start - 1 +
580 dev_priv->gart_size) & 0xffff0000) |
581 (dev_priv->gart_vm_start >> 16)));
582
583 ring_start = (dev_priv->cp_ring->offset
584 - dev->agp->base
585 + dev_priv->gart_vm_start);
586 } else
587 #endif
588 ring_start = (dev_priv->cp_ring->offset
589 - (unsigned long)dev->sg->virtual
590 + dev_priv->gart_vm_start);
591
592 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
593
594 /* Set the write pointer delay */
595 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
596
597 /* Initialize the ring buffer's read and write pointers */
598 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
599 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
600 SET_RING_HEAD(dev_priv, cur_read_ptr);
601 dev_priv->ring.tail = cur_read_ptr;
602
603 #if __OS_HAS_AGP
604 if (dev_priv->flags & RADEON_IS_AGP) {
605 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
606 dev_priv->ring_rptr->offset
607 - dev->agp->base + dev_priv->gart_vm_start);
608 } else
609 #endif
610 {
611 struct drm_sg_mem *entry = dev->sg;
612 unsigned long tmp_ofs, page_ofs;
613
614 tmp_ofs = dev_priv->ring_rptr->offset -
615 (unsigned long)dev->sg->virtual;
616 page_ofs = tmp_ofs >> PAGE_SHIFT;
617
618 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
619 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
620 (unsigned long)entry->busaddr[page_ofs],
621 entry->handle + tmp_ofs);
622 }
623
624 /* Set ring buffer size */
625 #ifdef __BIG_ENDIAN
626 RADEON_WRITE(RADEON_CP_RB_CNTL,
627 RADEON_BUF_SWAP_32BIT |
628 (dev_priv->ring.fetch_size_l2ow << 18) |
629 (dev_priv->ring.rptr_update_l2qw << 8) |
630 dev_priv->ring.size_l2qw);
631 #else
632 RADEON_WRITE(RADEON_CP_RB_CNTL,
633 (dev_priv->ring.fetch_size_l2ow << 18) |
634 (dev_priv->ring.rptr_update_l2qw << 8) |
635 dev_priv->ring.size_l2qw);
636 #endif
637
638
639 /* Initialize the scratch register pointer. This will cause
640 * the scratch register values to be written out to memory
641 * whenever they are updated.
642 *
643 * We simply put this behind the ring read pointer, this works
644 * with PCI GART as well as (whatever kind of) AGP GART
645 */
646 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
647 + RADEON_SCRATCH_REG_OFFSET);
648
649 dev_priv->scratch = ((__volatile__ u32 *)
650 dev_priv->ring_rptr->handle +
651 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
652
653 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
654
655 /* Turn on bus mastering */
656 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
657 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
658 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
659 /* rs400, rs690/rs740 */
660 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS400_BUS_MASTER_DIS;
661 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
662 } else if (!(((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
663 ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R423))) {
664 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs480 */
665 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
666 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
667 } /* PCIE cards appears to not need this */
668
669 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
670 RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
671
672 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
673 RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
674 dev_priv->sarea_priv->last_dispatch);
675
676 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
677 RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
678
679 radeon_do_wait_for_idle(dev_priv);
680
681 /* Sync everything up */
682 RADEON_WRITE(RADEON_ISYNC_CNTL,
683 (RADEON_ISYNC_ANY2D_IDLE3D |
684 RADEON_ISYNC_ANY3D_IDLE2D |
685 RADEON_ISYNC_WAIT_IDLEGUI |
686 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
687
688 }
689
690 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
691 {
692 u32 tmp;
693
694 /* Start with assuming that writeback doesn't work */
695 dev_priv->writeback_works = 0;
696
697 /* Writeback doesn't seem to work everywhere, test it here and possibly
698 * enable it if it appears to work
699 */
700 DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
701 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
702
703 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
704 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
705 0xdeadbeef)
706 break;
707 DRM_UDELAY(1);
708 }
709
710 if (tmp < dev_priv->usec_timeout) {
711 dev_priv->writeback_works = 1;
712 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
713 } else {
714 dev_priv->writeback_works = 0;
715 DRM_INFO("writeback test failed\n");
716 }
717 if (radeon_no_wb == 1) {
718 dev_priv->writeback_works = 0;
719 DRM_INFO("writeback forced off\n");
720 }
721
722 if (!dev_priv->writeback_works) {
723 /* Disable writeback to avoid unnecessary bus master transfer */
724 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
725 RADEON_RB_NO_UPDATE);
726 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
727 }
728 }
729
730 /* Enable or disable IGP GART on the chip */
731 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
732 {
733 u32 temp;
734
735 if (on) {
736 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
737 dev_priv->gart_vm_start,
738 (long)dev_priv->gart_info.bus_addr,
739 dev_priv->gart_size);
740
741 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
742 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
743 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
744 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
745 RS690_BLOCK_GFX_D3_EN));
746 else
747 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
748
749 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
750 RS480_VA_SIZE_32MB));
751
752 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
753 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
754 RS480_TLB_ENABLE |
755 RS480_GTW_LAC_EN |
756 RS480_1LEVEL_GART));
757
758 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
759 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
760 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
761
762 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
763 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
764 RS480_REQ_TYPE_SNOOP_DIS));
765
766 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
767
768 dev_priv->gart_size = 32*1024*1024;
769 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
770 0xffff0000) | (dev_priv->gart_vm_start >> 16));
771
772 radeon_write_agp_location(dev_priv, temp);
773
774 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
775 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
776 RS480_VA_SIZE_32MB));
777
778 do {
779 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
780 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
781 break;
782 DRM_UDELAY(1);
783 } while (1);
784
785 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
786 RS480_GART_CACHE_INVALIDATE);
787
788 do {
789 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
790 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
791 break;
792 DRM_UDELAY(1);
793 } while (1);
794
795 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
796 } else {
797 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
798 }
799 }
800
801 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
802 {
803 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
804 if (on) {
805
806 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
807 dev_priv->gart_vm_start,
808 (long)dev_priv->gart_info.bus_addr,
809 dev_priv->gart_size);
810 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
811 dev_priv->gart_vm_start);
812 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
813 dev_priv->gart_info.bus_addr);
814 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
815 dev_priv->gart_vm_start);
816 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
817 dev_priv->gart_vm_start +
818 dev_priv->gart_size - 1);
819
820 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
821
822 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
823 RADEON_PCIE_TX_GART_EN);
824 } else {
825 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
826 tmp & ~RADEON_PCIE_TX_GART_EN);
827 }
828 }
829
830 /* Enable or disable PCI GART on the chip */
831 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
832 {
833 u32 tmp;
834
835 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
836 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
837 (dev_priv->flags & RADEON_IS_IGPGART)) {
838 radeon_set_igpgart(dev_priv, on);
839 return;
840 }
841
842 if (dev_priv->flags & RADEON_IS_PCIE) {
843 radeon_set_pciegart(dev_priv, on);
844 return;
845 }
846
847 tmp = RADEON_READ(RADEON_AIC_CNTL);
848
849 if (on) {
850 RADEON_WRITE(RADEON_AIC_CNTL,
851 tmp | RADEON_PCIGART_TRANSLATE_EN);
852
853 /* set PCI GART page-table base address
854 */
855 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
856
857 /* set address range for PCI address translate
858 */
859 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
860 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
861 + dev_priv->gart_size - 1);
862
863 /* Turn off AGP aperture -- is this required for PCI GART?
864 */
865 radeon_write_agp_location(dev_priv, 0xffffffc0);
866 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
867 } else {
868 RADEON_WRITE(RADEON_AIC_CNTL,
869 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
870 }
871 }
872
873 static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
874 {
875 drm_radeon_private_t *dev_priv = dev->dev_private;
876
877 DRM_DEBUG("\n");
878
879 /* if we require new memory map but we don't have it fail */
880 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
881 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
882 radeon_do_cleanup_cp(dev);
883 return -EINVAL;
884 }
885
886 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
887 DRM_DEBUG("Forcing AGP card to PCI mode\n");
888 dev_priv->flags &= ~RADEON_IS_AGP;
889 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
890 && !init->is_pci) {
891 DRM_DEBUG("Restoring AGP flag\n");
892 dev_priv->flags |= RADEON_IS_AGP;
893 }
894
895 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
896 DRM_ERROR("PCI GART memory not allocated!\n");
897 radeon_do_cleanup_cp(dev);
898 return -EINVAL;
899 }
900
901 dev_priv->usec_timeout = init->usec_timeout;
902 if (dev_priv->usec_timeout < 1 ||
903 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
904 DRM_DEBUG("TIMEOUT problem!\n");
905 radeon_do_cleanup_cp(dev);
906 return -EINVAL;
907 }
908
909 /* Enable vblank on CRTC1 for older X servers
910 */
911 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
912
913 switch(init->func) {
914 case RADEON_INIT_R200_CP:
915 dev_priv->microcode_version = UCODE_R200;
916 break;
917 case RADEON_INIT_R300_CP:
918 dev_priv->microcode_version = UCODE_R300;
919 break;
920 default:
921 dev_priv->microcode_version = UCODE_R100;
922 }
923
924 dev_priv->do_boxes = 0;
925 dev_priv->cp_mode = init->cp_mode;
926
927 /* We don't support anything other than bus-mastering ring mode,
928 * but the ring can be in either AGP or PCI space for the ring
929 * read pointer.
930 */
931 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
932 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
933 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
934 radeon_do_cleanup_cp(dev);
935 return -EINVAL;
936 }
937
938 switch (init->fb_bpp) {
939 case 16:
940 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
941 break;
942 case 32:
943 default:
944 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
945 break;
946 }
947 dev_priv->front_offset = init->front_offset;
948 dev_priv->front_pitch = init->front_pitch;
949 dev_priv->back_offset = init->back_offset;
950 dev_priv->back_pitch = init->back_pitch;
951
952 switch (init->depth_bpp) {
953 case 16:
954 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
955 break;
956 case 32:
957 default:
958 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
959 break;
960 }
961 dev_priv->depth_offset = init->depth_offset;
962 dev_priv->depth_pitch = init->depth_pitch;
963
964 /* Hardware state for depth clears. Remove this if/when we no
965 * longer clear the depth buffer with a 3D rectangle. Hard-code
966 * all values to prevent unwanted 3D state from slipping through
967 * and screwing with the clear operation.
968 */
969 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
970 (dev_priv->color_fmt << 10) |
971 (dev_priv->microcode_version ==
972 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
973
974 dev_priv->depth_clear.rb3d_zstencilcntl =
975 (dev_priv->depth_fmt |
976 RADEON_Z_TEST_ALWAYS |
977 RADEON_STENCIL_TEST_ALWAYS |
978 RADEON_STENCIL_S_FAIL_REPLACE |
979 RADEON_STENCIL_ZPASS_REPLACE |
980 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
981
982 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
983 RADEON_BFACE_SOLID |
984 RADEON_FFACE_SOLID |
985 RADEON_FLAT_SHADE_VTX_LAST |
986 RADEON_DIFFUSE_SHADE_FLAT |
987 RADEON_ALPHA_SHADE_FLAT |
988 RADEON_SPECULAR_SHADE_FLAT |
989 RADEON_FOG_SHADE_FLAT |
990 RADEON_VTX_PIX_CENTER_OGL |
991 RADEON_ROUND_MODE_TRUNC |
992 RADEON_ROUND_PREC_8TH_PIX);
993
994
995 dev_priv->ring_offset = init->ring_offset;
996 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
997 dev_priv->buffers_offset = init->buffers_offset;
998 dev_priv->gart_textures_offset = init->gart_textures_offset;
999
1000 dev_priv->sarea = drm_getsarea(dev);
1001 if (!dev_priv->sarea) {
1002 DRM_ERROR("could not find sarea!\n");
1003 radeon_do_cleanup_cp(dev);
1004 return -EINVAL;
1005 }
1006
1007 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1008 if (!dev_priv->cp_ring) {
1009 DRM_ERROR("could not find cp ring region!\n");
1010 radeon_do_cleanup_cp(dev);
1011 return -EINVAL;
1012 }
1013 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1014 if (!dev_priv->ring_rptr) {
1015 DRM_ERROR("could not find ring read pointer!\n");
1016 radeon_do_cleanup_cp(dev);
1017 return -EINVAL;
1018 }
1019 dev->agp_buffer_token = init->buffers_offset;
1020 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1021 if (!dev->agp_buffer_map) {
1022 DRM_ERROR("could not find dma buffer region!\n");
1023 radeon_do_cleanup_cp(dev);
1024 return -EINVAL;
1025 }
1026
1027 if (init->gart_textures_offset) {
1028 dev_priv->gart_textures =
1029 drm_core_findmap(dev, init->gart_textures_offset);
1030 if (!dev_priv->gart_textures) {
1031 DRM_ERROR("could not find GART texture region!\n");
1032 radeon_do_cleanup_cp(dev);
1033 return -EINVAL;
1034 }
1035 }
1036
1037 dev_priv->sarea_priv =
1038 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1039 init->sarea_priv_offset);
1040
1041 #if __OS_HAS_AGP
1042 if (dev_priv->flags & RADEON_IS_AGP) {
1043 drm_core_ioremap(dev_priv->cp_ring, dev);
1044 drm_core_ioremap(dev_priv->ring_rptr, dev);
1045 drm_core_ioremap(dev->agp_buffer_map, dev);
1046 if (!dev_priv->cp_ring->handle ||
1047 !dev_priv->ring_rptr->handle ||
1048 !dev->agp_buffer_map->handle) {
1049 DRM_ERROR("could not find ioremap agp regions!\n");
1050 radeon_do_cleanup_cp(dev);
1051 return -EINVAL;
1052 }
1053 } else
1054 #endif
1055 {
1056 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1057 dev_priv->ring_rptr->handle =
1058 (void *)dev_priv->ring_rptr->offset;
1059 dev->agp_buffer_map->handle =
1060 (void *)dev->agp_buffer_map->offset;
1061
1062 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1063 dev_priv->cp_ring->handle);
1064 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1065 dev_priv->ring_rptr->handle);
1066 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1067 dev->agp_buffer_map->handle);
1068 }
1069
1070 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1071 dev_priv->fb_size =
1072 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1073 - dev_priv->fb_location;
1074
1075 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1076 ((dev_priv->front_offset
1077 + dev_priv->fb_location) >> 10));
1078
1079 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1080 ((dev_priv->back_offset
1081 + dev_priv->fb_location) >> 10));
1082
1083 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1084 ((dev_priv->depth_offset
1085 + dev_priv->fb_location) >> 10));
1086
1087 dev_priv->gart_size = init->gart_size;
1088
1089 /* New let's set the memory map ... */
1090 if (dev_priv->new_memmap) {
1091 u32 base = 0;
1092
1093 DRM_INFO("Setting GART location based on new memory map\n");
1094
1095 /* If using AGP, try to locate the AGP aperture at the same
1096 * location in the card and on the bus, though we have to
1097 * align it down.
1098 */
1099 #if __OS_HAS_AGP
1100 if (dev_priv->flags & RADEON_IS_AGP) {
1101 base = dev->agp->base;
1102 /* Check if valid */
1103 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1104 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1105 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1106 dev->agp->base);
1107 base = 0;
1108 }
1109 }
1110 #endif
1111 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1112 if (base == 0) {
1113 base = dev_priv->fb_location + dev_priv->fb_size;
1114 if (base < dev_priv->fb_location ||
1115 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1116 base = dev_priv->fb_location
1117 - dev_priv->gart_size;
1118 }
1119 dev_priv->gart_vm_start = base & 0xffc00000u;
1120 if (dev_priv->gart_vm_start != base)
1121 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1122 base, dev_priv->gart_vm_start);
1123 } else {
1124 DRM_INFO("Setting GART location based on old memory map\n");
1125 dev_priv->gart_vm_start = dev_priv->fb_location +
1126 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1127 }
1128
1129 #if __OS_HAS_AGP
1130 if (dev_priv->flags & RADEON_IS_AGP)
1131 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1132 - dev->agp->base
1133 + dev_priv->gart_vm_start);
1134 else
1135 #endif
1136 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1137 - (unsigned long)dev->sg->virtual
1138 + dev_priv->gart_vm_start);
1139
1140 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1141 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1142 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1143 dev_priv->gart_buffers_offset);
1144
1145 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1146 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1147 + init->ring_size / sizeof(u32));
1148 dev_priv->ring.size = init->ring_size;
1149 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1150
1151 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1152 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1153
1154 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1155 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1156 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1157
1158 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1159
1160 #if __OS_HAS_AGP
1161 if (dev_priv->flags & RADEON_IS_AGP) {
1162 /* Turn off PCI GART */
1163 radeon_set_pcigart(dev_priv, 0);
1164 } else
1165 #endif
1166 {
1167 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1168 /* if we have an offset set from userspace */
1169 if (dev_priv->pcigart_offset_set) {
1170 dev_priv->gart_info.bus_addr =
1171 dev_priv->pcigart_offset + dev_priv->fb_location;
1172 dev_priv->gart_info.mapping.offset =
1173 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1174 dev_priv->gart_info.mapping.size =
1175 dev_priv->gart_info.table_size;
1176
1177 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1178 dev_priv->gart_info.addr =
1179 dev_priv->gart_info.mapping.handle;
1180
1181 if (dev_priv->flags & RADEON_IS_PCIE)
1182 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1183 else
1184 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1185 dev_priv->gart_info.gart_table_location =
1186 DRM_ATI_GART_FB;
1187
1188 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1189 dev_priv->gart_info.addr,
1190 dev_priv->pcigart_offset);
1191 } else {
1192 if (dev_priv->flags & RADEON_IS_IGPGART)
1193 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1194 else
1195 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1196 dev_priv->gart_info.gart_table_location =
1197 DRM_ATI_GART_MAIN;
1198 dev_priv->gart_info.addr = NULL;
1199 dev_priv->gart_info.bus_addr = 0;
1200 if (dev_priv->flags & RADEON_IS_PCIE) {
1201 DRM_ERROR
1202 ("Cannot use PCI Express without GART in FB memory\n");
1203 radeon_do_cleanup_cp(dev);
1204 return -EINVAL;
1205 }
1206 }
1207
1208 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1209 DRM_ERROR("failed to init PCI GART!\n");
1210 radeon_do_cleanup_cp(dev);
1211 return -ENOMEM;
1212 }
1213
1214 /* Turn on PCI GART */
1215 radeon_set_pcigart(dev_priv, 1);
1216 }
1217
1218 radeon_cp_load_microcode(dev_priv);
1219 radeon_cp_init_ring_buffer(dev, dev_priv);
1220
1221 dev_priv->last_buf = 0;
1222
1223 radeon_do_engine_reset(dev);
1224 radeon_test_writeback(dev_priv);
1225
1226 return 0;
1227 }
1228
1229 static int radeon_do_cleanup_cp(struct drm_device * dev)
1230 {
1231 drm_radeon_private_t *dev_priv = dev->dev_private;
1232 DRM_DEBUG("\n");
1233
1234 /* Make sure interrupts are disabled here because the uninstall ioctl
1235 * may not have been called from userspace and after dev_private
1236 * is freed, it's too late.
1237 */
1238 if (dev->irq_enabled)
1239 drm_irq_uninstall(dev);
1240
1241 #if __OS_HAS_AGP
1242 if (dev_priv->flags & RADEON_IS_AGP) {
1243 if (dev_priv->cp_ring != NULL) {
1244 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1245 dev_priv->cp_ring = NULL;
1246 }
1247 if (dev_priv->ring_rptr != NULL) {
1248 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1249 dev_priv->ring_rptr = NULL;
1250 }
1251 if (dev->agp_buffer_map != NULL) {
1252 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1253 dev->agp_buffer_map = NULL;
1254 }
1255 } else
1256 #endif
1257 {
1258
1259 if (dev_priv->gart_info.bus_addr) {
1260 /* Turn off PCI GART */
1261 radeon_set_pcigart(dev_priv, 0);
1262 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1263 DRM_ERROR("failed to cleanup PCI GART!\n");
1264 }
1265
1266 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1267 {
1268 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1269 dev_priv->gart_info.addr = 0;
1270 }
1271 }
1272 /* only clear to the start of flags */
1273 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1274
1275 return 0;
1276 }
1277
1278 /* This code will reinit the Radeon CP hardware after a resume from disc.
1279 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1280 * here we make sure that all Radeon hardware initialisation is re-done without
1281 * affecting running applications.
1282 *
1283 * Charl P. Botha <http://cpbotha.net>
1284 */
1285 static int radeon_do_resume_cp(struct drm_device * dev)
1286 {
1287 drm_radeon_private_t *dev_priv = dev->dev_private;
1288
1289 if (!dev_priv) {
1290 DRM_ERROR("Called with no initialization\n");
1291 return -EINVAL;
1292 }
1293
1294 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1295
1296 #if __OS_HAS_AGP
1297 if (dev_priv->flags & RADEON_IS_AGP) {
1298 /* Turn off PCI GART */
1299 radeon_set_pcigart(dev_priv, 0);
1300 } else
1301 #endif
1302 {
1303 /* Turn on PCI GART */
1304 radeon_set_pcigart(dev_priv, 1);
1305 }
1306
1307 radeon_cp_load_microcode(dev_priv);
1308 radeon_cp_init_ring_buffer(dev, dev_priv);
1309
1310 radeon_do_engine_reset(dev);
1311 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1312
1313 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1314
1315 return 0;
1316 }
1317
1318 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1319 {
1320 drm_radeon_init_t *init = data;
1321
1322 LOCK_TEST_WITH_RETURN(dev, file_priv);
1323
1324 if (init->func == RADEON_INIT_R300_CP)
1325 r300_init_reg_flags(dev);
1326
1327 switch (init->func) {
1328 case RADEON_INIT_CP:
1329 case RADEON_INIT_R200_CP:
1330 case RADEON_INIT_R300_CP:
1331 return radeon_do_init_cp(dev, init);
1332 case RADEON_CLEANUP_CP:
1333 return radeon_do_cleanup_cp(dev);
1334 }
1335
1336 return -EINVAL;
1337 }
1338
1339 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1340 {
1341 drm_radeon_private_t *dev_priv = dev->dev_private;
1342 DRM_DEBUG("\n");
1343
1344 LOCK_TEST_WITH_RETURN(dev, file_priv);
1345
1346 if (dev_priv->cp_running) {
1347 DRM_DEBUG("while CP running\n");
1348 return 0;
1349 }
1350 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1351 DRM_DEBUG("called with bogus CP mode (%d)\n",
1352 dev_priv->cp_mode);
1353 return 0;
1354 }
1355
1356 radeon_do_cp_start(dev_priv);
1357
1358 return 0;
1359 }
1360
1361 /* Stop the CP. The engine must have been idled before calling this
1362 * routine.
1363 */
1364 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1365 {
1366 drm_radeon_private_t *dev_priv = dev->dev_private;
1367 drm_radeon_cp_stop_t *stop = data;
1368 int ret;
1369 DRM_DEBUG("\n");
1370
1371 LOCK_TEST_WITH_RETURN(dev, file_priv);
1372
1373 if (!dev_priv->cp_running)
1374 return 0;
1375
1376 /* Flush any pending CP commands. This ensures any outstanding
1377 * commands are exectuted by the engine before we turn it off.
1378 */
1379 if (stop->flush) {
1380 radeon_do_cp_flush(dev_priv);
1381 }
1382
1383 /* If we fail to make the engine go idle, we return an error
1384 * code so that the DRM ioctl wrapper can try again.
1385 */
1386 if (stop->idle) {
1387 ret = radeon_do_cp_idle(dev_priv);
1388 if (ret)
1389 return ret;
1390 }
1391
1392 /* Finally, we can turn off the CP. If the engine isn't idle,
1393 * we will get some dropped triangles as they won't be fully
1394 * rendered before the CP is shut down.
1395 */
1396 radeon_do_cp_stop(dev_priv);
1397
1398 /* Reset the engine */
1399 radeon_do_engine_reset(dev);
1400
1401 return 0;
1402 }
1403
1404 void radeon_do_release(struct drm_device * dev)
1405 {
1406 drm_radeon_private_t *dev_priv = dev->dev_private;
1407 int i, ret;
1408
1409 if (dev_priv) {
1410 if (dev_priv->cp_running) {
1411 /* Stop the cp */
1412 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1413 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1414 #ifdef __linux__
1415 schedule();
1416 #else
1417 tsleep(&ret, PZERO, "rdnrel", 1);
1418 #endif
1419 }
1420 radeon_do_cp_stop(dev_priv);
1421 radeon_do_engine_reset(dev);
1422 }
1423
1424 /* Disable *all* interrupts */
1425 if (dev_priv->mmio) /* remove this after permanent addmaps */
1426 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1427
1428 if (dev_priv->mmio) { /* remove all surfaces */
1429 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1430 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1431 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1432 16 * i, 0);
1433 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1434 16 * i, 0);
1435 }
1436 }
1437
1438 /* Free memory heap structures */
1439 radeon_mem_takedown(&(dev_priv->gart_heap));
1440 radeon_mem_takedown(&(dev_priv->fb_heap));
1441
1442 /* deallocate kernel resources */
1443 radeon_do_cleanup_cp(dev);
1444 }
1445 }
1446
1447 /* Just reset the CP ring. Called as part of an X Server engine reset.
1448 */
1449 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1450 {
1451 drm_radeon_private_t *dev_priv = dev->dev_private;
1452 DRM_DEBUG("\n");
1453
1454 LOCK_TEST_WITH_RETURN(dev, file_priv);
1455
1456 if (!dev_priv) {
1457 DRM_DEBUG("called before init done\n");
1458 return -EINVAL;
1459 }
1460
1461 radeon_do_cp_reset(dev_priv);
1462
1463 /* The CP is no longer running after an engine reset */
1464 dev_priv->cp_running = 0;
1465
1466 return 0;
1467 }
1468
1469 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1470 {
1471 drm_radeon_private_t *dev_priv = dev->dev_private;
1472 DRM_DEBUG("\n");
1473
1474 LOCK_TEST_WITH_RETURN(dev, file_priv);
1475
1476 return radeon_do_cp_idle(dev_priv);
1477 }
1478
1479 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1480 */
1481 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1482 {
1483
1484 return radeon_do_resume_cp(dev);
1485 }
1486
1487 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1488 {
1489 DRM_DEBUG("\n");
1490
1491 LOCK_TEST_WITH_RETURN(dev, file_priv);
1492
1493 return radeon_do_engine_reset(dev);
1494 }
1495
1496 /* ================================================================
1497 * Fullscreen mode
1498 */
1499
1500 /* KW: Deprecated to say the least:
1501 */
1502 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1503 {
1504 return 0;
1505 }
1506
1507 /* ================================================================
1508 * Freelist management
1509 */
1510
1511 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1512 * bufs until freelist code is used. Note this hides a problem with
1513 * the scratch register * (used to keep track of last buffer
1514 * completed) being written to before * the last buffer has actually
1515 * completed rendering.
1516 *
1517 * KW: It's also a good way to find free buffers quickly.
1518 *
1519 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1520 * sleep. However, bugs in older versions of radeon_accel.c mean that
1521 * we essentially have to do this, else old clients will break.
1522 *
1523 * However, it does leave open a potential deadlock where all the
1524 * buffers are held by other clients, which can't release them because
1525 * they can't get the lock.
1526 */
1527
1528 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1529 {
1530 struct drm_device_dma *dma = dev->dma;
1531 drm_radeon_private_t *dev_priv = dev->dev_private;
1532 drm_radeon_buf_priv_t *buf_priv;
1533 struct drm_buf *buf;
1534 int i, t;
1535 int start;
1536
1537 if (++dev_priv->last_buf >= dma->buf_count)
1538 dev_priv->last_buf = 0;
1539
1540 start = dev_priv->last_buf;
1541
1542 for (t = 0; t < dev_priv->usec_timeout; t++) {
1543 u32 done_age = GET_SCRATCH(1);
1544 DRM_DEBUG("done_age = %d\n", done_age);
1545 for (i = start; i < dma->buf_count; i++) {
1546 buf = dma->buflist[i];
1547 buf_priv = buf->dev_private;
1548 if (buf->file_priv == NULL || (buf->pending &&
1549 buf_priv->age <=
1550 done_age)) {
1551 dev_priv->stats.requested_bufs++;
1552 buf->pending = 0;
1553 return buf;
1554 }
1555 start = 0;
1556 }
1557
1558 if (t) {
1559 DRM_UDELAY(1);
1560 dev_priv->stats.freelist_loops++;
1561 }
1562 }
1563
1564 DRM_DEBUG("returning NULL!\n");
1565 return NULL;
1566 }
1567
1568 #if 0
1569 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1570 {
1571 struct drm_device_dma *dma = dev->dma;
1572 drm_radeon_private_t *dev_priv = dev->dev_private;
1573 drm_radeon_buf_priv_t *buf_priv;
1574 struct drm_buf *buf;
1575 int i, t;
1576 int start;
1577 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1578
1579 if (++dev_priv->last_buf >= dma->buf_count)
1580 dev_priv->last_buf = 0;
1581
1582 start = dev_priv->last_buf;
1583 dev_priv->stats.freelist_loops++;
1584
1585 for (t = 0; t < 2; t++) {
1586 for (i = start; i < dma->buf_count; i++) {
1587 buf = dma->buflist[i];
1588 buf_priv = buf->dev_private;
1589 if (buf->file_priv == 0 || (buf->pending &&
1590 buf_priv->age <=
1591 done_age)) {
1592 dev_priv->stats.requested_bufs++;
1593 buf->pending = 0;
1594 return buf;
1595 }
1596 }
1597 start = 0;
1598 }
1599
1600 return NULL;
1601 }
1602 #endif
1603
1604 void radeon_freelist_reset(struct drm_device * dev)
1605 {
1606 struct drm_device_dma *dma = dev->dma;
1607 drm_radeon_private_t *dev_priv = dev->dev_private;
1608 int i;
1609
1610 dev_priv->last_buf = 0;
1611 for (i = 0; i < dma->buf_count; i++) {
1612 struct drm_buf *buf = dma->buflist[i];
1613 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1614 buf_priv->age = 0;
1615 }
1616 }
1617
1618 /* ================================================================
1619 * CP command submission
1620 */
1621
1622 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1623 {
1624 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1625 int i;
1626 u32 last_head = GET_RING_HEAD(dev_priv);
1627
1628 for (i = 0; i < dev_priv->usec_timeout; i++) {
1629 u32 head = GET_RING_HEAD(dev_priv);
1630
1631 ring->space = (head - ring->tail) * sizeof(u32);
1632 if (ring->space <= 0)
1633 ring->space += ring->size;
1634 if (ring->space > n)
1635 return 0;
1636
1637 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1638
1639 if (head != last_head)
1640 i = 0;
1641 last_head = head;
1642
1643 DRM_UDELAY(1);
1644 }
1645
1646 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1647 #if RADEON_FIFO_DEBUG
1648 radeon_status(dev_priv);
1649 DRM_ERROR("failed!\n");
1650 #endif
1651 return -EBUSY;
1652 }
1653
1654 static int radeon_cp_get_buffers(struct drm_device *dev,
1655 struct drm_file *file_priv,
1656 struct drm_dma * d)
1657 {
1658 int i;
1659 struct drm_buf *buf;
1660
1661 for (i = d->granted_count; i < d->request_count; i++) {
1662 buf = radeon_freelist_get(dev);
1663 if (!buf)
1664 return -EBUSY; /* NOTE: broken client */
1665
1666 buf->file_priv = file_priv;
1667
1668 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1669 sizeof(buf->idx)))
1670 return -EFAULT;
1671 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1672 sizeof(buf->total)))
1673 return -EFAULT;
1674
1675 d->granted_count++;
1676 }
1677 return 0;
1678 }
1679
1680 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1681 {
1682 struct drm_device_dma *dma = dev->dma;
1683 int ret = 0;
1684 struct drm_dma *d = data;
1685
1686 LOCK_TEST_WITH_RETURN(dev, file_priv);
1687
1688 /* Please don't send us buffers.
1689 */
1690 if (d->send_count != 0) {
1691 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1692 DRM_CURRENTPID, d->send_count);
1693 return -EINVAL;
1694 }
1695
1696 /* We'll send you buffers.
1697 */
1698 if (d->request_count < 0 || d->request_count > dma->buf_count) {
1699 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1700 DRM_CURRENTPID, d->request_count, dma->buf_count);
1701 return -EINVAL;
1702 }
1703
1704 d->granted_count = 0;
1705
1706 if (d->request_count) {
1707 ret = radeon_cp_get_buffers(dev, file_priv, d);
1708 }
1709
1710 return ret;
1711 }
1712
1713 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1714 {
1715 drm_radeon_private_t *dev_priv;
1716 int ret = 0;
1717
1718 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
1719 if (dev_priv == NULL)
1720 return -ENOMEM;
1721
1722 memset(dev_priv, 0, sizeof(drm_radeon_private_t));
1723 dev->dev_private = (void *)dev_priv;
1724 dev_priv->flags = flags;
1725
1726 switch (flags & RADEON_FAMILY_MASK) {
1727 case CHIP_R100:
1728 case CHIP_RV200:
1729 case CHIP_R200:
1730 case CHIP_R300:
1731 case CHIP_R350:
1732 case CHIP_R420:
1733 case CHIP_R423:
1734 case CHIP_RV410:
1735 case CHIP_RV515:
1736 case CHIP_R520:
1737 case CHIP_RV570:
1738 case CHIP_R580:
1739 dev_priv->flags |= RADEON_HAS_HIERZ;
1740 break;
1741 default:
1742 /* all other chips have no hierarchical z buffer */
1743 break;
1744 }
1745
1746 if (drm_device_is_agp(dev))
1747 dev_priv->flags |= RADEON_IS_AGP;
1748 else if (drm_device_is_pcie(dev))
1749 dev_priv->flags |= RADEON_IS_PCIE;
1750 else
1751 dev_priv->flags |= RADEON_IS_PCI;
1752
1753 DRM_DEBUG("%s card detected\n",
1754 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1755 return ret;
1756 }
1757
1758 /* Create mappings for registers and framebuffer so userland doesn't necessarily
1759 * have to find them.
1760 */
1761 int radeon_driver_firstopen(struct drm_device *dev)
1762 {
1763 int ret;
1764 drm_local_map_t *map;
1765 drm_radeon_private_t *dev_priv = dev->dev_private;
1766
1767 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
1768
1769 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
1770 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
1771 _DRM_READ_ONLY, &dev_priv->mmio);
1772 if (ret != 0)
1773 return ret;
1774
1775 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
1776 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
1777 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
1778 _DRM_WRITE_COMBINING, &map);
1779 if (ret != 0)
1780 return ret;
1781
1782 return 0;
1783 }
1784
1785 int radeon_driver_unload(struct drm_device *dev)
1786 {
1787 drm_radeon_private_t *dev_priv = dev->dev_private;
1788
1789 DRM_DEBUG("\n");
1790 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
1791
1792 dev->dev_private = NULL;
1793 return 0;
1794 }
Support for the Chinese Samsung S3C2440 based development boards