arch/powerpc/platforms/8xx/mpc86xads_setup.c

   1 /*arch/powerpc/platforms/8xx/mpc86xads_setup.c
   2  *
   3  * Platform setup for the Freescale mpc86xads board
   4  *
   5  * Vitaly Bordug <vbordug@ru.mvista.com>
   6  *
   7  * Copyright 2005 MontaVista Software Inc.
   8  *
   9  * This file is licensed under the terms of the GNU General Public License
  10  * version 2. This program is licensed "as is" without any warranty of any
  11  * kind, whether express or implied.
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/module.h>
  16 #include <linux/param.h>
  17 #include <linux/string.h>
  18 #include <linux/ioport.h>
  19 #include <linux/device.h>
  20 #include <linux/delay.h>
  21 #include <linux/root_dev.h>
  22
  23 #include <linux/fs_enet_pd.h>
  24 #include <linux/fs_uart_pd.h>
  25 #include <linux/mii.h>
  26
  27 #include <asm/delay.h>
  28 #include <asm/io.h>
  29 #include <asm/machdep.h>
  30 #include <asm/page.h>
  31 #include <asm/processor.h>
  32 #include <asm/system.h>
  33 #include <asm/time.h>
  34 #include <asm/mpc8xx.h>
  35 #include <asm/8xx_immap.h>
  36 #include <asm/commproc.h>
  37 #include <asm/fs_pd.h>
  38 #include <asm/prom.h>
  39
  40 extern void cpm_reset(void);
  41 extern void mpc8xx_show_cpuinfo(struct seq_file*);
  42 extern void mpc8xx_restart(char *cmd);
  43 extern void mpc8xx_calibrate_decr(void);
  44 extern int mpc8xx_set_rtc_time(struct rtc_time *tm);
  45 extern void mpc8xx_get_rtc_time(struct rtc_time *tm);
  46 extern void m8xx_pic_init(void);
  47 extern unsigned int mpc8xx_get_irq(void);
  48
  49 static void init_smc1_uart_ioports(struct fs_uart_platform_info* fpi);
  50 static void init_smc2_uart_ioports(struct fs_uart_platform_info* fpi);
  51 static void init_scc1_ioports(struct fs_platform_info* ptr);
  52
  53 void __init mpc86xads_board_setup(void)
  54 {
  55         cpm8xx_t *cp;
  56         unsigned int *bcsr_io;
  57         u8 tmpval8;
  58
  59         bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
  60         cp = (cpm8xx_t *)immr_map(im_cpm);
  61
  62         if (bcsr_io == NULL) {
  63                 printk(KERN_CRIT "Could not remap BCSR\n");
  64                 return;
  65         }
  66 #ifdef CONFIG_SERIAL_CPM_SMC1
  67         clrbits32(bcsr_io, BCSR1_RS232EN_1);
  68         clrbits32(&cp->cp_simode, 0xe0000000 >> 17);    /* brg1 */
  69         tmpval8 = in_8(&(cp->cp_smc[0].smc_smcm)) | (SMCM_RX | SMCM_TX);
  70         out_8(&(cp->cp_smc[0].smc_smcm), tmpval8);
  71         clrbits16(&cp->cp_smc[0].smc_smcmr, SMCMR_REN | SMCMR_TEN);
  72 #else
  73         setbits32(bcsr_io,BCSR1_RS232EN_1);
  74         out_be16(&cp->cp_smc[0].smc_smcmr, 0);
  75         out_8(&cp->cp_smc[0].smc_smce, 0);
  76 #endif
  77
  78 #ifdef CONFIG_SERIAL_CPM_SMC2
  79         clrbits32(bcsr_io,BCSR1_RS232EN_2);
  80         clrbits32(&cp->cp_simode, 0xe0000000 >> 1);
  81         setbits32(&cp->cp_simode, 0x20000000 >> 1);     /* brg2 */
  82         tmpval8 = in_8(&(cp->cp_smc[1].smc_smcm)) | (SMCM_RX | SMCM_TX);
  83         out_8(&(cp->cp_smc[1].smc_smcm), tmpval8);
  84         clrbits16(&cp->cp_smc[1].smc_smcmr, SMCMR_REN | SMCMR_TEN);
  85
  86         init_smc2_uart_ioports(0);
  87 #else
  88         setbits32(bcsr_io,BCSR1_RS232EN_2);
  89         out_be16(&cp->cp_smc[1].smc_smcmr, 0);
  90         out_8(&cp->cp_smc[1].smc_smce, 0);
  91 #endif
  92         immr_unmap(cp);
  93         iounmap(bcsr_io);
  94 }
  95
  96
  97 static void init_fec1_ioports(struct fs_platform_info* ptr)
  98 {
  99         iop8xx_t *io_port = (iop8xx_t *)immr_map(im_ioport);
 100
 101         /* configure FEC1 pins  */
 102
 103         setbits16(&io_port->iop_pdpar, 0x1fff);
 104         setbits16(&io_port->iop_pddir, 0x1fff);
 105
 106         immr_unmap(io_port);
 107 }
 108
 109 void init_fec_ioports(struct fs_platform_info *fpi)
 110 {
 111         int fec_no = fs_get_fec_index(fpi->fs_no);
 112
 113         switch (fec_no) {
 114         case 0:
 115                 init_fec1_ioports(fpi);
 116                 break;
 117         default:
 118                 printk(KERN_ERR "init_fec_ioports: invalid FEC number\n");
 119                 return;
 120         }
 121 }
 122
 123 static void init_scc1_ioports(struct fs_platform_info* fpi)
 124 {
 125         unsigned *bcsr_io;
 126         iop8xx_t *io_port;
 127         cpm8xx_t *cp;
 128
 129         bcsr_io = ioremap(BCSR_ADDR, BCSR_SIZE);
 130         io_port = (iop8xx_t *)immr_map(im_ioport);
 131         cp = (cpm8xx_t *)immr_map(im_cpm);
 132
 133         if (bcsr_io == NULL) {
 134                 printk(KERN_CRIT "Could not remap BCSR\n");
 135                 return;
 136         }
 137
 138         /* Configure port A pins for Txd and Rxd.
 139          */
 140         setbits16(&io_port->iop_papar, PA_ENET_RXD | PA_ENET_TXD);
 141         clrbits16(&io_port->iop_padir, PA_ENET_RXD | PA_ENET_TXD);
 142         clrbits16(&io_port->iop_paodr, PA_ENET_TXD);
 143
 144         /* Configure port C pins to enable CLSN and RENA.
 145          */
 146         clrbits16(&io_port->iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA);
 147         clrbits16(&io_port->iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA);
 148         setbits16(&io_port->iop_pcso, PC_ENET_CLSN | PC_ENET_RENA);
 149
 150         /* Configure port A for TCLK and RCLK.
 151          */
 152         setbits16(&io_port->iop_papar, PA_ENET_TCLK | PA_ENET_RCLK);
 153         clrbits16(&io_port->iop_padir, PA_ENET_TCLK | PA_ENET_RCLK);
 154         clrbits32(&cp->cp_pbpar, PB_ENET_TENA);
 155         clrbits32(&cp->cp_pbdir, PB_ENET_TENA);
 156
 157         /* Configure Serial Interface clock routing.
 158          * First, clear all SCC bits to zero, then set the ones we want.
 159          */
 160         clrbits32(&cp->cp_sicr, SICR_ENET_MASK);
 161         setbits32(&cp->cp_sicr, SICR_ENET_CLKRT);
 162
 163         /* In the original SCC enet driver the following code is placed at
 164            the end of the initialization */
 165         setbits32(&cp->cp_pbpar, PB_ENET_TENA);
 166         setbits32(&cp->cp_pbdir, PB_ENET_TENA);
 167
 168         clrbits32(bcsr_io+1, BCSR1_ETHEN);
 169         iounmap(bcsr_io);
 170         immr_unmap(cp);
 171         immr_unmap(io_port);
 172 }
 173
 174 void init_scc_ioports(struct fs_platform_info *fpi)
 175 {
 176         int scc_no = fs_get_scc_index(fpi->fs_no);
 177
 178         switch (scc_no) {
 179         case 0:
 180                 init_scc1_ioports(fpi);
 181                 break;
 182         default:
 183                 printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
 184                 return;
 185         }
 186 }
 187
 188
 189
 190 static void init_smc1_uart_ioports(struct fs_uart_platform_info* ptr)
 191 {
 192         unsigned *bcsr_io;
 193         cpm8xx_t *cp = (cpm8xx_t *)immr_map(im_cpm);
 194
 195         setbits32(&cp->cp_pbpar, 0x000000c0);
 196         clrbits32(&cp->cp_pbdir, 0x000000c0);
 197         clrbits16(&cp->cp_pbodr, 0x00c0);
 198         immr_unmap(cp);
 199
 200         bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
 201
 202         if (bcsr_io == NULL) {
 203                 printk(KERN_CRIT "Could not remap BCSR1\n");
 204                 return;
 205         }
 206         clrbits32(bcsr_io,BCSR1_RS232EN_1);
 207         iounmap(bcsr_io);
 208 }
 209
 210 static void init_smc2_uart_ioports(struct fs_uart_platform_info* fpi)
 211 {
 212         unsigned *bcsr_io;
 213         cpm8xx_t *cp = (cpm8xx_t *)immr_map(im_cpm);
 214
 215         setbits32(&cp->cp_pbpar, 0x00000c00);
 216         clrbits32(&cp->cp_pbdir, 0x00000c00);
 217         clrbits16(&cp->cp_pbodr, 0x0c00);
 218         immr_unmap(cp);
 219
 220         bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
 221
 222         if (bcsr_io == NULL) {
 223                 printk(KERN_CRIT "Could not remap BCSR1\n");
 224                 return;
 225         }
 226         clrbits32(bcsr_io,BCSR1_RS232EN_2);
 227         iounmap(bcsr_io);
 228 }
 229
 230 void init_smc_ioports(struct fs_uart_platform_info *data)
 231 {
 232         int smc_no = fs_uart_id_fsid2smc(data->fs_no);
 233
 234         switch (smc_no) {
 235         case 0:
 236                 init_smc1_uart_ioports(data);
 237                 data->brg = data->clk_rx;
 238                 break;
 239         case 1:
 240                 init_smc2_uart_ioports(data);
 241                 data->brg = data->clk_rx;
 242                 break;
 243         default:
 244                 printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
 245                 return;
 246         }
 247 }
 248
 249 int platform_device_skip(const char *model, int id)
 250 {
 251         return 0;
 252 }
 253
 254 static void __init mpc86xads_setup_arch(void)
 255 {
 256         cpm_reset();
 257
 258         mpc86xads_board_setup();
 259
 260         ROOT_DEV = Root_NFS;
 261 }
 262
 263 static int __init mpc86xads_probe(void)
 264 {
 265         char *model = of_get_flat_dt_prop(of_get_flat_dt_root(),
 266                                           "model", NULL);
 267         if (model == NULL)
 268                 return 0;
 269         if (strcmp(model, "MPC866ADS"))
 270                 return 0;
 271
 272         return 1;
 273 }
 274
 275 define_machine(mpc86x_ads) {
 276         .name                   = "MPC86x ADS",
 277         .probe                  = mpc86xads_probe,
 278         .setup_arch             = mpc86xads_setup_arch,
 279         .init_IRQ               = m8xx_pic_init,
 280         .show_cpuinfo           = mpc8xx_show_cpuinfo,
 281         .get_irq                = mpc8xx_get_irq,
 282         .restart                = mpc8xx_restart,
 283         .calibrate_decr         = mpc8xx_calibrate_decr,
 284         .set_rtc_time           = mpc8xx_set_rtc_time,
 285         .get_rtc_time           = mpc8xx_get_rtc_time,
 286 };