arch/powerpc/platforms/8xx/m8xx_setup.c

   1 /*
   2  *  Copyright (C) 1995  Linus Torvalds
   3  *  Adapted from 'alpha' version by Gary Thomas
   4  *  Modified by Cort Dougan (cort@cs.nmt.edu)
   5  *  Modified for MBX using prep/chrp/pmac functions by Dan (dmalek@jlc.net)
   6  *  Further modified for generic 8xx by Dan.
   7  */
   8
   9 /*
  10  * bootup setup stuff..
  11  */
  12
  13 #include <linux/errno.h>
  14 #include <linux/sched.h>
  15 #include <linux/kernel.h>
  16 #include <linux/mm.h>
  17 #include <linux/stddef.h>
  18 #include <linux/unistd.h>
  19 #include <linux/ptrace.h>
  20 #include <linux/slab.h>
  21 #include <linux/user.h>
  22 #include <linux/a.out.h>
  23 #include <linux/tty.h>
  24 #include <linux/major.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/reboot.h>
  27 #include <linux/init.h>
  28 #include <linux/initrd.h>
  29 #include <linux/ioport.h>
  30 #include <linux/bootmem.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/root_dev.h>
  33 #include <linux/time.h>
  34 #include <linux/rtc.h>
  35 #include <linux/fsl_devices.h>
  36
  37 #include <asm/mmu.h>
  38 #include <asm/reg.h>
  39 #include <asm/io.h>
  40 #include <asm/pgtable.h>
  41 #include <asm/mpc8xx.h>
  42 #include <asm/8xx_immap.h>
  43 #include <asm/machdep.h>
  44 #include <asm/time.h>
  45 #include <asm/prom.h>
  46 #include <asm/fs_pd.h>
  47 #include <mm/mmu_decl.h>
  48
  49 #include "sysdev/mpc8xx_pic.h"
  50
  51 #ifdef CONFIG_PCMCIA_M8XX
  52 struct mpc8xx_pcmcia_ops m8xx_pcmcia_ops;
  53 #endif
  54
  55 void m8xx_calibrate_decr(void);
  56 #ifdef CONFIG_8xx_WDT
  57 extern void m8xx_wdt_handler_install(bd_t *bp);
  58 #endif
  59 extern int cpm_pic_init(void);
  60 extern int cpm_get_irq(void);
  61
  62 /* A place holder for time base interrupts, if they are ever enabled. */
  63 irqreturn_t timebase_interrupt(int irq, void * dev)
  64 {
  65         printk ("timebase_interrupt()\n");
  66
  67         return IRQ_HANDLED;
  68 }
  69
  70 static struct irqaction tbint_irqaction = {
  71         .handler = timebase_interrupt,
  72         .mask = CPU_MASK_NONE,
  73         .name = "tbint",
  74 };
  75
  76 /* per-board overridable init_internal_rtc() function. */
  77 void __init __attribute__ ((weak))
  78 init_internal_rtc(void)
  79 {
  80         sit8xx_t *sys_tmr = (sit8xx_t *) immr_map(im_sit);
  81
  82         /* Disable the RTC one second and alarm interrupts. */
  83         clrbits16(&sys_tmr->sit_rtcsc, (RTCSC_SIE | RTCSC_ALE));
  84
  85         /* Enable the RTC */
  86         setbits16(&sys_tmr->sit_rtcsc, (RTCSC_RTF | RTCSC_RTE));
  87         immr_unmap(sys_tmr);
  88 }
  89
  90 static int __init get_freq(char *name, unsigned long *val)
  91 {
  92         struct device_node *cpu;
  93         const unsigned int *fp;
  94         int found = 0;
  95
  96         /* The cpu node should have timebase and clock frequency properties */
  97         cpu = of_find_node_by_type(NULL, "cpu");
  98
  99         if (cpu) {
 100                 fp = of_get_property(cpu, name, NULL);
 101                 if (fp) {
 102                         found = 1;
 103                         *val = *fp;
 104                 }
 105
 106                 of_node_put(cpu);
 107         }
 108
 109         return found;
 110 }
 111
 112 /* The decrementer counts at the system (internal) clock frequency divided by
 113  * sixteen, or external oscillator divided by four.  We force the processor
 114  * to use system clock divided by sixteen.
 115  */
 116 void __init mpc8xx_calibrate_decr(void)
 117 {
 118         struct device_node *cpu;
 119         cark8xx_t *clk_r1;
 120         car8xx_t *clk_r2;
 121         sitk8xx_t *sys_tmr1;
 122         sit8xx_t *sys_tmr2;
 123         int irq, virq;
 124
 125         clk_r1 = (cark8xx_t *) immr_map(im_clkrstk);
 126
 127         /* Unlock the SCCR. */
 128         out_be32(&clk_r1->cark_sccrk, ~KAPWR_KEY);
 129         out_be32(&clk_r1->cark_sccrk, KAPWR_KEY);
 130         immr_unmap(clk_r1);
 131
 132         /* Force all 8xx processors to use divide by 16 processor clock. */
 133         clk_r2 = (car8xx_t *) immr_map(im_clkrst);
 134         setbits32(&clk_r2->car_sccr, 0x02000000);
 135         immr_unmap(clk_r2);
 136
 137         /* Processor frequency is MHz.
 138          */
 139         ppc_tb_freq = 50000000;
 140         if (!get_freq("bus-frequency", &ppc_tb_freq)) {
 141                 printk(KERN_ERR "WARNING: Estimating decrementer frequency "
 142                                 "(not found)\n");
 143         }
 144         ppc_tb_freq /= 16;
 145         ppc_proc_freq = 50000000;
 146         if (!get_freq("clock-frequency", &ppc_proc_freq))
 147                 printk(KERN_ERR "WARNING: Estimating processor frequency"
 148                                 "(not found)\n");
 149
 150         printk("Decrementer Frequency = 0x%lx\n", ppc_tb_freq);
 151
 152         /* Perform some more timer/timebase initialization.  This used
 153          * to be done elsewhere, but other changes caused it to get
 154          * called more than once....that is a bad thing.
 155          *
 156          * First, unlock all of the registers we are going to modify.
 157          * To protect them from corruption during power down, registers
 158          * that are maintained by keep alive power are "locked".  To
 159          * modify these registers we have to write the key value to
 160          * the key location associated with the register.
 161          * Some boards power up with these unlocked, while others
 162          * are locked.  Writing anything (including the unlock code?)
 163          * to the unlocked registers will lock them again.  So, here
 164          * we guarantee the registers are locked, then we unlock them
 165          * for our use.
 166          */
 167         sys_tmr1 = (sitk8xx_t *) immr_map(im_sitk);
 168         out_be32(&sys_tmr1->sitk_tbscrk, ~KAPWR_KEY);
 169         out_be32(&sys_tmr1->sitk_rtcsck, ~KAPWR_KEY);
 170         out_be32(&sys_tmr1->sitk_tbk, ~KAPWR_KEY);
 171         out_be32(&sys_tmr1->sitk_tbscrk, KAPWR_KEY);
 172         out_be32(&sys_tmr1->sitk_rtcsck, KAPWR_KEY);
 173         out_be32(&sys_tmr1->sitk_tbk, KAPWR_KEY);
 174         immr_unmap(sys_tmr1);
 175
 176         init_internal_rtc();
 177
 178         /* Enabling the decrementer also enables the timebase interrupts
 179          * (or from the other point of view, to get decrementer interrupts
 180          * we have to enable the timebase).  The decrementer interrupt
 181          * is wired into the vector table, nothing to do here for that.
 182          */
 183         cpu = of_find_node_by_type(NULL, "cpu");
 184         virq= irq_of_parse_and_map(cpu, 0);
 185         irq = irq_map[virq].hwirq;
 186
 187         sys_tmr2 = (sit8xx_t *) immr_map(im_sit);
 188         out_be16(&sys_tmr2->sit_tbscr, ((1 << (7 - (irq/2))) << 8) |
 189                                         (TBSCR_TBF | TBSCR_TBE));
 190         immr_unmap(sys_tmr2);
 191
 192         if (setup_irq(virq, &tbint_irqaction))
 193                 panic("Could not allocate timer IRQ!");
 194
 195 #ifdef CONFIG_8xx_WDT
 196         /* Install watchdog timer handler early because it might be
 197          * already enabled by the bootloader
 198          */
 199         m8xx_wdt_handler_install(binfo);
 200 #endif
 201 }
 202
 203 /* The RTC on the MPC8xx is an internal register.
 204  * We want to protect this during power down, so we need to unlock,
 205  * modify, and re-lock.
 206  */
 207
 208 int mpc8xx_set_rtc_time(struct rtc_time *tm)
 209 {
 210         sitk8xx_t *sys_tmr1;
 211         sit8xx_t *sys_tmr2;
 212         int time;
 213
 214         sys_tmr1 = (sitk8xx_t *) immr_map(im_sitk);
 215         sys_tmr2 = (sit8xx_t *) immr_map(im_sit);
 216         time = mktime(tm->tm_year+1900, tm->tm_mon+1, tm->tm_mday,
 217                       tm->tm_hour, tm->tm_min, tm->tm_sec);
 218
 219         out_be32(&sys_tmr1->sitk_rtck, KAPWR_KEY);
 220         out_be32(&sys_tmr2->sit_rtc, time);
 221         out_be32(&sys_tmr1->sitk_rtck, ~KAPWR_KEY);
 222
 223         immr_unmap(sys_tmr2);
 224         immr_unmap(sys_tmr1);
 225         return 0;
 226 }
 227
 228 void mpc8xx_get_rtc_time(struct rtc_time *tm)
 229 {
 230         unsigned long data;
 231         sit8xx_t *sys_tmr = (sit8xx_t *) immr_map(im_sit);
 232
 233         /* Get time from the RTC. */
 234         data = in_be32(&sys_tmr->sit_rtc);
 235         to_tm(data, tm);
 236         tm->tm_year -= 1900;
 237         tm->tm_mon -= 1;
 238         immr_unmap(sys_tmr);
 239         return;
 240 }
 241
 242 void mpc8xx_restart(char *cmd)
 243 {
 244         __volatile__ unsigned char dummy;
 245         car8xx_t * clk_r = (car8xx_t *) immr_map(im_clkrst);
 246
 247
 248         local_irq_disable();
 249
 250         setbits32(&clk_r->car_plprcr, 0x00000080);
 251         /* Clear the ME bit in MSR to cause checkstop on machine check
 252         */
 253         mtmsr(mfmsr() & ~0x1000);
 254
 255         dummy = in_8(&clk_r->res[0]);
 256         printk("Restart failed\n");
 257         while(1);
 258 }
 259
 260 void mpc8xx_show_cpuinfo(struct seq_file *m)
 261 {
 262         struct device_node *root;
 263         uint memsize = total_memory;
 264         const char *model = "";
 265
 266         seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
 267
 268         root = of_find_node_by_path("/");
 269         if (root)
 270                 model = of_get_property(root, "model", NULL);
 271         seq_printf(m, "Machine\t\t: %s\n", model);
 272         of_node_put(root);
 273
 274         seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
 275 }
 276
 277 static void cpm_cascade(unsigned int irq, struct irq_desc *desc)
 278 {
 279         int cascade_irq;
 280
 281         if ((cascade_irq = cpm_get_irq()) >= 0) {
 282                 struct irq_desc *cdesc = irq_desc + cascade_irq;
 283
 284                 generic_handle_irq(cascade_irq);
 285                 cdesc->chip->eoi(cascade_irq);
 286         }
 287         desc->chip->eoi(irq);
 288 }
 289
 290 /* Initialize the internal interrupt controller.  The number of
 291  * interrupts supported can vary with the processor type, and the
 292  * 82xx family can have up to 64.
 293  * External interrupts can be either edge or level triggered, and
 294  * need to be initialized by the appropriate driver.
 295  */
 296 void __init m8xx_pic_init(void)
 297 {
 298         int irq;
 299
 300         if (mpc8xx_pic_init()) {
 301                 printk(KERN_ERR "Failed interrupt 8xx controller  initialization\n");
 302                 return;
 303         }
 304
 305         irq = cpm_pic_init();
 306         if (irq != NO_IRQ)
 307                 set_irq_chained_handler(irq, cpm_cascade);
 308 }