arch/powerpc/platforms/85xx/mpc85xx_mds.c

   1 /*
   2  * Copyright (C) Freescale Semicondutor, Inc. 2006-2007. All rights reserved.
   3  *
   4  * Author: Andy Fleming <afleming@freescale.com>
   5  *
   6  * Based on 83xx/mpc8360e_pb.c by:
   7  *         Li Yang <LeoLi@freescale.com>
   8  *         Yin Olivia <Hong-hua.Yin@freescale.com>
   9  *
  10  * Description:
  11  * MPC85xx MDS board specific routines.
  12  *
  13  * This program is free software; you can redistribute  it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  */
  18
  19 #include <linux/stddef.h>
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/reboot.h>
  24 #include <linux/pci.h>
  25 #include <linux/kdev_t.h>
  26 #include <linux/major.h>
  27 #include <linux/console.h>
  28 #include <linux/delay.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/initrd.h>
  31 #include <linux/module.h>
  32 #include <linux/fsl_devices.h>
  33
  34 #include <asm/of_device.h>
  35 #include <asm/of_platform.h>
  36 #include <asm/system.h>
  37 #include <asm/atomic.h>
  38 #include <asm/time.h>
  39 #include <asm/io.h>
  40 #include <asm/machdep.h>
  41 #include <asm/pci-bridge.h>
  42 #include <asm/mpc85xx.h>
  43 #include <asm/irq.h>
  44 #include <mm/mmu_decl.h>
  45 #include <asm/prom.h>
  46 #include <asm/udbg.h>
  47 #include <sysdev/fsl_soc.h>
  48 #include <sysdev/fsl_pci.h>
  49 #include <asm/qe.h>
  50 #include <asm/qe_ic.h>
  51 #include <asm/mpic.h>
  52
  53 #include "mpc85xx.h"
  54
  55 #undef DEBUG
  56 #ifdef DEBUG
  57 #define DBG(fmt...) udbg_printf(fmt)
  58 #else
  59 #define DBG(fmt...)
  60 #endif
  61
  62 /* ************************************************************************
  63  *
  64  * Setup the architecture
  65  *
  66  */
  67 static void __init mpc85xx_mds_setup_arch(void)
  68 {
  69         struct device_node *np;
  70         static u8 *bcsr_regs = NULL;
  71
  72         if (ppc_md.progress)
  73                 ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
  74
  75         np = of_find_node_by_type(NULL, "cpu");
  76         if (np != NULL) {
  77                 const unsigned int *fp =
  78                     of_get_property(np, "clock-frequency", NULL);
  79                 if (fp != NULL)
  80                         loops_per_jiffy = *fp / HZ;
  81                 else
  82                         loops_per_jiffy = 50000000 / HZ;
  83                 of_node_put(np);
  84         }
  85
  86         /* Map BCSR area */
  87         np = of_find_node_by_name(NULL, "bcsr");
  88         if (np != NULL) {
  89                 struct resource res;
  90
  91                 of_address_to_resource(np, 0, &res);
  92                 bcsr_regs = ioremap(res.start, res.end - res.start +1);
  93                 of_node_put(np);
  94         }
  95
  96 #ifdef CONFIG_PCI
  97         for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
  98                 fsl_add_bridge(np, 1);
  99         of_node_put(np);
 100 #endif
 101
 102 #ifdef CONFIG_QUICC_ENGINE
 103         if ((np = of_find_node_by_name(NULL, "qe")) != NULL) {
 104                 qe_reset();
 105                 of_node_put(np);
 106         }
 107
 108         if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
 109                 struct device_node *ucc = NULL;
 110
 111                 par_io_init(np);
 112                 of_node_put(np);
 113
 114                 for ( ;(ucc = of_find_node_by_name(ucc, "ucc")) != NULL;)
 115                         par_io_of_config(ucc);
 116
 117                 of_node_put(ucc);
 118         }
 119
 120         if (bcsr_regs) {
 121                 u8 bcsr_phy;
 122
 123                 /* Reset the Ethernet PHY */
 124                 bcsr_phy = in_be8(&bcsr_regs[9]);
 125                 bcsr_phy &= ~0x20;
 126                 out_be8(&bcsr_regs[9], bcsr_phy);
 127
 128                 udelay(1000);
 129
 130                 bcsr_phy = in_be8(&bcsr_regs[9]);
 131                 bcsr_phy |= 0x20;
 132                 out_be8(&bcsr_regs[9], bcsr_phy);
 133
 134                 iounmap(bcsr_regs);
 135         }
 136
 137 #endif  /* CONFIG_QUICC_ENGINE */
 138 }
 139
 140 static struct of_device_id mpc85xx_ids[] = {
 141         { .type = "soc", },
 142         { .compatible = "soc", },
 143         { .type = "qe", },
 144         {},
 145 };
 146
 147 static int __init mpc85xx_publish_devices(void)
 148 {
 149         if (!machine_is(mpc85xx_mds))
 150                 return 0;
 151
 152         /* Publish the QE devices */
 153         of_platform_bus_probe(NULL,mpc85xx_ids,NULL);
 154
 155         return 0;
 156 }
 157 device_initcall(mpc85xx_publish_devices);
 158
 159 static void __init mpc85xx_mds_pic_init(void)
 160 {
 161         struct mpic *mpic;
 162         struct resource r;
 163         struct device_node *np = NULL;
 164
 165         np = of_find_node_by_type(NULL, "open-pic");
 166         if (!np)
 167                 return;
 168
 169         if (of_address_to_resource(np, 0, &r)) {
 170                 printk(KERN_ERR "Failed to map mpic register space\n");
 171                 of_node_put(np);
 172                 return;
 173         }
 174
 175         mpic = mpic_alloc(np, r.start,
 176                         MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN,
 177                         0, 256, " OpenPIC  ");
 178         BUG_ON(mpic == NULL);
 179         of_node_put(np);
 180
 181         mpic_init(mpic);
 182
 183 #ifdef CONFIG_QUICC_ENGINE
 184         np = of_find_node_by_type(NULL, "qeic");
 185         if (!np)
 186                 return;
 187
 188         qe_ic_init(np, 0);
 189         of_node_put(np);
 190 #endif                          /* CONFIG_QUICC_ENGINE */
 191 }
 192
 193 static int __init mpc85xx_mds_probe(void)
 194 {
 195         unsigned long root = of_get_flat_dt_root();
 196
 197         return of_flat_dt_is_compatible(root, "MPC85xxMDS");
 198 }
 199
 200 define_machine(mpc85xx_mds) {
 201         .name           = "MPC85xx MDS",
 202         .probe          = mpc85xx_mds_probe,
 203         .setup_arch     = mpc85xx_mds_setup_arch,
 204         .init_IRQ       = mpc85xx_mds_pic_init,
 205         .get_irq        = mpic_get_irq,
 206         .restart        = mpc85xx_restart,
 207         .calibrate_decr = generic_calibrate_decr,
 208         .progress       = udbg_progress,
 209         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 210 };