arch/powerpc/platforms/82xx/mpc82xx_ads.c

   1 /*
   2  * MPC82xx_ads setup and early boot code plus other random bits.
   3  *
   4  * Author: Vitaly Bordug <vbordug@ru.mvista.com>
   5  * m82xx_restart fix by Wade Farnsworth <wfarnsworth@mvista.com>
   6  *
   7  * Copyright (c) 2006 MontaVista Software, Inc.
   8  *
   9  * This program is free software; you can redistribute  it and/or modify it
  10  * under  the terms of  the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the  License, or (at your
  12  * option) any later version.
  13  */
  14
  15 #include <linux/stddef.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/errno.h>
  19 #include <linux/reboot.h>
  20 #include <linux/pci.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/kdev_t.h>
  23 #include <linux/major.h>
  24 #include <linux/console.h>
  25 #include <linux/delay.h>
  26 #include <linux/seq_file.h>
  27 #include <linux/root_dev.h>
  28 #include <linux/initrd.h>
  29 #include <linux/module.h>
  30 #include <linux/fsl_devices.h>
  31 #include <linux/fs_uart_pd.h>
  32
  33 #include <asm/system.h>
  34 #include <asm/pgtable.h>
  35 #include <asm/page.h>
  36 #include <asm/atomic.h>
  37 #include <asm/time.h>
  38 #include <asm/io.h>
  39 #include <asm/machdep.h>
  40 #include <asm/pci-bridge.h>
  41 #include <asm/mpc8260.h>
  42 #include <asm/irq.h>
  43 #include <mm/mmu_decl.h>
  44 #include <asm/prom.h>
  45 #include <asm/cpm2.h>
  46 #include <asm/udbg.h>
  47 #include <asm/i8259.h>
  48 #include <linux/fs_enet_pd.h>
  49
  50 #include <sysdev/fsl_soc.h>
  51 #include <sysdev/cpm2_pic.h>
  52
  53 #include "pq2ads.h"
  54
  55 #ifdef CONFIG_PCI
  56 static uint pci_clk_frq;
  57 static struct {
  58         unsigned long *pci_int_stat_reg;
  59         unsigned long *pci_int_mask_reg;
  60 } pci_regs;
  61
  62 static unsigned long pci_int_base;
  63 static struct irq_host *pci_pic_host;
  64 static struct device_node *pci_pic_node;
  65 #endif
  66
  67 static void __init mpc82xx_ads_pic_init(void)
  68 {
  69         struct device_node *np = of_find_compatible_node(NULL, "cpm-pic", "CPM2");
  70         struct resource r;
  71         cpm2_map_t *cpm_reg;
  72
  73         if (np == NULL) {
  74                 printk(KERN_ERR "PIC init: can not find cpm-pic node\n");
  75                 return;
  76         }
  77         if (of_address_to_resource(np, 0, &r)) {
  78                 printk(KERN_ERR "PIC init: invalid resource\n");
  79                 of_node_put(np);
  80                 return;
  81         }
  82         cpm2_pic_init(np);
  83         of_node_put(np);
  84
  85         /* Initialize the default interrupt mapping priorities,
  86          * in case the boot rom changed something on us.
  87          */
  88         cpm_reg = (cpm2_map_t *) ioremap(get_immrbase(), sizeof(cpm2_map_t));
  89         cpm_reg->im_intctl.ic_siprr = 0x05309770;
  90         iounmap(cpm_reg);
  91 #ifdef CONFIG_PCI
  92         /* Initialize stuff for the 82xx CPLD IC and install demux  */
  93         m82xx_pci_init_irq();
  94 #endif
  95 }
  96
  97 static void init_fcc1_ioports(struct fs_platform_info *fpi)
  98 {
  99         struct io_port *io;
 100         u32 tempval;
 101         cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
 102         struct device_node *np;
 103         struct resource r;
 104         u32 *bcsr;
 105
 106         np = of_find_node_by_type(NULL, "memory");
 107         if (!np) {
 108                 printk(KERN_INFO "No memory node in device tree\n");
 109                 return;
 110         }
 111         if (of_address_to_resource(np, 1, &r)) {
 112                 printk(KERN_INFO "No memory reg property [1] in devicetree\n");
 113                 return;
 114         }
 115         of_node_put(np);
 116         bcsr = ioremap(r.start + 4, sizeof(u32));
 117         io = &immap->im_ioport;
 118
 119         /* Enable the PHY */
 120         clrbits32(bcsr, BCSR1_FETHIEN);
 121         setbits32(bcsr, BCSR1_FETH_RST);
 122
 123         /* FCC1 pins are on port A/C. */
 124         /* Configure port A and C pins for FCC1 Ethernet. */
 125
 126         tempval = in_be32(&io->iop_pdira);
 127         tempval &= ~PA1_DIRA0;
 128         tempval |= PA1_DIRA1;
 129         out_be32(&io->iop_pdira, tempval);
 130
 131         tempval = in_be32(&io->iop_psora);
 132         tempval &= ~PA1_PSORA0;
 133         tempval |= PA1_PSORA1;
 134         out_be32(&io->iop_psora, tempval);
 135
 136         setbits32(&io->iop_ppara, PA1_DIRA0 | PA1_DIRA1);
 137
 138         /* Alter clocks */
 139         tempval = PC_CLK(fpi->clk_tx - 8) | PC_CLK(fpi->clk_rx - 8);
 140
 141         clrbits32(&io->iop_psorc, tempval);
 142         clrbits32(&io->iop_pdirc, tempval);
 143         setbits32(&io->iop_pparc, tempval);
 144
 145         cpm2_clk_setup(CPM_CLK_FCC1, fpi->clk_rx, CPM_CLK_RX);
 146         cpm2_clk_setup(CPM_CLK_FCC1, fpi->clk_tx, CPM_CLK_TX);
 147
 148         iounmap(bcsr);
 149         iounmap(immap);
 150 }
 151
 152 static void init_fcc2_ioports(struct fs_platform_info *fpi)
 153 {
 154         cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
 155         struct device_node *np;
 156         struct resource r;
 157         u32 *bcsr;
 158
 159         struct io_port *io;
 160         u32 tempval;
 161
 162         np = of_find_node_by_type(NULL, "memory");
 163         if (!np) {
 164                 printk(KERN_INFO "No memory node in device tree\n");
 165                 return;
 166         }
 167         if (of_address_to_resource(np, 1, &r)) {
 168                 printk(KERN_INFO "No memory reg property [1] in devicetree\n");
 169                 return;
 170         }
 171         of_node_put(np);
 172         io = &immap->im_ioport;
 173         bcsr = ioremap(r.start + 12, sizeof(u32));
 174
 175         /* Enable the PHY */
 176         clrbits32(bcsr, BCSR3_FETHIEN2);
 177         setbits32(bcsr, BCSR3_FETH2_RST);
 178
 179         /* FCC2 are port B/C. */
 180         /* Configure port A and C pins for FCC2 Ethernet. */
 181
 182         tempval = in_be32(&io->iop_pdirb);
 183         tempval &= ~PB2_DIRB0;
 184         tempval |= PB2_DIRB1;
 185         out_be32(&io->iop_pdirb, tempval);
 186
 187         tempval = in_be32(&io->iop_psorb);
 188         tempval &= ~PB2_PSORB0;
 189         tempval |= PB2_PSORB1;
 190         out_be32(&io->iop_psorb, tempval);
 191
 192         setbits32(&io->iop_pparb, PB2_DIRB0 | PB2_DIRB1);
 193
 194         tempval = PC_CLK(fpi->clk_tx - 8) | PC_CLK(fpi->clk_rx - 8);
 195
 196         /* Alter clocks */
 197         clrbits32(&io->iop_psorc, tempval);
 198         clrbits32(&io->iop_pdirc, tempval);
 199         setbits32(&io->iop_pparc, tempval);
 200
 201         cpm2_clk_setup(CPM_CLK_FCC2, fpi->clk_rx, CPM_CLK_RX);
 202         cpm2_clk_setup(CPM_CLK_FCC2, fpi->clk_tx, CPM_CLK_TX);
 203
 204         iounmap(bcsr);
 205         iounmap(immap);
 206 }
 207
 208 void init_fcc_ioports(struct fs_platform_info *fpi)
 209 {
 210         int fcc_no = fs_get_fcc_index(fpi->fs_no);
 211
 212         switch (fcc_no) {
 213         case 0:
 214                 init_fcc1_ioports(fpi);
 215                 break;
 216         case 1:
 217                 init_fcc2_ioports(fpi);
 218                 break;
 219         default:
 220                 printk(KERN_ERR "init_fcc_ioports: invalid FCC number\n");
 221                 return;
 222         }
 223 }
 224
 225 static void init_scc1_uart_ioports(struct fs_uart_platform_info *data)
 226 {
 227         cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
 228
 229         /* SCC1 is only on port D */
 230         setbits32(&immap->im_ioport.iop_ppard, 0x00000003);
 231         clrbits32(&immap->im_ioport.iop_psord, 0x00000001);
 232         setbits32(&immap->im_ioport.iop_psord, 0x00000002);
 233         clrbits32(&immap->im_ioport.iop_pdird, 0x00000001);
 234         setbits32(&immap->im_ioport.iop_pdird, 0x00000002);
 235
 236         clrbits32(&immap->im_cpmux.cmx_scr, (0x00000007 << (4 - data->clk_tx)));
 237         clrbits32(&immap->im_cpmux.cmx_scr, (0x00000038 << (4 - data->clk_rx)));
 238         setbits32(&immap->im_cpmux.cmx_scr,
 239                   ((data->clk_tx - 1) << (4 - data->clk_tx)));
 240         setbits32(&immap->im_cpmux.cmx_scr,
 241                   ((data->clk_rx - 1) << (4 - data->clk_rx)));
 242
 243         iounmap(immap);
 244 }
 245
 246 static void init_scc4_uart_ioports(struct fs_uart_platform_info *data)
 247 {
 248         cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
 249
 250         setbits32(&immap->im_ioport.iop_ppard, 0x00000600);
 251         clrbits32(&immap->im_ioport.iop_psord, 0x00000600);
 252         clrbits32(&immap->im_ioport.iop_pdird, 0x00000200);
 253         setbits32(&immap->im_ioport.iop_pdird, 0x00000400);
 254
 255         clrbits32(&immap->im_cpmux.cmx_scr, (0x00000007 << (4 - data->clk_tx)));
 256         clrbits32(&immap->im_cpmux.cmx_scr, (0x00000038 << (4 - data->clk_rx)));
 257         setbits32(&immap->im_cpmux.cmx_scr,
 258                   ((data->clk_tx - 1) << (4 - data->clk_tx)));
 259         setbits32(&immap->im_cpmux.cmx_scr,
 260                   ((data->clk_rx - 1) << (4 - data->clk_rx)));
 261
 262         iounmap(immap);
 263 }
 264
 265 void init_scc_ioports(struct fs_uart_platform_info *data)
 266 {
 267         int scc_no = fs_get_scc_index(data->fs_no);
 268
 269         switch (scc_no) {
 270         case 0:
 271                 init_scc1_uart_ioports(data);
 272                 data->brg = data->clk_rx;
 273                 break;
 274         case 3:
 275                 init_scc4_uart_ioports(data);
 276                 data->brg = data->clk_rx;
 277                 break;
 278         default:
 279                 printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
 280                 return;
 281         }
 282 }
 283
 284 void __init m82xx_board_setup(void)
 285 {
 286         cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
 287         struct device_node *np;
 288         struct resource r;
 289         u32 *bcsr;
 290
 291         np = of_find_node_by_type(NULL, "memory");
 292         if (!np) {
 293                 printk(KERN_INFO "No memory node in device tree\n");
 294                 return;
 295         }
 296         if (of_address_to_resource(np, 1, &r)) {
 297                 printk(KERN_INFO "No memory reg property [1] in devicetree\n");
 298                 return;
 299         }
 300         of_node_put(np);
 301         bcsr = ioremap(r.start + 4, sizeof(u32));
 302         /* Enable the 2nd UART port */
 303         clrbits32(bcsr, BCSR1_RS232_EN2);
 304
 305 #ifdef CONFIG_SERIAL_CPM_SCC1
 306         clrbits32((u32 *) & immap->im_scc[0].scc_sccm,
 307                   UART_SCCM_TX | UART_SCCM_RX);
 308         clrbits32((u32 *) & immap->im_scc[0].scc_gsmrl,
 309                   SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 310 #endif
 311
 312 #ifdef CONFIG_SERIAL_CPM_SCC2
 313         clrbits32((u32 *) & immap->im_scc[1].scc_sccm,
 314                   UART_SCCM_TX | UART_SCCM_RX);
 315         clrbits32((u32 *) & immap->im_scc[1].scc_gsmrl,
 316                   SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 317 #endif
 318
 319 #ifdef CONFIG_SERIAL_CPM_SCC3
 320         clrbits32((u32 *) & immap->im_scc[2].scc_sccm,
 321                   UART_SCCM_TX | UART_SCCM_RX);
 322         clrbits32((u32 *) & immap->im_scc[2].scc_gsmrl,
 323                   SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 324 #endif
 325
 326 #ifdef CONFIG_SERIAL_CPM_SCC4
 327         clrbits32((u32 *) & immap->im_scc[3].scc_sccm,
 328                   UART_SCCM_TX | UART_SCCM_RX);
 329         clrbits32((u32 *) & immap->im_scc[3].scc_gsmrl,
 330                   SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 331 #endif
 332
 333         iounmap(bcsr);
 334         iounmap(immap);
 335 }
 336
 337 #ifdef CONFIG_PCI
 338 static void m82xx_pci_mask_irq(unsigned int irq)
 339 {
 340         int bit = irq - pci_int_base;
 341
 342         *pci_regs.pci_int_mask_reg |= (1 << (31 - bit));
 343         return;
 344 }
 345
 346 static void m82xx_pci_unmask_irq(unsigned int irq)
 347 {
 348         int bit = irq - pci_int_base;
 349
 350         *pci_regs.pci_int_mask_reg &= ~(1 << (31 - bit));
 351         return;
 352 }
 353
 354 static void m82xx_pci_mask_and_ack(unsigned int irq)
 355 {
 356         int bit = irq - pci_int_base;
 357
 358         *pci_regs.pci_int_mask_reg |= (1 << (31 - bit));
 359         return;
 360 }
 361
 362 static void m82xx_pci_end_irq(unsigned int irq)
 363 {
 364         int bit = irq - pci_int_base;
 365
 366         *pci_regs.pci_int_mask_reg &= ~(1 << (31 - bit));
 367         return;
 368 }
 369
 370 struct hw_interrupt_type m82xx_pci_ic = {
 371         .typename = "MPC82xx ADS PCI",
 372         .name = "MPC82xx ADS PCI",
 373         .enable = m82xx_pci_unmask_irq,
 374         .disable = m82xx_pci_mask_irq,
 375         .ack = m82xx_pci_mask_and_ack,
 376         .end = m82xx_pci_end_irq,
 377         .mask = m82xx_pci_mask_irq,
 378         .mask_ack = m82xx_pci_mask_and_ack,
 379         .unmask = m82xx_pci_unmask_irq,
 380         .eoi = m82xx_pci_end_irq,
 381 };
 382
 383 static void
 384 m82xx_pci_irq_demux(unsigned int irq, struct irq_desc *desc)
 385 {
 386         unsigned long stat, mask, pend;
 387         int bit;
 388
 389         for (;;) {
 390                 stat = *pci_regs.pci_int_stat_reg;
 391                 mask = *pci_regs.pci_int_mask_reg;
 392                 pend = stat & ~mask & 0xf0000000;
 393                 if (!pend)
 394                         break;
 395                 for (bit = 0; pend != 0; ++bit, pend <<= 1) {
 396                         if (pend & 0x80000000)
 397                                 __do_IRQ(pci_int_base + bit);
 398                 }
 399         }
 400 }
 401
 402 static int pci_pic_host_match(struct irq_host *h, struct device_node *node)
 403 {
 404         return node == pci_pic_node;
 405 }
 406
 407 static int pci_pic_host_map(struct irq_host *h, unsigned int virq,
 408                             irq_hw_number_t hw)
 409 {
 410         get_irq_desc(virq)->status |= IRQ_LEVEL;
 411         set_irq_chip(virq, &m82xx_pci_ic);
 412         return 0;
 413 }
 414
 415 static void pci_host_unmap(struct irq_host *h, unsigned int virq)
 416 {
 417         /* remove chip and handler */
 418         set_irq_chip(virq, NULL);
 419 }
 420
 421 static struct irq_host_ops pci_pic_host_ops = {
 422         .match = pci_pic_host_match,
 423         .map = pci_pic_host_map,
 424         .unmap = pci_host_unmap,
 425 };
 426
 427 void m82xx_pci_init_irq(void)
 428 {
 429         int irq;
 430         cpm2_map_t *immap;
 431         struct device_node *np;
 432         struct resource r;
 433         const u32 *regs;
 434         unsigned int size;
 435         const u32 *irq_map;
 436         int i;
 437         unsigned int irq_max, irq_min;
 438
 439         if ((np = of_find_node_by_type(NULL, "soc")) == NULL) {
 440                 printk(KERN_INFO "No SOC node in device tree\n");
 441                 return;
 442         }
 443         memset(&r, 0, sizeof(r));
 444         if (of_address_to_resource(np, 0, &r)) {
 445                 printk(KERN_INFO "No SOC reg property in device tree\n");
 446                 return;
 447         }
 448         immap = ioremap(r.start, sizeof(*immap));
 449         of_node_put(np);
 450
 451         /* install the demultiplexer for the PCI cascade interrupt */
 452         np = of_find_node_by_type(NULL, "pci");
 453         if (!np) {
 454                 printk(KERN_INFO "No pci node on device tree\n");
 455                 iounmap(immap);
 456                 return;
 457         }
 458         irq_map = of_get_property(np, "interrupt-map", &size);
 459         if ((!irq_map) || (size <= 7)) {
 460                 printk(KERN_INFO "No interrupt-map property of pci node\n");
 461                 iounmap(immap);
 462                 return;
 463         }
 464         size /= sizeof(irq_map[0]);
 465         for (i = 0, irq_max = 0, irq_min = 512; i < size; i += 7, irq_map += 7) {
 466                 if (irq_map[5] < irq_min)
 467                         irq_min = irq_map[5];
 468                 if (irq_map[5] > irq_max)
 469                         irq_max = irq_map[5];
 470         }
 471         pci_int_base = irq_min;
 472         irq = irq_of_parse_and_map(np, 0);
 473         set_irq_chained_handler(irq, m82xx_pci_irq_demux);
 474         of_node_put(np);
 475         np = of_find_node_by_type(NULL, "pci-pic");
 476         if (!np) {
 477                 printk(KERN_INFO "No pci pic node on device tree\n");
 478                 iounmap(immap);
 479                 return;
 480         }
 481         pci_pic_node = of_node_get(np);
 482         /* PCI interrupt controller registers: status and mask */
 483         regs = of_get_property(np, "reg", &size);
 484         if ((!regs) || (size <= 2)) {
 485                 printk(KERN_INFO "No reg property in pci pic node\n");
 486                 iounmap(immap);
 487                 return;
 488         }
 489         pci_regs.pci_int_stat_reg =
 490             ioremap(regs[0], sizeof(*pci_regs.pci_int_stat_reg));
 491         pci_regs.pci_int_mask_reg =
 492             ioremap(regs[1], sizeof(*pci_regs.pci_int_mask_reg));
 493         of_node_put(np);
 494         /* configure chip select for PCI interrupt controller */
 495         immap->im_memctl.memc_br3 = regs[0] | 0x00001801;
 496         immap->im_memctl.memc_or3 = 0xffff8010;
 497         /* make PCI IRQ level sensitive */
 498         immap->im_intctl.ic_siexr &= ~(1 << (14 - (irq - SIU_INT_IRQ1)));
 499
 500         /* mask all PCI interrupts */
 501         *pci_regs.pci_int_mask_reg |= 0xfff00000;
 502         iounmap(immap);
 503         pci_pic_host =
 504             irq_alloc_host(IRQ_HOST_MAP_LINEAR, irq_max - irq_min + 1,
 505                            &pci_pic_host_ops, irq_max + 1);
 506         return;
 507 }
 508
 509 static int m82xx_pci_exclude_device(struct pci_controller *hose,
 510                                     u_char bus, u_char devfn)
 511 {
 512         if (bus == 0 && PCI_SLOT(devfn) == 0)
 513                 return PCIBIOS_DEVICE_NOT_FOUND;
 514         else
 515                 return PCIBIOS_SUCCESSFUL;
 516 }
 517
 518 static void __init mpc82xx_add_bridge(struct device_node *np)
 519 {
 520         int len;
 521         struct pci_controller *hose;
 522         struct resource r;
 523         const int *bus_range;
 524         const uint *ptr;
 525
 526         memset(&r, 0, sizeof(r));
 527         if (of_address_to_resource(np, 0, &r)) {
 528                 printk(KERN_INFO "No PCI reg property in device tree\n");
 529                 return;
 530         }
 531         if (!(ptr = of_get_property(np, "clock-frequency", NULL))) {
 532                 printk(KERN_INFO "No clock-frequency property in PCI node");
 533                 return;
 534         }
 535         pci_clk_frq = *ptr;
 536         of_node_put(np);
 537         bus_range = of_get_property(np, "bus-range", &len);
 538         if (bus_range == NULL || len < 2 * sizeof(int)) {
 539                 printk(KERN_WARNING "Can't get bus-range for %s, assume"
 540                        " bus 0\n", np->full_name);
 541         }
 542
 543         pci_assign_all_buses = 1;
 544
 545         hose = pcibios_alloc_controller(np);
 546
 547         if (!hose)
 548                 return;
 549
 550         hose->first_busno = bus_range ? bus_range[0] : 0;
 551         hose->last_busno = bus_range ? bus_range[1] : 0xff;
 552
 553         setup_indirect_pci(hose,
 554                            r.start + offsetof(pci_cpm2_t, pci_cfg_addr),
 555                            r.start + offsetof(pci_cpm2_t, pci_cfg_data),
 556                            0);
 557
 558         pci_process_bridge_OF_ranges(hose, np, 1);
 559 }
 560 #endif
 561
 562 /*
 563  * Setup the architecture
 564  */
 565 static void __init mpc82xx_ads_setup_arch(void)
 566 {
 567 #ifdef CONFIG_PCI
 568         struct device_node *np;
 569 #endif
 570
 571         if (ppc_md.progress)
 572                 ppc_md.progress("mpc82xx_ads_setup_arch()", 0);
 573         cpm2_reset();
 574
 575         /* Map I/O region to a 256MB BAT */
 576
 577         m82xx_board_setup();
 578
 579 #ifdef CONFIG_PCI
 580         ppc_md.pci_exclude_device = m82xx_pci_exclude_device;
 581         for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
 582                 mpc82xx_add_bridge(np);
 583
 584         of_node_put(np);
 585 #endif
 586
 587 #ifdef  CONFIG_ROOT_NFS
 588         ROOT_DEV = Root_NFS;
 589 #else
 590         ROOT_DEV = Root_HDA1;
 591 #endif
 592
 593         if (ppc_md.progress)
 594                 ppc_md.progress("mpc82xx_ads_setup_arch(), finish", 0);
 595 }
 596
 597 /*
 598  * Called very early, device-tree isn't unflattened
 599  */
 600 static int __init mpc82xx_ads_probe(void)
 601 {
 602         /* We always match for now, eventually we should look at
 603          * the flat dev tree to ensure this is the board we are
 604          * supposed to run on
 605          */
 606         return 1;
 607 }
 608
 609 #define RMR_CSRE 0x00000001
 610 static void m82xx_restart(char *cmd)
 611 {
 612         __volatile__ unsigned char dummy;
 613
 614         local_irq_disable();
 615         ((cpm2_map_t *) cpm2_immr)->im_clkrst.car_rmr |= RMR_CSRE;
 616
 617         /* Clear the ME,EE,IR & DR bits in MSR to cause checkstop */
 618         mtmsr(mfmsr() & ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR));
 619         dummy = ((cpm2_map_t *) cpm2_immr)->im_clkrst.res[0];
 620         printk("Restart failed\n");
 621         while (1) ;
 622 }
 623
 624 static void m82xx_halt(void)
 625 {
 626         local_irq_disable();
 627         while (1) ;
 628 }
 629
 630 define_machine(mpc82xx_ads)
 631 {
 632         .name = "MPC82xx ADS",
 633         .probe = mpc82xx_ads_probe,
 634         .setup_arch =    mpc82xx_ads_setup_arch,
 635         .init_IRQ =    mpc82xx_ads_pic_init,
 636         .show_cpuinfo =    mpc82xx_ads_show_cpuinfo,
 637         .get_irq =    cpm2_get_irq,
 638         .calibrate_decr =    m82xx_calibrate_decr,
 639         .restart = m82xx_restart,.halt = m82xx_halt,
 640 };