arch/arm/mach-s3c2410/dma.c

   1 /* linux/arch/arm/mach-s3c2410/dma.c
   2  *
   3  * Copyright (c) 2006 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2410 DMA selection
   7  *
   8  * http://armlinux.simtec.co.uk/
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13 */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/sysdev.h>
  18 #include <linux/serial_core.h>
  19
  20 #include <mach/dma.h>
  21
  22 #include <plat/cpu.h>
  23 #include <plat/dma.h>
  24
  25 #include <plat/regs-serial.h>
  26 #include <mach/regs-gpio.h>
  27 #include <plat/regs-ac97.h>
  28 #include <mach/regs-mem.h>
  29 #include <mach/regs-lcd.h>
  30 #include <mach/regs-sdi.h>
  31 #include <asm/plat-s3c24xx/regs-iis.h>
  32 #include <plat/regs-spi.h>
  33
  34 static struct s3c24xx_dma_map __initdata s3c2410_dma_mappings[] = {
  35         [DMACH_XD0] = {
  36                 .name           = "xdreq0",
  37                 .channels[0]    = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
  38         },
  39         [DMACH_XD1] = {
  40                 .name           = "xdreq1",
  41                 .channels[1]    = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
  42         },
  43         [DMACH_SDI] = {
  44                 .name           = "sdi",
  45                 .channels[0]    = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
  46                 .channels[2]    = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
  47                 .channels[3]    = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
  48                 .hw_addr.to     = S3C2410_PA_IIS + S3C2410_IISFIFO,
  49                 .hw_addr.from   = S3C2410_PA_IIS + S3C2410_IISFIFO,
  50         },
  51         [DMACH_SPI0] = {
  52                 .name           = "spi0",
  53                 .channels[1]    = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
  54                 .hw_addr.to     = S3C2410_PA_SPI + S3C2410_SPTDAT,
  55                 .hw_addr.from   = S3C2410_PA_SPI + S3C2410_SPRDAT,
  56         },
  57         [DMACH_SPI1] = {
  58                 .name           = "spi1",
  59                 .channels[3]    = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
  60                 .hw_addr.to     = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
  61                 .hw_addr.from   = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
  62         },
  63         [DMACH_UART0] = {
  64                 .name           = "uart0",
  65                 .channels[0]    = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
  66                 .hw_addr.to     = S3C2410_PA_UART0 + S3C2410_UTXH,
  67                 .hw_addr.from   = S3C2410_PA_UART0 + S3C2410_URXH,
  68         },
  69         [DMACH_UART1] = {
  70                 .name           = "uart1",
  71                 .channels[1]    = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
  72                 .hw_addr.to     = S3C2410_PA_UART1 + S3C2410_UTXH,
  73                 .hw_addr.from   = S3C2410_PA_UART1 + S3C2410_URXH,
  74         },
  75         [DMACH_UART2] = {
  76                 .name           = "uart2",
  77                 .channels[3]    = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
  78                 .hw_addr.to     = S3C2410_PA_UART2 + S3C2410_UTXH,
  79                 .hw_addr.from   = S3C2410_PA_UART2 + S3C2410_URXH,
  80         },
  81         [DMACH_TIMER] = {
  82                 .name           = "timer",
  83                 .channels[0]    = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
  84                 .channels[2]    = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
  85                 .channels[3]    = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
  86         },
  87         [DMACH_I2S_IN] = {
  88                 .name           = "i2s-sdi",
  89                 .channels[1]    = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
  90                 .channels[2]    = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
  91                 .hw_addr.from   = S3C2410_PA_IIS + S3C2410_IISFIFO,
  92         },
  93         [DMACH_I2S_OUT] = {
  94                 .name           = "i2s-sdo",
  95                 .channels[2]    = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
  96                 .hw_addr.to     = S3C2410_PA_IIS + S3C2410_IISFIFO,
  97         },
  98         [DMACH_USB_EP1] = {
  99                 .name           = "usb-ep1",
 100                 .channels[0]    = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
 101         },
 102         [DMACH_USB_EP2] = {
 103                 .name           = "usb-ep2",
 104                 .channels[1]    = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
 105         },
 106         [DMACH_USB_EP3] = {
 107                 .name           = "usb-ep3",
 108                 .channels[2]    = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
 109         },
 110         [DMACH_USB_EP4] = {
 111                 .name           = "usb-ep4",
 112                 .channels[3]    =S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
 113         },
 114 };
 115
 116 static void s3c2410_dma_select(struct s3c2410_dma_chan *chan,
 117                                struct s3c24xx_dma_map *map)
 118 {
 119         chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
 120 }
 121
 122 static struct s3c24xx_dma_selection __initdata s3c2410_dma_sel = {
 123         .select         = s3c2410_dma_select,
 124         .dcon_mask      = 7 << 24,
 125         .map            = s3c2410_dma_mappings,
 126         .map_size       = ARRAY_SIZE(s3c2410_dma_mappings),
 127 };
 128
 129 static struct s3c24xx_dma_order __initdata s3c2410_dma_order = {
 130         .channels       = {
 131                 [DMACH_SDI]     = {
 132                         .list   = {
 133                                 [0]     = 3 | DMA_CH_VALID,
 134                                 [1]     = 2 | DMA_CH_VALID,
 135                                 [2]     = 0 | DMA_CH_VALID,
 136                         },
 137                 },
 138                 [DMACH_I2S_IN]  = {
 139                         .list   = {
 140                                 [0]     = 1 | DMA_CH_VALID,
 141                                 [1]     = 2 | DMA_CH_VALID,
 142                         },
 143                 },
 144         },
 145 };
 146
 147 static int __init s3c2410_dma_add(struct sys_device *sysdev)
 148 {
 149         s3c2410_dma_init();
 150         s3c24xx_dma_order_set(&s3c2410_dma_order);
 151         return s3c24xx_dma_init_map(&s3c2410_dma_sel);
 152 }
 153
 154 #if defined(CONFIG_CPU_S3C2410)
 155 static struct sysdev_driver s3c2410_dma_driver = {
 156         .add    = s3c2410_dma_add,
 157 };
 158
 159 static int __init s3c2410_dma_drvinit(void)
 160 {
 161         return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_dma_driver);
 162 }
 163
 164 arch_initcall(s3c2410_dma_drvinit);
 165 #endif
 166
 167 #if defined(CONFIG_CPU_S3C2442)
 168 /* S3C2442 DMA contains the same selection table as the S3C2410 */
 169 static struct sysdev_driver s3c2442_dma_driver = {
 170         .add    = s3c2410_dma_add,
 171 };
 172
 173 static int __init s3c2442_dma_drvinit(void)
 174 {
 175         return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_dma_driver);
 176 }
 177
 178 arch_initcall(s3c2442_dma_drvinit);
 179 #endif
 180