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x86, delay: tsc based udelay should have rdtsc_barrier
[linux-2.6/mini2440.git] / drivers / net / qlge / qlge_main.c
blob90d1f76c0e8b074729047d5d7aed9440b8d8315f
1 /*
2 * QLogic qlge NIC HBA Driver
3 * Copyright (c) 2003-2008 QLogic Corporation
4 * See LICENSE.qlge for copyright and licensing details.
5 * Author: Linux qlge network device driver by
6 * Ron Mercer <ron.mercer@qlogic.com>
7 */
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/types.h>
11 #include <linux/module.h>
12 #include <linux/list.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/pagemap.h>
16 #include <linux/sched.h>
17 #include <linux/slab.h>
18 #include <linux/dmapool.h>
19 #include <linux/mempool.h>
20 #include <linux/spinlock.h>
21 #include <linux/kthread.h>
22 #include <linux/interrupt.h>
23 #include <linux/errno.h>
24 #include <linux/ioport.h>
25 #include <linux/in.h>
26 #include <linux/ip.h>
27 #include <linux/ipv6.h>
28 #include <net/ipv6.h>
29 #include <linux/tcp.h>
30 #include <linux/udp.h>
31 #include <linux/if_arp.h>
32 #include <linux/if_ether.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/skbuff.h>
37 #include <linux/rtnetlink.h>
38 #include <linux/if_vlan.h>
39 #include <linux/delay.h>
40 #include <linux/mm.h>
41 #include <linux/vmalloc.h>
42 #include <net/ip6_checksum.h>
43
44 #include "qlge.h"
45
46 char qlge_driver_name[] = DRV_NAME;
47 const char qlge_driver_version[] = DRV_VERSION;
48
49 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
50 MODULE_DESCRIPTION(DRV_STRING " ");
51 MODULE_LICENSE("GPL");
52 MODULE_VERSION(DRV_VERSION);
53
54 static const u32 default_msg =
55 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
56 /* NETIF_MSG_TIMER | */
57 NETIF_MSG_IFDOWN |
58 NETIF_MSG_IFUP |
59 NETIF_MSG_RX_ERR |
60 NETIF_MSG_TX_ERR |
61 /* NETIF_MSG_TX_QUEUED | */
62 /* NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS | */
63 /* NETIF_MSG_PKTDATA | */
64 NETIF_MSG_HW | NETIF_MSG_WOL | 0;
65
66 static int debug = 0x00007fff; /* defaults above */
67 module_param(debug, int, 0);
68 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
69
70 #define MSIX_IRQ 0
71 #define MSI_IRQ 1
72 #define LEG_IRQ 2
73 static int irq_type = MSIX_IRQ;
74 module_param(irq_type, int, MSIX_IRQ);
75 MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
76
77 static struct pci_device_id qlge_pci_tbl[] __devinitdata = {
78 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8012)},
79 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8000)},
80 /* required last entry */
81 {0,}
82 };
83
84 MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
85
86 /* This hardware semaphore causes exclusive access to
87 * resources shared between the NIC driver, MPI firmware,
88 * FCOE firmware and the FC driver.
89 */
90 static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
91 {
92 u32 sem_bits = 0;
93
94 switch (sem_mask) {
95 case SEM_XGMAC0_MASK:
96 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
97 break;
98 case SEM_XGMAC1_MASK:
99 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
100 break;
101 case SEM_ICB_MASK:
102 sem_bits = SEM_SET << SEM_ICB_SHIFT;
103 break;
104 case SEM_MAC_ADDR_MASK:
105 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
106 break;
107 case SEM_FLASH_MASK:
108 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
109 break;
110 case SEM_PROBE_MASK:
111 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
112 break;
113 case SEM_RT_IDX_MASK:
114 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
115 break;
116 case SEM_PROC_REG_MASK:
117 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
118 break;
119 default:
120 QPRINTK(qdev, PROBE, ALERT, "Bad Semaphore mask!.\n");
121 return -EINVAL;
122 }
123
124 ql_write32(qdev, SEM, sem_bits | sem_mask);
125 return !(ql_read32(qdev, SEM) & sem_bits);
126 }
127
128 int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
129 {
130 unsigned int wait_count = 30;
131 do {
132 if (!ql_sem_trylock(qdev, sem_mask))
133 return 0;
134 udelay(100);
135 } while (--wait_count);
136 return -ETIMEDOUT;
137 }
138
139 void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
140 {
141 ql_write32(qdev, SEM, sem_mask);
142 ql_read32(qdev, SEM); /* flush */
143 }
144
145 /* This function waits for a specific bit to come ready
146 * in a given register. It is used mostly by the initialize
147 * process, but is also used in kernel thread API such as
148 * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
149 */
150 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
151 {
152 u32 temp;
153 int count = UDELAY_COUNT;
154
155 while (count) {
156 temp = ql_read32(qdev, reg);
157
158 /* check for errors */
159 if (temp & err_bit) {
160 QPRINTK(qdev, PROBE, ALERT,
161 "register 0x%.08x access error, value = 0x%.08x!.\n",
162 reg, temp);
163 return -EIO;
164 } else if (temp & bit)
165 return 0;
166 udelay(UDELAY_DELAY);
167 count--;
168 }
169 QPRINTK(qdev, PROBE, ALERT,
170 "Timed out waiting for reg %x to come ready.\n", reg);
171 return -ETIMEDOUT;
172 }
173
174 /* The CFG register is used to download TX and RX control blocks
175 * to the chip. This function waits for an operation to complete.
176 */
177 static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
178 {
179 int count = UDELAY_COUNT;
180 u32 temp;
181
182 while (count) {
183 temp = ql_read32(qdev, CFG);
184 if (temp & CFG_LE)
185 return -EIO;
186 if (!(temp & bit))
187 return 0;
188 udelay(UDELAY_DELAY);
189 count--;
190 }
191 return -ETIMEDOUT;
192 }
193
194
195 /* Used to issue init control blocks to hw. Maps control block,
196 * sets address, triggers download, waits for completion.
197 */
198 int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
199 u16 q_id)
200 {
201 u64 map;
202 int status = 0;
203 int direction;
204 u32 mask;
205 u32 value;
206
207 direction =
208 (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
209 PCI_DMA_FROMDEVICE;
210
211 map = pci_map_single(qdev->pdev, ptr, size, direction);
212 if (pci_dma_mapping_error(qdev->pdev, map)) {
213 QPRINTK(qdev, IFUP, ERR, "Couldn't map DMA area.\n");
214 return -ENOMEM;
215 }
216
217 status = ql_wait_cfg(qdev, bit);
218 if (status) {
219 QPRINTK(qdev, IFUP, ERR,
220 "Timed out waiting for CFG to come ready.\n");
221 goto exit;
222 }
223
224 status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
225 if (status)
226 goto exit;
227 ql_write32(qdev, ICB_L, (u32) map);
228 ql_write32(qdev, ICB_H, (u32) (map >> 32));
229 ql_sem_unlock(qdev, SEM_ICB_MASK); /* does flush too */
230
231 mask = CFG_Q_MASK | (bit << 16);
232 value = bit | (q_id << CFG_Q_SHIFT);
233 ql_write32(qdev, CFG, (mask | value));
234
235 /*
236 * Wait for the bit to clear after signaling hw.
237 */
238 status = ql_wait_cfg(qdev, bit);
239 exit:
240 pci_unmap_single(qdev->pdev, map, size, direction);
241 return status;
242 }
243
244 /* Get a specific MAC address from the CAM. Used for debug and reg dump. */
245 int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
246 u32 *value)
247 {
248 u32 offset = 0;
249 int status;
250
251 switch (type) {
252 case MAC_ADDR_TYPE_MULTI_MAC:
253 case MAC_ADDR_TYPE_CAM_MAC:
254 {
255 status =
256 ql_wait_reg_rdy(qdev,
257 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
258 if (status)
259 goto exit;
260 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
261 (index << MAC_ADDR_IDX_SHIFT) | /* index */
262 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
263 status =
264 ql_wait_reg_rdy(qdev,
265 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
266 if (status)
267 goto exit;
268 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
269 status =
270 ql_wait_reg_rdy(qdev,
271 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
272 if (status)
273 goto exit;
274 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
275 (index << MAC_ADDR_IDX_SHIFT) | /* index */
276 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
277 status =
278 ql_wait_reg_rdy(qdev,
279 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
280 if (status)
281 goto exit;
282 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
283 if (type == MAC_ADDR_TYPE_CAM_MAC) {
284 status =
285 ql_wait_reg_rdy(qdev,
286 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
287 if (status)
288 goto exit;
289 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
290 (index << MAC_ADDR_IDX_SHIFT) | /* index */
291 MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
292 status =
293 ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
294 MAC_ADDR_MR, 0);
295 if (status)
296 goto exit;
297 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
298 }
299 break;
300 }
301 case MAC_ADDR_TYPE_VLAN:
302 case MAC_ADDR_TYPE_MULTI_FLTR:
303 default:
304 QPRINTK(qdev, IFUP, CRIT,
305 "Address type %d not yet supported.\n", type);
306 status = -EPERM;
307 }
308 exit:
309 return status;
310 }
311
312 /* Set up a MAC, multicast or VLAN address for the
313 * inbound frame matching.
314 */
315 static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
316 u16 index)
317 {
318 u32 offset = 0;
319 int status = 0;
320
321 switch (type) {
322 case MAC_ADDR_TYPE_MULTI_MAC:
323 case MAC_ADDR_TYPE_CAM_MAC:
324 {
325 u32 cam_output;
326 u32 upper = (addr[0] << 8) | addr[1];
327 u32 lower =
328 (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
329 (addr[5]);
330
331 QPRINTK(qdev, IFUP, DEBUG,
332 "Adding %s address %pM"
333 " at index %d in the CAM.\n",
334 ((type ==
335 MAC_ADDR_TYPE_MULTI_MAC) ? "MULTICAST" :
336 "UNICAST"), addr, index);
337
338 status =
339 ql_wait_reg_rdy(qdev,
340 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
341 if (status)
342 goto exit;
343 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
344 (index << MAC_ADDR_IDX_SHIFT) | /* index */
345 type); /* type */
346 ql_write32(qdev, MAC_ADDR_DATA, lower);
347 status =
348 ql_wait_reg_rdy(qdev,
349 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
350 if (status)
351 goto exit;
352 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
353 (index << MAC_ADDR_IDX_SHIFT) | /* index */
354 type); /* type */
355 ql_write32(qdev, MAC_ADDR_DATA, upper);
356 status =
357 ql_wait_reg_rdy(qdev,
358 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
359 if (status)
360 goto exit;
361 ql_write32(qdev, MAC_ADDR_IDX, (offset) | /* offset */
362 (index << MAC_ADDR_IDX_SHIFT) | /* index */
363 type); /* type */
364 /* This field should also include the queue id
365 and possibly the function id. Right now we hardcode
366 the route field to NIC core.
367 */
368 if (type == MAC_ADDR_TYPE_CAM_MAC) {
369 cam_output = (CAM_OUT_ROUTE_NIC |
370 (qdev->
371 func << CAM_OUT_FUNC_SHIFT) |
372 (qdev->
373 rss_ring_first_cq_id <<
374 CAM_OUT_CQ_ID_SHIFT));
375 if (qdev->vlgrp)
376 cam_output |= CAM_OUT_RV;
377 /* route to NIC core */
378 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
379 }
380 break;
381 }
382 case MAC_ADDR_TYPE_VLAN:
383 {
384 u32 enable_bit = *((u32 *) &addr[0]);
385 /* For VLAN, the addr actually holds a bit that
386 * either enables or disables the vlan id we are
387 * addressing. It's either MAC_ADDR_E on or off.
388 * That's bit-27 we're talking about.
389 */
390 QPRINTK(qdev, IFUP, INFO, "%s VLAN ID %d %s the CAM.\n",
391 (enable_bit ? "Adding" : "Removing"),
392 index, (enable_bit ? "to" : "from"));
393
394 status =
395 ql_wait_reg_rdy(qdev,
396 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
397 if (status)
398 goto exit;
399 ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
400 (index << MAC_ADDR_IDX_SHIFT) | /* index */
401 type | /* type */
402 enable_bit); /* enable/disable */
403 break;
404 }
405 case MAC_ADDR_TYPE_MULTI_FLTR:
406 default:
407 QPRINTK(qdev, IFUP, CRIT,
408 "Address type %d not yet supported.\n", type);
409 status = -EPERM;
410 }
411 exit:
412 return status;
413 }
414
415 /* Get a specific frame routing value from the CAM.
416 * Used for debug and reg dump.
417 */
418 int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
419 {
420 int status = 0;
421
422 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
423 if (status)
424 goto exit;
425
426 ql_write32(qdev, RT_IDX,
427 RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
428 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0);
429 if (status)
430 goto exit;
431 *value = ql_read32(qdev, RT_DATA);
432 exit:
433 return status;
434 }
435
436 /* The NIC function for this chip has 16 routing indexes. Each one can be used
437 * to route different frame types to various inbound queues. We send broadcast/
438 * multicast/error frames to the default queue for slow handling,
439 * and CAM hit/RSS frames to the fast handling queues.
440 */
441 static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
442 int enable)
443 {
444 int status = -EINVAL; /* Return error if no mask match. */
445 u32 value = 0;
446
447 QPRINTK(qdev, IFUP, DEBUG,
448 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
449 (enable ? "Adding" : "Removing"),
450 ((index == RT_IDX_ALL_ERR_SLOT) ? "MAC ERROR/ALL ERROR" : ""),
451 ((index == RT_IDX_IP_CSUM_ERR_SLOT) ? "IP CSUM ERROR" : ""),
452 ((index ==
453 RT_IDX_TCP_UDP_CSUM_ERR_SLOT) ? "TCP/UDP CSUM ERROR" : ""),
454 ((index == RT_IDX_BCAST_SLOT) ? "BROADCAST" : ""),
455 ((index == RT_IDX_MCAST_MATCH_SLOT) ? "MULTICAST MATCH" : ""),
456 ((index == RT_IDX_ALLMULTI_SLOT) ? "ALL MULTICAST MATCH" : ""),
457 ((index == RT_IDX_UNUSED6_SLOT) ? "UNUSED6" : ""),
458 ((index == RT_IDX_UNUSED7_SLOT) ? "UNUSED7" : ""),
459 ((index == RT_IDX_RSS_MATCH_SLOT) ? "RSS ALL/IPV4 MATCH" : ""),
460 ((index == RT_IDX_RSS_IPV6_SLOT) ? "RSS IPV6" : ""),
461 ((index == RT_IDX_RSS_TCP4_SLOT) ? "RSS TCP4" : ""),
462 ((index == RT_IDX_RSS_TCP6_SLOT) ? "RSS TCP6" : ""),
463 ((index == RT_IDX_CAM_HIT_SLOT) ? "CAM HIT" : ""),
464 ((index == RT_IDX_UNUSED013) ? "UNUSED13" : ""),
465 ((index == RT_IDX_UNUSED014) ? "UNUSED14" : ""),
466 ((index == RT_IDX_PROMISCUOUS_SLOT) ? "PROMISCUOUS" : ""),
467 (enable ? "to" : "from"));
468
469 switch (mask) {
470 case RT_IDX_CAM_HIT:
471 {
472 value = RT_IDX_DST_CAM_Q | /* dest */
473 RT_IDX_TYPE_NICQ | /* type */
474 (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
475 break;
476 }
477 case RT_IDX_VALID: /* Promiscuous Mode frames. */
478 {
479 value = RT_IDX_DST_DFLT_Q | /* dest */
480 RT_IDX_TYPE_NICQ | /* type */
481 (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
482 break;
483 }
484 case RT_IDX_ERR: /* Pass up MAC,IP,TCP/UDP error frames. */
485 {
486 value = RT_IDX_DST_DFLT_Q | /* dest */
487 RT_IDX_TYPE_NICQ | /* type */
488 (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
489 break;
490 }
491 case RT_IDX_BCAST: /* Pass up Broadcast frames to default Q. */
492 {
493 value = RT_IDX_DST_DFLT_Q | /* dest */
494 RT_IDX_TYPE_NICQ | /* type */
495 (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
496 break;
497 }
498 case RT_IDX_MCAST: /* Pass up All Multicast frames. */
499 {
500 value = RT_IDX_DST_CAM_Q | /* dest */
501 RT_IDX_TYPE_NICQ | /* type */
502 (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
503 break;
504 }
505 case RT_IDX_MCAST_MATCH: /* Pass up matched Multicast frames. */
506 {
507 value = RT_IDX_DST_CAM_Q | /* dest */
508 RT_IDX_TYPE_NICQ | /* type */
509 (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
510 break;
511 }
512 case RT_IDX_RSS_MATCH: /* Pass up matched RSS frames. */
513 {
514 value = RT_IDX_DST_RSS | /* dest */
515 RT_IDX_TYPE_NICQ | /* type */
516 (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
517 break;
518 }
519 case 0: /* Clear the E-bit on an entry. */
520 {
521 value = RT_IDX_DST_DFLT_Q | /* dest */
522 RT_IDX_TYPE_NICQ | /* type */
523 (index << RT_IDX_IDX_SHIFT);/* index */
524 break;
525 }
526 default:
527 QPRINTK(qdev, IFUP, ERR, "Mask type %d not yet supported.\n",
528 mask);
529 status = -EPERM;
530 goto exit;
531 }
532
533 if (value) {
534 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
535 if (status)
536 goto exit;
537 value |= (enable ? RT_IDX_E : 0);
538 ql_write32(qdev, RT_IDX, value);
539 ql_write32(qdev, RT_DATA, enable ? mask : 0);
540 }
541 exit:
542 return status;
543 }
544
545 static void ql_enable_interrupts(struct ql_adapter *qdev)
546 {
547 ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
548 }
549
550 static void ql_disable_interrupts(struct ql_adapter *qdev)
551 {
552 ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
553 }
554
555 /* If we're running with multiple MSI-X vectors then we enable on the fly.
556 * Otherwise, we may have multiple outstanding workers and don't want to
557 * enable until the last one finishes. In this case, the irq_cnt gets
558 * incremented everytime we queue a worker and decremented everytime
559 * a worker finishes. Once it hits zero we enable the interrupt.
560 */
561 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
562 {
563 u32 var = 0;
564 unsigned long hw_flags = 0;
565 struct intr_context *ctx = qdev->intr_context + intr;
566
567 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
568 /* Always enable if we're MSIX multi interrupts and
569 * it's not the default (zeroeth) interrupt.
570 */
571 ql_write32(qdev, INTR_EN,
572 ctx->intr_en_mask);
573 var = ql_read32(qdev, STS);
574 return var;
575 }
576
577 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
578 if (atomic_dec_and_test(&ctx->irq_cnt)) {
579 ql_write32(qdev, INTR_EN,
580 ctx->intr_en_mask);
581 var = ql_read32(qdev, STS);
582 }
583 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
584 return var;
585 }
586
587 static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
588 {
589 u32 var = 0;
590 struct intr_context *ctx;
591
592 /* HW disables for us if we're MSIX multi interrupts and
593 * it's not the default (zeroeth) interrupt.
594 */
595 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
596 return 0;
597
598 ctx = qdev->intr_context + intr;
599 spin_lock(&qdev->hw_lock);
600 if (!atomic_read(&ctx->irq_cnt)) {
601 ql_write32(qdev, INTR_EN,
602 ctx->intr_dis_mask);
603 var = ql_read32(qdev, STS);
604 }
605 atomic_inc(&ctx->irq_cnt);
606 spin_unlock(&qdev->hw_lock);
607 return var;
608 }
609
610 static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
611 {
612 int i;
613 for (i = 0; i < qdev->intr_count; i++) {
614 /* The enable call does a atomic_dec_and_test
615 * and enables only if the result is zero.
616 * So we precharge it here.
617 */
618 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
619 i == 0))
620 atomic_set(&qdev->intr_context[i].irq_cnt, 1);
621 ql_enable_completion_interrupt(qdev, i);
622 }
623
624 }
625
626 static int ql_validate_flash(struct ql_adapter *qdev, u32 size, const char *str)
627 {
628 int status, i;
629 u16 csum = 0;
630 __le16 *flash = (__le16 *)&qdev->flash;
631
632 status = strncmp((char *)&qdev->flash, str, 4);
633 if (status) {
634 QPRINTK(qdev, IFUP, ERR, "Invalid flash signature.\n");
635 return status;
636 }
637
638 for (i = 0; i < size; i++)
639 csum += le16_to_cpu(*flash++);
640
641 if (csum)
642 QPRINTK(qdev, IFUP, ERR,
643 "Invalid flash checksum, csum = 0x%.04x.\n", csum);
644
645 return csum;
646 }
647
648 static int ql_read_flash_word(struct ql_adapter *qdev, int offset, __le32 *data)
649 {
650 int status = 0;
651 /* wait for reg to come ready */
652 status = ql_wait_reg_rdy(qdev,
653 FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
654 if (status)
655 goto exit;
656 /* set up for reg read */
657 ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
658 /* wait for reg to come ready */
659 status = ql_wait_reg_rdy(qdev,
660 FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
661 if (status)
662 goto exit;
663 /* This data is stored on flash as an array of
664 * __le32. Since ql_read32() returns cpu endian
665 * we need to swap it back.
666 */
667 *data = cpu_to_le32(ql_read32(qdev, FLASH_DATA));
668 exit:
669 return status;
670 }
671
672 static int ql_get_8000_flash_params(struct ql_adapter *qdev)
673 {
674 u32 i, size;
675 int status;
676 __le32 *p = (__le32 *)&qdev->flash;
677 u32 offset;
678 u8 mac_addr[6];
679
680 /* Get flash offset for function and adjust
681 * for dword access.
682 */
683 if (!qdev->port)
684 offset = FUNC0_FLASH_OFFSET / sizeof(u32);
685 else
686 offset = FUNC1_FLASH_OFFSET / sizeof(u32);
687
688 if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
689 return -ETIMEDOUT;
690
691 size = sizeof(struct flash_params_8000) / sizeof(u32);
692 for (i = 0; i < size; i++, p++) {
693 status = ql_read_flash_word(qdev, i+offset, p);
694 if (status) {
695 QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
696 goto exit;
697 }
698 }
699
700 status = ql_validate_flash(qdev,
701 sizeof(struct flash_params_8000) / sizeof(u16),
702 "8000");
703 if (status) {
704 QPRINTK(qdev, IFUP, ERR, "Invalid flash.\n");
705 status = -EINVAL;
706 goto exit;
707 }
708
709 /* Extract either manufacturer or BOFM modified
710 * MAC address.
711 */
712 if (qdev->flash.flash_params_8000.data_type1 == 2)
713 memcpy(mac_addr,
714 qdev->flash.flash_params_8000.mac_addr1,
715 qdev->ndev->addr_len);
716 else
717 memcpy(mac_addr,
718 qdev->flash.flash_params_8000.mac_addr,
719 qdev->ndev->addr_len);
720
721 if (!is_valid_ether_addr(mac_addr)) {
722 QPRINTK(qdev, IFUP, ERR, "Invalid MAC address.\n");
723 status = -EINVAL;
724 goto exit;
725 }
726
727 memcpy(qdev->ndev->dev_addr,
728 mac_addr,
729 qdev->ndev->addr_len);
730
731 exit:
732 ql_sem_unlock(qdev, SEM_FLASH_MASK);
733 return status;
734 }
735
736 static int ql_get_8012_flash_params(struct ql_adapter *qdev)
737 {
738 int i;
739 int status;
740 __le32 *p = (__le32 *)&qdev->flash;
741 u32 offset = 0;
742 u32 size = sizeof(struct flash_params_8012) / sizeof(u32);
743
744 /* Second function's parameters follow the first
745 * function's.
746 */
747 if (qdev->port)
748 offset = size;
749
750 if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
751 return -ETIMEDOUT;
752
753 for (i = 0; i < size; i++, p++) {
754 status = ql_read_flash_word(qdev, i+offset, p);
755 if (status) {
756 QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
757 goto exit;
758 }
759
760 }
761
762 status = ql_validate_flash(qdev,
763 sizeof(struct flash_params_8012) / sizeof(u16),
764 "8012");
765 if (status) {
766 QPRINTK(qdev, IFUP, ERR, "Invalid flash.\n");
767 status = -EINVAL;
768 goto exit;
769 }
770
771 if (!is_valid_ether_addr(qdev->flash.flash_params_8012.mac_addr)) {
772 status = -EINVAL;
773 goto exit;
774 }
775
776 memcpy(qdev->ndev->dev_addr,
777 qdev->flash.flash_params_8012.mac_addr,
778 qdev->ndev->addr_len);
779
780 exit:
781 ql_sem_unlock(qdev, SEM_FLASH_MASK);
782 return status;
783 }
784
785 /* xgmac register are located behind the xgmac_addr and xgmac_data
786 * register pair. Each read/write requires us to wait for the ready
787 * bit before reading/writing the data.
788 */
789 static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
790 {
791 int status;
792 /* wait for reg to come ready */
793 status = ql_wait_reg_rdy(qdev,
794 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
795 if (status)
796 return status;
797 /* write the data to the data reg */
798 ql_write32(qdev, XGMAC_DATA, data);
799 /* trigger the write */
800 ql_write32(qdev, XGMAC_ADDR, reg);
801 return status;
802 }
803
804 /* xgmac register are located behind the xgmac_addr and xgmac_data
805 * register pair. Each read/write requires us to wait for the ready
806 * bit before reading/writing the data.
807 */
808 int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
809 {
810 int status = 0;
811 /* wait for reg to come ready */
812 status = ql_wait_reg_rdy(qdev,
813 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
814 if (status)
815 goto exit;
816 /* set up for reg read */
817 ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
818 /* wait for reg to come ready */
819 status = ql_wait_reg_rdy(qdev,
820 XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
821 if (status)
822 goto exit;
823 /* get the data */
824 *data = ql_read32(qdev, XGMAC_DATA);
825 exit:
826 return status;
827 }
828
829 /* This is used for reading the 64-bit statistics regs. */
830 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
831 {
832 int status = 0;
833 u32 hi = 0;
834 u32 lo = 0;
835
836 status = ql_read_xgmac_reg(qdev, reg, &lo);
837 if (status)
838 goto exit;
839
840 status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
841 if (status)
842 goto exit;
843
844 *data = (u64) lo | ((u64) hi << 32);
845
846 exit:
847 return status;
848 }
849
850 static int ql_8000_port_initialize(struct ql_adapter *qdev)
851 {
852 int status;
853 /*
854 * Get MPI firmware version for driver banner
855 * and ethool info.
856 */
857 status = ql_mb_about_fw(qdev);
858 if (status)
859 goto exit;
860 status = ql_mb_get_fw_state(qdev);
861 if (status)
862 goto exit;
863 /* Wake up a worker to get/set the TX/RX frame sizes. */
864 queue_delayed_work(qdev->workqueue, &qdev->mpi_port_cfg_work, 0);
865 exit:
866 return status;
867 }
868
869 /* Take the MAC Core out of reset.
870 * Enable statistics counting.
871 * Take the transmitter/receiver out of reset.
872 * This functionality may be done in the MPI firmware at a
873 * later date.
874 */
875 static int ql_8012_port_initialize(struct ql_adapter *qdev)
876 {
877 int status = 0;
878 u32 data;
879
880 if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
881 /* Another function has the semaphore, so
882 * wait for the port init bit to come ready.
883 */
884 QPRINTK(qdev, LINK, INFO,
885 "Another function has the semaphore, so wait for the port init bit to come ready.\n");
886 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
887 if (status) {
888 QPRINTK(qdev, LINK, CRIT,
889 "Port initialize timed out.\n");
890 }
891 return status;
892 }
893
894 QPRINTK(qdev, LINK, INFO, "Got xgmac semaphore!.\n");
895 /* Set the core reset. */
896 status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
897 if (status)
898 goto end;
899 data |= GLOBAL_CFG_RESET;
900 status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
901 if (status)
902 goto end;
903
904 /* Clear the core reset and turn on jumbo for receiver. */
905 data &= ~GLOBAL_CFG_RESET; /* Clear core reset. */
906 data |= GLOBAL_CFG_JUMBO; /* Turn on jumbo. */
907 data |= GLOBAL_CFG_TX_STAT_EN;
908 data |= GLOBAL_CFG_RX_STAT_EN;
909 status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
910 if (status)
911 goto end;
912
913 /* Enable transmitter, and clear it's reset. */
914 status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
915 if (status)
916 goto end;
917 data &= ~TX_CFG_RESET; /* Clear the TX MAC reset. */
918 data |= TX_CFG_EN; /* Enable the transmitter. */
919 status = ql_write_xgmac_reg(qdev, TX_CFG, data);
920 if (status)
921 goto end;
922
923 /* Enable receiver and clear it's reset. */
924 status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
925 if (status)
926 goto end;
927 data &= ~RX_CFG_RESET; /* Clear the RX MAC reset. */
928 data |= RX_CFG_EN; /* Enable the receiver. */
929 status = ql_write_xgmac_reg(qdev, RX_CFG, data);
930 if (status)
931 goto end;
932
933 /* Turn on jumbo. */
934 status =
935 ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
936 if (status)
937 goto end;
938 status =
939 ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
940 if (status)
941 goto end;
942
943 /* Signal to the world that the port is enabled. */
944 ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
945 end:
946 ql_sem_unlock(qdev, qdev->xg_sem_mask);
947 return status;
948 }
949
950 /* Get the next large buffer. */
951 static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
952 {
953 struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
954 rx_ring->lbq_curr_idx++;
955 if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
956 rx_ring->lbq_curr_idx = 0;
957 rx_ring->lbq_free_cnt++;
958 return lbq_desc;
959 }
960
961 /* Get the next small buffer. */
962 static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
963 {
964 struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
965 rx_ring->sbq_curr_idx++;
966 if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
967 rx_ring->sbq_curr_idx = 0;
968 rx_ring->sbq_free_cnt++;
969 return sbq_desc;
970 }
971
972 /* Update an rx ring index. */
973 static void ql_update_cq(struct rx_ring *rx_ring)
974 {
975 rx_ring->cnsmr_idx++;
976 rx_ring->curr_entry++;
977 if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
978 rx_ring->cnsmr_idx = 0;
979 rx_ring->curr_entry = rx_ring->cq_base;
980 }
981 }
982
983 static void ql_write_cq_idx(struct rx_ring *rx_ring)
984 {
985 ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
986 }
987
988 /* Process (refill) a large buffer queue. */
989 static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
990 {
991 u32 clean_idx = rx_ring->lbq_clean_idx;
992 u32 start_idx = clean_idx;
993 struct bq_desc *lbq_desc;
994 u64 map;
995 int i;
996
997 while (rx_ring->lbq_free_cnt > 16) {
998 for (i = 0; i < 16; i++) {
999 QPRINTK(qdev, RX_STATUS, DEBUG,
1000 "lbq: try cleaning clean_idx = %d.\n",
1001 clean_idx);
1002 lbq_desc = &rx_ring->lbq[clean_idx];
1003 if (lbq_desc->p.lbq_page == NULL) {
1004 QPRINTK(qdev, RX_STATUS, DEBUG,
1005 "lbq: getting new page for index %d.\n",
1006 lbq_desc->index);
1007 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
1008 if (lbq_desc->p.lbq_page == NULL) {
1009 rx_ring->lbq_clean_idx = clean_idx;
1010 QPRINTK(qdev, RX_STATUS, ERR,
1011 "Couldn't get a page.\n");
1012 return;
1013 }
1014 map = pci_map_page(qdev->pdev,
1015 lbq_desc->p.lbq_page,
1016 0, PAGE_SIZE,
1017 PCI_DMA_FROMDEVICE);
1018 if (pci_dma_mapping_error(qdev->pdev, map)) {
1019 rx_ring->lbq_clean_idx = clean_idx;
1020 put_page(lbq_desc->p.lbq_page);
1021 lbq_desc->p.lbq_page = NULL;
1022 QPRINTK(qdev, RX_STATUS, ERR,
1023 "PCI mapping failed.\n");
1024 return;
1025 }
1026 pci_unmap_addr_set(lbq_desc, mapaddr, map);
1027 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
1028 *lbq_desc->addr = cpu_to_le64(map);
1029 }
1030 clean_idx++;
1031 if (clean_idx == rx_ring->lbq_len)
1032 clean_idx = 0;
1033 }
1034
1035 rx_ring->lbq_clean_idx = clean_idx;
1036 rx_ring->lbq_prod_idx += 16;
1037 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
1038 rx_ring->lbq_prod_idx = 0;
1039 rx_ring->lbq_free_cnt -= 16;
1040 }
1041
1042 if (start_idx != clean_idx) {
1043 QPRINTK(qdev, RX_STATUS, DEBUG,
1044 "lbq: updating prod idx = %d.\n",
1045 rx_ring->lbq_prod_idx);
1046 ql_write_db_reg(rx_ring->lbq_prod_idx,
1047 rx_ring->lbq_prod_idx_db_reg);
1048 }
1049 }
1050
1051 /* Process (refill) a small buffer queue. */
1052 static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
1053 {
1054 u32 clean_idx = rx_ring->sbq_clean_idx;
1055 u32 start_idx = clean_idx;
1056 struct bq_desc *sbq_desc;
1057 u64 map;
1058 int i;
1059
1060 while (rx_ring->sbq_free_cnt > 16) {
1061 for (i = 0; i < 16; i++) {
1062 sbq_desc = &rx_ring->sbq[clean_idx];
1063 QPRINTK(qdev, RX_STATUS, DEBUG,
1064 "sbq: try cleaning clean_idx = %d.\n",
1065 clean_idx);
1066 if (sbq_desc->p.skb == NULL) {
1067 QPRINTK(qdev, RX_STATUS, DEBUG,
1068 "sbq: getting new skb for index %d.\n",
1069 sbq_desc->index);
1070 sbq_desc->p.skb =
1071 netdev_alloc_skb(qdev->ndev,
1072 rx_ring->sbq_buf_size);
1073 if (sbq_desc->p.skb == NULL) {
1074 QPRINTK(qdev, PROBE, ERR,
1075 "Couldn't get an skb.\n");
1076 rx_ring->sbq_clean_idx = clean_idx;
1077 return;
1078 }
1079 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
1080 map = pci_map_single(qdev->pdev,
1081 sbq_desc->p.skb->data,
1082 rx_ring->sbq_buf_size /
1083 2, PCI_DMA_FROMDEVICE);
1084 if (pci_dma_mapping_error(qdev->pdev, map)) {
1085 QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
1086 rx_ring->sbq_clean_idx = clean_idx;
1087 dev_kfree_skb_any(sbq_desc->p.skb);
1088 sbq_desc->p.skb = NULL;
1089 return;
1090 }
1091 pci_unmap_addr_set(sbq_desc, mapaddr, map);
1092 pci_unmap_len_set(sbq_desc, maplen,
1093 rx_ring->sbq_buf_size / 2);
1094 *sbq_desc->addr = cpu_to_le64(map);
1095 }
1096
1097 clean_idx++;
1098 if (clean_idx == rx_ring->sbq_len)
1099 clean_idx = 0;
1100 }
1101 rx_ring->sbq_clean_idx = clean_idx;
1102 rx_ring->sbq_prod_idx += 16;
1103 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
1104 rx_ring->sbq_prod_idx = 0;
1105 rx_ring->sbq_free_cnt -= 16;
1106 }
1107
1108 if (start_idx != clean_idx) {
1109 QPRINTK(qdev, RX_STATUS, DEBUG,
1110 "sbq: updating prod idx = %d.\n",
1111 rx_ring->sbq_prod_idx);
1112 ql_write_db_reg(rx_ring->sbq_prod_idx,
1113 rx_ring->sbq_prod_idx_db_reg);
1114 }
1115 }
1116
1117 static void ql_update_buffer_queues(struct ql_adapter *qdev,
1118 struct rx_ring *rx_ring)
1119 {
1120 ql_update_sbq(qdev, rx_ring);
1121 ql_update_lbq(qdev, rx_ring);
1122 }
1123
1124 /* Unmaps tx buffers. Can be called from send() if a pci mapping
1125 * fails at some stage, or from the interrupt when a tx completes.
1126 */
1127 static void ql_unmap_send(struct ql_adapter *qdev,
1128 struct tx_ring_desc *tx_ring_desc, int mapped)
1129 {
1130 int i;
1131 for (i = 0; i < mapped; i++) {
1132 if (i == 0 || (i == 7 && mapped > 7)) {
1133 /*
1134 * Unmap the skb->data area, or the
1135 * external sglist (AKA the Outbound
1136 * Address List (OAL)).
1137 * If its the zeroeth element, then it's
1138 * the skb->data area. If it's the 7th
1139 * element and there is more than 6 frags,
1140 * then its an OAL.
1141 */
1142 if (i == 7) {
1143 QPRINTK(qdev, TX_DONE, DEBUG,
1144 "unmapping OAL area.\n");
1145 }
1146 pci_unmap_single(qdev->pdev,
1147 pci_unmap_addr(&tx_ring_desc->map[i],
1148 mapaddr),
1149 pci_unmap_len(&tx_ring_desc->map[i],
1150 maplen),
1151 PCI_DMA_TODEVICE);
1152 } else {
1153 QPRINTK(qdev, TX_DONE, DEBUG, "unmapping frag %d.\n",
1154 i);
1155 pci_unmap_page(qdev->pdev,
1156 pci_unmap_addr(&tx_ring_desc->map[i],
1157 mapaddr),
1158 pci_unmap_len(&tx_ring_desc->map[i],
1159 maplen), PCI_DMA_TODEVICE);
1160 }
1161 }
1162
1163 }
1164
1165 /* Map the buffers for this transmit. This will return
1166 * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1167 */
1168 static int ql_map_send(struct ql_adapter *qdev,
1169 struct ob_mac_iocb_req *mac_iocb_ptr,
1170 struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1171 {
1172 int len = skb_headlen(skb);
1173 dma_addr_t map;
1174 int frag_idx, err, map_idx = 0;
1175 struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1176 int frag_cnt = skb_shinfo(skb)->nr_frags;
1177
1178 if (frag_cnt) {
1179 QPRINTK(qdev, TX_QUEUED, DEBUG, "frag_cnt = %d.\n", frag_cnt);
1180 }
1181 /*
1182 * Map the skb buffer first.
1183 */
1184 map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1185
1186 err = pci_dma_mapping_error(qdev->pdev, map);
1187 if (err) {
1188 QPRINTK(qdev, TX_QUEUED, ERR,
1189 "PCI mapping failed with error: %d\n", err);
1190
1191 return NETDEV_TX_BUSY;
1192 }
1193
1194 tbd->len = cpu_to_le32(len);
1195 tbd->addr = cpu_to_le64(map);
1196 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1197 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1198 map_idx++;
1199
1200 /*
1201 * This loop fills the remainder of the 8 address descriptors
1202 * in the IOCB. If there are more than 7 fragments, then the
1203 * eighth address desc will point to an external list (OAL).
1204 * When this happens, the remainder of the frags will be stored
1205 * in this list.
1206 */
1207 for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1208 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1209 tbd++;
1210 if (frag_idx == 6 && frag_cnt > 7) {
1211 /* Let's tack on an sglist.
1212 * Our control block will now
1213 * look like this:
1214 * iocb->seg[0] = skb->data
1215 * iocb->seg[1] = frag[0]
1216 * iocb->seg[2] = frag[1]
1217 * iocb->seg[3] = frag[2]
1218 * iocb->seg[4] = frag[3]
1219 * iocb->seg[5] = frag[4]
1220 * iocb->seg[6] = frag[5]
1221 * iocb->seg[7] = ptr to OAL (external sglist)
1222 * oal->seg[0] = frag[6]
1223 * oal->seg[1] = frag[7]
1224 * oal->seg[2] = frag[8]
1225 * oal->seg[3] = frag[9]
1226 * oal->seg[4] = frag[10]
1227 * etc...
1228 */
1229 /* Tack on the OAL in the eighth segment of IOCB. */
1230 map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1231 sizeof(struct oal),
1232 PCI_DMA_TODEVICE);
1233 err = pci_dma_mapping_error(qdev->pdev, map);
1234 if (err) {
1235 QPRINTK(qdev, TX_QUEUED, ERR,
1236 "PCI mapping outbound address list with error: %d\n",
1237 err);
1238 goto map_error;
1239 }
1240
1241 tbd->addr = cpu_to_le64(map);
1242 /*
1243 * The length is the number of fragments
1244 * that remain to be mapped times the length
1245 * of our sglist (OAL).
1246 */
1247 tbd->len =
1248 cpu_to_le32((sizeof(struct tx_buf_desc) *
1249 (frag_cnt - frag_idx)) | TX_DESC_C);
1250 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1251 map);
1252 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1253 sizeof(struct oal));
1254 tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1255 map_idx++;
1256 }
1257
1258 map =
1259 pci_map_page(qdev->pdev, frag->page,
1260 frag->page_offset, frag->size,
1261 PCI_DMA_TODEVICE);
1262
1263 err = pci_dma_mapping_error(qdev->pdev, map);
1264 if (err) {
1265 QPRINTK(qdev, TX_QUEUED, ERR,
1266 "PCI mapping frags failed with error: %d.\n",
1267 err);
1268 goto map_error;
1269 }
1270
1271 tbd->addr = cpu_to_le64(map);
1272 tbd->len = cpu_to_le32(frag->size);
1273 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1274 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1275 frag->size);
1276
1277 }
1278 /* Save the number of segments we've mapped. */
1279 tx_ring_desc->map_cnt = map_idx;
1280 /* Terminate the last segment. */
1281 tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1282 return NETDEV_TX_OK;
1283
1284 map_error:
1285 /*
1286 * If the first frag mapping failed, then i will be zero.
1287 * This causes the unmap of the skb->data area. Otherwise
1288 * we pass in the number of frags that mapped successfully
1289 * so they can be umapped.
1290 */
1291 ql_unmap_send(qdev, tx_ring_desc, map_idx);
1292 return NETDEV_TX_BUSY;
1293 }
1294
1295 static void ql_realign_skb(struct sk_buff *skb, int len)
1296 {
1297 void *temp_addr = skb->data;
1298
1299 /* Undo the skb_reserve(skb,32) we did before
1300 * giving to hardware, and realign data on
1301 * a 2-byte boundary.
1302 */
1303 skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1304 skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1305 skb_copy_to_linear_data(skb, temp_addr,
1306 (unsigned int)len);
1307 }
1308
1309 /*
1310 * This function builds an skb for the given inbound
1311 * completion. It will be rewritten for readability in the near
1312 * future, but for not it works well.
1313 */
1314 static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1315 struct rx_ring *rx_ring,
1316 struct ib_mac_iocb_rsp *ib_mac_rsp)
1317 {
1318 struct bq_desc *lbq_desc;
1319 struct bq_desc *sbq_desc;
1320 struct sk_buff *skb = NULL;
1321 u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1322 u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1323
1324 /*
1325 * Handle the header buffer if present.
1326 */
1327 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1328 ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1329 QPRINTK(qdev, RX_STATUS, DEBUG, "Header of %d bytes in small buffer.\n", hdr_len);
1330 /*
1331 * Headers fit nicely into a small buffer.
1332 */
1333 sbq_desc = ql_get_curr_sbuf(rx_ring);
1334 pci_unmap_single(qdev->pdev,
1335 pci_unmap_addr(sbq_desc, mapaddr),
1336 pci_unmap_len(sbq_desc, maplen),
1337 PCI_DMA_FROMDEVICE);
1338 skb = sbq_desc->p.skb;
1339 ql_realign_skb(skb, hdr_len);
1340 skb_put(skb, hdr_len);
1341 sbq_desc->p.skb = NULL;
1342 }
1343
1344 /*
1345 * Handle the data buffer(s).
1346 */
1347 if (unlikely(!length)) { /* Is there data too? */
1348 QPRINTK(qdev, RX_STATUS, DEBUG,
1349 "No Data buffer in this packet.\n");
1350 return skb;
1351 }
1352
1353 if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1354 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1355 QPRINTK(qdev, RX_STATUS, DEBUG,
1356 "Headers in small, data of %d bytes in small, combine them.\n", length);
1357 /*
1358 * Data is less than small buffer size so it's
1359 * stuffed in a small buffer.
1360 * For this case we append the data
1361 * from the "data" small buffer to the "header" small
1362 * buffer.
1363 */
1364 sbq_desc = ql_get_curr_sbuf(rx_ring);
1365 pci_dma_sync_single_for_cpu(qdev->pdev,
1366 pci_unmap_addr
1367 (sbq_desc, mapaddr),
1368 pci_unmap_len
1369 (sbq_desc, maplen),
1370 PCI_DMA_FROMDEVICE);
1371 memcpy(skb_put(skb, length),
1372 sbq_desc->p.skb->data, length);
1373 pci_dma_sync_single_for_device(qdev->pdev,
1374 pci_unmap_addr
1375 (sbq_desc,
1376 mapaddr),
1377 pci_unmap_len
1378 (sbq_desc,
1379 maplen),
1380 PCI_DMA_FROMDEVICE);
1381 } else {
1382 QPRINTK(qdev, RX_STATUS, DEBUG,
1383 "%d bytes in a single small buffer.\n", length);
1384 sbq_desc = ql_get_curr_sbuf(rx_ring);
1385 skb = sbq_desc->p.skb;
1386 ql_realign_skb(skb, length);
1387 skb_put(skb, length);
1388 pci_unmap_single(qdev->pdev,
1389 pci_unmap_addr(sbq_desc,
1390 mapaddr),
1391 pci_unmap_len(sbq_desc,
1392 maplen),
1393 PCI_DMA_FROMDEVICE);
1394 sbq_desc->p.skb = NULL;
1395 }
1396 } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1397 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1398 QPRINTK(qdev, RX_STATUS, DEBUG,
1399 "Header in small, %d bytes in large. Chain large to small!\n", length);
1400 /*
1401 * The data is in a single large buffer. We
1402 * chain it to the header buffer's skb and let
1403 * it rip.
1404 */
1405 lbq_desc = ql_get_curr_lbuf(rx_ring);
1406 pci_unmap_page(qdev->pdev,
1407 pci_unmap_addr(lbq_desc,
1408 mapaddr),
1409 pci_unmap_len(lbq_desc, maplen),
1410 PCI_DMA_FROMDEVICE);
1411 QPRINTK(qdev, RX_STATUS, DEBUG,
1412 "Chaining page to skb.\n");
1413 skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1414 0, length);
1415 skb->len += length;
1416 skb->data_len += length;
1417 skb->truesize += length;
1418 lbq_desc->p.lbq_page = NULL;
1419 } else {
1420 /*
1421 * The headers and data are in a single large buffer. We
1422 * copy it to a new skb and let it go. This can happen with
1423 * jumbo mtu on a non-TCP/UDP frame.
1424 */
1425 lbq_desc = ql_get_curr_lbuf(rx_ring);
1426 skb = netdev_alloc_skb(qdev->ndev, length);
1427 if (skb == NULL) {
1428 QPRINTK(qdev, PROBE, DEBUG,
1429 "No skb available, drop the packet.\n");
1430 return NULL;
1431 }
1432 pci_unmap_page(qdev->pdev,
1433 pci_unmap_addr(lbq_desc,
1434 mapaddr),
1435 pci_unmap_len(lbq_desc, maplen),
1436 PCI_DMA_FROMDEVICE);
1437 skb_reserve(skb, NET_IP_ALIGN);
1438 QPRINTK(qdev, RX_STATUS, DEBUG,
1439 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length);
1440 skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1441 0, length);
1442 skb->len += length;
1443 skb->data_len += length;
1444 skb->truesize += length;
1445 length -= length;
1446 lbq_desc->p.lbq_page = NULL;
1447 __pskb_pull_tail(skb,
1448 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1449 VLAN_ETH_HLEN : ETH_HLEN);
1450 }
1451 } else {
1452 /*
1453 * The data is in a chain of large buffers
1454 * pointed to by a small buffer. We loop
1455 * thru and chain them to the our small header
1456 * buffer's skb.
1457 * frags: There are 18 max frags and our small
1458 * buffer will hold 32 of them. The thing is,
1459 * we'll use 3 max for our 9000 byte jumbo
1460 * frames. If the MTU goes up we could
1461 * eventually be in trouble.
1462 */
1463 int size, offset, i = 0;
1464 __le64 *bq, bq_array[8];
1465 sbq_desc = ql_get_curr_sbuf(rx_ring);
1466 pci_unmap_single(qdev->pdev,
1467 pci_unmap_addr(sbq_desc, mapaddr),
1468 pci_unmap_len(sbq_desc, maplen),
1469 PCI_DMA_FROMDEVICE);
1470 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1471 /*
1472 * This is an non TCP/UDP IP frame, so
1473 * the headers aren't split into a small
1474 * buffer. We have to use the small buffer
1475 * that contains our sg list as our skb to
1476 * send upstairs. Copy the sg list here to
1477 * a local buffer and use it to find the
1478 * pages to chain.
1479 */
1480 QPRINTK(qdev, RX_STATUS, DEBUG,
1481 "%d bytes of headers & data in chain of large.\n", length);
1482 skb = sbq_desc->p.skb;
1483 bq = &bq_array[0];
1484 memcpy(bq, skb->data, sizeof(bq_array));
1485 sbq_desc->p.skb = NULL;
1486 skb_reserve(skb, NET_IP_ALIGN);
1487 } else {
1488 QPRINTK(qdev, RX_STATUS, DEBUG,
1489 "Headers in small, %d bytes of data in chain of large.\n", length);
1490 bq = (__le64 *)sbq_desc->p.skb->data;
1491 }
1492 while (length > 0) {
1493 lbq_desc = ql_get_curr_lbuf(rx_ring);
1494 pci_unmap_page(qdev->pdev,
1495 pci_unmap_addr(lbq_desc,
1496 mapaddr),
1497 pci_unmap_len(lbq_desc,
1498 maplen),
1499 PCI_DMA_FROMDEVICE);
1500 size = (length < PAGE_SIZE) ? length : PAGE_SIZE;
1501 offset = 0;
1502
1503 QPRINTK(qdev, RX_STATUS, DEBUG,
1504 "Adding page %d to skb for %d bytes.\n",
1505 i, size);
1506 skb_fill_page_desc(skb, i, lbq_desc->p.lbq_page,
1507 offset, size);
1508 skb->len += size;
1509 skb->data_len += size;
1510 skb->truesize += size;
1511 length -= size;
1512 lbq_desc->p.lbq_page = NULL;
1513 bq++;
1514 i++;
1515 }
1516 __pskb_pull_tail(skb, (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1517 VLAN_ETH_HLEN : ETH_HLEN);
1518 }
1519 return skb;
1520 }
1521
1522 /* Process an inbound completion from an rx ring. */
1523 static void ql_process_mac_rx_intr(struct ql_adapter *qdev,
1524 struct rx_ring *rx_ring,
1525 struct ib_mac_iocb_rsp *ib_mac_rsp)
1526 {
1527 struct net_device *ndev = qdev->ndev;
1528 struct sk_buff *skb = NULL;
1529 u16 vlan_id = (le16_to_cpu(ib_mac_rsp->vlan_id) &
1530 IB_MAC_IOCB_RSP_VLAN_MASK)
1531
1532 QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1533
1534 skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1535 if (unlikely(!skb)) {
1536 QPRINTK(qdev, RX_STATUS, DEBUG,
1537 "No skb available, drop packet.\n");
1538 return;
1539 }
1540
1541 /* Frame error, so drop the packet. */
1542 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) {
1543 QPRINTK(qdev, DRV, ERR, "Receive error, flags2 = 0x%x\n",
1544 ib_mac_rsp->flags2);
1545 dev_kfree_skb_any(skb);
1546 return;
1547 }
1548
1549 /* The max framesize filter on this chip is set higher than
1550 * MTU since FCoE uses 2k frames.
1551 */
1552 if (skb->len > ndev->mtu + ETH_HLEN) {
1553 dev_kfree_skb_any(skb);
1554 return;
1555 }
1556
1557 prefetch(skb->data);
1558 skb->dev = ndev;
1559 if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1560 QPRINTK(qdev, RX_STATUS, DEBUG, "%s%s%s Multicast.\n",
1561 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1562 IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1563 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1564 IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1565 (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1566 IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1567 }
1568 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
1569 QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
1570 }
1571
1572 skb->protocol = eth_type_trans(skb, ndev);
1573 skb->ip_summed = CHECKSUM_NONE;
1574
1575 /* If rx checksum is on, and there are no
1576 * csum or frame errors.
1577 */
1578 if (qdev->rx_csum &&
1579 !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) {
1580 /* TCP frame. */
1581 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) {
1582 QPRINTK(qdev, RX_STATUS, DEBUG,
1583 "TCP checksum done!\n");
1584 skb->ip_summed = CHECKSUM_UNNECESSARY;
1585 } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1586 (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) {
1587 /* Unfragmented ipv4 UDP frame. */
1588 struct iphdr *iph = (struct iphdr *) skb->data;
1589 if (!(iph->frag_off &
1590 cpu_to_be16(IP_MF|IP_OFFSET))) {
1591 skb->ip_summed = CHECKSUM_UNNECESSARY;
1592 QPRINTK(qdev, RX_STATUS, DEBUG,
1593 "TCP checksum done!\n");
1594 }
1595 }
1596 }
1597
1598 qdev->stats.rx_packets++;
1599 qdev->stats.rx_bytes += skb->len;
1600 skb_record_rx_queue(skb,
1601 rx_ring->cq_id - qdev->rss_ring_first_cq_id);
1602 if (skb->ip_summed == CHECKSUM_UNNECESSARY) {
1603 if (qdev->vlgrp &&
1604 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) &&
1605 (vlan_id != 0))
1606 vlan_gro_receive(&rx_ring->napi, qdev->vlgrp,
1607 vlan_id, skb);
1608 else
1609 napi_gro_receive(&rx_ring->napi, skb);
1610 } else {
1611 if (qdev->vlgrp &&
1612 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) &&
1613 (vlan_id != 0))
1614 vlan_hwaccel_receive_skb(skb, qdev->vlgrp, vlan_id);
1615 else
1616 netif_receive_skb(skb);
1617 }
1618 }
1619
1620 /* Process an outbound completion from an rx ring. */
1621 static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
1622 struct ob_mac_iocb_rsp *mac_rsp)
1623 {
1624 struct tx_ring *tx_ring;
1625 struct tx_ring_desc *tx_ring_desc;
1626
1627 QL_DUMP_OB_MAC_RSP(mac_rsp);
1628 tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
1629 tx_ring_desc = &tx_ring->q[mac_rsp->tid];
1630 ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
1631 qdev->stats.tx_bytes += tx_ring_desc->map_cnt;
1632 qdev->stats.tx_packets++;
1633 dev_kfree_skb(tx_ring_desc->skb);
1634 tx_ring_desc->skb = NULL;
1635
1636 if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
1637 OB_MAC_IOCB_RSP_S |
1638 OB_MAC_IOCB_RSP_L |
1639 OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
1640 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
1641 QPRINTK(qdev, TX_DONE, WARNING,
1642 "Total descriptor length did not match transfer length.\n");
1643 }
1644 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
1645 QPRINTK(qdev, TX_DONE, WARNING,
1646 "Frame too short to be legal, not sent.\n");
1647 }
1648 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
1649 QPRINTK(qdev, TX_DONE, WARNING,
1650 "Frame too long, but sent anyway.\n");
1651 }
1652 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
1653 QPRINTK(qdev, TX_DONE, WARNING,
1654 "PCI backplane error. Frame not sent.\n");
1655 }
1656 }
1657 atomic_inc(&tx_ring->tx_count);
1658 }
1659
1660 /* Fire up a handler to reset the MPI processor. */
1661 void ql_queue_fw_error(struct ql_adapter *qdev)
1662 {
1663 netif_carrier_off(qdev->ndev);
1664 queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
1665 }
1666
1667 void ql_queue_asic_error(struct ql_adapter *qdev)
1668 {
1669 netif_carrier_off(qdev->ndev);
1670 ql_disable_interrupts(qdev);
1671 /* Clear adapter up bit to signal the recovery
1672 * process that it shouldn't kill the reset worker
1673 * thread
1674 */
1675 clear_bit(QL_ADAPTER_UP, &qdev->flags);
1676 queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
1677 }
1678
1679 static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
1680 struct ib_ae_iocb_rsp *ib_ae_rsp)
1681 {
1682 switch (ib_ae_rsp->event) {
1683 case MGMT_ERR_EVENT:
1684 QPRINTK(qdev, RX_ERR, ERR,
1685 "Management Processor Fatal Error.\n");
1686 ql_queue_fw_error(qdev);
1687 return;
1688
1689 case CAM_LOOKUP_ERR_EVENT:
1690 QPRINTK(qdev, LINK, ERR,
1691 "Multiple CAM hits lookup occurred.\n");
1692 QPRINTK(qdev, DRV, ERR, "This event shouldn't occur.\n");
1693 ql_queue_asic_error(qdev);
1694 return;
1695
1696 case SOFT_ECC_ERROR_EVENT:
1697 QPRINTK(qdev, RX_ERR, ERR, "Soft ECC error detected.\n");
1698 ql_queue_asic_error(qdev);
1699 break;
1700
1701 case PCI_ERR_ANON_BUF_RD:
1702 QPRINTK(qdev, RX_ERR, ERR,
1703 "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1704 ib_ae_rsp->q_id);
1705 ql_queue_asic_error(qdev);
1706 break;
1707
1708 default:
1709 QPRINTK(qdev, DRV, ERR, "Unexpected event %d.\n",
1710 ib_ae_rsp->event);
1711 ql_queue_asic_error(qdev);
1712 break;
1713 }
1714 }
1715
1716 static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
1717 {
1718 struct ql_adapter *qdev = rx_ring->qdev;
1719 u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1720 struct ob_mac_iocb_rsp *net_rsp = NULL;
1721 int count = 0;
1722
1723 struct tx_ring *tx_ring;
1724 /* While there are entries in the completion queue. */
1725 while (prod != rx_ring->cnsmr_idx) {
1726
1727 QPRINTK(qdev, RX_STATUS, DEBUG,
1728 "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1729 prod, rx_ring->cnsmr_idx);
1730
1731 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
1732 rmb();
1733 switch (net_rsp->opcode) {
1734
1735 case OPCODE_OB_MAC_TSO_IOCB:
1736 case OPCODE_OB_MAC_IOCB:
1737 ql_process_mac_tx_intr(qdev, net_rsp);
1738 break;
1739 default:
1740 QPRINTK(qdev, RX_STATUS, DEBUG,
1741 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1742 net_rsp->opcode);
1743 }
1744 count++;
1745 ql_update_cq(rx_ring);
1746 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1747 }
1748 ql_write_cq_idx(rx_ring);
1749 tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
1750 if (__netif_subqueue_stopped(qdev->ndev, tx_ring->wq_id) &&
1751 net_rsp != NULL) {
1752 if (atomic_read(&tx_ring->queue_stopped) &&
1753 (atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
1754 /*
1755 * The queue got stopped because the tx_ring was full.
1756 * Wake it up, because it's now at least 25% empty.
1757 */
1758 netif_wake_subqueue(qdev->ndev, tx_ring->wq_id);
1759 }
1760
1761 return count;
1762 }
1763
1764 static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
1765 {
1766 struct ql_adapter *qdev = rx_ring->qdev;
1767 u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1768 struct ql_net_rsp_iocb *net_rsp;
1769 int count = 0;
1770
1771 /* While there are entries in the completion queue. */
1772 while (prod != rx_ring->cnsmr_idx) {
1773
1774 QPRINTK(qdev, RX_STATUS, DEBUG,
1775 "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1776 prod, rx_ring->cnsmr_idx);
1777
1778 net_rsp = rx_ring->curr_entry;
1779 rmb();
1780 switch (net_rsp->opcode) {
1781 case OPCODE_IB_MAC_IOCB:
1782 ql_process_mac_rx_intr(qdev, rx_ring,
1783 (struct ib_mac_iocb_rsp *)
1784 net_rsp);
1785 break;
1786
1787 case OPCODE_IB_AE_IOCB:
1788 ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
1789 net_rsp);
1790 break;
1791 default:
1792 {
1793 QPRINTK(qdev, RX_STATUS, DEBUG,
1794 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1795 net_rsp->opcode);
1796 }
1797 }
1798 count++;
1799 ql_update_cq(rx_ring);
1800 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1801 if (count == budget)
1802 break;
1803 }
1804 ql_update_buffer_queues(qdev, rx_ring);
1805 ql_write_cq_idx(rx_ring);
1806 return count;
1807 }
1808
1809 static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
1810 {
1811 struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
1812 struct ql_adapter *qdev = rx_ring->qdev;
1813 int work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
1814
1815 QPRINTK(qdev, RX_STATUS, DEBUG, "Enter, NAPI POLL cq_id = %d.\n",
1816 rx_ring->cq_id);
1817
1818 if (work_done < budget) {
1819 napi_complete(napi);
1820 ql_enable_completion_interrupt(qdev, rx_ring->irq);
1821 }
1822 return work_done;
1823 }
1824
1825 static void ql_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
1826 {
1827 struct ql_adapter *qdev = netdev_priv(ndev);
1828
1829 qdev->vlgrp = grp;
1830 if (grp) {
1831 QPRINTK(qdev, IFUP, DEBUG, "Turning on VLAN in NIC_RCV_CFG.\n");
1832 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
1833 NIC_RCV_CFG_VLAN_MATCH_AND_NON);
1834 } else {
1835 QPRINTK(qdev, IFUP, DEBUG,
1836 "Turning off VLAN in NIC_RCV_CFG.\n");
1837 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
1838 }
1839 }
1840
1841 static void ql_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
1842 {
1843 struct ql_adapter *qdev = netdev_priv(ndev);
1844 u32 enable_bit = MAC_ADDR_E;
1845 int status;
1846
1847 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1848 if (status)
1849 return;
1850 spin_lock(&qdev->hw_lock);
1851 if (ql_set_mac_addr_reg
1852 (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1853 QPRINTK(qdev, IFUP, ERR, "Failed to init vlan address.\n");
1854 }
1855 spin_unlock(&qdev->hw_lock);
1856 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1857 }
1858
1859 static void ql_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
1860 {
1861 struct ql_adapter *qdev = netdev_priv(ndev);
1862 u32 enable_bit = 0;
1863 int status;
1864
1865 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1866 if (status)
1867 return;
1868
1869 spin_lock(&qdev->hw_lock);
1870 if (ql_set_mac_addr_reg
1871 (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1872 QPRINTK(qdev, IFUP, ERR, "Failed to clear vlan address.\n");
1873 }
1874 spin_unlock(&qdev->hw_lock);
1875 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1876
1877 }
1878
1879 /* Worker thread to process a given rx_ring that is dedicated
1880 * to outbound completions.
1881 */
1882 static void ql_tx_clean(struct work_struct *work)
1883 {
1884 struct rx_ring *rx_ring =
1885 container_of(work, struct rx_ring, rx_work.work);
1886 ql_clean_outbound_rx_ring(rx_ring);
1887 ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1888
1889 }
1890
1891 /* Worker thread to process a given rx_ring that is dedicated
1892 * to inbound completions.
1893 */
1894 static void ql_rx_clean(struct work_struct *work)
1895 {
1896 struct rx_ring *rx_ring =
1897 container_of(work, struct rx_ring, rx_work.work);
1898 ql_clean_inbound_rx_ring(rx_ring, 64);
1899 ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1900 }
1901
1902 /* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1903 static irqreturn_t qlge_msix_tx_isr(int irq, void *dev_id)
1904 {
1905 struct rx_ring *rx_ring = dev_id;
1906 queue_delayed_work_on(rx_ring->cpu, rx_ring->qdev->q_workqueue,
1907 &rx_ring->rx_work, 0);
1908 return IRQ_HANDLED;
1909 }
1910
1911 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1912 static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
1913 {
1914 struct rx_ring *rx_ring = dev_id;
1915 napi_schedule(&rx_ring->napi);
1916 return IRQ_HANDLED;
1917 }
1918
1919 /* This handles a fatal error, MPI activity, and the default
1920 * rx_ring in an MSI-X multiple vector environment.
1921 * In MSI/Legacy environment it also process the rest of
1922 * the rx_rings.
1923 */
1924 static irqreturn_t qlge_isr(int irq, void *dev_id)
1925 {
1926 struct rx_ring *rx_ring = dev_id;
1927 struct ql_adapter *qdev = rx_ring->qdev;
1928 struct intr_context *intr_context = &qdev->intr_context[0];
1929 u32 var;
1930 int i;
1931 int work_done = 0;
1932
1933 spin_lock(&qdev->hw_lock);
1934 if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
1935 QPRINTK(qdev, INTR, DEBUG, "Shared Interrupt, Not ours!\n");
1936 spin_unlock(&qdev->hw_lock);
1937 return IRQ_NONE;
1938 }
1939 spin_unlock(&qdev->hw_lock);
1940
1941 var = ql_disable_completion_interrupt(qdev, intr_context->intr);
1942
1943 /*
1944 * Check for fatal error.
1945 */
1946 if (var & STS_FE) {
1947 ql_queue_asic_error(qdev);
1948 QPRINTK(qdev, INTR, ERR, "Got fatal error, STS = %x.\n", var);
1949 var = ql_read32(qdev, ERR_STS);
1950 QPRINTK(qdev, INTR, ERR,
1951 "Resetting chip. Error Status Register = 0x%x\n", var);
1952 return IRQ_HANDLED;
1953 }
1954
1955 /*
1956 * Check MPI processor activity.
1957 */
1958 if (var & STS_PI) {
1959 /*
1960 * We've got an async event or mailbox completion.
1961 * Handle it and clear the source of the interrupt.
1962 */
1963 QPRINTK(qdev, INTR, ERR, "Got MPI processor interrupt.\n");
1964 ql_disable_completion_interrupt(qdev, intr_context->intr);
1965 queue_delayed_work_on(smp_processor_id(), qdev->workqueue,
1966 &qdev->mpi_work, 0);
1967 work_done++;
1968 }
1969
1970 /*
1971 * Check the default queue and wake handler if active.
1972 */
1973 rx_ring = &qdev->rx_ring[0];
1974 if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) {
1975 QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n");
1976 ql_disable_completion_interrupt(qdev, intr_context->intr);
1977 queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue,
1978 &rx_ring->rx_work, 0);
1979 work_done++;
1980 }
1981
1982 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
1983 /*
1984 * Start the DPC for each active queue.
1985 */
1986 for (i = 1; i < qdev->rx_ring_count; i++) {
1987 rx_ring = &qdev->rx_ring[i];
1988 if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
1989 rx_ring->cnsmr_idx) {
1990 QPRINTK(qdev, INTR, INFO,
1991 "Waking handler for rx_ring[%d].\n", i);
1992 ql_disable_completion_interrupt(qdev,
1993 intr_context->
1994 intr);
1995 if (i < qdev->rss_ring_first_cq_id)
1996 queue_delayed_work_on(rx_ring->cpu,
1997 qdev->q_workqueue,
1998 &rx_ring->rx_work,
1999 0);
2000 else
2001 napi_schedule(&rx_ring->napi);
2002 work_done++;
2003 }
2004 }
2005 }
2006 ql_enable_completion_interrupt(qdev, intr_context->intr);
2007 return work_done ? IRQ_HANDLED : IRQ_NONE;
2008 }
2009
2010 static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
2011 {
2012
2013 if (skb_is_gso(skb)) {
2014 int err;
2015 if (skb_header_cloned(skb)) {
2016 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2017 if (err)
2018 return err;
2019 }
2020
2021 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
2022 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
2023 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
2024 mac_iocb_ptr->total_hdrs_len =
2025 cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
2026 mac_iocb_ptr->net_trans_offset =
2027 cpu_to_le16(skb_network_offset(skb) |
2028 skb_transport_offset(skb)
2029 << OB_MAC_TRANSPORT_HDR_SHIFT);
2030 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
2031 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
2032 if (likely(skb->protocol == htons(ETH_P_IP))) {
2033 struct iphdr *iph = ip_hdr(skb);
2034 iph->check = 0;
2035 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2036 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2037 iph->daddr, 0,
2038 IPPROTO_TCP,
2039 0);
2040 } else if (skb->protocol == htons(ETH_P_IPV6)) {
2041 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
2042 tcp_hdr(skb)->check =
2043 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2044 &ipv6_hdr(skb)->daddr,
2045 0, IPPROTO_TCP, 0);
2046 }
2047 return 1;
2048 }
2049 return 0;
2050 }
2051
2052 static void ql_hw_csum_setup(struct sk_buff *skb,
2053 struct ob_mac_tso_iocb_req *mac_iocb_ptr)
2054 {
2055 int len;
2056 struct iphdr *iph = ip_hdr(skb);
2057 __sum16 *check;
2058 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
2059 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
2060 mac_iocb_ptr->net_trans_offset =
2061 cpu_to_le16(skb_network_offset(skb) |
2062 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
2063
2064 mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2065 len = (ntohs(iph->tot_len) - (iph->ihl << 2));
2066 if (likely(iph->protocol == IPPROTO_TCP)) {
2067 check = &(tcp_hdr(skb)->check);
2068 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
2069 mac_iocb_ptr->total_hdrs_len =
2070 cpu_to_le16(skb_transport_offset(skb) +
2071 (tcp_hdr(skb)->doff << 2));
2072 } else {
2073 check = &(udp_hdr(skb)->check);
2074 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
2075 mac_iocb_ptr->total_hdrs_len =
2076 cpu_to_le16(skb_transport_offset(skb) +
2077 sizeof(struct udphdr));
2078 }
2079 *check = ~csum_tcpudp_magic(iph->saddr,
2080 iph->daddr, len, iph->protocol, 0);
2081 }
2082
2083 static int qlge_send(struct sk_buff *skb, struct net_device *ndev)
2084 {
2085 struct tx_ring_desc *tx_ring_desc;
2086 struct ob_mac_iocb_req *mac_iocb_ptr;
2087 struct ql_adapter *qdev = netdev_priv(ndev);
2088 int tso;
2089 struct tx_ring *tx_ring;
2090 u32 tx_ring_idx = (u32) skb->queue_mapping;
2091
2092 tx_ring = &qdev->tx_ring[tx_ring_idx];
2093
2094 if (skb_padto(skb, ETH_ZLEN))
2095 return NETDEV_TX_OK;
2096
2097 if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
2098 QPRINTK(qdev, TX_QUEUED, INFO,
2099 "%s: shutting down tx queue %d du to lack of resources.\n",
2100 __func__, tx_ring_idx);
2101 netif_stop_subqueue(ndev, tx_ring->wq_id);
2102 atomic_inc(&tx_ring->queue_stopped);
2103 return NETDEV_TX_BUSY;
2104 }
2105 tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
2106 mac_iocb_ptr = tx_ring_desc->queue_entry;
2107 memset((void *)mac_iocb_ptr, 0, sizeof(mac_iocb_ptr));
2108
2109 mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
2110 mac_iocb_ptr->tid = tx_ring_desc->index;
2111 /* We use the upper 32-bits to store the tx queue for this IO.
2112 * When we get the completion we can use it to establish the context.
2113 */
2114 mac_iocb_ptr->txq_idx = tx_ring_idx;
2115 tx_ring_desc->skb = skb;
2116
2117 mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
2118
2119 if (qdev->vlgrp && vlan_tx_tag_present(skb)) {
2120 QPRINTK(qdev, TX_QUEUED, DEBUG, "Adding a vlan tag %d.\n",
2121 vlan_tx_tag_get(skb));
2122 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
2123 mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
2124 }
2125 tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2126 if (tso < 0) {
2127 dev_kfree_skb_any(skb);
2128 return NETDEV_TX_OK;
2129 } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
2130 ql_hw_csum_setup(skb,
2131 (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2132 }
2133 if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) !=
2134 NETDEV_TX_OK) {
2135 QPRINTK(qdev, TX_QUEUED, ERR,
2136 "Could not map the segments.\n");
2137 return NETDEV_TX_BUSY;
2138 }
2139 QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
2140 tx_ring->prod_idx++;
2141 if (tx_ring->prod_idx == tx_ring->wq_len)
2142 tx_ring->prod_idx = 0;
2143 wmb();
2144
2145 ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
2146 QPRINTK(qdev, TX_QUEUED, DEBUG, "tx queued, slot %d, len %d\n",
2147 tx_ring->prod_idx, skb->len);
2148
2149 atomic_dec(&tx_ring->tx_count);
2150 return NETDEV_TX_OK;
2151 }
2152
2153 static void ql_free_shadow_space(struct ql_adapter *qdev)
2154 {
2155 if (qdev->rx_ring_shadow_reg_area) {
2156 pci_free_consistent(qdev->pdev,
2157 PAGE_SIZE,
2158 qdev->rx_ring_shadow_reg_area,
2159 qdev->rx_ring_shadow_reg_dma);
2160 qdev->rx_ring_shadow_reg_area = NULL;
2161 }
2162 if (qdev->tx_ring_shadow_reg_area) {
2163 pci_free_consistent(qdev->pdev,
2164 PAGE_SIZE,
2165 qdev->tx_ring_shadow_reg_area,
2166 qdev->tx_ring_shadow_reg_dma);
2167 qdev->tx_ring_shadow_reg_area = NULL;
2168 }
2169 }
2170
2171 static int ql_alloc_shadow_space(struct ql_adapter *qdev)
2172 {
2173 qdev->rx_ring_shadow_reg_area =
2174 pci_alloc_consistent(qdev->pdev,
2175 PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
2176 if (qdev->rx_ring_shadow_reg_area == NULL) {
2177 QPRINTK(qdev, IFUP, ERR,
2178 "Allocation of RX shadow space failed.\n");
2179 return -ENOMEM;
2180 }
2181 memset(qdev->rx_ring_shadow_reg_area, 0, PAGE_SIZE);
2182 qdev->tx_ring_shadow_reg_area =
2183 pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
2184 &qdev->tx_ring_shadow_reg_dma);
2185 if (qdev->tx_ring_shadow_reg_area == NULL) {
2186 QPRINTK(qdev, IFUP, ERR,
2187 "Allocation of TX shadow space failed.\n");
2188 goto err_wqp_sh_area;
2189 }
2190 memset(qdev->tx_ring_shadow_reg_area, 0, PAGE_SIZE);
2191 return 0;
2192
2193 err_wqp_sh_area:
2194 pci_free_consistent(qdev->pdev,
2195 PAGE_SIZE,
2196 qdev->rx_ring_shadow_reg_area,
2197 qdev->rx_ring_shadow_reg_dma);
2198 return -ENOMEM;
2199 }
2200
2201 static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2202 {
2203 struct tx_ring_desc *tx_ring_desc;
2204 int i;
2205 struct ob_mac_iocb_req *mac_iocb_ptr;
2206
2207 mac_iocb_ptr = tx_ring->wq_base;
2208 tx_ring_desc = tx_ring->q;
2209 for (i = 0; i < tx_ring->wq_len; i++) {
2210 tx_ring_desc->index = i;
2211 tx_ring_desc->skb = NULL;
2212 tx_ring_desc->queue_entry = mac_iocb_ptr;
2213 mac_iocb_ptr++;
2214 tx_ring_desc++;
2215 }
2216 atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2217 atomic_set(&tx_ring->queue_stopped, 0);
2218 }
2219
2220 static void ql_free_tx_resources(struct ql_adapter *qdev,
2221 struct tx_ring *tx_ring)
2222 {
2223 if (tx_ring->wq_base) {
2224 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2225 tx_ring->wq_base, tx_ring->wq_base_dma);
2226 tx_ring->wq_base = NULL;
2227 }
2228 kfree(tx_ring->q);
2229 tx_ring->q = NULL;
2230 }
2231
2232 static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2233 struct tx_ring *tx_ring)
2234 {
2235 tx_ring->wq_base =
2236 pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2237 &tx_ring->wq_base_dma);
2238
2239 if ((tx_ring->wq_base == NULL)
2240 || tx_ring->wq_base_dma & WQ_ADDR_ALIGN) {
2241 QPRINTK(qdev, IFUP, ERR, "tx_ring alloc failed.\n");
2242 return -ENOMEM;
2243 }
2244 tx_ring->q =
2245 kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2246 if (tx_ring->q == NULL)
2247 goto err;
2248
2249 return 0;
2250 err:
2251 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2252 tx_ring->wq_base, tx_ring->wq_base_dma);
2253 return -ENOMEM;
2254 }
2255
2256 static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2257 {
2258 int i;
2259 struct bq_desc *lbq_desc;
2260
2261 for (i = 0; i < rx_ring->lbq_len; i++) {
2262 lbq_desc = &rx_ring->lbq[i];
2263 if (lbq_desc->p.lbq_page) {
2264 pci_unmap_page(qdev->pdev,
2265 pci_unmap_addr(lbq_desc, mapaddr),
2266 pci_unmap_len(lbq_desc, maplen),
2267 PCI_DMA_FROMDEVICE);
2268
2269 put_page(lbq_desc->p.lbq_page);
2270 lbq_desc->p.lbq_page = NULL;
2271 }
2272 }
2273 }
2274
2275 static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2276 {
2277 int i;
2278 struct bq_desc *sbq_desc;
2279
2280 for (i = 0; i < rx_ring->sbq_len; i++) {
2281 sbq_desc = &rx_ring->sbq[i];
2282 if (sbq_desc == NULL) {
2283 QPRINTK(qdev, IFUP, ERR, "sbq_desc %d is NULL.\n", i);
2284 return;
2285 }
2286 if (sbq_desc->p.skb) {
2287 pci_unmap_single(qdev->pdev,
2288 pci_unmap_addr(sbq_desc, mapaddr),
2289 pci_unmap_len(sbq_desc, maplen),
2290 PCI_DMA_FROMDEVICE);
2291 dev_kfree_skb(sbq_desc->p.skb);
2292 sbq_desc->p.skb = NULL;
2293 }
2294 }
2295 }
2296
2297 /* Free all large and small rx buffers associated
2298 * with the completion queues for this device.
2299 */
2300 static void ql_free_rx_buffers(struct ql_adapter *qdev)
2301 {
2302 int i;
2303 struct rx_ring *rx_ring;
2304
2305 for (i = 0; i < qdev->rx_ring_count; i++) {
2306 rx_ring = &qdev->rx_ring[i];
2307 if (rx_ring->lbq)
2308 ql_free_lbq_buffers(qdev, rx_ring);
2309 if (rx_ring->sbq)
2310 ql_free_sbq_buffers(qdev, rx_ring);
2311 }
2312 }
2313
2314 static void ql_alloc_rx_buffers(struct ql_adapter *qdev)
2315 {
2316 struct rx_ring *rx_ring;
2317 int i;
2318
2319 for (i = 0; i < qdev->rx_ring_count; i++) {
2320 rx_ring = &qdev->rx_ring[i];
2321 if (rx_ring->type != TX_Q)
2322 ql_update_buffer_queues(qdev, rx_ring);
2323 }
2324 }
2325
2326 static void ql_init_lbq_ring(struct ql_adapter *qdev,
2327 struct rx_ring *rx_ring)
2328 {
2329 int i;
2330 struct bq_desc *lbq_desc;
2331 __le64 *bq = rx_ring->lbq_base;
2332
2333 memset(rx_ring->lbq, 0, rx_ring->lbq_len * sizeof(struct bq_desc));
2334 for (i = 0; i < rx_ring->lbq_len; i++) {
2335 lbq_desc = &rx_ring->lbq[i];
2336 memset(lbq_desc, 0, sizeof(*lbq_desc));
2337 lbq_desc->index = i;
2338 lbq_desc->addr = bq;
2339 bq++;
2340 }
2341 }
2342
2343 static void ql_init_sbq_ring(struct ql_adapter *qdev,
2344 struct rx_ring *rx_ring)
2345 {
2346 int i;
2347 struct bq_desc *sbq_desc;
2348 __le64 *bq = rx_ring->sbq_base;
2349
2350 memset(rx_ring->sbq, 0, rx_ring->sbq_len * sizeof(struct bq_desc));
2351 for (i = 0; i < rx_ring->sbq_len; i++) {
2352 sbq_desc = &rx_ring->sbq[i];
2353 memset(sbq_desc, 0, sizeof(*sbq_desc));
2354 sbq_desc->index = i;
2355 sbq_desc->addr = bq;
2356 bq++;
2357 }
2358 }
2359
2360 static void ql_free_rx_resources(struct ql_adapter *qdev,
2361 struct rx_ring *rx_ring)
2362 {
2363 /* Free the small buffer queue. */
2364 if (rx_ring->sbq_base) {
2365 pci_free_consistent(qdev->pdev,
2366 rx_ring->sbq_size,
2367 rx_ring->sbq_base, rx_ring->sbq_base_dma);
2368 rx_ring->sbq_base = NULL;
2369 }
2370
2371 /* Free the small buffer queue control blocks. */
2372 kfree(rx_ring->sbq);
2373 rx_ring->sbq = NULL;
2374
2375 /* Free the large buffer queue. */
2376 if (rx_ring->lbq_base) {
2377 pci_free_consistent(qdev->pdev,
2378 rx_ring->lbq_size,
2379 rx_ring->lbq_base, rx_ring->lbq_base_dma);
2380 rx_ring->lbq_base = NULL;
2381 }
2382
2383 /* Free the large buffer queue control blocks. */
2384 kfree(rx_ring->lbq);
2385 rx_ring->lbq = NULL;
2386
2387 /* Free the rx queue. */
2388 if (rx_ring->cq_base) {
2389 pci_free_consistent(qdev->pdev,
2390 rx_ring->cq_size,
2391 rx_ring->cq_base, rx_ring->cq_base_dma);
2392 rx_ring->cq_base = NULL;
2393 }
2394 }
2395
2396 /* Allocate queues and buffers for this completions queue based
2397 * on the values in the parameter structure. */
2398 static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2399 struct rx_ring *rx_ring)
2400 {
2401
2402 /*
2403 * Allocate the completion queue for this rx_ring.
2404 */
2405 rx_ring->cq_base =
2406 pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2407 &rx_ring->cq_base_dma);
2408
2409 if (rx_ring->cq_base == NULL) {
2410 QPRINTK(qdev, IFUP, ERR, "rx_ring alloc failed.\n");
2411 return -ENOMEM;
2412 }
2413
2414 if (rx_ring->sbq_len) {
2415 /*
2416 * Allocate small buffer queue.
2417 */
2418 rx_ring->sbq_base =
2419 pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
2420 &rx_ring->sbq_base_dma);
2421
2422 if (rx_ring->sbq_base == NULL) {
2423 QPRINTK(qdev, IFUP, ERR,
2424 "Small buffer queue allocation failed.\n");
2425 goto err_mem;
2426 }
2427
2428 /*
2429 * Allocate small buffer queue control blocks.
2430 */
2431 rx_ring->sbq =
2432 kmalloc(rx_ring->sbq_len * sizeof(struct bq_desc),
2433 GFP_KERNEL);
2434 if (rx_ring->sbq == NULL) {
2435 QPRINTK(qdev, IFUP, ERR,
2436 "Small buffer queue control block allocation failed.\n");
2437 goto err_mem;
2438 }
2439
2440 ql_init_sbq_ring(qdev, rx_ring);
2441 }
2442
2443 if (rx_ring->lbq_len) {
2444 /*
2445 * Allocate large buffer queue.
2446 */
2447 rx_ring->lbq_base =
2448 pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
2449 &rx_ring->lbq_base_dma);
2450
2451 if (rx_ring->lbq_base == NULL) {
2452 QPRINTK(qdev, IFUP, ERR,
2453 "Large buffer queue allocation failed.\n");
2454 goto err_mem;
2455 }
2456 /*
2457 * Allocate large buffer queue control blocks.
2458 */
2459 rx_ring->lbq =
2460 kmalloc(rx_ring->lbq_len * sizeof(struct bq_desc),
2461 GFP_KERNEL);
2462 if (rx_ring->lbq == NULL) {
2463 QPRINTK(qdev, IFUP, ERR,
2464 "Large buffer queue control block allocation failed.\n");
2465 goto err_mem;
2466 }
2467
2468 ql_init_lbq_ring(qdev, rx_ring);
2469 }
2470
2471 return 0;
2472
2473 err_mem:
2474 ql_free_rx_resources(qdev, rx_ring);
2475 return -ENOMEM;
2476 }
2477
2478 static void ql_tx_ring_clean(struct ql_adapter *qdev)
2479 {
2480 struct tx_ring *tx_ring;
2481 struct tx_ring_desc *tx_ring_desc;
2482 int i, j;
2483
2484 /*
2485 * Loop through all queues and free
2486 * any resources.
2487 */
2488 for (j = 0; j < qdev->tx_ring_count; j++) {
2489 tx_ring = &qdev->tx_ring[j];
2490 for (i = 0; i < tx_ring->wq_len; i++) {
2491 tx_ring_desc = &tx_ring->q[i];
2492 if (tx_ring_desc && tx_ring_desc->skb) {
2493 QPRINTK(qdev, IFDOWN, ERR,
2494 "Freeing lost SKB %p, from queue %d, index %d.\n",
2495 tx_ring_desc->skb, j,
2496 tx_ring_desc->index);
2497 ql_unmap_send(qdev, tx_ring_desc,
2498 tx_ring_desc->map_cnt);
2499 dev_kfree_skb(tx_ring_desc->skb);
2500 tx_ring_desc->skb = NULL;
2501 }
2502 }
2503 }
2504 }
2505
2506 static void ql_free_mem_resources(struct ql_adapter *qdev)
2507 {
2508 int i;
2509
2510 for (i = 0; i < qdev->tx_ring_count; i++)
2511 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
2512 for (i = 0; i < qdev->rx_ring_count; i++)
2513 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
2514 ql_free_shadow_space(qdev);
2515 }
2516
2517 static int ql_alloc_mem_resources(struct ql_adapter *qdev)
2518 {
2519 int i;
2520
2521 /* Allocate space for our shadow registers and such. */
2522 if (ql_alloc_shadow_space(qdev))
2523 return -ENOMEM;
2524
2525 for (i = 0; i < qdev->rx_ring_count; i++) {
2526 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
2527 QPRINTK(qdev, IFUP, ERR,
2528 "RX resource allocation failed.\n");
2529 goto err_mem;
2530 }
2531 }
2532 /* Allocate tx queue resources */
2533 for (i = 0; i < qdev->tx_ring_count; i++) {
2534 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
2535 QPRINTK(qdev, IFUP, ERR,
2536 "TX resource allocation failed.\n");
2537 goto err_mem;
2538 }
2539 }
2540 return 0;
2541
2542 err_mem:
2543 ql_free_mem_resources(qdev);
2544 return -ENOMEM;
2545 }
2546
2547 /* Set up the rx ring control block and pass it to the chip.
2548 * The control block is defined as
2549 * "Completion Queue Initialization Control Block", or cqicb.
2550 */
2551 static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2552 {
2553 struct cqicb *cqicb = &rx_ring->cqicb;
2554 void *shadow_reg = qdev->rx_ring_shadow_reg_area +
2555 (rx_ring->cq_id * RX_RING_SHADOW_SPACE);
2556 u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
2557 (rx_ring->cq_id * RX_RING_SHADOW_SPACE);
2558 void __iomem *doorbell_area =
2559 qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
2560 int err = 0;
2561 u16 bq_len;
2562 u64 tmp;
2563 __le64 *base_indirect_ptr;
2564 int page_entries;
2565
2566 /* Set up the shadow registers for this ring. */
2567 rx_ring->prod_idx_sh_reg = shadow_reg;
2568 rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
2569 shadow_reg += sizeof(u64);
2570 shadow_reg_dma += sizeof(u64);
2571 rx_ring->lbq_base_indirect = shadow_reg;
2572 rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
2573 shadow_reg += (sizeof(u64) * MAX_DB_PAGES_PER_BQ(rx_ring->lbq_len));
2574 shadow_reg_dma += (sizeof(u64) * MAX_DB_PAGES_PER_BQ(rx_ring->lbq_len));
2575 rx_ring->sbq_base_indirect = shadow_reg;
2576 rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
2577
2578 /* PCI doorbell mem area + 0x00 for consumer index register */
2579 rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
2580 rx_ring->cnsmr_idx = 0;
2581 rx_ring->curr_entry = rx_ring->cq_base;
2582
2583 /* PCI doorbell mem area + 0x04 for valid register */
2584 rx_ring->valid_db_reg = doorbell_area + 0x04;
2585
2586 /* PCI doorbell mem area + 0x18 for large buffer consumer */
2587 rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
2588
2589 /* PCI doorbell mem area + 0x1c */
2590 rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
2591
2592 memset((void *)cqicb, 0, sizeof(struct cqicb));
2593 cqicb->msix_vect = rx_ring->irq;
2594
2595 bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len;
2596 cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT);
2597
2598 cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma);
2599
2600 cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma);
2601
2602 /*
2603 * Set up the control block load flags.
2604 */
2605 cqicb->flags = FLAGS_LC | /* Load queue base address */
2606 FLAGS_LV | /* Load MSI-X vector */
2607 FLAGS_LI; /* Load irq delay values */
2608 if (rx_ring->lbq_len) {
2609 cqicb->flags |= FLAGS_LL; /* Load lbq values */
2610 tmp = (u64)rx_ring->lbq_base_dma;;
2611 base_indirect_ptr = (__le64 *) rx_ring->lbq_base_indirect;
2612 page_entries = 0;
2613 do {
2614 *base_indirect_ptr = cpu_to_le64(tmp);
2615 tmp += DB_PAGE_SIZE;
2616 base_indirect_ptr++;
2617 page_entries++;
2618 } while (page_entries < MAX_DB_PAGES_PER_BQ(rx_ring->lbq_len));
2619 cqicb->lbq_addr =
2620 cpu_to_le64(rx_ring->lbq_base_indirect_dma);
2621 bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 :
2622 (u16) rx_ring->lbq_buf_size;
2623 cqicb->lbq_buf_size = cpu_to_le16(bq_len);
2624 bq_len = (rx_ring->lbq_len == 65536) ? 0 :
2625 (u16) rx_ring->lbq_len;
2626 cqicb->lbq_len = cpu_to_le16(bq_len);
2627 rx_ring->lbq_prod_idx = 0;
2628 rx_ring->lbq_curr_idx = 0;
2629 rx_ring->lbq_clean_idx = 0;
2630 rx_ring->lbq_free_cnt = rx_ring->lbq_len;
2631 }
2632 if (rx_ring->sbq_len) {
2633 cqicb->flags |= FLAGS_LS; /* Load sbq values */
2634 tmp = (u64)rx_ring->sbq_base_dma;;
2635 base_indirect_ptr = (__le64 *) rx_ring->sbq_base_indirect;
2636 page_entries = 0;
2637 do {
2638 *base_indirect_ptr = cpu_to_le64(tmp);
2639 tmp += DB_PAGE_SIZE;
2640 base_indirect_ptr++;
2641 page_entries++;
2642 } while (page_entries < MAX_DB_PAGES_PER_BQ(rx_ring->sbq_len));
2643 cqicb->sbq_addr =
2644 cpu_to_le64(rx_ring->sbq_base_indirect_dma);
2645 cqicb->sbq_buf_size =
2646 cpu_to_le16((u16)(rx_ring->sbq_buf_size/2));
2647 bq_len = (rx_ring->sbq_len == 65536) ? 0 :
2648 (u16) rx_ring->sbq_len;
2649 cqicb->sbq_len = cpu_to_le16(bq_len);
2650 rx_ring->sbq_prod_idx = 0;
2651 rx_ring->sbq_curr_idx = 0;
2652 rx_ring->sbq_clean_idx = 0;
2653 rx_ring->sbq_free_cnt = rx_ring->sbq_len;
2654 }
2655 switch (rx_ring->type) {
2656 case TX_Q:
2657 /* If there's only one interrupt, then we use
2658 * worker threads to process the outbound
2659 * completion handling rx_rings. We do this so
2660 * they can be run on multiple CPUs. There is
2661 * room to play with this more where we would only
2662 * run in a worker if there are more than x number
2663 * of outbound completions on the queue and more
2664 * than one queue active. Some threshold that
2665 * would indicate a benefit in spite of the cost
2666 * of a context switch.
2667 * If there's more than one interrupt, then the
2668 * outbound completions are processed in the ISR.
2669 */
2670 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags))
2671 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2672 else {
2673 /* With all debug warnings on we see a WARN_ON message
2674 * when we free the skb in the interrupt context.
2675 */
2676 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2677 }
2678 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
2679 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
2680 break;
2681 case DEFAULT_Q:
2682 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_rx_clean);
2683 cqicb->irq_delay = 0;
2684 cqicb->pkt_delay = 0;
2685 break;
2686 case RX_Q:
2687 /* Inbound completion handling rx_rings run in
2688 * separate NAPI contexts.
2689 */
2690 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
2691 64);
2692 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
2693 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
2694 break;
2695 default:
2696 QPRINTK(qdev, IFUP, DEBUG, "Invalid rx_ring->type = %d.\n",
2697 rx_ring->type);
2698 }
2699 QPRINTK(qdev, IFUP, DEBUG, "Initializing rx work queue.\n");
2700 err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
2701 CFG_LCQ, rx_ring->cq_id);
2702 if (err) {
2703 QPRINTK(qdev, IFUP, ERR, "Failed to load CQICB.\n");
2704 return err;
2705 }
2706 return err;
2707 }
2708
2709 static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2710 {
2711 struct wqicb *wqicb = (struct wqicb *)tx_ring;
2712 void __iomem *doorbell_area =
2713 qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
2714 void *shadow_reg = qdev->tx_ring_shadow_reg_area +
2715 (tx_ring->wq_id * sizeof(u64));
2716 u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
2717 (tx_ring->wq_id * sizeof(u64));
2718 int err = 0;
2719
2720 /*
2721 * Assign doorbell registers for this tx_ring.
2722 */
2723 /* TX PCI doorbell mem area for tx producer index */
2724 tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
2725 tx_ring->prod_idx = 0;
2726 /* TX PCI doorbell mem area + 0x04 */
2727 tx_ring->valid_db_reg = doorbell_area + 0x04;
2728
2729 /*
2730 * Assign shadow registers for this tx_ring.
2731 */
2732 tx_ring->cnsmr_idx_sh_reg = shadow_reg;
2733 tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
2734
2735 wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
2736 wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
2737 Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
2738 wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
2739 wqicb->rid = 0;
2740 wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma);
2741
2742 wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma);
2743
2744 ql_init_tx_ring(qdev, tx_ring);
2745
2746 err = ql_write_cfg(qdev, wqicb, sizeof(wqicb), CFG_LRQ,
2747 (u16) tx_ring->wq_id);
2748 if (err) {
2749 QPRINTK(qdev, IFUP, ERR, "Failed to load tx_ring.\n");
2750 return err;
2751 }
2752 QPRINTK(qdev, IFUP, DEBUG, "Successfully loaded WQICB.\n");
2753 return err;
2754 }
2755
2756 static void ql_disable_msix(struct ql_adapter *qdev)
2757 {
2758 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2759 pci_disable_msix(qdev->pdev);
2760 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
2761 kfree(qdev->msi_x_entry);
2762 qdev->msi_x_entry = NULL;
2763 } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
2764 pci_disable_msi(qdev->pdev);
2765 clear_bit(QL_MSI_ENABLED, &qdev->flags);
2766 }
2767 }
2768
2769 static void ql_enable_msix(struct ql_adapter *qdev)
2770 {
2771 int i;
2772
2773 qdev->intr_count = 1;
2774 /* Get the MSIX vectors. */
2775 if (irq_type == MSIX_IRQ) {
2776 /* Try to alloc space for the msix struct,
2777 * if it fails then go to MSI/legacy.
2778 */
2779 qdev->msi_x_entry = kcalloc(qdev->rx_ring_count,
2780 sizeof(struct msix_entry),
2781 GFP_KERNEL);
2782 if (!qdev->msi_x_entry) {
2783 irq_type = MSI_IRQ;
2784 goto msi;
2785 }
2786
2787 for (i = 0; i < qdev->rx_ring_count; i++)
2788 qdev->msi_x_entry[i].entry = i;
2789
2790 if (!pci_enable_msix
2791 (qdev->pdev, qdev->msi_x_entry, qdev->rx_ring_count)) {
2792 set_bit(QL_MSIX_ENABLED, &qdev->flags);
2793 qdev->intr_count = qdev->rx_ring_count;
2794 QPRINTK(qdev, IFUP, DEBUG,
2795 "MSI-X Enabled, got %d vectors.\n",
2796 qdev->intr_count);
2797 return;
2798 } else {
2799 kfree(qdev->msi_x_entry);
2800 qdev->msi_x_entry = NULL;
2801 QPRINTK(qdev, IFUP, WARNING,
2802 "MSI-X Enable failed, trying MSI.\n");
2803 irq_type = MSI_IRQ;
2804 }
2805 }
2806 msi:
2807 if (irq_type == MSI_IRQ) {
2808 if (!pci_enable_msi(qdev->pdev)) {
2809 set_bit(QL_MSI_ENABLED, &qdev->flags);
2810 QPRINTK(qdev, IFUP, INFO,
2811 "Running with MSI interrupts.\n");
2812 return;
2813 }
2814 }
2815 irq_type = LEG_IRQ;
2816 QPRINTK(qdev, IFUP, DEBUG, "Running with legacy interrupts.\n");
2817 }
2818
2819 /*
2820 * Here we build the intr_context structures based on
2821 * our rx_ring count and intr vector count.
2822 * The intr_context structure is used to hook each vector
2823 * to possibly different handlers.
2824 */
2825 static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
2826 {
2827 int i = 0;
2828 struct intr_context *intr_context = &qdev->intr_context[0];
2829
2830 ql_enable_msix(qdev);
2831
2832 if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
2833 /* Each rx_ring has it's
2834 * own intr_context since we have separate
2835 * vectors for each queue.
2836 * This only true when MSI-X is enabled.
2837 */
2838 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2839 qdev->rx_ring[i].irq = i;
2840 intr_context->intr = i;
2841 intr_context->qdev = qdev;
2842 /*
2843 * We set up each vectors enable/disable/read bits so
2844 * there's no bit/mask calculations in the critical path.
2845 */
2846 intr_context->intr_en_mask =
2847 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2848 INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
2849 | i;
2850 intr_context->intr_dis_mask =
2851 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2852 INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
2853 INTR_EN_IHD | i;
2854 intr_context->intr_read_mask =
2855 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2856 INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
2857 i;
2858
2859 if (i == 0) {
2860 /*
2861 * Default queue handles bcast/mcast plus
2862 * async events. Needs buffers.
2863 */
2864 intr_context->handler = qlge_isr;
2865 sprintf(intr_context->name, "%s-default-queue",
2866 qdev->ndev->name);
2867 } else if (i < qdev->rss_ring_first_cq_id) {
2868 /*
2869 * Outbound queue is for outbound completions only.
2870 */
2871 intr_context->handler = qlge_msix_tx_isr;
2872 sprintf(intr_context->name, "%s-tx-%d",
2873 qdev->ndev->name, i);
2874 } else {
2875 /*
2876 * Inbound queues handle unicast frames only.
2877 */
2878 intr_context->handler = qlge_msix_rx_isr;
2879 sprintf(intr_context->name, "%s-rx-%d",
2880 qdev->ndev->name, i);
2881 }
2882 }
2883 } else {
2884 /*
2885 * All rx_rings use the same intr_context since
2886 * there is only one vector.
2887 */
2888 intr_context->intr = 0;
2889 intr_context->qdev = qdev;
2890 /*
2891 * We set up each vectors enable/disable/read bits so
2892 * there's no bit/mask calculations in the critical path.
2893 */
2894 intr_context->intr_en_mask =
2895 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
2896 intr_context->intr_dis_mask =
2897 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2898 INTR_EN_TYPE_DISABLE;
2899 intr_context->intr_read_mask =
2900 INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
2901 /*
2902 * Single interrupt means one handler for all rings.
2903 */
2904 intr_context->handler = qlge_isr;
2905 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
2906 for (i = 0; i < qdev->rx_ring_count; i++)
2907 qdev->rx_ring[i].irq = 0;
2908 }
2909 }
2910
2911 static void ql_free_irq(struct ql_adapter *qdev)
2912 {
2913 int i;
2914 struct intr_context *intr_context = &qdev->intr_context[0];
2915
2916 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2917 if (intr_context->hooked) {
2918 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2919 free_irq(qdev->msi_x_entry[i].vector,
2920 &qdev->rx_ring[i]);
2921 QPRINTK(qdev, IFDOWN, DEBUG,
2922 "freeing msix interrupt %d.\n", i);
2923 } else {
2924 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
2925 QPRINTK(qdev, IFDOWN, DEBUG,
2926 "freeing msi interrupt %d.\n", i);
2927 }
2928 }
2929 }
2930 ql_disable_msix(qdev);
2931 }
2932
2933 static int ql_request_irq(struct ql_adapter *qdev)
2934 {
2935 int i;
2936 int status = 0;
2937 struct pci_dev *pdev = qdev->pdev;
2938 struct intr_context *intr_context = &qdev->intr_context[0];
2939
2940 ql_resolve_queues_to_irqs(qdev);
2941
2942 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2943 atomic_set(&intr_context->irq_cnt, 0);
2944 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2945 status = request_irq(qdev->msi_x_entry[i].vector,
2946 intr_context->handler,
2947 0,
2948 intr_context->name,
2949 &qdev->rx_ring[i]);
2950 if (status) {
2951 QPRINTK(qdev, IFUP, ERR,
2952 "Failed request for MSIX interrupt %d.\n",
2953 i);
2954 goto err_irq;
2955 } else {
2956 QPRINTK(qdev, IFUP, DEBUG,
2957 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2958 i,
2959 qdev->rx_ring[i].type ==
2960 DEFAULT_Q ? "DEFAULT_Q" : "",
2961 qdev->rx_ring[i].type ==
2962 TX_Q ? "TX_Q" : "",
2963 qdev->rx_ring[i].type ==
2964 RX_Q ? "RX_Q" : "", intr_context->name);
2965 }
2966 } else {
2967 QPRINTK(qdev, IFUP, DEBUG,
2968 "trying msi or legacy interrupts.\n");
2969 QPRINTK(qdev, IFUP, DEBUG,
2970 "%s: irq = %d.\n", __func__, pdev->irq);
2971 QPRINTK(qdev, IFUP, DEBUG,
2972 "%s: context->name = %s.\n", __func__,
2973 intr_context->name);
2974 QPRINTK(qdev, IFUP, DEBUG,
2975 "%s: dev_id = 0x%p.\n", __func__,
2976 &qdev->rx_ring[0]);
2977 status =
2978 request_irq(pdev->irq, qlge_isr,
2979 test_bit(QL_MSI_ENABLED,
2980 &qdev->
2981 flags) ? 0 : IRQF_SHARED,
2982 intr_context->name, &qdev->rx_ring[0]);
2983 if (status)
2984 goto err_irq;
2985
2986 QPRINTK(qdev, IFUP, ERR,
2987 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2988 i,
2989 qdev->rx_ring[0].type ==
2990 DEFAULT_Q ? "DEFAULT_Q" : "",
2991 qdev->rx_ring[0].type == TX_Q ? "TX_Q" : "",
2992 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
2993 intr_context->name);
2994 }
2995 intr_context->hooked = 1;
2996 }
2997 return status;
2998 err_irq:
2999 QPRINTK(qdev, IFUP, ERR, "Failed to get the interrupts!!!/n");
3000 ql_free_irq(qdev);
3001 return status;
3002 }
3003
3004 static int ql_start_rss(struct ql_adapter *qdev)
3005 {
3006 struct ricb *ricb = &qdev->ricb;
3007 int status = 0;
3008 int i;
3009 u8 *hash_id = (u8 *) ricb->hash_cq_id;
3010
3011 memset((void *)ricb, 0, sizeof(ricb));
3012
3013 ricb->base_cq = qdev->rss_ring_first_cq_id | RSS_L4K;
3014 ricb->flags =
3015 (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RI4 | RSS_RI6 | RSS_RT4 |
3016 RSS_RT6);
3017 ricb->mask = cpu_to_le16(qdev->rss_ring_count - 1);
3018
3019 /*
3020 * Fill out the Indirection Table.
3021 */
3022 for (i = 0; i < 256; i++)
3023 hash_id[i] = i & (qdev->rss_ring_count - 1);
3024
3025 /*
3026 * Random values for the IPv6 and IPv4 Hash Keys.
3027 */
3028 get_random_bytes((void *)&ricb->ipv6_hash_key[0], 40);
3029 get_random_bytes((void *)&ricb->ipv4_hash_key[0], 16);
3030
3031 QPRINTK(qdev, IFUP, DEBUG, "Initializing RSS.\n");
3032
3033 status = ql_write_cfg(qdev, ricb, sizeof(ricb), CFG_LR, 0);
3034 if (status) {
3035 QPRINTK(qdev, IFUP, ERR, "Failed to load RICB.\n");
3036 return status;
3037 }
3038 QPRINTK(qdev, IFUP, DEBUG, "Successfully loaded RICB.\n");
3039 return status;
3040 }
3041
3042 /* Initialize the frame-to-queue routing. */
3043 static int ql_route_initialize(struct ql_adapter *qdev)
3044 {
3045 int status = 0;
3046 int i;
3047
3048 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3049 if (status)
3050 return status;
3051
3052 /* Clear all the entries in the routing table. */
3053 for (i = 0; i < 16; i++) {
3054 status = ql_set_routing_reg(qdev, i, 0, 0);
3055 if (status) {
3056 QPRINTK(qdev, IFUP, ERR,
3057 "Failed to init routing register for CAM packets.\n");
3058 goto exit;
3059 }
3060 }
3061
3062 status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1);
3063 if (status) {
3064 QPRINTK(qdev, IFUP, ERR,
3065 "Failed to init routing register for error packets.\n");
3066 goto exit;
3067 }
3068 status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
3069 if (status) {
3070 QPRINTK(qdev, IFUP, ERR,
3071 "Failed to init routing register for broadcast packets.\n");
3072 goto exit;
3073 }
3074 /* If we have more than one inbound queue, then turn on RSS in the
3075 * routing block.
3076 */
3077 if (qdev->rss_ring_count > 1) {
3078 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
3079 RT_IDX_RSS_MATCH, 1);
3080 if (status) {
3081 QPRINTK(qdev, IFUP, ERR,
3082 "Failed to init routing register for MATCH RSS packets.\n");
3083 goto exit;
3084 }
3085 }
3086
3087 status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
3088 RT_IDX_CAM_HIT, 1);
3089 if (status)
3090 QPRINTK(qdev, IFUP, ERR,
3091 "Failed to init routing register for CAM packets.\n");
3092 exit:
3093 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3094 return status;
3095 }
3096
3097 int ql_cam_route_initialize(struct ql_adapter *qdev)
3098 {
3099 int status;
3100
3101 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3102 if (status)
3103 return status;
3104 status = ql_set_mac_addr_reg(qdev, (u8 *) qdev->ndev->perm_addr,
3105 MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
3106 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3107 if (status) {
3108 QPRINTK(qdev, IFUP, ERR, "Failed to init mac address.\n");
3109 return status;
3110 }
3111
3112 status = ql_route_initialize(qdev);
3113 if (status)
3114 QPRINTK(qdev, IFUP, ERR, "Failed to init routing table.\n");
3115
3116 return status;
3117 }
3118
3119 static int ql_adapter_initialize(struct ql_adapter *qdev)
3120 {
3121 u32 value, mask;
3122 int i;
3123 int status = 0;
3124
3125 /*
3126 * Set up the System register to halt on errors.
3127 */
3128 value = SYS_EFE | SYS_FAE;
3129 mask = value << 16;
3130 ql_write32(qdev, SYS, mask | value);
3131
3132 /* Set the default queue, and VLAN behavior. */
3133 value = NIC_RCV_CFG_DFQ | NIC_RCV_CFG_RV;
3134 mask = NIC_RCV_CFG_DFQ_MASK | (NIC_RCV_CFG_RV << 16);
3135 ql_write32(qdev, NIC_RCV_CFG, (mask | value));
3136
3137 /* Set the MPI interrupt to enabled. */
3138 ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
3139
3140 /* Enable the function, set pagesize, enable error checking. */
3141 value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
3142 FSC_EC | FSC_VM_PAGE_4K | FSC_SH;
3143
3144 /* Set/clear header splitting. */
3145 mask = FSC_VM_PAGESIZE_MASK |
3146 FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
3147 ql_write32(qdev, FSC, mask | value);
3148
3149 ql_write32(qdev, SPLT_HDR, SPLT_HDR_EP |
3150 min(SMALL_BUFFER_SIZE, MAX_SPLIT_SIZE));
3151
3152 /* Start up the rx queues. */
3153 for (i = 0; i < qdev->rx_ring_count; i++) {
3154 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
3155 if (status) {
3156 QPRINTK(qdev, IFUP, ERR,
3157 "Failed to start rx ring[%d].\n", i);
3158 return status;
3159 }
3160 }
3161
3162 /* If there is more than one inbound completion queue
3163 * then download a RICB to configure RSS.
3164 */
3165 if (qdev->rss_ring_count > 1) {
3166 status = ql_start_rss(qdev);
3167 if (status) {
3168 QPRINTK(qdev, IFUP, ERR, "Failed to start RSS.\n");
3169 return status;
3170 }
3171 }
3172
3173 /* Start up the tx queues. */
3174 for (i = 0; i < qdev->tx_ring_count; i++) {
3175 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3176 if (status) {
3177 QPRINTK(qdev, IFUP, ERR,
3178 "Failed to start tx ring[%d].\n", i);
3179 return status;
3180 }
3181 }
3182
3183 /* Initialize the port and set the max framesize. */
3184 status = qdev->nic_ops->port_initialize(qdev);
3185 if (status) {
3186 QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
3187 return status;
3188 }
3189
3190 /* Set up the MAC address and frame routing filter. */
3191 status = ql_cam_route_initialize(qdev);
3192 if (status) {
3193 QPRINTK(qdev, IFUP, ERR,
3194 "Failed to init CAM/Routing tables.\n");
3195 return status;
3196 }
3197
3198 /* Start NAPI for the RSS queues. */
3199 for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) {
3200 QPRINTK(qdev, IFUP, DEBUG, "Enabling NAPI for rx_ring[%d].\n",
3201 i);
3202 napi_enable(&qdev->rx_ring[i].napi);
3203 }
3204
3205 return status;
3206 }
3207
3208 /* Issue soft reset to chip. */
3209 static int ql_adapter_reset(struct ql_adapter *qdev)
3210 {
3211 u32 value;
3212 int status = 0;
3213 unsigned long end_jiffies = jiffies +
3214 max((unsigned long)1, usecs_to_jiffies(30));
3215
3216 ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3217
3218 do {
3219 value = ql_read32(qdev, RST_FO);
3220 if ((value & RST_FO_FR) == 0)
3221 break;
3222 cpu_relax();
3223 } while (time_before(jiffies, end_jiffies));
3224
3225 if (value & RST_FO_FR) {
3226 QPRINTK(qdev, IFDOWN, ERR,
3227 "ETIMEDOUT!!! errored out of resetting the chip!\n");
3228 status = -ETIMEDOUT;
3229 }
3230
3231 return status;
3232 }
3233
3234 static void ql_display_dev_info(struct net_device *ndev)
3235 {
3236 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3237
3238 QPRINTK(qdev, PROBE, INFO,
3239 "Function #%d, Port %d, NIC Roll %d, NIC Rev = %d, "
3240 "XG Roll = %d, XG Rev = %d.\n",
3241 qdev->func,
3242 qdev->port,
3243 qdev->chip_rev_id & 0x0000000f,
3244 qdev->chip_rev_id >> 4 & 0x0000000f,
3245 qdev->chip_rev_id >> 8 & 0x0000000f,
3246 qdev->chip_rev_id >> 12 & 0x0000000f);
3247 QPRINTK(qdev, PROBE, INFO, "MAC address %pM\n", ndev->dev_addr);
3248 }
3249
3250 static int ql_adapter_down(struct ql_adapter *qdev)
3251 {
3252 int i, status = 0;
3253 struct rx_ring *rx_ring;
3254
3255 netif_carrier_off(qdev->ndev);
3256
3257 /* Don't kill the reset worker thread if we
3258 * are in the process of recovery.
3259 */
3260 if (test_bit(QL_ADAPTER_UP, &qdev->flags))
3261 cancel_delayed_work_sync(&qdev->asic_reset_work);
3262 cancel_delayed_work_sync(&qdev->mpi_reset_work);
3263 cancel_delayed_work_sync(&qdev->mpi_work);
3264 cancel_delayed_work_sync(&qdev->mpi_idc_work);
3265 cancel_delayed_work_sync(&qdev->mpi_port_cfg_work);
3266
3267 /* The default queue at index 0 is always processed in
3268 * a workqueue.
3269 */
3270 cancel_delayed_work_sync(&qdev->rx_ring[0].rx_work);
3271
3272 /* The rest of the rx_rings are processed in
3273 * a workqueue only if it's a single interrupt
3274 * environment (MSI/Legacy).
3275 */
3276 for (i = 1; i < qdev->rx_ring_count; i++) {
3277 rx_ring = &qdev->rx_ring[i];
3278 /* Only the RSS rings use NAPI on multi irq
3279 * environment. Outbound completion processing
3280 * is done in interrupt context.
3281 */
3282 if (i >= qdev->rss_ring_first_cq_id) {
3283 napi_disable(&rx_ring->napi);
3284 } else {
3285 cancel_delayed_work_sync(&rx_ring->rx_work);
3286 }
3287 }
3288
3289 clear_bit(QL_ADAPTER_UP, &qdev->flags);
3290
3291 ql_disable_interrupts(qdev);
3292
3293 ql_tx_ring_clean(qdev);
3294
3295 /* Call netif_napi_del() from common point.
3296 */
3297 for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++)
3298 netif_napi_del(&qdev->rx_ring[i].napi);
3299
3300 ql_free_rx_buffers(qdev);
3301
3302 spin_lock(&qdev->hw_lock);
3303 status = ql_adapter_reset(qdev);
3304 if (status)
3305 QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n",
3306 qdev->func);
3307 spin_unlock(&qdev->hw_lock);
3308 return status;
3309 }
3310
3311 static int ql_adapter_up(struct ql_adapter *qdev)
3312 {
3313 int err = 0;
3314
3315 err = ql_adapter_initialize(qdev);
3316 if (err) {
3317 QPRINTK(qdev, IFUP, INFO, "Unable to initialize adapter.\n");
3318 goto err_init;
3319 }
3320 set_bit(QL_ADAPTER_UP, &qdev->flags);
3321 ql_alloc_rx_buffers(qdev);
3322 if ((ql_read32(qdev, STS) & qdev->port_init))
3323 netif_carrier_on(qdev->ndev);
3324 ql_enable_interrupts(qdev);
3325 ql_enable_all_completion_interrupts(qdev);
3326 netif_tx_start_all_queues(qdev->ndev);
3327
3328 return 0;
3329 err_init:
3330 ql_adapter_reset(qdev);
3331 return err;
3332 }
3333
3334 static void ql_release_adapter_resources(struct ql_adapter *qdev)
3335 {
3336 ql_free_mem_resources(qdev);
3337 ql_free_irq(qdev);
3338 }
3339
3340 static int ql_get_adapter_resources(struct ql_adapter *qdev)
3341 {
3342 int status = 0;
3343
3344 if (ql_alloc_mem_resources(qdev)) {
3345 QPRINTK(qdev, IFUP, ERR, "Unable to allocate memory.\n");
3346 return -ENOMEM;
3347 }
3348 status = ql_request_irq(qdev);
3349 if (status)
3350 goto err_irq;
3351 return status;
3352 err_irq:
3353 ql_free_mem_resources(qdev);
3354 return status;
3355 }
3356
3357 static int qlge_close(struct net_device *ndev)
3358 {
3359 struct ql_adapter *qdev = netdev_priv(ndev);
3360
3361 /*
3362 * Wait for device to recover from a reset.
3363 * (Rarely happens, but possible.)
3364 */
3365 while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3366 msleep(1);
3367 ql_adapter_down(qdev);
3368 ql_release_adapter_resources(qdev);
3369 return 0;
3370 }
3371
3372 static int ql_configure_rings(struct ql_adapter *qdev)
3373 {
3374 int i;
3375 struct rx_ring *rx_ring;
3376 struct tx_ring *tx_ring;
3377 int cpu_cnt = num_online_cpus();
3378
3379 /*
3380 * For each processor present we allocate one
3381 * rx_ring for outbound completions, and one
3382 * rx_ring for inbound completions. Plus there is
3383 * always the one default queue. For the CPU
3384 * counts we end up with the following rx_rings:
3385 * rx_ring count =
3386 * one default queue +
3387 * (CPU count * outbound completion rx_ring) +
3388 * (CPU count * inbound (RSS) completion rx_ring)
3389 * To keep it simple we limit the total number of
3390 * queues to < 32, so we truncate CPU to 8.
3391 * This limitation can be removed when requested.
3392 */
3393
3394 if (cpu_cnt > MAX_CPUS)
3395 cpu_cnt = MAX_CPUS;
3396
3397 /*
3398 * rx_ring[0] is always the default queue.
3399 */
3400 /* Allocate outbound completion ring for each CPU. */
3401 qdev->tx_ring_count = cpu_cnt;
3402 /* Allocate inbound completion (RSS) ring for each CPU. */
3403 qdev->rss_ring_count = cpu_cnt;
3404 /* cq_id for the first inbound ring handler. */
3405 qdev->rss_ring_first_cq_id = cpu_cnt + 1;
3406 /*
3407 * qdev->rx_ring_count:
3408 * Total number of rx_rings. This includes the one
3409 * default queue, a number of outbound completion
3410 * handler rx_rings, and the number of inbound
3411 * completion handler rx_rings.
3412 */
3413 qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count + 1;
3414
3415 for (i = 0; i < qdev->tx_ring_count; i++) {
3416 tx_ring = &qdev->tx_ring[i];
3417 memset((void *)tx_ring, 0, sizeof(tx_ring));
3418 tx_ring->qdev = qdev;
3419 tx_ring->wq_id = i;
3420 tx_ring->wq_len = qdev->tx_ring_size;
3421 tx_ring->wq_size =
3422 tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
3423
3424 /*
3425 * The completion queue ID for the tx rings start
3426 * immediately after the default Q ID, which is zero.
3427 */
3428 tx_ring->cq_id = i + 1;
3429 }
3430
3431 for (i = 0; i < qdev->rx_ring_count; i++) {
3432 rx_ring = &qdev->rx_ring[i];
3433 memset((void *)rx_ring, 0, sizeof(rx_ring));
3434 rx_ring->qdev = qdev;
3435 rx_ring->cq_id = i;
3436 rx_ring->cpu = i % cpu_cnt; /* CPU to run handler on. */
3437 if (i == 0) { /* Default queue at index 0. */
3438 /*
3439 * Default queue handles bcast/mcast plus
3440 * async events. Needs buffers.
3441 */
3442 rx_ring->cq_len = qdev->rx_ring_size;
3443 rx_ring->cq_size =
3444 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3445 rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3446 rx_ring->lbq_size =
3447 rx_ring->lbq_len * sizeof(__le64);
3448 rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3449 rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3450 rx_ring->sbq_size =
3451 rx_ring->sbq_len * sizeof(__le64);
3452 rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3453 rx_ring->type = DEFAULT_Q;
3454 } else if (i < qdev->rss_ring_first_cq_id) {
3455 /*
3456 * Outbound queue handles outbound completions only.
3457 */
3458 /* outbound cq is same size as tx_ring it services. */
3459 rx_ring->cq_len = qdev->tx_ring_size;
3460 rx_ring->cq_size =
3461 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3462 rx_ring->lbq_len = 0;
3463 rx_ring->lbq_size = 0;
3464 rx_ring->lbq_buf_size = 0;
3465 rx_ring->sbq_len = 0;
3466 rx_ring->sbq_size = 0;
3467 rx_ring->sbq_buf_size = 0;
3468 rx_ring->type = TX_Q;
3469 } else { /* Inbound completions (RSS) queues */
3470 /*
3471 * Inbound queues handle unicast frames only.
3472 */
3473 rx_ring->cq_len = qdev->rx_ring_size;
3474 rx_ring->cq_size =
3475 rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3476 rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3477 rx_ring->lbq_size =
3478 rx_ring->lbq_len * sizeof(__le64);
3479 rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3480 rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3481 rx_ring->sbq_size =
3482 rx_ring->sbq_len * sizeof(__le64);
3483 rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3484 rx_ring->type = RX_Q;
3485 }
3486 }
3487 return 0;
3488 }
3489
3490 static int qlge_open(struct net_device *ndev)
3491 {
3492 int err = 0;
3493 struct ql_adapter *qdev = netdev_priv(ndev);
3494
3495 err = ql_configure_rings(qdev);
3496 if (err)
3497 return err;
3498
3499 err = ql_get_adapter_resources(qdev);
3500 if (err)
3501 goto error_up;
3502
3503 err = ql_adapter_up(qdev);
3504 if (err)
3505 goto error_up;
3506
3507 return err;
3508
3509 error_up:
3510 ql_release_adapter_resources(qdev);
3511 return err;
3512 }
3513
3514 static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
3515 {
3516 struct ql_adapter *qdev = netdev_priv(ndev);
3517
3518 if (ndev->mtu == 1500 && new_mtu == 9000) {
3519 QPRINTK(qdev, IFUP, ERR, "Changing to jumbo MTU.\n");
3520 queue_delayed_work(qdev->workqueue,
3521 &qdev->mpi_port_cfg_work, 0);
3522 } else if (ndev->mtu == 9000 && new_mtu == 1500) {
3523 QPRINTK(qdev, IFUP, ERR, "Changing to normal MTU.\n");
3524 } else if ((ndev->mtu == 1500 && new_mtu == 1500) ||
3525 (ndev->mtu == 9000 && new_mtu == 9000)) {
3526 return 0;
3527 } else
3528 return -EINVAL;
3529 ndev->mtu = new_mtu;
3530 return 0;
3531 }
3532
3533 static struct net_device_stats *qlge_get_stats(struct net_device
3534 *ndev)
3535 {
3536 struct ql_adapter *qdev = netdev_priv(ndev);
3537 return &qdev->stats;
3538 }
3539
3540 static void qlge_set_multicast_list(struct net_device *ndev)
3541 {
3542 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3543 struct dev_mc_list *mc_ptr;
3544 int i, status;
3545
3546 status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3547 if (status)
3548 return;
3549 spin_lock(&qdev->hw_lock);
3550 /*
3551 * Set or clear promiscuous mode if a
3552 * transition is taking place.
3553 */
3554 if (ndev->flags & IFF_PROMISC) {
3555 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3556 if (ql_set_routing_reg
3557 (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
3558 QPRINTK(qdev, HW, ERR,
3559 "Failed to set promiscous mode.\n");
3560 } else {
3561 set_bit(QL_PROMISCUOUS, &qdev->flags);
3562 }
3563 }
3564 } else {
3565 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3566 if (ql_set_routing_reg
3567 (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
3568 QPRINTK(qdev, HW, ERR,
3569 "Failed to clear promiscous mode.\n");
3570 } else {
3571 clear_bit(QL_PROMISCUOUS, &qdev->flags);
3572 }
3573 }
3574 }
3575
3576 /*
3577 * Set or clear all multicast mode if a
3578 * transition is taking place.
3579 */
3580 if ((ndev->flags & IFF_ALLMULTI) ||
3581 (ndev->mc_count > MAX_MULTICAST_ENTRIES)) {
3582 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
3583 if (ql_set_routing_reg
3584 (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
3585 QPRINTK(qdev, HW, ERR,
3586 "Failed to set all-multi mode.\n");
3587 } else {
3588 set_bit(QL_ALLMULTI, &qdev->flags);
3589 }
3590 }
3591 } else {
3592 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
3593 if (ql_set_routing_reg
3594 (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
3595 QPRINTK(qdev, HW, ERR,
3596 "Failed to clear all-multi mode.\n");
3597 } else {
3598 clear_bit(QL_ALLMULTI, &qdev->flags);
3599 }
3600 }
3601 }
3602
3603 if (ndev->mc_count) {
3604 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3605 if (status)
3606 goto exit;
3607 for (i = 0, mc_ptr = ndev->mc_list; mc_ptr;
3608 i++, mc_ptr = mc_ptr->next)
3609 if (ql_set_mac_addr_reg(qdev, (u8 *) mc_ptr->dmi_addr,
3610 MAC_ADDR_TYPE_MULTI_MAC, i)) {
3611 QPRINTK(qdev, HW, ERR,
3612 "Failed to loadmulticast address.\n");
3613 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3614 goto exit;
3615 }
3616 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3617 if (ql_set_routing_reg
3618 (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
3619 QPRINTK(qdev, HW, ERR,
3620 "Failed to set multicast match mode.\n");
3621 } else {
3622 set_bit(QL_ALLMULTI, &qdev->flags);
3623 }
3624 }
3625 exit:
3626 spin_unlock(&qdev->hw_lock);
3627 ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3628 }
3629
3630 static int qlge_set_mac_address(struct net_device *ndev, void *p)
3631 {
3632 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3633 struct sockaddr *addr = p;
3634 int status;
3635
3636 if (netif_running(ndev))
3637 return -EBUSY;
3638
3639 if (!is_valid_ether_addr(addr->sa_data))
3640 return -EADDRNOTAVAIL;
3641 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3642
3643 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3644 if (status)
3645 return status;
3646 spin_lock(&qdev->hw_lock);
3647 status = ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
3648 MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
3649 spin_unlock(&qdev->hw_lock);
3650 if (status)
3651 QPRINTK(qdev, HW, ERR, "Failed to load MAC address.\n");
3652 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3653 return status;
3654 }
3655
3656 static void qlge_tx_timeout(struct net_device *ndev)
3657 {
3658 struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3659 ql_queue_asic_error(qdev);
3660 }
3661
3662 static void ql_asic_reset_work(struct work_struct *work)
3663 {
3664 struct ql_adapter *qdev =
3665 container_of(work, struct ql_adapter, asic_reset_work.work);
3666 int status;
3667
3668 status = ql_adapter_down(qdev);
3669 if (status)
3670 goto error;
3671
3672 status = ql_adapter_up(qdev);
3673 if (status)
3674 goto error;
3675
3676 return;
3677 error:
3678 QPRINTK(qdev, IFUP, ALERT,
3679 "Driver up/down cycle failed, closing device\n");
3680 rtnl_lock();
3681 set_bit(QL_ADAPTER_UP, &qdev->flags);
3682 dev_close(qdev->ndev);
3683 rtnl_unlock();
3684 }
3685
3686 static struct nic_operations qla8012_nic_ops = {
3687 .get_flash = ql_get_8012_flash_params,
3688 .port_initialize = ql_8012_port_initialize,
3689 };
3690
3691 static struct nic_operations qla8000_nic_ops = {
3692 .get_flash = ql_get_8000_flash_params,
3693 .port_initialize = ql_8000_port_initialize,
3694 };
3695
3696 /* Find the pcie function number for the other NIC
3697 * on this chip. Since both NIC functions share a
3698 * common firmware we have the lowest enabled function
3699 * do any common work. Examples would be resetting
3700 * after a fatal firmware error, or doing a firmware
3701 * coredump.
3702 */
3703 static int ql_get_alt_pcie_func(struct ql_adapter *qdev)
3704 {
3705 int status = 0;
3706 u32 temp;
3707 u32 nic_func1, nic_func2;
3708
3709 status = ql_read_mpi_reg(qdev, MPI_TEST_FUNC_PORT_CFG,
3710 &temp);
3711 if (status)
3712 return status;
3713
3714 nic_func1 = ((temp >> MPI_TEST_NIC1_FUNC_SHIFT) &
3715 MPI_TEST_NIC_FUNC_MASK);
3716 nic_func2 = ((temp >> MPI_TEST_NIC2_FUNC_SHIFT) &
3717 MPI_TEST_NIC_FUNC_MASK);
3718
3719 if (qdev->func == nic_func1)
3720 qdev->alt_func = nic_func2;
3721 else if (qdev->func == nic_func2)
3722 qdev->alt_func = nic_func1;
3723 else
3724 status = -EIO;
3725
3726 return status;
3727 }
3728
3729 static int ql_get_board_info(struct ql_adapter *qdev)
3730 {
3731 int status;
3732 qdev->func =
3733 (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
3734 if (qdev->func > 3)
3735 return -EIO;
3736
3737 status = ql_get_alt_pcie_func(qdev);
3738 if (status)
3739 return status;
3740
3741 qdev->port = (qdev->func < qdev->alt_func) ? 0 : 1;
3742 if (qdev->port) {
3743 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
3744 qdev->port_link_up = STS_PL1;
3745 qdev->port_init = STS_PI1;
3746 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
3747 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
3748 } else {
3749 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
3750 qdev->port_link_up = STS_PL0;
3751 qdev->port_init = STS_PI0;
3752 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
3753 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
3754 }
3755 qdev->chip_rev_id = ql_read32(qdev, REV_ID);
3756 qdev->device_id = qdev->pdev->device;
3757 if (qdev->device_id == QLGE_DEVICE_ID_8012)
3758 qdev->nic_ops = &qla8012_nic_ops;
3759 else if (qdev->device_id == QLGE_DEVICE_ID_8000)
3760 qdev->nic_ops = &qla8000_nic_ops;
3761 return status;
3762 }
3763
3764 static void ql_release_all(struct pci_dev *pdev)
3765 {
3766 struct net_device *ndev = pci_get_drvdata(pdev);
3767 struct ql_adapter *qdev = netdev_priv(ndev);
3768
3769 if (qdev->workqueue) {
3770 destroy_workqueue(qdev->workqueue);
3771 qdev->workqueue = NULL;
3772 }
3773 if (qdev->q_workqueue) {
3774 destroy_workqueue(qdev->q_workqueue);
3775 qdev->q_workqueue = NULL;
3776 }
3777 if (qdev->reg_base)
3778 iounmap(qdev->reg_base);
3779 if (qdev->doorbell_area)
3780 iounmap(qdev->doorbell_area);
3781 pci_release_regions(pdev);
3782 pci_set_drvdata(pdev, NULL);
3783 }
3784
3785 static int __devinit ql_init_device(struct pci_dev *pdev,
3786 struct net_device *ndev, int cards_found)
3787 {
3788 struct ql_adapter *qdev = netdev_priv(ndev);
3789 int pos, err = 0;
3790 u16 val16;
3791
3792 memset((void *)qdev, 0, sizeof(qdev));
3793 err = pci_enable_device(pdev);
3794 if (err) {
3795 dev_err(&pdev->dev, "PCI device enable failed.\n");
3796 return err;
3797 }
3798
3799 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3800 if (pos <= 0) {
3801 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
3802 "aborting.\n");
3803 goto err_out;
3804 } else {
3805 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
3806 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
3807 val16 |= (PCI_EXP_DEVCTL_CERE |
3808 PCI_EXP_DEVCTL_NFERE |
3809 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
3810 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
3811 }
3812
3813 err = pci_request_regions(pdev, DRV_NAME);
3814 if (err) {
3815 dev_err(&pdev->dev, "PCI region request failed.\n");
3816 goto err_out;
3817 }
3818
3819 pci_set_master(pdev);
3820 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3821 set_bit(QL_DMA64, &qdev->flags);
3822 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3823 } else {
3824 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3825 if (!err)
3826 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3827 }
3828
3829 if (err) {
3830 dev_err(&pdev->dev, "No usable DMA configuration.\n");
3831 goto err_out;
3832 }
3833
3834 pci_set_drvdata(pdev, ndev);
3835 qdev->reg_base =
3836 ioremap_nocache(pci_resource_start(pdev, 1),
3837 pci_resource_len(pdev, 1));
3838 if (!qdev->reg_base) {
3839 dev_err(&pdev->dev, "Register mapping failed.\n");
3840 err = -ENOMEM;
3841 goto err_out;
3842 }
3843
3844 qdev->doorbell_area_size = pci_resource_len(pdev, 3);
3845 qdev->doorbell_area =
3846 ioremap_nocache(pci_resource_start(pdev, 3),
3847 pci_resource_len(pdev, 3));
3848 if (!qdev->doorbell_area) {
3849 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
3850 err = -ENOMEM;
3851 goto err_out;
3852 }
3853
3854 qdev->ndev = ndev;
3855 qdev->pdev = pdev;
3856 err = ql_get_board_info(qdev);
3857 if (err) {
3858 dev_err(&pdev->dev, "Register access failed.\n");
3859 err = -EIO;
3860 goto err_out;
3861 }
3862 qdev->msg_enable = netif_msg_init(debug, default_msg);
3863 spin_lock_init(&qdev->hw_lock);
3864 spin_lock_init(&qdev->stats_lock);
3865
3866 /* make sure the EEPROM is good */
3867 err = qdev->nic_ops->get_flash(qdev);
3868 if (err) {
3869 dev_err(&pdev->dev, "Invalid FLASH.\n");
3870 goto err_out;
3871 }
3872
3873 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3874
3875 /* Set up the default ring sizes. */
3876 qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
3877 qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
3878
3879 /* Set up the coalescing parameters. */
3880 qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
3881 qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
3882 qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3883 qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3884
3885 /*
3886 * Set up the operating parameters.
3887 */
3888 qdev->rx_csum = 1;
3889
3890 qdev->q_workqueue = create_workqueue(ndev->name);
3891 qdev->workqueue = create_singlethread_workqueue(ndev->name);
3892 INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
3893 INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
3894 INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
3895 INIT_DELAYED_WORK(&qdev->mpi_port_cfg_work, ql_mpi_port_cfg_work);
3896 INIT_DELAYED_WORK(&qdev->mpi_idc_work, ql_mpi_idc_work);
3897 mutex_init(&qdev->mpi_mutex);
3898 init_completion(&qdev->ide_completion);
3899
3900 if (!cards_found) {
3901 dev_info(&pdev->dev, "%s\n", DRV_STRING);
3902 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
3903 DRV_NAME, DRV_VERSION);
3904 }
3905 return 0;
3906 err_out:
3907 ql_release_all(pdev);
3908 pci_disable_device(pdev);
3909 return err;
3910 }
3911
3912
3913 static const struct net_device_ops qlge_netdev_ops = {
3914 .ndo_open = qlge_open,
3915 .ndo_stop = qlge_close,
3916 .ndo_start_xmit = qlge_send,
3917 .ndo_change_mtu = qlge_change_mtu,
3918 .ndo_get_stats = qlge_get_stats,
3919 .ndo_set_multicast_list = qlge_set_multicast_list,
3920 .ndo_set_mac_address = qlge_set_mac_address,
3921 .ndo_validate_addr = eth_validate_addr,
3922 .ndo_tx_timeout = qlge_tx_timeout,
3923 .ndo_vlan_rx_register = ql_vlan_rx_register,
3924 .ndo_vlan_rx_add_vid = ql_vlan_rx_add_vid,
3925 .ndo_vlan_rx_kill_vid = ql_vlan_rx_kill_vid,
3926 };
3927
3928 static int __devinit qlge_probe(struct pci_dev *pdev,
3929 const struct pci_device_id *pci_entry)
3930 {
3931 struct net_device *ndev = NULL;
3932 struct ql_adapter *qdev = NULL;
3933 static int cards_found = 0;
3934 int err = 0;
3935
3936 ndev = alloc_etherdev_mq(sizeof(struct ql_adapter),
3937 min(MAX_CPUS, (int)num_online_cpus()));
3938 if (!ndev)
3939 return -ENOMEM;
3940
3941 err = ql_init_device(pdev, ndev, cards_found);
3942 if (err < 0) {
3943 free_netdev(ndev);
3944 return err;
3945 }
3946
3947 qdev = netdev_priv(ndev);
3948 SET_NETDEV_DEV(ndev, &pdev->dev);
3949 ndev->features = (0
3950 | NETIF_F_IP_CSUM
3951 | NETIF_F_SG
3952 | NETIF_F_TSO
3953 | NETIF_F_TSO6
3954 | NETIF_F_TSO_ECN
3955 | NETIF_F_HW_VLAN_TX
3956 | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER);
3957 ndev->features |= NETIF_F_GRO;
3958
3959 if (test_bit(QL_DMA64, &qdev->flags))
3960 ndev->features |= NETIF_F_HIGHDMA;
3961
3962 /*
3963 * Set up net_device structure.
3964 */
3965 ndev->tx_queue_len = qdev->tx_ring_size;
3966 ndev->irq = pdev->irq;
3967
3968 ndev->netdev_ops = &qlge_netdev_ops;
3969 SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
3970 ndev->watchdog_timeo = 10 * HZ;
3971
3972 err = register_netdev(ndev);
3973 if (err) {
3974 dev_err(&pdev->dev, "net device registration failed.\n");
3975 ql_release_all(pdev);
3976 pci_disable_device(pdev);
3977 return err;
3978 }
3979 netif_carrier_off(ndev);
3980 ql_display_dev_info(ndev);
3981 cards_found++;
3982 return 0;
3983 }
3984
3985 static void __devexit qlge_remove(struct pci_dev *pdev)
3986 {
3987 struct net_device *ndev = pci_get_drvdata(pdev);
3988 unregister_netdev(ndev);
3989 ql_release_all(pdev);
3990 pci_disable_device(pdev);
3991 free_netdev(ndev);
3992 }
3993
3994 /*
3995 * This callback is called by the PCI subsystem whenever
3996 * a PCI bus error is detected.
3997 */
3998 static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
3999 enum pci_channel_state state)
4000 {
4001 struct net_device *ndev = pci_get_drvdata(pdev);
4002 struct ql_adapter *qdev = netdev_priv(ndev);
4003
4004 if (netif_running(ndev))
4005 ql_adapter_down(qdev);
4006
4007 pci_disable_device(pdev);
4008
4009 /* Request a slot reset. */
4010 return PCI_ERS_RESULT_NEED_RESET;
4011 }
4012
4013 /*
4014 * This callback is called after the PCI buss has been reset.
4015 * Basically, this tries to restart the card from scratch.
4016 * This is a shortened version of the device probe/discovery code,
4017 * it resembles the first-half of the () routine.
4018 */
4019 static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
4020 {
4021 struct net_device *ndev = pci_get_drvdata(pdev);
4022 struct ql_adapter *qdev = netdev_priv(ndev);
4023
4024 if (pci_enable_device(pdev)) {
4025 QPRINTK(qdev, IFUP, ERR,
4026 "Cannot re-enable PCI device after reset.\n");
4027 return PCI_ERS_RESULT_DISCONNECT;
4028 }
4029
4030 pci_set_master(pdev);
4031
4032 netif_carrier_off(ndev);
4033 ql_adapter_reset(qdev);
4034
4035 /* Make sure the EEPROM is good */
4036 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
4037
4038 if (!is_valid_ether_addr(ndev->perm_addr)) {
4039 QPRINTK(qdev, IFUP, ERR, "After reset, invalid MAC address.\n");
4040 return PCI_ERS_RESULT_DISCONNECT;
4041 }
4042
4043 return PCI_ERS_RESULT_RECOVERED;
4044 }
4045
4046 static void qlge_io_resume(struct pci_dev *pdev)
4047 {
4048 struct net_device *ndev = pci_get_drvdata(pdev);
4049 struct ql_adapter *qdev = netdev_priv(ndev);
4050
4051 pci_set_master(pdev);
4052
4053 if (netif_running(ndev)) {
4054 if (ql_adapter_up(qdev)) {
4055 QPRINTK(qdev, IFUP, ERR,
4056 "Device initialization failed after reset.\n");
4057 return;
4058 }
4059 }
4060
4061 netif_device_attach(ndev);
4062 }
4063
4064 static struct pci_error_handlers qlge_err_handler = {
4065 .error_detected = qlge_io_error_detected,
4066 .slot_reset = qlge_io_slot_reset,
4067 .resume = qlge_io_resume,
4068 };
4069
4070 static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
4071 {
4072 struct net_device *ndev = pci_get_drvdata(pdev);
4073 struct ql_adapter *qdev = netdev_priv(ndev);
4074 int err;
4075
4076 netif_device_detach(ndev);
4077
4078 if (netif_running(ndev)) {
4079 err = ql_adapter_down(qdev);
4080 if (!err)
4081 return err;
4082 }
4083
4084 err = pci_save_state(pdev);
4085 if (err)
4086 return err;
4087
4088 pci_disable_device(pdev);
4089
4090 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4091
4092 return 0;
4093 }
4094
4095 #ifdef CONFIG_PM
4096 static int qlge_resume(struct pci_dev *pdev)
4097 {
4098 struct net_device *ndev = pci_get_drvdata(pdev);
4099 struct ql_adapter *qdev = netdev_priv(ndev);
4100 int err;
4101
4102 pci_set_power_state(pdev, PCI_D0);
4103 pci_restore_state(pdev);
4104 err = pci_enable_device(pdev);
4105 if (err) {
4106 QPRINTK(qdev, IFUP, ERR, "Cannot enable PCI device from suspend\n");
4107 return err;
4108 }
4109 pci_set_master(pdev);
4110
4111 pci_enable_wake(pdev, PCI_D3hot, 0);
4112 pci_enable_wake(pdev, PCI_D3cold, 0);
4113
4114 if (netif_running(ndev)) {
4115 err = ql_adapter_up(qdev);
4116 if (err)
4117 return err;
4118 }
4119
4120 netif_device_attach(ndev);
4121
4122 return 0;
4123 }
4124 #endif /* CONFIG_PM */
4125
4126 static void qlge_shutdown(struct pci_dev *pdev)
4127 {
4128 qlge_suspend(pdev, PMSG_SUSPEND);
4129 }
4130
4131 static struct pci_driver qlge_driver = {
4132 .name = DRV_NAME,
4133 .id_table = qlge_pci_tbl,
4134 .probe = qlge_probe,
4135 .remove = __devexit_p(qlge_remove),
4136 #ifdef CONFIG_PM
4137 .suspend = qlge_suspend,
4138 .resume = qlge_resume,
4139 #endif
4140 .shutdown = qlge_shutdown,
4141 .err_handler = &qlge_err_handler
4142 };
4143
4144 static int __init qlge_init_module(void)
4145 {
4146 return pci_register_driver(&qlge_driver);
4147 }
4148
4149 static void __exit qlge_exit(void)
4150 {
4151 pci_unregister_driver(&qlge_driver);
4152 }
4153
4154 module_init(qlge_init_module);
4155 module_exit(qlge_exit);
Support for the Chinese Samsung S3C2440 based development boards