drivers/net/netxen/netxen_nic.h

   1 /*
   2  * Copyright (C) 2003 - 2009 NetXen, Inc.
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18  * MA  02111-1307, USA.
  19  *
  20  * The full GNU General Public License is included in this distribution
  21  * in the file called LICENSE.
  22  *
  23  * Contact Information:
  24  *    info@netxen.com
  25  * NetXen Inc,
  26  * 18922 Forge Drive
  27  * Cupertino, CA 95014-0701
  28  *
  29  */
  30
  31 #ifndef _NETXEN_NIC_H_
  32 #define _NETXEN_NIC_H_
  33
  34 #include <linux/module.h>
  35 #include <linux/kernel.h>
  36 #include <linux/types.h>
  37 #include <linux/ioport.h>
  38 #include <linux/pci.h>
  39 #include <linux/netdevice.h>
  40 #include <linux/etherdevice.h>
  41 #include <linux/ip.h>
  42 #include <linux/in.h>
  43 #include <linux/tcp.h>
  44 #include <linux/skbuff.h>
  45 #include <linux/firmware.h>
  46
  47 #include <linux/ethtool.h>
  48 #include <linux/mii.h>
  49 #include <linux/timer.h>
  50
  51 #include <linux/vmalloc.h>
  52
  53 #include <asm/io.h>
  54 #include <asm/byteorder.h>
  55
  56 #include "netxen_nic_hw.h"
  57
  58 #define _NETXEN_NIC_LINUX_MAJOR 4
  59 #define _NETXEN_NIC_LINUX_MINOR 0
  60 #define _NETXEN_NIC_LINUX_SUBVERSION 30
  61 #define NETXEN_NIC_LINUX_VERSIONID  "4.0.30"
  62
  63 #define NETXEN_VERSION_CODE(a, b, c)    (((a) << 16) + ((b) << 8) + (c))
  64
  65 #define NETXEN_NUM_FLASH_SECTORS (64)
  66 #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
  67 #define NETXEN_FLASH_TOTAL_SIZE  (NETXEN_NUM_FLASH_SECTORS \
  68                                         * NETXEN_FLASH_SECTOR_SIZE)
  69
  70 #define PHAN_VENDOR_ID 0x4040
  71
  72 #define RCV_DESC_RINGSIZE(rds_ring)     \
  73         (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
  74 #define RCV_BUFF_RINGSIZE(rds_ring)     \
  75         (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc)
  76 #define STATUS_DESC_RINGSIZE(sds_ring)  \
  77         (sizeof(struct status_desc) * (sds_ring)->num_desc)
  78 #define TX_BUFF_RINGSIZE(tx_ring)       \
  79         (sizeof(struct netxen_cmd_buffer) * tx_ring->num_desc)
  80 #define TX_DESC_RINGSIZE(tx_ring)       \
  81         (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
  82
  83 #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
  84
  85 #define NETXEN_RCV_PRODUCER_OFFSET      0
  86 #define NETXEN_RCV_PEG_DB_ID            2
  87 #define NETXEN_HOST_DUMMY_DMA_SIZE 1024
  88 #define FLASH_SUCCESS 0
  89
  90 #define ADDR_IN_WINDOW1(off)    \
  91         ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
  92
  93 /*
  94  * normalize a 64MB crb address to 32MB PCI window
  95  * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
  96  */
  97 #define NETXEN_CRB_NORMAL(reg)  \
  98         ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
  99
 100 #define NETXEN_CRB_NORMALIZE(adapter, reg) \
 101         pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
 102
 103 #define DB_NORMALIZE(adapter, off) \
 104         (adapter->ahw.db_base + (off))
 105
 106 #define NX_P2_C0                0x24
 107 #define NX_P2_C1                0x25
 108 #define NX_P3_A0                0x30
 109 #define NX_P3_A2                0x30
 110 #define NX_P3_B0                0x40
 111 #define NX_P3_B1                0x41
 112 #define NX_P3_B2                0x42
 113
 114 #define NX_IS_REVISION_P2(REVISION)     (REVISION <= NX_P2_C1)
 115 #define NX_IS_REVISION_P3(REVISION)     (REVISION >= NX_P3_A0)
 116
 117 #define FIRST_PAGE_GROUP_START  0
 118 #define FIRST_PAGE_GROUP_END    0x100000
 119
 120 #define SECOND_PAGE_GROUP_START 0x6000000
 121 #define SECOND_PAGE_GROUP_END   0x68BC000
 122
 123 #define THIRD_PAGE_GROUP_START  0x70E4000
 124 #define THIRD_PAGE_GROUP_END    0x8000000
 125
 126 #define FIRST_PAGE_GROUP_SIZE  FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
 127 #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
 128 #define THIRD_PAGE_GROUP_SIZE  THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
 129
 130 #define P2_MAX_MTU                     (8000)
 131 #define P3_MAX_MTU                     (9600)
 132 #define NX_ETHERMTU                    1500
 133 #define NX_MAX_ETHERHDR                32 /* This contains some padding */
 134
 135 #define NX_RX_NORMAL_BUF_MAX_LEN       (NX_MAX_ETHERHDR + NX_ETHERMTU)
 136 #define NX_P2_RX_JUMBO_BUF_MAX_LEN     (NX_MAX_ETHERHDR + P2_MAX_MTU)
 137 #define NX_P3_RX_JUMBO_BUF_MAX_LEN     (NX_MAX_ETHERHDR + P3_MAX_MTU)
 138 #define NX_CT_DEFAULT_RX_BUF_LEN        2048
 139
 140 #define MAX_RX_BUFFER_LENGTH            1760
 141 #define MAX_RX_JUMBO_BUFFER_LENGTH      8062
 142 #define MAX_RX_LRO_BUFFER_LENGTH        (8062)
 143 #define RX_DMA_MAP_LEN                  (MAX_RX_BUFFER_LENGTH - 2)
 144 #define RX_JUMBO_DMA_MAP_LEN    \
 145         (MAX_RX_JUMBO_BUFFER_LENGTH - 2)
 146 #define RX_LRO_DMA_MAP_LEN              (MAX_RX_LRO_BUFFER_LENGTH - 2)
 147
 148 /*
 149  * Maximum number of ring contexts
 150  */
 151 #define MAX_RING_CTX 1
 152
 153 /* Opcodes to be used with the commands */
 154 #define TX_ETHER_PKT    0x01
 155 #define TX_TCP_PKT      0x02
 156 #define TX_UDP_PKT      0x03
 157 #define TX_IP_PKT       0x04
 158 #define TX_TCP_LSO      0x05
 159 #define TX_TCP_LSO6     0x06
 160 #define TX_IPSEC        0x07
 161 #define TX_IPSEC_CMD    0x0a
 162 #define TX_TCPV6_PKT    0x0b
 163 #define TX_UDPV6_PKT    0x0c
 164
 165 /* The following opcodes are for internal consumption. */
 166 #define NETXEN_CONTROL_OP       0x10
 167 #define PEGNET_REQUEST          0x11
 168
 169 #define MAX_NUM_CARDS           4
 170
 171 #define MAX_BUFFERS_PER_CMD     32
 172 #define TX_STOP_THRESH          ((MAX_SKB_FRAGS >> 2) + 4)
 173
 174 /*
 175  * Following are the states of the Phantom. Phantom will set them and
 176  * Host will read to check if the fields are correct.
 177  */
 178 #define PHAN_INITIALIZE_START           0xff00
 179 #define PHAN_INITIALIZE_FAILED          0xffff
 180 #define PHAN_INITIALIZE_COMPLETE        0xff01
 181
 182 /* Host writes the following to notify that it has done the init-handshake */
 183 #define PHAN_INITIALIZE_ACK     0xf00f
 184
 185 #define NUM_RCV_DESC_RINGS      3
 186 #define NUM_STS_DESC_RINGS      4
 187
 188 #define RCV_RING_NORMAL 0
 189 #define RCV_RING_JUMBO  1
 190 #define RCV_RING_LRO    2
 191
 192 #define MAX_CMD_DESCRIPTORS             4096
 193 #define MAX_RCV_DESCRIPTORS             16384
 194 #define MAX_CMD_DESCRIPTORS_HOST        1024
 195 #define MAX_RCV_DESCRIPTORS_1G          2048
 196 #define MAX_RCV_DESCRIPTORS_10G         4096
 197 #define MAX_JUMBO_RCV_DESCRIPTORS       1024
 198 #define MAX_LRO_RCV_DESCRIPTORS         8
 199 #define NETXEN_CTX_SIGNATURE    0xdee0
 200 #define NETXEN_CTX_SIGNATURE_V2 0x0002dee0
 201 #define NETXEN_CTX_RESET        0xbad0
 202 #define NETXEN_RCV_PRODUCER(ringid)     (ringid)
 203
 204 #define PHAN_PEG_RCV_INITIALIZED        0xff01
 205 #define PHAN_PEG_RCV_START_INITIALIZE   0xff00
 206
 207 #define get_next_index(index, length)   \
 208         (((index) + 1) & ((length) - 1))
 209
 210 #define get_index_range(index,length,count)     \
 211         (((index) + (count)) & ((length) - 1))
 212
 213 #define MPORT_SINGLE_FUNCTION_MODE 0x1111
 214 #define MPORT_MULTI_FUNCTION_MODE 0x2222
 215
 216 #include "netxen_nic_phan_reg.h"
 217
 218 /*
 219  * NetXen host-peg signal message structure
 220  *
 221  *      Bit 0-1         : peg_id => 0x2 for tx and 01 for rx
 222  *      Bit 2           : priv_id => must be 1
 223  *      Bit 3-17        : count => for doorbell
 224  *      Bit 18-27       : ctx_id => Context id
 225  *      Bit 28-31       : opcode
 226  */
 227
 228 typedef u32 netxen_ctx_msg;
 229
 230 #define netxen_set_msg_peg_id(config_word, val) \
 231         ((config_word) &= ~3, (config_word) |= val & 3)
 232 #define netxen_set_msg_privid(config_word)      \
 233         ((config_word) |= 1 << 2)
 234 #define netxen_set_msg_count(config_word, val)  \
 235         ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
 236 #define netxen_set_msg_ctxid(config_word, val)  \
 237         ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
 238 #define netxen_set_msg_opcode(config_word, val) \
 239         ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
 240
 241 struct netxen_rcv_ring {
 242         __le64 addr;
 243         __le32 size;
 244         __le32 rsrvd;
 245 };
 246
 247 struct netxen_sts_ring {
 248         __le64 addr;
 249         __le32 size;
 250         __le16 msi_index;
 251         __le16 rsvd;
 252 } ;
 253
 254 struct netxen_ring_ctx {
 255
 256         /* one command ring */
 257         __le64 cmd_consumer_offset;
 258         __le64 cmd_ring_addr;
 259         __le32 cmd_ring_size;
 260         __le32 rsrvd;
 261
 262         /* three receive rings */
 263         struct netxen_rcv_ring rcv_rings[NUM_RCV_DESC_RINGS];
 264
 265         __le64 sts_ring_addr;
 266         __le32 sts_ring_size;
 267
 268         __le32 ctx_id;
 269
 270         __le64 rsrvd_2[3];
 271         __le32 sts_ring_count;
 272         __le32 rsrvd_3;
 273         struct netxen_sts_ring sts_rings[NUM_STS_DESC_RINGS];
 274
 275 } __attribute__ ((aligned(64)));
 276
 277 /*
 278  * Following data structures describe the descriptors that will be used.
 279  * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
 280  * we are doing LSO (above the 1500 size packet) only.
 281  */
 282
 283 /*
 284  * The size of reference handle been changed to 16 bits to pass the MSS fields
 285  * for the LSO packet
 286  */
 287
 288 #define FLAGS_CHECKSUM_ENABLED  0x01
 289 #define FLAGS_LSO_ENABLED       0x02
 290 #define FLAGS_IPSEC_SA_ADD      0x04
 291 #define FLAGS_IPSEC_SA_DELETE   0x08
 292 #define FLAGS_VLAN_TAGGED       0x10
 293
 294 #define netxen_set_cmd_desc_port(cmd_desc, var) \
 295         ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
 296 #define netxen_set_cmd_desc_ctxid(cmd_desc, var)        \
 297         ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
 298
 299 #define netxen_set_tx_port(_desc, _port) \
 300         (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)
 301
 302 #define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \
 303         (_desc)->flags_opcode = \
 304         cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))
 305
 306 #define netxen_set_tx_frags_len(_desc, _frags, _len) \
 307         (_desc)->num_of_buffers_total_length = \
 308         cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))
 309
 310 struct cmd_desc_type0 {
 311         u8 tcp_hdr_offset;      /* For LSO only */
 312         u8 ip_hdr_offset;       /* For LSO only */
 313         /* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */
 314         __le16 flags_opcode;
 315         /* Bit pattern: 0-7 total number of segments,
 316            8-31 Total size of the packet */
 317         __le32 num_of_buffers_total_length;
 318         union {
 319                 struct {
 320                         __le32 addr_low_part2;
 321                         __le32 addr_high_part2;
 322                 };
 323                 __le64 addr_buffer2;
 324         };
 325
 326         __le16 reference_handle;        /* changed to u16 to add mss */
 327         __le16 mss;             /* passed by NDIS_PACKET for LSO */
 328         /* Bit pattern 0-3 port, 0-3 ctx id */
 329         u8 port_ctxid;
 330         u8 total_hdr_length;    /* LSO only : MAC+IP+TCP Hdr size */
 331         __le16 conn_id;         /* IPSec offoad only */
 332
 333         union {
 334                 struct {
 335                         __le32 addr_low_part3;
 336                         __le32 addr_high_part3;
 337                 };
 338                 __le64 addr_buffer3;
 339         };
 340         union {
 341                 struct {
 342                         __le32 addr_low_part1;
 343                         __le32 addr_high_part1;
 344                 };
 345                 __le64 addr_buffer1;
 346         };
 347
 348         __le16 buffer_length[4];
 349
 350         union {
 351                 struct {
 352                         __le32 addr_low_part4;
 353                         __le32 addr_high_part4;
 354                 };
 355                 __le64 addr_buffer4;
 356         };
 357
 358         __le64 unused;
 359
 360 } __attribute__ ((aligned(64)));
 361
 362 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
 363 struct rcv_desc {
 364         __le16 reference_handle;
 365         __le16 reserved;
 366         __le32 buffer_length;   /* allocated buffer length (usually 2K) */
 367         __le64 addr_buffer;
 368 };
 369
 370 /* opcode field in status_desc */
 371 #define NETXEN_NIC_RXPKT_DESC  0x04
 372 #define NETXEN_OLD_RXPKT_DESC  0x3f
 373 #define NETXEN_NIC_RESPONSE_DESC 0x05
 374
 375 /* for status field in status_desc */
 376 #define STATUS_NEED_CKSUM       (1)
 377 #define STATUS_CKSUM_OK         (2)
 378
 379 /* owner bits of status_desc */
 380 #define STATUS_OWNER_HOST       (0x1ULL << 56)
 381 #define STATUS_OWNER_PHANTOM    (0x2ULL << 56)
 382
 383 /* Status descriptor:
 384    0-3 port, 4-7 status, 8-11 type, 12-27 total_length
 385    28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
 386    53-55 desc_cnt, 56-57 owner, 58-63 opcode
 387  */
 388 #define netxen_get_sts_port(sts_data)   \
 389         ((sts_data) & 0x0F)
 390 #define netxen_get_sts_status(sts_data) \
 391         (((sts_data) >> 4) & 0x0F)
 392 #define netxen_get_sts_type(sts_data)   \
 393         (((sts_data) >> 8) & 0x0F)
 394 #define netxen_get_sts_totallength(sts_data)    \
 395         (((sts_data) >> 12) & 0xFFFF)
 396 #define netxen_get_sts_refhandle(sts_data)      \
 397         (((sts_data) >> 28) & 0xFFFF)
 398 #define netxen_get_sts_prot(sts_data)   \
 399         (((sts_data) >> 44) & 0x0F)
 400 #define netxen_get_sts_pkt_offset(sts_data)     \
 401         (((sts_data) >> 48) & 0x1F)
 402 #define netxen_get_sts_desc_cnt(sts_data)       \
 403         (((sts_data) >> 53) & 0x7)
 404 #define netxen_get_sts_opcode(sts_data) \
 405         (((sts_data) >> 58) & 0x03F)
 406
 407 struct status_desc {
 408         __le64 status_desc_data[2];
 409 } __attribute__ ((aligned(16)));
 410
 411 /* The version of the main data structure */
 412 #define NETXEN_BDINFO_VERSION 1
 413
 414 /* Magic number to let user know flash is programmed */
 415 #define NETXEN_BDINFO_MAGIC 0x12345678
 416
 417 /* Max number of Gig ports on a Phantom board */
 418 #define NETXEN_MAX_PORTS 4
 419
 420 #define NETXEN_BRDTYPE_P1_BD            0x0000
 421 #define NETXEN_BRDTYPE_P1_SB            0x0001
 422 #define NETXEN_BRDTYPE_P1_SMAX          0x0002
 423 #define NETXEN_BRDTYPE_P1_SOCK          0x0003
 424
 425 #define NETXEN_BRDTYPE_P2_SOCK_31       0x0008
 426 #define NETXEN_BRDTYPE_P2_SOCK_35       0x0009
 427 #define NETXEN_BRDTYPE_P2_SB35_4G       0x000a
 428 #define NETXEN_BRDTYPE_P2_SB31_10G      0x000b
 429 #define NETXEN_BRDTYPE_P2_SB31_2G       0x000c
 430
 431 #define NETXEN_BRDTYPE_P2_SB31_10G_IMEZ         0x000d
 432 #define NETXEN_BRDTYPE_P2_SB31_10G_HMEZ         0x000e
 433 #define NETXEN_BRDTYPE_P2_SB31_10G_CX4          0x000f
 434
 435 #define NETXEN_BRDTYPE_P3_REF_QG        0x0021
 436 #define NETXEN_BRDTYPE_P3_HMEZ          0x0022
 437 #define NETXEN_BRDTYPE_P3_10G_CX4_LP    0x0023
 438 #define NETXEN_BRDTYPE_P3_4_GB          0x0024
 439 #define NETXEN_BRDTYPE_P3_IMEZ          0x0025
 440 #define NETXEN_BRDTYPE_P3_10G_SFP_PLUS  0x0026
 441 #define NETXEN_BRDTYPE_P3_10000_BASE_T  0x0027
 442 #define NETXEN_BRDTYPE_P3_XG_LOM        0x0028
 443 #define NETXEN_BRDTYPE_P3_4_GB_MM       0x0029
 444 #define NETXEN_BRDTYPE_P3_10G_SFP_CT    0x002a
 445 #define NETXEN_BRDTYPE_P3_10G_SFP_QT    0x002b
 446 #define NETXEN_BRDTYPE_P3_10G_CX4       0x0031
 447 #define NETXEN_BRDTYPE_P3_10G_XFP       0x0032
 448 #define NETXEN_BRDTYPE_P3_10G_TP        0x0080
 449
 450 struct netxen_board_info {
 451         u32 header_version;
 452
 453         u32 board_mfg;
 454         u32 board_type;
 455         u32 board_num;
 456         u32 chip_id;
 457         u32 chip_minor;
 458         u32 chip_major;
 459         u32 chip_pkg;
 460         u32 chip_lot;
 461
 462         u32 port_mask;          /* available niu ports */
 463         u32 peg_mask;           /* available pegs */
 464         u32 icache_ok;          /* can we run with icache? */
 465         u32 dcache_ok;          /* can we run with dcache? */
 466         u32 casper_ok;
 467
 468         u32 mac_addr_lo_0;
 469         u32 mac_addr_lo_1;
 470         u32 mac_addr_lo_2;
 471         u32 mac_addr_lo_3;
 472
 473         /* MN-related config */
 474         u32 mn_sync_mode;       /* enable/ sync shift cclk/ sync shift mclk */
 475         u32 mn_sync_shift_cclk;
 476         u32 mn_sync_shift_mclk;
 477         u32 mn_wb_en;
 478         u32 mn_crystal_freq;    /* in MHz */
 479         u32 mn_speed;           /* in MHz */
 480         u32 mn_org;
 481         u32 mn_depth;
 482         u32 mn_ranks_0;         /* ranks per slot */
 483         u32 mn_ranks_1;         /* ranks per slot */
 484         u32 mn_rd_latency_0;
 485         u32 mn_rd_latency_1;
 486         u32 mn_rd_latency_2;
 487         u32 mn_rd_latency_3;
 488         u32 mn_rd_latency_4;
 489         u32 mn_rd_latency_5;
 490         u32 mn_rd_latency_6;
 491         u32 mn_rd_latency_7;
 492         u32 mn_rd_latency_8;
 493         u32 mn_dll_val[18];
 494         u32 mn_mode_reg;        /* MIU DDR Mode Register */
 495         u32 mn_ext_mode_reg;    /* MIU DDR Extended Mode Register */
 496         u32 mn_timing_0;        /* MIU Memory Control Timing Rgister */
 497         u32 mn_timing_1;        /* MIU Extended Memory Ctrl Timing Register */
 498         u32 mn_timing_2;        /* MIU Extended Memory Ctrl Timing2 Register */
 499
 500         /* SN-related config */
 501         u32 sn_sync_mode;       /* enable/ sync shift cclk / sync shift mclk */
 502         u32 sn_pt_mode;         /* pass through mode */
 503         u32 sn_ecc_en;
 504         u32 sn_wb_en;
 505         u32 sn_crystal_freq;
 506         u32 sn_speed;
 507         u32 sn_org;
 508         u32 sn_depth;
 509         u32 sn_dll_tap;
 510         u32 sn_rd_latency;
 511
 512         u32 mac_addr_hi_0;
 513         u32 mac_addr_hi_1;
 514         u32 mac_addr_hi_2;
 515         u32 mac_addr_hi_3;
 516
 517         u32 magic;              /* indicates flash has been initialized */
 518
 519         u32 mn_rdimm;
 520         u32 mn_dll_override;
 521
 522 };
 523
 524 #define FLASH_NUM_PORTS         (4)
 525
 526 struct netxen_flash_mac_addr {
 527         u32 flash_addr[32];
 528 };
 529
 530 struct netxen_user_old_info {
 531         u8 flash_md5[16];
 532         u8 crbinit_md5[16];
 533         u8 brdcfg_md5[16];
 534         /* bootloader */
 535         u32 bootld_version;
 536         u32 bootld_size;
 537         u8 bootld_md5[16];
 538         /* image */
 539         u32 image_version;
 540         u32 image_size;
 541         u8 image_md5[16];
 542         /* primary image status */
 543         u32 primary_status;
 544         u32 secondary_present;
 545
 546         /* MAC address , 4 ports */
 547         struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS];
 548 };
 549 #define FLASH_NUM_MAC_PER_PORT  32
 550 struct netxen_user_info {
 551         u8 flash_md5[16 * 64];
 552         /* bootloader */
 553         u32 bootld_version;
 554         u32 bootld_size;
 555         /* image */
 556         u32 image_version;
 557         u32 image_size;
 558         /* primary image status */
 559         u32 primary_status;
 560         u32 secondary_present;
 561
 562         /* MAC address , 4 ports, 32 address per port */
 563         u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
 564         u32 sub_sys_id;
 565         u8 serial_num[32];
 566
 567         /* Any user defined data */
 568 };
 569
 570 /*
 571  * Flash Layout - new format.
 572  */
 573 struct netxen_new_user_info {
 574         u8 flash_md5[16 * 64];
 575         /* bootloader */
 576         u32 bootld_version;
 577         u32 bootld_size;
 578         /* image */
 579         u32 image_version;
 580         u32 image_size;
 581         /* primary image status */
 582         u32 primary_status;
 583         u32 secondary_present;
 584
 585         /* MAC address , 4 ports, 32 address per port */
 586         u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
 587         u32 sub_sys_id;
 588         u8 serial_num[32];
 589
 590         /* Any user defined data */
 591 };
 592
 593 #define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6
 594 #define SECONDARY_IMAGE_ABSENT  0xffffffff
 595 #define PRIMARY_IMAGE_GOOD      0x5a5a5a5a
 596 #define PRIMARY_IMAGE_BAD       0xffffffff
 597
 598 /* Flash memory map */
 599 #define NETXEN_CRBINIT_START    0       /* crbinit section */
 600 #define NETXEN_BRDCFG_START     0x4000  /* board config */
 601 #define NETXEN_INITCODE_START   0x6000  /* pegtune code */
 602 #define NETXEN_BOOTLD_START     0x10000 /* bootld */
 603 #define NETXEN_IMAGE_START      0x43000 /* compressed image */
 604 #define NETXEN_SECONDARY_START  0x200000        /* backup images */
 605 #define NETXEN_PXE_START        0x3E0000        /* PXE boot rom */
 606 #define NETXEN_USER_START       0x3E8000        /* Firmare info */
 607 #define NETXEN_FIXED_START      0x3F0000        /* backup of crbinit */
 608
 609 #define NX_FW_VERSION_OFFSET    (NETXEN_USER_START+0x408)
 610 #define NX_FW_SIZE_OFFSET       (NETXEN_USER_START+0x40c)
 611 #define NX_BIOS_VERSION_OFFSET  (NETXEN_USER_START+0x83c)
 612 #define NX_FW_MAGIC_OFFSET      (NETXEN_BRDCFG_START+0x128)
 613 #define NX_FW_MIN_SIZE          (0x3fffff)
 614 #define NX_P2_MN_ROMIMAGE       0
 615 #define NX_P3_CT_ROMIMAGE       1
 616 #define NX_P3_MN_ROMIMAGE       2
 617
 618 #define NETXEN_USER_START_OLD NETXEN_PXE_START  /* for backward compatibility */
 619
 620 #define NETXEN_FLASH_START              (NETXEN_CRBINIT_START)
 621 #define NETXEN_INIT_SECTOR              (0)
 622 #define NETXEN_PRIMARY_START            (NETXEN_BOOTLD_START)
 623 #define NETXEN_FLASH_CRBINIT_SIZE       (0x4000)
 624 #define NETXEN_FLASH_BRDCFG_SIZE        (sizeof(struct netxen_board_info))
 625 #define NETXEN_FLASH_USER_SIZE          (sizeof(struct netxen_user_info)/sizeof(u32))
 626 #define NETXEN_FLASH_SECONDARY_SIZE     (NETXEN_USER_START-NETXEN_SECONDARY_START)
 627 #define NETXEN_NUM_PRIMARY_SECTORS      (0x20)
 628 #define NETXEN_NUM_CONFIG_SECTORS       (1)
 629 extern char netxen_nic_driver_name[];
 630
 631 /* Number of status descriptors to handle per interrupt */
 632 #define MAX_STATUS_HANDLE       (64)
 633
 634 /*
 635  * netxen_skb_frag{} is to contain mapping info for each SG list. This
 636  * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
 637  */
 638 struct netxen_skb_frag {
 639         u64 dma;
 640         u64 length;
 641 };
 642
 643 #define _netxen_set_bits(config_word, start, bits, val) {\
 644         unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));\
 645         unsigned long long __tvalue = (val);    \
 646         (config_word) &= ~__tmask;      \
 647         (config_word) |= (((__tvalue) << (start)) & __tmask); \
 648 }
 649
 650 #define _netxen_clear_bits(config_word, start, bits) {\
 651         unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));  \
 652         (config_word) &= ~__tmask; \
 653 }
 654
 655 /*    Following defines are for the state of the buffers    */
 656 #define NETXEN_BUFFER_FREE      0
 657 #define NETXEN_BUFFER_BUSY      1
 658
 659 /*
 660  * There will be one netxen_buffer per skb packet.    These will be
 661  * used to save the dma info for pci_unmap_page()
 662  */
 663 struct netxen_cmd_buffer {
 664         struct sk_buff *skb;
 665         struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
 666         u32 frag_count;
 667 };
 668
 669 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
 670 struct netxen_rx_buffer {
 671         struct list_head list;
 672         struct sk_buff *skb;
 673         u64 dma;
 674         u16 ref_handle;
 675         u16 state;
 676 };
 677
 678 /* Board types */
 679 #define NETXEN_NIC_GBE  0x01
 680 #define NETXEN_NIC_XGBE 0x02
 681
 682 /*
 683  * One hardware_context{} per adapter
 684  * contains interrupt info as well shared hardware info.
 685  */
 686 struct netxen_hardware_context {
 687         void __iomem *pci_base0;
 688         void __iomem *pci_base1;
 689         void __iomem *pci_base2;
 690         void __iomem *db_base;
 691         unsigned long db_len;
 692         unsigned long pci_len0;
 693
 694         int qdr_sn_window;
 695         int ddr_mn_window;
 696         unsigned long mn_win_crb;
 697         unsigned long ms_win_crb;
 698
 699         u8 cut_through;
 700         u8 revision_id;
 701         u8 pci_func;
 702         u8 linkup;
 703         u16 port_type;
 704         u16 board_type;
 705 };
 706
 707 #define MINIMUM_ETHERNET_FRAME_SIZE     64      /* With FCS */
 708 #define ETHERNET_FCS_SIZE               4
 709
 710 struct netxen_adapter_stats {
 711         u64  xmitcalled;
 712         u64  xmitfinished;
 713         u64  rxdropped;
 714         u64  txdropped;
 715         u64  csummed;
 716         u64  no_rcv;
 717         u64  rxbytes;
 718         u64  txbytes;
 719 };
 720
 721 /*
 722  * Rcv Descriptor Context. One such per Rcv Descriptor. There may
 723  * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
 724  */
 725 struct nx_host_rds_ring {
 726         u32 producer;
 727         u32 crb_rcv_producer;
 728         u32 num_desc;
 729         u32 dma_size;
 730         u32 skb_size;
 731         u32 flags;
 732         struct rcv_desc *desc_head;
 733         struct netxen_rx_buffer *rx_buf_arr;
 734         struct list_head free_list;
 735         spinlock_t lock;
 736         dma_addr_t phys_addr;
 737 };
 738
 739 struct nx_host_sds_ring {
 740         u32 consumer;
 741         u32 crb_sts_consumer;
 742         u32 crb_intr_mask;
 743         u32 num_desc;
 744
 745         struct status_desc *desc_head;
 746         struct netxen_adapter *adapter;
 747         struct napi_struct napi;
 748         struct list_head free_list[NUM_RCV_DESC_RINGS];
 749
 750         int irq;
 751
 752         dma_addr_t phys_addr;
 753         char name[IFNAMSIZ+4];
 754 };
 755
 756 struct nx_host_tx_ring {
 757         u32 producer;
 758         __le32 *hw_consumer;
 759         u32 sw_consumer;
 760         u32 crb_cmd_producer;
 761         u32 crb_cmd_consumer;
 762         u32 num_desc;
 763
 764         struct netxen_cmd_buffer *cmd_buf_arr;
 765         struct cmd_desc_type0 *desc_head;
 766         dma_addr_t phys_addr;
 767 };
 768
 769 /*
 770  * Receive context. There is one such structure per instance of the
 771  * receive processing. Any state information that is relevant to
 772  * the receive, and is must be in this structure. The global data may be
 773  * present elsewhere.
 774  */
 775 struct netxen_recv_context {
 776         u32 state;
 777         u16 context_id;
 778         u16 virt_port;
 779
 780         struct nx_host_rds_ring *rds_rings;
 781         struct nx_host_sds_ring *sds_rings;
 782
 783         struct netxen_ring_ctx *hwctx;
 784         dma_addr_t phys_addr;
 785 };
 786
 787 /* New HW context creation */
 788
 789 #define NX_OS_CRB_RETRY_COUNT   4000
 790 #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \
 791         (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
 792
 793 #define NX_CDRP_CLEAR           0x00000000
 794 #define NX_CDRP_CMD_BIT         0x80000000
 795
 796 /*
 797  * All responses must have the NX_CDRP_CMD_BIT cleared
 798  * in the crb NX_CDRP_CRB_OFFSET.
 799  */
 800 #define NX_CDRP_FORM_RSP(rsp)   (rsp)
 801 #define NX_CDRP_IS_RSP(rsp)     (((rsp) & NX_CDRP_CMD_BIT) == 0)
 802
 803 #define NX_CDRP_RSP_OK          0x00000001
 804 #define NX_CDRP_RSP_FAIL        0x00000002
 805 #define NX_CDRP_RSP_TIMEOUT     0x00000003
 806
 807 /*
 808  * All commands must have the NX_CDRP_CMD_BIT set in
 809  * the crb NX_CDRP_CRB_OFFSET.
 810  */
 811 #define NX_CDRP_FORM_CMD(cmd)   (NX_CDRP_CMD_BIT | (cmd))
 812 #define NX_CDRP_IS_CMD(cmd)     (((cmd) & NX_CDRP_CMD_BIT) != 0)
 813
 814 #define NX_CDRP_CMD_SUBMIT_CAPABILITIES     0x00000001
 815 #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX    0x00000002
 816 #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX    0x00000003
 817 #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX  0x00000004
 818 #define NX_CDRP_CMD_READ_MAX_RX_CTX         0x00000005
 819 #define NX_CDRP_CMD_READ_MAX_TX_CTX         0x00000006
 820 #define NX_CDRP_CMD_CREATE_RX_CTX           0x00000007
 821 #define NX_CDRP_CMD_DESTROY_RX_CTX          0x00000008
 822 #define NX_CDRP_CMD_CREATE_TX_CTX           0x00000009
 823 #define NX_CDRP_CMD_DESTROY_TX_CTX          0x0000000a
 824 #define NX_CDRP_CMD_SETUP_STATISTICS        0x0000000e
 825 #define NX_CDRP_CMD_GET_STATISTICS          0x0000000f
 826 #define NX_CDRP_CMD_DELETE_STATISTICS       0x00000010
 827 #define NX_CDRP_CMD_SET_MTU                 0x00000012
 828 #define NX_CDRP_CMD_MAX                     0x00000013
 829
 830 #define NX_RCODE_SUCCESS                0
 831 #define NX_RCODE_NO_HOST_MEM            1
 832 #define NX_RCODE_NO_HOST_RESOURCE       2
 833 #define NX_RCODE_NO_CARD_CRB            3
 834 #define NX_RCODE_NO_CARD_MEM            4
 835 #define NX_RCODE_NO_CARD_RESOURCE       5
 836 #define NX_RCODE_INVALID_ARGS           6
 837 #define NX_RCODE_INVALID_ACTION         7
 838 #define NX_RCODE_INVALID_STATE          8
 839 #define NX_RCODE_NOT_SUPPORTED          9
 840 #define NX_RCODE_NOT_PERMITTED          10
 841 #define NX_RCODE_NOT_READY              11
 842 #define NX_RCODE_DOES_NOT_EXIST         12
 843 #define NX_RCODE_ALREADY_EXISTS         13
 844 #define NX_RCODE_BAD_SIGNATURE          14
 845 #define NX_RCODE_CMD_NOT_IMPL           15
 846 #define NX_RCODE_CMD_INVALID            16
 847 #define NX_RCODE_TIMEOUT                17
 848 #define NX_RCODE_CMD_FAILED             18
 849 #define NX_RCODE_MAX_EXCEEDED           19
 850 #define NX_RCODE_MAX                    20
 851
 852 #define NX_DESTROY_CTX_RESET            0
 853 #define NX_DESTROY_CTX_D3_RESET         1
 854 #define NX_DESTROY_CTX_MAX              2
 855
 856 /*
 857  * Capabilities
 858  */
 859 #define NX_CAP_BIT(class, bit)          (1 << bit)
 860 #define NX_CAP0_LEGACY_CONTEXT          NX_CAP_BIT(0, 0)
 861 #define NX_CAP0_MULTI_CONTEXT           NX_CAP_BIT(0, 1)
 862 #define NX_CAP0_LEGACY_MN               NX_CAP_BIT(0, 2)
 863 #define NX_CAP0_LEGACY_MS               NX_CAP_BIT(0, 3)
 864 #define NX_CAP0_CUT_THROUGH             NX_CAP_BIT(0, 4)
 865 #define NX_CAP0_LRO                     NX_CAP_BIT(0, 5)
 866 #define NX_CAP0_LSO                     NX_CAP_BIT(0, 6)
 867 #define NX_CAP0_JUMBO_CONTIGUOUS        NX_CAP_BIT(0, 7)
 868 #define NX_CAP0_LRO_CONTIGUOUS          NX_CAP_BIT(0, 8)
 869
 870 /*
 871  * Context state
 872  */
 873 #define NX_HOST_CTX_STATE_FREED         0
 874 #define NX_HOST_CTX_STATE_ALLOCATED     1
 875 #define NX_HOST_CTX_STATE_ACTIVE        2
 876 #define NX_HOST_CTX_STATE_DISABLED      3
 877 #define NX_HOST_CTX_STATE_QUIESCED      4
 878 #define NX_HOST_CTX_STATE_MAX           5
 879
 880 /*
 881  * Rx context
 882  */
 883
 884 typedef struct {
 885         __le64 host_phys_addr;  /* Ring base addr */
 886         __le32 ring_size;               /* Ring entries */
 887         __le16 msi_index;
 888         __le16 rsvd;            /* Padding */
 889 } nx_hostrq_sds_ring_t;
 890
 891 typedef struct {
 892         __le64 host_phys_addr;  /* Ring base addr */
 893         __le64 buff_size;               /* Packet buffer size */
 894         __le32 ring_size;               /* Ring entries */
 895         __le32 ring_kind;               /* Class of ring */
 896 } nx_hostrq_rds_ring_t;
 897
 898 typedef struct {
 899         __le64 host_rsp_dma_addr;       /* Response dma'd here */
 900         __le32 capabilities[4]; /* Flag bit vector */
 901         __le32 host_int_crb_mode;       /* Interrupt crb usage */
 902         __le32 host_rds_crb_mode;       /* RDS crb usage */
 903         /* These ring offsets are relative to data[0] below */
 904         __le32 rds_ring_offset; /* Offset to RDS config */
 905         __le32 sds_ring_offset; /* Offset to SDS config */
 906         __le16 num_rds_rings;   /* Count of RDS rings */
 907         __le16 num_sds_rings;   /* Count of SDS rings */
 908         __le16 rsvd1;           /* Padding */
 909         __le16 rsvd2;           /* Padding */
 910         u8  reserved[128];      /* reserve space for future expansion*/
 911         /* MUST BE 64-bit aligned.
 912            The following is packed:
 913            - N hostrq_rds_rings
 914            - N hostrq_sds_rings */
 915         char data[0];
 916 } nx_hostrq_rx_ctx_t;
 917
 918 typedef struct {
 919         __le32 host_producer_crb;       /* Crb to use */
 920         __le32 rsvd1;           /* Padding */
 921 } nx_cardrsp_rds_ring_t;
 922
 923 typedef struct {
 924         __le32 host_consumer_crb;       /* Crb to use */
 925         __le32 interrupt_crb;   /* Crb to use */
 926 } nx_cardrsp_sds_ring_t;
 927
 928 typedef struct {
 929         /* These ring offsets are relative to data[0] below */
 930         __le32 rds_ring_offset; /* Offset to RDS config */
 931         __le32 sds_ring_offset; /* Offset to SDS config */
 932         __le32 host_ctx_state;  /* Starting State */
 933         __le32 num_fn_per_port; /* How many PCI fn share the port */
 934         __le16 num_rds_rings;   /* Count of RDS rings */
 935         __le16 num_sds_rings;   /* Count of SDS rings */
 936         __le16 context_id;              /* Handle for context */
 937         u8  phys_port;          /* Physical id of port */
 938         u8  virt_port;          /* Virtual/Logical id of port */
 939         u8  reserved[128];      /* save space for future expansion */
 940         /*  MUST BE 64-bit aligned.
 941            The following is packed:
 942            - N cardrsp_rds_rings
 943            - N cardrs_sds_rings */
 944         char data[0];
 945 } nx_cardrsp_rx_ctx_t;
 946
 947 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings)       \
 948         (sizeof(HOSTRQ_RX) +                                    \
 949         (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) +            \
 950         (sds_rings)*(sizeof(nx_hostrq_sds_ring_t)))
 951
 952 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings)     \
 953         (sizeof(CARDRSP_RX) +                                   \
 954         (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) +           \
 955         (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t)))
 956
 957 /*
 958  * Tx context
 959  */
 960
 961 typedef struct {
 962         __le64 host_phys_addr;  /* Ring base addr */
 963         __le32 ring_size;               /* Ring entries */
 964         __le32 rsvd;            /* Padding */
 965 } nx_hostrq_cds_ring_t;
 966
 967 typedef struct {
 968         __le64 host_rsp_dma_addr;       /* Response dma'd here */
 969         __le64 cmd_cons_dma_addr;       /*  */
 970         __le64 dummy_dma_addr;  /*  */
 971         __le32 capabilities[4]; /* Flag bit vector */
 972         __le32 host_int_crb_mode;       /* Interrupt crb usage */
 973         __le32 rsvd1;           /* Padding */
 974         __le16 rsvd2;           /* Padding */
 975         __le16 interrupt_ctl;
 976         __le16 msi_index;
 977         __le16 rsvd3;           /* Padding */
 978         nx_hostrq_cds_ring_t cds_ring;  /* Desc of cds ring */
 979         u8  reserved[128];      /* future expansion */
 980 } nx_hostrq_tx_ctx_t;
 981
 982 typedef struct {
 983         __le32 host_producer_crb;       /* Crb to use */
 984         __le32 interrupt_crb;   /* Crb to use */
 985 } nx_cardrsp_cds_ring_t;
 986
 987 typedef struct {
 988         __le32 host_ctx_state;  /* Starting state */
 989         __le16 context_id;              /* Handle for context */
 990         u8  phys_port;          /* Physical id of port */
 991         u8  virt_port;          /* Virtual/Logical id of port */
 992         nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
 993         u8  reserved[128];      /* future expansion */
 994 } nx_cardrsp_tx_ctx_t;
 995
 996 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX)     (sizeof(HOSTRQ_TX))
 997 #define SIZEOF_CARDRSP_TX(CARDRSP_TX)   (sizeof(CARDRSP_TX))
 998
 999 /* CRB */
1000
1001 #define NX_HOST_RDS_CRB_MODE_UNIQUE     0
1002 #define NX_HOST_RDS_CRB_MODE_SHARED     1
1003 #define NX_HOST_RDS_CRB_MODE_CUSTOM     2
1004 #define NX_HOST_RDS_CRB_MODE_MAX        3
1005
1006 #define NX_HOST_INT_CRB_MODE_UNIQUE     0
1007 #define NX_HOST_INT_CRB_MODE_SHARED     1
1008 #define NX_HOST_INT_CRB_MODE_NORX       2
1009 #define NX_HOST_INT_CRB_MODE_NOTX       3
1010 #define NX_HOST_INT_CRB_MODE_NORXTX     4
1011
1012
1013 /* MAC */
1014
1015 #define MC_COUNT_P2     16
1016 #define MC_COUNT_P3     38
1017
1018 #define NETXEN_MAC_NOOP 0
1019 #define NETXEN_MAC_ADD  1
1020 #define NETXEN_MAC_DEL  2
1021
1022 typedef struct nx_mac_list_s {
1023         struct list_head list;
1024         uint8_t mac_addr[ETH_ALEN+2];
1025 } nx_mac_list_t;
1026
1027 /*
1028  * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
1029  * adjusted based on configured MTU.
1030  */
1031 #define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3
1032 #define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256
1033 #define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64
1034 #define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4
1035
1036 #define NETXEN_NIC_INTR_DEFAULT                 0x04
1037
1038 typedef union {
1039         struct {
1040                 uint16_t        rx_packets;
1041                 uint16_t        rx_time_us;
1042                 uint16_t        tx_packets;
1043                 uint16_t        tx_time_us;
1044         } data;
1045         uint64_t                word;
1046 } nx_nic_intr_coalesce_data_t;
1047
1048 typedef struct {
1049         uint16_t                        stats_time_us;
1050         uint16_t                        rate_sample_time;
1051         uint16_t                        flags;
1052         uint16_t                        rsvd_1;
1053         uint32_t                        low_threshold;
1054         uint32_t                        high_threshold;
1055         nx_nic_intr_coalesce_data_t     normal;
1056         nx_nic_intr_coalesce_data_t     low;
1057         nx_nic_intr_coalesce_data_t     high;
1058         nx_nic_intr_coalesce_data_t     irq;
1059 } nx_nic_intr_coalesce_t;
1060
1061 #define NX_HOST_REQUEST         0x13
1062 #define NX_NIC_REQUEST          0x14
1063
1064 #define NX_MAC_EVENT            0x1
1065
1066 /*
1067  * Driver --> Firmware
1068  */
1069 #define NX_NIC_H2C_OPCODE_START                         0
1070 #define NX_NIC_H2C_OPCODE_CONFIG_RSS                    1
1071 #define NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL                2
1072 #define NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE          3
1073 #define NX_NIC_H2C_OPCODE_CONFIG_LED                    4
1074 #define NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS            5
1075 #define NX_NIC_H2C_OPCODE_CONFIG_L2_MAC                 6
1076 #define NX_NIC_H2C_OPCODE_LRO_REQUEST                   7
1077 #define NX_NIC_H2C_OPCODE_GET_SNMP_STATS                8
1078 #define NX_NIC_H2C_OPCODE_PROXY_START_REQUEST           9
1079 #define NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST            10
1080 #define NX_NIC_H2C_OPCODE_PROXY_SET_MTU                 11
1081 #define NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE     12
1082 #define NX_NIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST      13
1083 #define NX_NIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST       14
1084 #define NX_NIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST        15
1085 #define NX_NIC_H2C_OPCODE_GET_NET_STATS                 16
1086 #define NX_NIC_H2C_OPCODE_PROXY_UPDATE_P2V              17
1087 #define NX_NIC_H2C_OPCODE_CONFIG_IPADDR                 18
1088 #define NX_NIC_H2C_OPCODE_CONFIG_LOOPBACK               19
1089 #define NX_NIC_H2C_OPCODE_PROXY_STOP_DONE               20
1090 #define NX_NIC_H2C_OPCODE_GET_LINKEVENT                 21
1091 #define NX_NIC_C2C_OPCODE                               22
1092 #define NX_NIC_H2C_OPCODE_LAST                          23
1093
1094 /*
1095  * Firmware --> Driver
1096  */
1097
1098 #define NX_NIC_C2H_OPCODE_START                         128
1099 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_RESPONSE           129
1100 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE       130
1101 #define NX_NIC_C2H_OPCODE_CONFIG_MAC_RESPONSE           131
1102 #define NX_NIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE   132
1103 #define NX_NIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE        133
1104 #define NX_NIC_C2H_OPCODE_LRO_DELETE_RESPONSE           134
1105 #define NX_NIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE      135
1106 #define NX_NIC_C2H_OPCODE_GET_SNMP_STATS                136
1107 #define NX_NIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY        137
1108 #define NX_NIC_C2H_OPCODE_INSTALL_LICENSE_REPLY         138
1109 #define NX_NIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
1110 #define NX_NIC_C2H_OPCODE_GET_NET_STATS_RESPONSE        140
1111 #define NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE        141
1112 #define NX_NIC_C2H_OPCODE_LAST                          142
1113
1114 #define VPORT_MISS_MODE_DROP            0 /* drop all unmatched */
1115 #define VPORT_MISS_MODE_ACCEPT_ALL      1 /* accept all packets */
1116 #define VPORT_MISS_MODE_ACCEPT_MULTI    2 /* accept unmatched multicast */
1117
1118 #define NX_FW_CAPABILITY_LINK_NOTIFICATION      (1 << 5)
1119 #define NX_FW_CAPABILITY_SWITCHING              (1 << 6)
1120
1121 /* module types */
1122 #define LINKEVENT_MODULE_NOT_PRESENT                    1
1123 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN                2
1124 #define LINKEVENT_MODULE_OPTICAL_SRLR                   3
1125 #define LINKEVENT_MODULE_OPTICAL_LRM                    4
1126 #define LINKEVENT_MODULE_OPTICAL_SFP_1G                 5
1127 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE       6
1128 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN    7
1129 #define LINKEVENT_MODULE_TWINAX                         8
1130
1131 #define LINKSPEED_10GBPS        10000
1132 #define LINKSPEED_1GBPS         1000
1133 #define LINKSPEED_100MBPS       100
1134 #define LINKSPEED_10MBPS        10
1135
1136 #define LINKSPEED_ENCODED_10MBPS        0
1137 #define LINKSPEED_ENCODED_100MBPS       1
1138 #define LINKSPEED_ENCODED_1GBPS         2
1139
1140 #define LINKEVENT_AUTONEG_DISABLED      0
1141 #define LINKEVENT_AUTONEG_ENABLED       1
1142
1143 #define LINKEVENT_HALF_DUPLEX           0
1144 #define LINKEVENT_FULL_DUPLEX           1
1145
1146 #define LINKEVENT_LINKSPEED_MBPS        0
1147 #define LINKEVENT_LINKSPEED_ENCODED     1
1148
1149 /* firmware response header:
1150  *      63:58 - message type
1151  *      57:56 - owner
1152  *      55:53 - desc count
1153  *      52:48 - reserved
1154  *      47:40 - completion id
1155  *      39:32 - opcode
1156  *      31:16 - error code
1157  *      15:00 - reserved
1158  */
1159 #define netxen_get_nic_msgtype(msg_hdr) \
1160         ((msg_hdr >> 58) & 0x3F)
1161 #define netxen_get_nic_msg_compid(msg_hdr)      \
1162         ((msg_hdr >> 40) & 0xFF)
1163 #define netxen_get_nic_msg_opcode(msg_hdr)      \
1164         ((msg_hdr >> 32) & 0xFF)
1165 #define netxen_get_nic_msg_errcode(msg_hdr)     \
1166         ((msg_hdr >> 16) & 0xFFFF)
1167
1168 typedef struct {
1169         union {
1170                 struct {
1171                         u64 hdr;
1172                         u64 body[7];
1173                 };
1174                 u64 words[8];
1175         };
1176 } nx_fw_msg_t;
1177
1178 typedef struct {
1179         __le64 qhdr;
1180         __le64 req_hdr;
1181         __le64 words[6];
1182 } nx_nic_req_t;
1183
1184 typedef struct {
1185         u8 op;
1186         u8 tag;
1187         u8 mac_addr[6];
1188 } nx_mac_req_t;
1189
1190 #define MAX_PENDING_DESC_BLOCK_SIZE     64
1191
1192 #define NETXEN_NIC_MSI_ENABLED          0x02
1193 #define NETXEN_NIC_MSIX_ENABLED         0x04
1194 #define NETXEN_IS_MSI_FAMILY(adapter) \
1195         ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED))
1196
1197 #define MSIX_ENTRIES_PER_ADAPTER        NUM_STS_DESC_RINGS
1198 #define NETXEN_MSIX_TBL_SPACE           8192
1199 #define NETXEN_PCI_REG_MSIX_TBL         0x44
1200
1201 #define NETXEN_DB_MAPSIZE_BYTES         0x1000
1202
1203 #define NETXEN_NETDEV_WEIGHT 128
1204 #define NETXEN_ADAPTER_UP_MAGIC 777
1205 #define NETXEN_NIC_PEG_TUNE 0
1206
1207 struct netxen_dummy_dma {
1208         void *addr;
1209         dma_addr_t phys_addr;
1210 };
1211
1212 struct netxen_adapter {
1213         struct netxen_hardware_context ahw;
1214
1215         struct net_device *netdev;
1216         struct pci_dev *pdev;
1217         struct list_head mac_list;
1218
1219         u32 curr_window;
1220         u32 crb_win;
1221         rwlock_t adapter_lock;
1222
1223         spinlock_t tx_clean_lock;
1224
1225         u16 num_txd;
1226         u16 num_rxd;
1227         u16 num_jumbo_rxd;
1228         u16 num_lro_rxd;
1229
1230         u8 max_rds_rings;
1231         u8 max_sds_rings;
1232         u8 driver_mismatch;
1233         u8 msix_supported;
1234         u8 rx_csum;
1235         u8 pci_using_dac;
1236         u8 portnum;
1237         u8 physical_port;
1238
1239         u8 mc_enabled;
1240         u8 max_mc_count;
1241         u8 rss_supported;
1242         u8 resv2;
1243         u32 resv3;
1244
1245         u8 has_link_events;
1246         u8 resv1;
1247         u16 tx_context_id;
1248         u16 mtu;
1249         u16 is_up;
1250
1251         u16 link_speed;
1252         u16 link_duplex;
1253         u16 link_autoneg;
1254         u16 module_type;
1255
1256         u32 capabilities;
1257         u32 flags;
1258         u32 irq;
1259         u32 temp;
1260
1261         u32 msi_tgt_status;
1262         u32 resv4;
1263
1264         struct netxen_adapter_stats stats;
1265
1266         struct netxen_recv_context recv_ctx;
1267         struct nx_host_tx_ring *tx_ring;
1268
1269         int (*enable_phy_interrupts) (struct netxen_adapter *);
1270         int (*disable_phy_interrupts) (struct netxen_adapter *);
1271         int (*macaddr_set) (struct netxen_adapter *, u8 *);
1272         int (*set_mtu) (struct netxen_adapter *, int);
1273         int (*set_promisc) (struct netxen_adapter *, u32);
1274         void (*set_multi) (struct net_device *);
1275         int (*phy_read) (struct netxen_adapter *, long reg, u32 *);
1276         int (*phy_write) (struct netxen_adapter *, long reg, u32 val);
1277         int (*init_port) (struct netxen_adapter *, int);
1278         int (*stop_port) (struct netxen_adapter *);
1279
1280         u32 (*hw_read_wx)(struct netxen_adapter *, ulong);
1281         int (*hw_write_wx)(struct netxen_adapter *, ulong, u32);
1282         int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int);
1283         int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int);
1284         int (*pci_write_immediate)(struct netxen_adapter *, u64, u32);
1285         u32 (*pci_read_immediate)(struct netxen_adapter *, u64);
1286         unsigned long (*pci_set_window)(struct netxen_adapter *,
1287                         unsigned long long);
1288
1289         struct netxen_legacy_intr_set legacy_intr;
1290
1291         struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1292
1293         struct netxen_dummy_dma dummy_dma;
1294
1295         struct work_struct watchdog_task;
1296         struct timer_list watchdog_timer;
1297         struct work_struct  tx_timeout_task;
1298
1299         struct net_device_stats net_stats;
1300
1301         nx_nic_intr_coalesce_t coal;
1302
1303         u32 fw_major;
1304         u32 fw_version;
1305         const struct firmware *fw;
1306 };
1307
1308 /*
1309  * NetXen dma watchdog control structure
1310  *
1311  *      Bit 0           : enabled => R/O: 1 watchdog active, 0 inactive
1312  *      Bit 1           : disable_request => 1 req disable dma watchdog
1313  *      Bit 2           : enable_request =>  1 req enable dma watchdog
1314  *      Bit 3-31        : unused
1315  */
1316
1317 #define netxen_set_dma_watchdog_disable_req(config_word) \
1318         _netxen_set_bits(config_word, 1, 1, 1)
1319 #define netxen_set_dma_watchdog_enable_req(config_word) \
1320         _netxen_set_bits(config_word, 2, 1, 1)
1321 #define netxen_get_dma_watchdog_enabled(config_word) \
1322         ((config_word) & 0x1)
1323 #define netxen_get_dma_watchdog_disabled(config_word) \
1324         (((config_word) >> 1) & 0x1)
1325
1326 int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1327 int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1328 int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1329 int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1330 int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
1331                             __u32 * readval);
1332 int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
1333                              long reg, __u32 val);
1334
1335 /* Functions available from netxen_nic_hw.c */
1336 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
1337 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
1338
1339 int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr);
1340 int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr);
1341
1342 #define NXRD32(adapter, off) \
1343         (adapter->hw_read_wx(adapter, off))
1344 #define NXWR32(adapter, off, val) \
1345         (adapter->hw_write_wx(adapter, off, val))
1346
1347 int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1348 void netxen_nic_get_firmware_info(struct netxen_adapter *adapter);
1349 int netxen_nic_wol_supported(struct netxen_adapter *adapter);
1350
1351 u32 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off);
1352 int netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
1353                 ulong off, u32 data);
1354 int netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1355                 u64 off, void *data, int size);
1356 int netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1357                 u64 off, void *data, int size);
1358 int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1359                 u64 off, u32 data);
1360 u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off);
1361 void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1362                 u64 off, u32 data);
1363 u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off);
1364 unsigned long netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1365                 unsigned long long addr);
1366 void netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter,
1367                 u32 wndw);
1368
1369 u32 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off);
1370 int netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1371                 ulong off, u32 data);
1372 int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1373                 u64 off, void *data, int size);
1374 int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1375                 u64 off, void *data, int size);
1376 int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1377                 u64 off, u32 data);
1378 u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off);
1379 void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
1380                 u64 off, u32 data);
1381 u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off);
1382 unsigned long netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1383                 unsigned long long addr);
1384
1385 /* Functions from netxen_nic_init.c */
1386 void netxen_free_adapter_offload(struct netxen_adapter *adapter);
1387 int netxen_initialize_adapter_offload(struct netxen_adapter *adapter);
1388 int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
1389 int netxen_load_firmware(struct netxen_adapter *adapter);
1390 void netxen_request_firmware(struct netxen_adapter *adapter);
1391 void netxen_release_firmware(struct netxen_adapter *adapter);
1392 int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
1393
1394 int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1395 int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
1396                                 u8 *bytes, size_t size);
1397 int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
1398                                 u8 *bytes, size_t size);
1399 int netxen_flash_unlock(struct netxen_adapter *adapter);
1400 int netxen_backup_crbinit(struct netxen_adapter *adapter);
1401 int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
1402 int netxen_flash_erase_primary(struct netxen_adapter *adapter);
1403 void netxen_halt_pegs(struct netxen_adapter *adapter);
1404
1405 int netxen_rom_se(struct netxen_adapter *adapter, int addr);
1406
1407 int netxen_alloc_sw_resources(struct netxen_adapter *adapter);
1408 void netxen_free_sw_resources(struct netxen_adapter *adapter);
1409
1410 int netxen_alloc_hw_resources(struct netxen_adapter *adapter);
1411 void netxen_free_hw_resources(struct netxen_adapter *adapter);
1412
1413 void netxen_release_rx_buffers(struct netxen_adapter *adapter);
1414 void netxen_release_tx_buffers(struct netxen_adapter *adapter);
1415
1416 void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
1417 int netxen_init_firmware(struct netxen_adapter *adapter);
1418 void netxen_nic_clear_stats(struct netxen_adapter *adapter);
1419 void netxen_watchdog_task(struct work_struct *work);
1420 void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
1421                 struct nx_host_rds_ring *rds_ring);
1422 int netxen_process_cmd_ring(struct netxen_adapter *adapter);
1423 int netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max);
1424 void netxen_p2_nic_set_multi(struct net_device *netdev);
1425 void netxen_p3_nic_set_multi(struct net_device *netdev);
1426 void netxen_p3_free_mac_list(struct netxen_adapter *adapter);
1427 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32);
1428 int netxen_config_intr_coalesce(struct netxen_adapter *adapter);
1429 int netxen_config_rss(struct netxen_adapter *adapter, int enable);
1430 int netxen_linkevent_request(struct netxen_adapter *adapter, int enable);
1431 void netxen_advert_link_change(struct netxen_adapter *adapter, int linkup);
1432
1433 int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu);
1434 int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
1435
1436 int netxen_nic_set_mac(struct net_device *netdev, void *p);
1437 struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
1438
1439 void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
1440                 struct nx_host_tx_ring *tx_ring);
1441
1442 /*
1443  * NetXen Board information
1444  */
1445
1446 #define NETXEN_MAX_SHORT_NAME 32
1447 struct netxen_brdinfo {
1448         int brdtype;    /* type of board */
1449         long ports;             /* max no of physical ports */
1450         char short_name[NETXEN_MAX_SHORT_NAME];
1451 };
1452
1453 static const struct netxen_brdinfo netxen_boards[] = {
1454         {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
1455         {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
1456         {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
1457         {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
1458         {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
1459         {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
1460         {NETXEN_BRDTYPE_P3_REF_QG,  4, "Reference Quad Gig "},
1461         {NETXEN_BRDTYPE_P3_HMEZ,    2, "Dual XGb HMEZ"},
1462         {NETXEN_BRDTYPE_P3_10G_CX4_LP,   2, "Dual XGb CX4 LP"},
1463         {NETXEN_BRDTYPE_P3_4_GB,    4, "Quad Gig LP"},
1464         {NETXEN_BRDTYPE_P3_IMEZ,    2, "Dual XGb IMEZ"},
1465         {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
1466         {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
1467         {NETXEN_BRDTYPE_P3_XG_LOM,  2, "Dual XGb LOM"},
1468         {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"},
1469         {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"},
1470         {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"},
1471         {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
1472         {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
1473 };
1474
1475 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
1476
1477 static inline void get_brd_name_by_type(u32 type, char *name)
1478 {
1479         int i, found = 0;
1480         for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1481                 if (netxen_boards[i].brdtype == type) {
1482                         strcpy(name, netxen_boards[i].short_name);
1483                         found = 1;
1484                         break;
1485                 }
1486
1487         }
1488         if (!found)
1489                 name = "Unknown";
1490 }
1491
1492 static inline int
1493 dma_watchdog_shutdown_request(struct netxen_adapter *adapter)
1494 {
1495         u32 ctrl;
1496
1497         /* check if already inactive */
1498         ctrl = adapter->hw_read_wx(adapter,
1499                         NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL));
1500
1501         if (netxen_get_dma_watchdog_enabled(ctrl) == 0)
1502                 return 1;
1503
1504         /* Send the disable request */
1505         netxen_set_dma_watchdog_disable_req(ctrl);
1506         NXWR32(adapter, NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1507
1508         return 0;
1509 }
1510
1511 static inline int
1512 dma_watchdog_shutdown_poll_result(struct netxen_adapter *adapter)
1513 {
1514         u32 ctrl;
1515
1516         ctrl = adapter->hw_read_wx(adapter,
1517                         NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL));
1518
1519         return (netxen_get_dma_watchdog_enabled(ctrl) == 0);
1520 }
1521
1522 static inline int
1523 dma_watchdog_wakeup(struct netxen_adapter *adapter)
1524 {
1525         u32 ctrl;
1526
1527         ctrl = adapter->hw_read_wx(adapter,
1528                         NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL));
1529
1530         if (netxen_get_dma_watchdog_enabled(ctrl))
1531                 return 1;
1532
1533         /* send the wakeup request */
1534         netxen_set_dma_watchdog_enable_req(ctrl);
1535
1536         NXWR32(adapter, NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1537
1538         return 0;
1539 }
1540
1541
1542 static inline u32 netxen_tx_avail(struct nx_host_tx_ring *tx_ring)
1543 {
1544         smp_mb();
1545         return find_diff_among(tx_ring->producer,
1546                         tx_ring->sw_consumer, tx_ring->num_desc);
1547
1548 }
1549
1550 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1551 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1552 extern void netxen_change_ringparam(struct netxen_adapter *adapter);
1553 extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
1554                                 int *valp);
1555
1556 extern struct ethtool_ops netxen_nic_ethtool_ops;
1557
1558 #endif                          /* __NETXEN_NIC_H_ */