1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #include <linux/delay.h>
33 static s32
e1000_get_phy_cfg_done(struct e1000_hw
*hw
);
34 static s32
e1000_phy_force_speed_duplex(struct e1000_hw
*hw
);
35 static s32
e1000_set_d0_lplu_state(struct e1000_hw
*hw
, bool active
);
36 static s32
e1000_wait_autoneg(struct e1000_hw
*hw
);
37 static u32
e1000_get_phy_addr_for_bm_page(u32 page
, u32 reg
);
38 static s32
e1000_access_phy_wakeup_reg_bm(struct e1000_hw
*hw
, u32 offset
,
39 u16
*data
, bool read
);
40 static u32
e1000_get_phy_addr_for_hv_page(u32 page
);
41 static s32
e1000_access_phy_debug_regs_hv(struct e1000_hw
*hw
, u32 offset
,
42 u16
*data
, bool read
);
44 /* Cable length tables */
45 static const u16 e1000_m88_cable_length_table
[] =
46 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED
};
48 static const u16 e1000_igp_2_cable_length_table
[] =
49 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
50 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
51 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
52 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
53 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
54 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
55 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
57 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
58 ARRAY_SIZE(e1000_igp_2_cable_length_table)
60 #define BM_PHY_REG_PAGE(offset) \
61 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
62 #define BM_PHY_REG_NUM(offset) \
63 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
64 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
65 ~MAX_PHY_REG_ADDRESS)))
67 #define HV_INTC_FC_PAGE_START 768
68 #define I82578_ADDR_REG 29
69 #define I82577_ADDR_REG 16
70 #define I82577_CFG_REG 22
71 #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
72 #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */
73 #define I82577_CTRL_REG 23
74 #define I82577_CTRL_DOWNSHIFT_MASK (7 << 10)
76 /* 82577 specific PHY registers */
77 #define I82577_PHY_CTRL_2 18
78 #define I82577_PHY_STATUS_2 26
79 #define I82577_PHY_DIAG_STATUS 31
81 /* I82577 PHY Status 2 */
82 #define I82577_PHY_STATUS2_REV_POLARITY 0x0400
83 #define I82577_PHY_STATUS2_MDIX 0x0800
84 #define I82577_PHY_STATUS2_SPEED_MASK 0x0300
85 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
87 /* I82577 PHY Control 2 */
88 #define I82577_PHY_CTRL2_AUTO_MDIX 0x0400
89 #define I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200
91 /* I82577 PHY Diagnostics Status */
92 #define I82577_DSTATUS_CABLE_LENGTH 0x03FC
93 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
95 /* BM PHY Copper Specific Control 1 */
96 #define BM_CS_CTRL1 16
98 /* BM PHY Copper Specific Status */
99 #define BM_CS_STATUS 17
100 #define BM_CS_STATUS_LINK_UP 0x0400
101 #define BM_CS_STATUS_RESOLVED 0x0800
102 #define BM_CS_STATUS_SPEED_MASK 0xC000
103 #define BM_CS_STATUS_SPEED_1000 0x8000
105 #define HV_MUX_DATA_CTRL PHY_REG(776, 16)
106 #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
107 #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
110 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
111 * @hw: pointer to the HW structure
113 * Read the PHY management control register and check whether a PHY reset
114 * is blocked. If a reset is not blocked return 0, otherwise
115 * return E1000_BLK_PHY_RESET (12).
117 s32
e1000e_check_reset_block_generic(struct e1000_hw
*hw
)
123 return (manc
& E1000_MANC_BLK_PHY_RST_ON_IDE
) ?
124 E1000_BLK_PHY_RESET
: 0;
128 * e1000e_get_phy_id - Retrieve the PHY ID and revision
129 * @hw: pointer to the HW structure
131 * Reads the PHY registers and stores the PHY ID and possibly the PHY
132 * revision in the hardware structure.
134 s32
e1000e_get_phy_id(struct e1000_hw
*hw
)
136 struct e1000_phy_info
*phy
= &hw
->phy
;
141 if (!(phy
->ops
.read_phy_reg
))
144 while (retry_count
< 2) {
145 ret_val
= e1e_rphy(hw
, PHY_ID1
, &phy_id
);
149 phy
->id
= (u32
)(phy_id
<< 16);
151 ret_val
= e1e_rphy(hw
, PHY_ID2
, &phy_id
);
155 phy
->id
|= (u32
)(phy_id
& PHY_REVISION_MASK
);
156 phy
->revision
= (u32
)(phy_id
& ~PHY_REVISION_MASK
);
158 if (phy
->id
!= 0 && phy
->id
!= PHY_REVISION_MASK
)
162 * If the PHY ID is still unknown, we may have an 82577i
163 * without link. We will try again after setting Slow
164 * MDIC mode. No harm in trying again in this case since
165 * the PHY ID is unknown at this point anyway
167 ret_val
= e1000_set_mdio_slow_mode_hv(hw
, true);
174 /* Revert to MDIO fast mode, if applicable */
176 ret_val
= e1000_set_mdio_slow_mode_hv(hw
, false);
182 * e1000e_phy_reset_dsp - Reset PHY DSP
183 * @hw: pointer to the HW structure
185 * Reset the digital signal processor.
187 s32
e1000e_phy_reset_dsp(struct e1000_hw
*hw
)
191 ret_val
= e1e_wphy(hw
, M88E1000_PHY_GEN_CONTROL
, 0xC1);
195 return e1e_wphy(hw
, M88E1000_PHY_GEN_CONTROL
, 0);
199 * e1000e_read_phy_reg_mdic - Read MDI control register
200 * @hw: pointer to the HW structure
201 * @offset: register offset to be read
202 * @data: pointer to the read data
204 * Reads the MDI control register in the PHY at offset and stores the
205 * information read to data.
207 s32
e1000e_read_phy_reg_mdic(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
209 struct e1000_phy_info
*phy
= &hw
->phy
;
212 if (offset
> MAX_PHY_REG_ADDRESS
) {
213 hw_dbg(hw
, "PHY Address %d is out of range\n", offset
);
214 return -E1000_ERR_PARAM
;
218 * Set up Op-code, Phy Address, and register offset in the MDI
219 * Control register. The MAC will take care of interfacing with the
220 * PHY to retrieve the desired data.
222 mdic
= ((offset
<< E1000_MDIC_REG_SHIFT
) |
223 (phy
->addr
<< E1000_MDIC_PHY_SHIFT
) |
224 (E1000_MDIC_OP_READ
));
229 * Poll the ready bit to see if the MDI read completed
230 * Increasing the time out as testing showed failures with
233 for (i
= 0; i
< (E1000_GEN_POLL_TIMEOUT
* 3); i
++) {
236 if (mdic
& E1000_MDIC_READY
)
239 if (!(mdic
& E1000_MDIC_READY
)) {
240 hw_dbg(hw
, "MDI Read did not complete\n");
241 return -E1000_ERR_PHY
;
243 if (mdic
& E1000_MDIC_ERROR
) {
244 hw_dbg(hw
, "MDI Error\n");
245 return -E1000_ERR_PHY
;
253 * e1000e_write_phy_reg_mdic - Write MDI control register
254 * @hw: pointer to the HW structure
255 * @offset: register offset to write to
256 * @data: data to write to register at offset
258 * Writes data to MDI control register in the PHY at offset.
260 s32
e1000e_write_phy_reg_mdic(struct e1000_hw
*hw
, u32 offset
, u16 data
)
262 struct e1000_phy_info
*phy
= &hw
->phy
;
265 if (offset
> MAX_PHY_REG_ADDRESS
) {
266 hw_dbg(hw
, "PHY Address %d is out of range\n", offset
);
267 return -E1000_ERR_PARAM
;
271 * Set up Op-code, Phy Address, and register offset in the MDI
272 * Control register. The MAC will take care of interfacing with the
273 * PHY to retrieve the desired data.
275 mdic
= (((u32
)data
) |
276 (offset
<< E1000_MDIC_REG_SHIFT
) |
277 (phy
->addr
<< E1000_MDIC_PHY_SHIFT
) |
278 (E1000_MDIC_OP_WRITE
));
283 * Poll the ready bit to see if the MDI read completed
284 * Increasing the time out as testing showed failures with
287 for (i
= 0; i
< (E1000_GEN_POLL_TIMEOUT
* 3); i
++) {
290 if (mdic
& E1000_MDIC_READY
)
293 if (!(mdic
& E1000_MDIC_READY
)) {
294 hw_dbg(hw
, "MDI Write did not complete\n");
295 return -E1000_ERR_PHY
;
297 if (mdic
& E1000_MDIC_ERROR
) {
298 hw_dbg(hw
, "MDI Error\n");
299 return -E1000_ERR_PHY
;
306 * e1000e_read_phy_reg_m88 - Read m88 PHY register
307 * @hw: pointer to the HW structure
308 * @offset: register offset to be read
309 * @data: pointer to the read data
311 * Acquires semaphore, if necessary, then reads the PHY register at offset
312 * and storing the retrieved information in data. Release any acquired
313 * semaphores before exiting.
315 s32
e1000e_read_phy_reg_m88(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
319 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
323 ret_val
= e1000e_read_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
326 hw
->phy
.ops
.release_phy(hw
);
332 * e1000e_write_phy_reg_m88 - Write m88 PHY register
333 * @hw: pointer to the HW structure
334 * @offset: register offset to write to
335 * @data: data to write at register offset
337 * Acquires semaphore, if necessary, then writes the data to PHY register
338 * at the offset. Release any acquired semaphores before exiting.
340 s32
e1000e_write_phy_reg_m88(struct e1000_hw
*hw
, u32 offset
, u16 data
)
344 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
348 ret_val
= e1000e_write_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
351 hw
->phy
.ops
.release_phy(hw
);
357 * e1000e_read_phy_reg_igp - Read igp PHY register
358 * @hw: pointer to the HW structure
359 * @offset: register offset to be read
360 * @data: pointer to the read data
362 * Acquires semaphore, if necessary, then reads the PHY register at offset
363 * and storing the retrieved information in data. Release any acquired
364 * semaphores before exiting.
366 s32
e1000e_read_phy_reg_igp(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
370 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
374 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
375 ret_val
= e1000e_write_phy_reg_mdic(hw
,
376 IGP01E1000_PHY_PAGE_SELECT
,
379 hw
->phy
.ops
.release_phy(hw
);
384 ret_val
= e1000e_read_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
387 hw
->phy
.ops
.release_phy(hw
);
393 * e1000e_write_phy_reg_igp - Write igp PHY register
394 * @hw: pointer to the HW structure
395 * @offset: register offset to write to
396 * @data: data to write at register offset
398 * Acquires semaphore, if necessary, then writes the data to PHY register
399 * at the offset. Release any acquired semaphores before exiting.
401 s32
e1000e_write_phy_reg_igp(struct e1000_hw
*hw
, u32 offset
, u16 data
)
405 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
409 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
410 ret_val
= e1000e_write_phy_reg_mdic(hw
,
411 IGP01E1000_PHY_PAGE_SELECT
,
414 hw
->phy
.ops
.release_phy(hw
);
419 ret_val
= e1000e_write_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
422 hw
->phy
.ops
.release_phy(hw
);
428 * e1000e_read_kmrn_reg - Read kumeran register
429 * @hw: pointer to the HW structure
430 * @offset: register offset to be read
431 * @data: pointer to the read data
433 * Acquires semaphore, if necessary. Then reads the PHY register at offset
434 * using the kumeran interface. The information retrieved is stored in data.
435 * Release any acquired semaphores before exiting.
437 s32
e1000e_read_kmrn_reg(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
442 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
446 kmrnctrlsta
= ((offset
<< E1000_KMRNCTRLSTA_OFFSET_SHIFT
) &
447 E1000_KMRNCTRLSTA_OFFSET
) | E1000_KMRNCTRLSTA_REN
;
448 ew32(KMRNCTRLSTA
, kmrnctrlsta
);
452 kmrnctrlsta
= er32(KMRNCTRLSTA
);
453 *data
= (u16
)kmrnctrlsta
;
455 hw
->phy
.ops
.release_phy(hw
);
461 * e1000e_write_kmrn_reg - Write kumeran register
462 * @hw: pointer to the HW structure
463 * @offset: register offset to write to
464 * @data: data to write at register offset
466 * Acquires semaphore, if necessary. Then write the data to PHY register
467 * at the offset using the kumeran interface. Release any acquired semaphores
470 s32
e1000e_write_kmrn_reg(struct e1000_hw
*hw
, u32 offset
, u16 data
)
475 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
479 kmrnctrlsta
= ((offset
<< E1000_KMRNCTRLSTA_OFFSET_SHIFT
) &
480 E1000_KMRNCTRLSTA_OFFSET
) | data
;
481 ew32(KMRNCTRLSTA
, kmrnctrlsta
);
484 hw
->phy
.ops
.release_phy(hw
);
490 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
491 * @hw: pointer to the HW structure
493 * Sets up Carrier-sense on Transmit and downshift values.
495 s32
e1000_copper_link_setup_82577(struct e1000_hw
*hw
)
497 struct e1000_phy_info
*phy
= &hw
->phy
;
501 /* Enable CRS on TX. This must be set for half-duplex operation. */
502 ret_val
= phy
->ops
.read_phy_reg(hw
, I82577_CFG_REG
, &phy_data
);
506 phy_data
|= I82577_CFG_ASSERT_CRS_ON_TX
;
508 /* Enable downshift */
509 phy_data
|= I82577_CFG_ENABLE_DOWNSHIFT
;
511 ret_val
= phy
->ops
.write_phy_reg(hw
, I82577_CFG_REG
, phy_data
);
515 /* Set number of link attempts before downshift */
516 ret_val
= phy
->ops
.read_phy_reg(hw
, I82577_CTRL_REG
, &phy_data
);
519 phy_data
&= ~I82577_CTRL_DOWNSHIFT_MASK
;
520 ret_val
= phy
->ops
.write_phy_reg(hw
, I82577_CTRL_REG
, phy_data
);
527 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
528 * @hw: pointer to the HW structure
530 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
531 * and downshift values are set also.
533 s32
e1000e_copper_link_setup_m88(struct e1000_hw
*hw
)
535 struct e1000_phy_info
*phy
= &hw
->phy
;
539 /* Enable CRS on Tx. This must be set for half-duplex operation. */
540 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
544 /* For BM PHY this bit is downshift enable */
545 if (phy
->type
!= e1000_phy_bm
)
546 phy_data
|= M88E1000_PSCR_ASSERT_CRS_ON_TX
;
550 * MDI/MDI-X = 0 (default)
551 * 0 - Auto for all speeds
554 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
556 phy_data
&= ~M88E1000_PSCR_AUTO_X_MODE
;
560 phy_data
|= M88E1000_PSCR_MDI_MANUAL_MODE
;
563 phy_data
|= M88E1000_PSCR_MDIX_MANUAL_MODE
;
566 phy_data
|= M88E1000_PSCR_AUTO_X_1000T
;
570 phy_data
|= M88E1000_PSCR_AUTO_X_MODE
;
576 * disable_polarity_correction = 0 (default)
577 * Automatic Correction for Reversed Cable Polarity
581 phy_data
&= ~M88E1000_PSCR_POLARITY_REVERSAL
;
582 if (phy
->disable_polarity_correction
== 1)
583 phy_data
|= M88E1000_PSCR_POLARITY_REVERSAL
;
585 /* Enable downshift on BM (disabled by default) */
586 if (phy
->type
== e1000_phy_bm
)
587 phy_data
|= BME1000_PSCR_ENABLE_DOWNSHIFT
;
589 ret_val
= e1e_wphy(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
593 if ((phy
->type
== e1000_phy_m88
) &&
594 (phy
->revision
< E1000_REVISION_4
) &&
595 (phy
->id
!= BME1000_E_PHY_ID_R2
)) {
597 * Force TX_CLK in the Extended PHY Specific Control Register
600 ret_val
= e1e_rphy(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, &phy_data
);
604 phy_data
|= M88E1000_EPSCR_TX_CLK_25
;
606 if ((phy
->revision
== 2) &&
607 (phy
->id
== M88E1111_I_PHY_ID
)) {
608 /* 82573L PHY - set the downshift counter to 5x. */
609 phy_data
&= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK
;
610 phy_data
|= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X
;
612 /* Configure Master and Slave downshift values */
613 phy_data
&= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK
|
614 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK
);
615 phy_data
|= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X
|
616 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X
);
618 ret_val
= e1e_wphy(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, phy_data
);
623 if ((phy
->type
== e1000_phy_bm
) && (phy
->id
== BME1000_E_PHY_ID_R2
)) {
624 /* Set PHY page 0, register 29 to 0x0003 */
625 ret_val
= e1e_wphy(hw
, 29, 0x0003);
629 /* Set PHY page 0, register 30 to 0x0000 */
630 ret_val
= e1e_wphy(hw
, 30, 0x0000);
635 /* Commit the changes. */
636 ret_val
= e1000e_commit_phy(hw
);
638 hw_dbg(hw
, "Error committing the PHY changes\n");
642 if (phy
->type
== e1000_phy_82578
) {
643 ret_val
= phy
->ops
.read_phy_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
,
648 /* 82578 PHY - set the downshift count to 1x. */
649 phy_data
|= I82578_EPSCR_DOWNSHIFT_ENABLE
;
650 phy_data
&= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK
;
651 ret_val
= phy
->ops
.write_phy_reg(hw
, M88E1000_EXT_PHY_SPEC_CTRL
,
661 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
662 * @hw: pointer to the HW structure
664 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
667 s32
e1000e_copper_link_setup_igp(struct e1000_hw
*hw
)
669 struct e1000_phy_info
*phy
= &hw
->phy
;
673 ret_val
= e1000_phy_hw_reset(hw
);
675 hw_dbg(hw
, "Error resetting the PHY.\n");
680 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
681 * timeout issues when LFS is enabled.
685 /* disable lplu d0 during driver init */
686 ret_val
= e1000_set_d0_lplu_state(hw
, 0);
688 hw_dbg(hw
, "Error Disabling LPLU D0\n");
691 /* Configure mdi-mdix settings */
692 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CTRL
, &data
);
696 data
&= ~IGP01E1000_PSCR_AUTO_MDIX
;
700 data
&= ~IGP01E1000_PSCR_FORCE_MDI_MDIX
;
703 data
|= IGP01E1000_PSCR_FORCE_MDI_MDIX
;
707 data
|= IGP01E1000_PSCR_AUTO_MDIX
;
710 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CTRL
, data
);
714 /* set auto-master slave resolution settings */
715 if (hw
->mac
.autoneg
) {
717 * when autonegotiation advertisement is only 1000Mbps then we
718 * should disable SmartSpeed and enable Auto MasterSlave
719 * resolution as hardware default.
721 if (phy
->autoneg_advertised
== ADVERTISE_1000_FULL
) {
722 /* Disable SmartSpeed */
723 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
728 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
729 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
734 /* Set auto Master/Slave resolution process */
735 ret_val
= e1e_rphy(hw
, PHY_1000T_CTRL
, &data
);
739 data
&= ~CR_1000T_MS_ENABLE
;
740 ret_val
= e1e_wphy(hw
, PHY_1000T_CTRL
, data
);
745 ret_val
= e1e_rphy(hw
, PHY_1000T_CTRL
, &data
);
749 /* load defaults for future use */
750 phy
->original_ms_type
= (data
& CR_1000T_MS_ENABLE
) ?
751 ((data
& CR_1000T_MS_VALUE
) ?
752 e1000_ms_force_master
:
753 e1000_ms_force_slave
) :
756 switch (phy
->ms_type
) {
757 case e1000_ms_force_master
:
758 data
|= (CR_1000T_MS_ENABLE
| CR_1000T_MS_VALUE
);
760 case e1000_ms_force_slave
:
761 data
|= CR_1000T_MS_ENABLE
;
762 data
&= ~(CR_1000T_MS_VALUE
);
765 data
&= ~CR_1000T_MS_ENABLE
;
769 ret_val
= e1e_wphy(hw
, PHY_1000T_CTRL
, data
);
776 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
777 * @hw: pointer to the HW structure
779 * Reads the MII auto-neg advertisement register and/or the 1000T control
780 * register and if the PHY is already setup for auto-negotiation, then
781 * return successful. Otherwise, setup advertisement and flow control to
782 * the appropriate values for the wanted auto-negotiation.
784 static s32
e1000_phy_setup_autoneg(struct e1000_hw
*hw
)
786 struct e1000_phy_info
*phy
= &hw
->phy
;
788 u16 mii_autoneg_adv_reg
;
789 u16 mii_1000t_ctrl_reg
= 0;
791 phy
->autoneg_advertised
&= phy
->autoneg_mask
;
793 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
794 ret_val
= e1e_rphy(hw
, PHY_AUTONEG_ADV
, &mii_autoneg_adv_reg
);
798 if (phy
->autoneg_mask
& ADVERTISE_1000_FULL
) {
799 /* Read the MII 1000Base-T Control Register (Address 9). */
800 ret_val
= e1e_rphy(hw
, PHY_1000T_CTRL
, &mii_1000t_ctrl_reg
);
806 * Need to parse both autoneg_advertised and fc and set up
807 * the appropriate PHY registers. First we will parse for
808 * autoneg_advertised software override. Since we can advertise
809 * a plethora of combinations, we need to check each bit
814 * First we clear all the 10/100 mb speed bits in the Auto-Neg
815 * Advertisement Register (Address 4) and the 1000 mb speed bits in
816 * the 1000Base-T Control Register (Address 9).
818 mii_autoneg_adv_reg
&= ~(NWAY_AR_100TX_FD_CAPS
|
819 NWAY_AR_100TX_HD_CAPS
|
820 NWAY_AR_10T_FD_CAPS
|
821 NWAY_AR_10T_HD_CAPS
);
822 mii_1000t_ctrl_reg
&= ~(CR_1000T_HD_CAPS
| CR_1000T_FD_CAPS
);
824 hw_dbg(hw
, "autoneg_advertised %x\n", phy
->autoneg_advertised
);
826 /* Do we want to advertise 10 Mb Half Duplex? */
827 if (phy
->autoneg_advertised
& ADVERTISE_10_HALF
) {
828 hw_dbg(hw
, "Advertise 10mb Half duplex\n");
829 mii_autoneg_adv_reg
|= NWAY_AR_10T_HD_CAPS
;
832 /* Do we want to advertise 10 Mb Full Duplex? */
833 if (phy
->autoneg_advertised
& ADVERTISE_10_FULL
) {
834 hw_dbg(hw
, "Advertise 10mb Full duplex\n");
835 mii_autoneg_adv_reg
|= NWAY_AR_10T_FD_CAPS
;
838 /* Do we want to advertise 100 Mb Half Duplex? */
839 if (phy
->autoneg_advertised
& ADVERTISE_100_HALF
) {
840 hw_dbg(hw
, "Advertise 100mb Half duplex\n");
841 mii_autoneg_adv_reg
|= NWAY_AR_100TX_HD_CAPS
;
844 /* Do we want to advertise 100 Mb Full Duplex? */
845 if (phy
->autoneg_advertised
& ADVERTISE_100_FULL
) {
846 hw_dbg(hw
, "Advertise 100mb Full duplex\n");
847 mii_autoneg_adv_reg
|= NWAY_AR_100TX_FD_CAPS
;
850 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
851 if (phy
->autoneg_advertised
& ADVERTISE_1000_HALF
)
852 hw_dbg(hw
, "Advertise 1000mb Half duplex request denied!\n");
854 /* Do we want to advertise 1000 Mb Full Duplex? */
855 if (phy
->autoneg_advertised
& ADVERTISE_1000_FULL
) {
856 hw_dbg(hw
, "Advertise 1000mb Full duplex\n");
857 mii_1000t_ctrl_reg
|= CR_1000T_FD_CAPS
;
861 * Check for a software override of the flow control settings, and
862 * setup the PHY advertisement registers accordingly. If
863 * auto-negotiation is enabled, then software will have to set the
864 * "PAUSE" bits to the correct value in the Auto-Negotiation
865 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
868 * The possible values of the "fc" parameter are:
869 * 0: Flow control is completely disabled
870 * 1: Rx flow control is enabled (we can receive pause frames
871 * but not send pause frames).
872 * 2: Tx flow control is enabled (we can send pause frames
873 * but we do not support receiving pause frames).
874 * 3: Both Rx and Tx flow control (symmetric) are enabled.
875 * other: No software override. The flow control configuration
876 * in the EEPROM is used.
878 switch (hw
->fc
.current_mode
) {
881 * Flow control (Rx & Tx) is completely disabled by a
882 * software over-ride.
884 mii_autoneg_adv_reg
&= ~(NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
886 case e1000_fc_rx_pause
:
888 * Rx Flow control is enabled, and Tx Flow control is
889 * disabled, by a software over-ride.
891 * Since there really isn't a way to advertise that we are
892 * capable of Rx Pause ONLY, we will advertise that we
893 * support both symmetric and asymmetric Rx PAUSE. Later
894 * (in e1000e_config_fc_after_link_up) we will disable the
895 * hw's ability to send PAUSE frames.
897 mii_autoneg_adv_reg
|= (NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
899 case e1000_fc_tx_pause
:
901 * Tx Flow control is enabled, and Rx Flow control is
902 * disabled, by a software over-ride.
904 mii_autoneg_adv_reg
|= NWAY_AR_ASM_DIR
;
905 mii_autoneg_adv_reg
&= ~NWAY_AR_PAUSE
;
909 * Flow control (both Rx and Tx) is enabled by a software
912 mii_autoneg_adv_reg
|= (NWAY_AR_ASM_DIR
| NWAY_AR_PAUSE
);
915 hw_dbg(hw
, "Flow control param set incorrectly\n");
916 ret_val
= -E1000_ERR_CONFIG
;
920 ret_val
= e1e_wphy(hw
, PHY_AUTONEG_ADV
, mii_autoneg_adv_reg
);
924 hw_dbg(hw
, "Auto-Neg Advertising %x\n", mii_autoneg_adv_reg
);
926 if (phy
->autoneg_mask
& ADVERTISE_1000_FULL
) {
927 ret_val
= e1e_wphy(hw
, PHY_1000T_CTRL
, mii_1000t_ctrl_reg
);
934 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
935 * @hw: pointer to the HW structure
937 * Performs initial bounds checking on autoneg advertisement parameter, then
938 * configure to advertise the full capability. Setup the PHY to autoneg
939 * and restart the negotiation process between the link partner. If
940 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
942 static s32
e1000_copper_link_autoneg(struct e1000_hw
*hw
)
944 struct e1000_phy_info
*phy
= &hw
->phy
;
949 * Perform some bounds checking on the autoneg advertisement
952 phy
->autoneg_advertised
&= phy
->autoneg_mask
;
955 * If autoneg_advertised is zero, we assume it was not defaulted
956 * by the calling code so we set to advertise full capability.
958 if (phy
->autoneg_advertised
== 0)
959 phy
->autoneg_advertised
= phy
->autoneg_mask
;
961 hw_dbg(hw
, "Reconfiguring auto-neg advertisement params\n");
962 ret_val
= e1000_phy_setup_autoneg(hw
);
964 hw_dbg(hw
, "Error Setting up Auto-Negotiation\n");
967 hw_dbg(hw
, "Restarting Auto-Neg\n");
970 * Restart auto-negotiation by setting the Auto Neg Enable bit and
971 * the Auto Neg Restart bit in the PHY control register.
973 ret_val
= e1e_rphy(hw
, PHY_CONTROL
, &phy_ctrl
);
977 phy_ctrl
|= (MII_CR_AUTO_NEG_EN
| MII_CR_RESTART_AUTO_NEG
);
978 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, phy_ctrl
);
983 * Does the user want to wait for Auto-Neg to complete here, or
984 * check at a later time (for example, callback routine).
986 if (phy
->autoneg_wait_to_complete
) {
987 ret_val
= e1000_wait_autoneg(hw
);
989 hw_dbg(hw
, "Error while waiting for "
990 "autoneg to complete\n");
995 hw
->mac
.get_link_status
= 1;
1001 * e1000e_setup_copper_link - Configure copper link settings
1002 * @hw: pointer to the HW structure
1004 * Calls the appropriate function to configure the link for auto-neg or forced
1005 * speed and duplex. Then we check for link, once link is established calls
1006 * to configure collision distance and flow control are called. If link is
1007 * not established, we return -E1000_ERR_PHY (-2).
1009 s32
e1000e_setup_copper_link(struct e1000_hw
*hw
)
1014 if (hw
->mac
.autoneg
) {
1016 * Setup autoneg and flow control advertisement and perform
1019 ret_val
= e1000_copper_link_autoneg(hw
);
1024 * PHY will be set to 10H, 10F, 100H or 100F
1025 * depending on user settings.
1027 hw_dbg(hw
, "Forcing Speed and Duplex\n");
1028 ret_val
= e1000_phy_force_speed_duplex(hw
);
1030 hw_dbg(hw
, "Error Forcing Speed and Duplex\n");
1036 * Check link status. Wait up to 100 microseconds for link to become
1039 ret_val
= e1000e_phy_has_link_generic(hw
,
1040 COPPER_LINK_UP_LIMIT
,
1047 hw_dbg(hw
, "Valid link established!!!\n");
1048 e1000e_config_collision_dist(hw
);
1049 ret_val
= e1000e_config_fc_after_link_up(hw
);
1051 hw_dbg(hw
, "Unable to establish link!!!\n");
1058 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1059 * @hw: pointer to the HW structure
1061 * Calls the PHY setup function to force speed and duplex. Clears the
1062 * auto-crossover to force MDI manually. Waits for link and returns
1063 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1065 s32
e1000e_phy_force_speed_duplex_igp(struct e1000_hw
*hw
)
1067 struct e1000_phy_info
*phy
= &hw
->phy
;
1072 ret_val
= e1e_rphy(hw
, PHY_CONTROL
, &phy_data
);
1076 e1000e_phy_force_speed_duplex_setup(hw
, &phy_data
);
1078 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, phy_data
);
1083 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1084 * forced whenever speed and duplex are forced.
1086 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CTRL
, &phy_data
);
1090 phy_data
&= ~IGP01E1000_PSCR_AUTO_MDIX
;
1091 phy_data
&= ~IGP01E1000_PSCR_FORCE_MDI_MDIX
;
1093 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CTRL
, phy_data
);
1097 hw_dbg(hw
, "IGP PSCR: %X\n", phy_data
);
1101 if (phy
->autoneg_wait_to_complete
) {
1102 hw_dbg(hw
, "Waiting for forced speed/duplex link on IGP phy.\n");
1104 ret_val
= e1000e_phy_has_link_generic(hw
,
1112 hw_dbg(hw
, "Link taking longer than expected.\n");
1115 ret_val
= e1000e_phy_has_link_generic(hw
,
1127 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1128 * @hw: pointer to the HW structure
1130 * Calls the PHY setup function to force speed and duplex. Clears the
1131 * auto-crossover to force MDI manually. Resets the PHY to commit the
1132 * changes. If time expires while waiting for link up, we reset the DSP.
1133 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1134 * successful completion, else return corresponding error code.
1136 s32
e1000e_phy_force_speed_duplex_m88(struct e1000_hw
*hw
)
1138 struct e1000_phy_info
*phy
= &hw
->phy
;
1144 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1145 * forced whenever speed and duplex are forced.
1147 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1151 phy_data
&= ~M88E1000_PSCR_AUTO_X_MODE
;
1152 ret_val
= e1e_wphy(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1156 hw_dbg(hw
, "M88E1000 PSCR: %X\n", phy_data
);
1158 ret_val
= e1e_rphy(hw
, PHY_CONTROL
, &phy_data
);
1162 e1000e_phy_force_speed_duplex_setup(hw
, &phy_data
);
1164 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, phy_data
);
1168 /* Reset the phy to commit changes. */
1169 ret_val
= e1000e_commit_phy(hw
);
1173 if (phy
->autoneg_wait_to_complete
) {
1174 hw_dbg(hw
, "Waiting for forced speed/duplex link on M88 phy.\n");
1176 ret_val
= e1000e_phy_has_link_generic(hw
, PHY_FORCE_LIMIT
,
1183 * We didn't get link.
1184 * Reset the DSP and cross our fingers.
1186 ret_val
= e1e_wphy(hw
, M88E1000_PHY_PAGE_SELECT
,
1190 ret_val
= e1000e_phy_reset_dsp(hw
);
1196 ret_val
= e1000e_phy_has_link_generic(hw
, PHY_FORCE_LIMIT
,
1202 ret_val
= e1e_rphy(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, &phy_data
);
1207 * Resetting the phy means we need to re-force TX_CLK in the
1208 * Extended PHY Specific Control Register to 25MHz clock from
1209 * the reset value of 2.5MHz.
1211 phy_data
|= M88E1000_EPSCR_TX_CLK_25
;
1212 ret_val
= e1e_wphy(hw
, M88E1000_EXT_PHY_SPEC_CTRL
, phy_data
);
1217 * In addition, we must re-enable CRS on Tx for both half and full
1220 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1224 phy_data
|= M88E1000_PSCR_ASSERT_CRS_ON_TX
;
1225 ret_val
= e1e_wphy(hw
, M88E1000_PHY_SPEC_CTRL
, phy_data
);
1231 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1232 * @hw: pointer to the HW structure
1233 * @phy_ctrl: pointer to current value of PHY_CONTROL
1235 * Forces speed and duplex on the PHY by doing the following: disable flow
1236 * control, force speed/duplex on the MAC, disable auto speed detection,
1237 * disable auto-negotiation, configure duplex, configure speed, configure
1238 * the collision distance, write configuration to CTRL register. The
1239 * caller must write to the PHY_CONTROL register for these settings to
1242 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw
*hw
, u16
*phy_ctrl
)
1244 struct e1000_mac_info
*mac
= &hw
->mac
;
1247 /* Turn off flow control when forcing speed/duplex */
1248 hw
->fc
.current_mode
= e1000_fc_none
;
1250 /* Force speed/duplex on the mac */
1252 ctrl
|= (E1000_CTRL_FRCSPD
| E1000_CTRL_FRCDPX
);
1253 ctrl
&= ~E1000_CTRL_SPD_SEL
;
1255 /* Disable Auto Speed Detection */
1256 ctrl
&= ~E1000_CTRL_ASDE
;
1258 /* Disable autoneg on the phy */
1259 *phy_ctrl
&= ~MII_CR_AUTO_NEG_EN
;
1261 /* Forcing Full or Half Duplex? */
1262 if (mac
->forced_speed_duplex
& E1000_ALL_HALF_DUPLEX
) {
1263 ctrl
&= ~E1000_CTRL_FD
;
1264 *phy_ctrl
&= ~MII_CR_FULL_DUPLEX
;
1265 hw_dbg(hw
, "Half Duplex\n");
1267 ctrl
|= E1000_CTRL_FD
;
1268 *phy_ctrl
|= MII_CR_FULL_DUPLEX
;
1269 hw_dbg(hw
, "Full Duplex\n");
1272 /* Forcing 10mb or 100mb? */
1273 if (mac
->forced_speed_duplex
& E1000_ALL_100_SPEED
) {
1274 ctrl
|= E1000_CTRL_SPD_100
;
1275 *phy_ctrl
|= MII_CR_SPEED_100
;
1276 *phy_ctrl
&= ~(MII_CR_SPEED_1000
| MII_CR_SPEED_10
);
1277 hw_dbg(hw
, "Forcing 100mb\n");
1279 ctrl
&= ~(E1000_CTRL_SPD_1000
| E1000_CTRL_SPD_100
);
1280 *phy_ctrl
|= MII_CR_SPEED_10
;
1281 *phy_ctrl
&= ~(MII_CR_SPEED_1000
| MII_CR_SPEED_100
);
1282 hw_dbg(hw
, "Forcing 10mb\n");
1285 e1000e_config_collision_dist(hw
);
1291 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1292 * @hw: pointer to the HW structure
1293 * @active: boolean used to enable/disable lplu
1295 * Success returns 0, Failure returns 1
1297 * The low power link up (lplu) state is set to the power management level D3
1298 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1299 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1300 * is used during Dx states where the power conservation is most important.
1301 * During driver activity, SmartSpeed should be enabled so performance is
1304 s32
e1000e_set_d3_lplu_state(struct e1000_hw
*hw
, bool active
)
1306 struct e1000_phy_info
*phy
= &hw
->phy
;
1310 ret_val
= e1e_rphy(hw
, IGP02E1000_PHY_POWER_MGMT
, &data
);
1315 data
&= ~IGP02E1000_PM_D3_LPLU
;
1316 ret_val
= e1e_wphy(hw
, IGP02E1000_PHY_POWER_MGMT
, data
);
1320 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1321 * during Dx states where the power conservation is most
1322 * important. During driver activity we should enable
1323 * SmartSpeed, so performance is maintained.
1325 if (phy
->smart_speed
== e1000_smart_speed_on
) {
1326 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1331 data
|= IGP01E1000_PSCFR_SMART_SPEED
;
1332 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1336 } else if (phy
->smart_speed
== e1000_smart_speed_off
) {
1337 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1342 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1343 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
,
1348 } else if ((phy
->autoneg_advertised
== E1000_ALL_SPEED_DUPLEX
) ||
1349 (phy
->autoneg_advertised
== E1000_ALL_NOT_GIG
) ||
1350 (phy
->autoneg_advertised
== E1000_ALL_10_SPEED
)) {
1351 data
|= IGP02E1000_PM_D3_LPLU
;
1352 ret_val
= e1e_wphy(hw
, IGP02E1000_PHY_POWER_MGMT
, data
);
1356 /* When LPLU is enabled, we should disable SmartSpeed */
1357 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, &data
);
1361 data
&= ~IGP01E1000_PSCFR_SMART_SPEED
;
1362 ret_val
= e1e_wphy(hw
, IGP01E1000_PHY_PORT_CONFIG
, data
);
1369 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1370 * @hw: pointer to the HW structure
1372 * Success returns 0, Failure returns 1
1374 * A downshift is detected by querying the PHY link health.
1376 s32
e1000e_check_downshift(struct e1000_hw
*hw
)
1378 struct e1000_phy_info
*phy
= &hw
->phy
;
1380 u16 phy_data
, offset
, mask
;
1382 switch (phy
->type
) {
1384 case e1000_phy_gg82563
:
1385 case e1000_phy_82578
:
1386 case e1000_phy_82577
:
1387 offset
= M88E1000_PHY_SPEC_STATUS
;
1388 mask
= M88E1000_PSSR_DOWNSHIFT
;
1390 case e1000_phy_igp_2
:
1391 case e1000_phy_igp_3
:
1392 offset
= IGP01E1000_PHY_LINK_HEALTH
;
1393 mask
= IGP01E1000_PLHR_SS_DOWNGRADE
;
1396 /* speed downshift not supported */
1397 phy
->speed_downgraded
= 0;
1401 ret_val
= e1e_rphy(hw
, offset
, &phy_data
);
1404 phy
->speed_downgraded
= (phy_data
& mask
);
1410 * e1000_check_polarity_m88 - Checks the polarity.
1411 * @hw: pointer to the HW structure
1413 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1415 * Polarity is determined based on the PHY specific status register.
1417 static s32
e1000_check_polarity_m88(struct e1000_hw
*hw
)
1419 struct e1000_phy_info
*phy
= &hw
->phy
;
1423 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_STATUS
, &data
);
1426 phy
->cable_polarity
= (data
& M88E1000_PSSR_REV_POLARITY
)
1427 ? e1000_rev_polarity_reversed
1428 : e1000_rev_polarity_normal
;
1434 * e1000_check_polarity_igp - Checks the polarity.
1435 * @hw: pointer to the HW structure
1437 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1439 * Polarity is determined based on the PHY port status register, and the
1440 * current speed (since there is no polarity at 100Mbps).
1442 static s32
e1000_check_polarity_igp(struct e1000_hw
*hw
)
1444 struct e1000_phy_info
*phy
= &hw
->phy
;
1446 u16 data
, offset
, mask
;
1449 * Polarity is determined based on the speed of
1452 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_STATUS
, &data
);
1456 if ((data
& IGP01E1000_PSSR_SPEED_MASK
) ==
1457 IGP01E1000_PSSR_SPEED_1000MBPS
) {
1458 offset
= IGP01E1000_PHY_PCS_INIT_REG
;
1459 mask
= IGP01E1000_PHY_POLARITY_MASK
;
1462 * This really only applies to 10Mbps since
1463 * there is no polarity for 100Mbps (always 0).
1465 offset
= IGP01E1000_PHY_PORT_STATUS
;
1466 mask
= IGP01E1000_PSSR_POLARITY_REVERSED
;
1469 ret_val
= e1e_rphy(hw
, offset
, &data
);
1472 phy
->cable_polarity
= (data
& mask
)
1473 ? e1000_rev_polarity_reversed
1474 : e1000_rev_polarity_normal
;
1480 * e1000_wait_autoneg - Wait for auto-neg completion
1481 * @hw: pointer to the HW structure
1483 * Waits for auto-negotiation to complete or for the auto-negotiation time
1484 * limit to expire, which ever happens first.
1486 static s32
e1000_wait_autoneg(struct e1000_hw
*hw
)
1491 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1492 for (i
= PHY_AUTO_NEG_LIMIT
; i
> 0; i
--) {
1493 ret_val
= e1e_rphy(hw
, PHY_STATUS
, &phy_status
);
1496 ret_val
= e1e_rphy(hw
, PHY_STATUS
, &phy_status
);
1499 if (phy_status
& MII_SR_AUTONEG_COMPLETE
)
1505 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1512 * e1000e_phy_has_link_generic - Polls PHY for link
1513 * @hw: pointer to the HW structure
1514 * @iterations: number of times to poll for link
1515 * @usec_interval: delay between polling attempts
1516 * @success: pointer to whether polling was successful or not
1518 * Polls the PHY status register for link, 'iterations' number of times.
1520 s32
e1000e_phy_has_link_generic(struct e1000_hw
*hw
, u32 iterations
,
1521 u32 usec_interval
, bool *success
)
1526 for (i
= 0; i
< iterations
; i
++) {
1528 * Some PHYs require the PHY_STATUS register to be read
1529 * twice due to the link bit being sticky. No harm doing
1530 * it across the board.
1532 ret_val
= e1e_rphy(hw
, PHY_STATUS
, &phy_status
);
1535 ret_val
= e1e_rphy(hw
, PHY_STATUS
, &phy_status
);
1538 if (phy_status
& MII_SR_LINK_STATUS
)
1540 if (usec_interval
>= 1000)
1541 mdelay(usec_interval
/1000);
1543 udelay(usec_interval
);
1546 *success
= (i
< iterations
);
1552 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1553 * @hw: pointer to the HW structure
1555 * Reads the PHY specific status register to retrieve the cable length
1556 * information. The cable length is determined by averaging the minimum and
1557 * maximum values to get the "average" cable length. The m88 PHY has four
1558 * possible cable length values, which are:
1559 * Register Value Cable Length
1563 * 3 110 - 140 meters
1566 s32
e1000e_get_cable_length_m88(struct e1000_hw
*hw
)
1568 struct e1000_phy_info
*phy
= &hw
->phy
;
1570 u16 phy_data
, index
;
1572 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_STATUS
, &phy_data
);
1576 index
= (phy_data
& M88E1000_PSSR_CABLE_LENGTH
) >>
1577 M88E1000_PSSR_CABLE_LENGTH_SHIFT
;
1578 phy
->min_cable_length
= e1000_m88_cable_length_table
[index
];
1579 phy
->max_cable_length
= e1000_m88_cable_length_table
[index
+1];
1581 phy
->cable_length
= (phy
->min_cable_length
+ phy
->max_cable_length
) / 2;
1587 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1588 * @hw: pointer to the HW structure
1590 * The automatic gain control (agc) normalizes the amplitude of the
1591 * received signal, adjusting for the attenuation produced by the
1592 * cable. By reading the AGC registers, which represent the
1593 * combination of course and fine gain value, the value can be put
1594 * into a lookup table to obtain the approximate cable length
1597 s32
e1000e_get_cable_length_igp_2(struct e1000_hw
*hw
)
1599 struct e1000_phy_info
*phy
= &hw
->phy
;
1601 u16 phy_data
, i
, agc_value
= 0;
1602 u16 cur_agc_index
, max_agc_index
= 0;
1603 u16 min_agc_index
= IGP02E1000_CABLE_LENGTH_TABLE_SIZE
- 1;
1604 u16 agc_reg_array
[IGP02E1000_PHY_CHANNEL_NUM
] =
1605 {IGP02E1000_PHY_AGC_A
,
1606 IGP02E1000_PHY_AGC_B
,
1607 IGP02E1000_PHY_AGC_C
,
1608 IGP02E1000_PHY_AGC_D
};
1610 /* Read the AGC registers for all channels */
1611 for (i
= 0; i
< IGP02E1000_PHY_CHANNEL_NUM
; i
++) {
1612 ret_val
= e1e_rphy(hw
, agc_reg_array
[i
], &phy_data
);
1617 * Getting bits 15:9, which represent the combination of
1618 * course and fine gain values. The result is a number
1619 * that can be put into the lookup table to obtain the
1620 * approximate cable length.
1622 cur_agc_index
= (phy_data
>> IGP02E1000_AGC_LENGTH_SHIFT
) &
1623 IGP02E1000_AGC_LENGTH_MASK
;
1625 /* Array index bound check. */
1626 if ((cur_agc_index
>= IGP02E1000_CABLE_LENGTH_TABLE_SIZE
) ||
1627 (cur_agc_index
== 0))
1628 return -E1000_ERR_PHY
;
1630 /* Remove min & max AGC values from calculation. */
1631 if (e1000_igp_2_cable_length_table
[min_agc_index
] >
1632 e1000_igp_2_cable_length_table
[cur_agc_index
])
1633 min_agc_index
= cur_agc_index
;
1634 if (e1000_igp_2_cable_length_table
[max_agc_index
] <
1635 e1000_igp_2_cable_length_table
[cur_agc_index
])
1636 max_agc_index
= cur_agc_index
;
1638 agc_value
+= e1000_igp_2_cable_length_table
[cur_agc_index
];
1641 agc_value
-= (e1000_igp_2_cable_length_table
[min_agc_index
] +
1642 e1000_igp_2_cable_length_table
[max_agc_index
]);
1643 agc_value
/= (IGP02E1000_PHY_CHANNEL_NUM
- 2);
1645 /* Calculate cable length with the error range of +/- 10 meters. */
1646 phy
->min_cable_length
= ((agc_value
- IGP02E1000_AGC_RANGE
) > 0) ?
1647 (agc_value
- IGP02E1000_AGC_RANGE
) : 0;
1648 phy
->max_cable_length
= agc_value
+ IGP02E1000_AGC_RANGE
;
1650 phy
->cable_length
= (phy
->min_cable_length
+ phy
->max_cable_length
) / 2;
1656 * e1000e_get_phy_info_m88 - Retrieve PHY information
1657 * @hw: pointer to the HW structure
1659 * Valid for only copper links. Read the PHY status register (sticky read)
1660 * to verify that link is up. Read the PHY special control register to
1661 * determine the polarity and 10base-T extended distance. Read the PHY
1662 * special status register to determine MDI/MDIx and current speed. If
1663 * speed is 1000, then determine cable length, local and remote receiver.
1665 s32
e1000e_get_phy_info_m88(struct e1000_hw
*hw
)
1667 struct e1000_phy_info
*phy
= &hw
->phy
;
1672 if (hw
->phy
.media_type
!= e1000_media_type_copper
) {
1673 hw_dbg(hw
, "Phy info is only valid for copper media\n");
1674 return -E1000_ERR_CONFIG
;
1677 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
1682 hw_dbg(hw
, "Phy info is only valid if link is up\n");
1683 return -E1000_ERR_CONFIG
;
1686 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_CTRL
, &phy_data
);
1690 phy
->polarity_correction
= (phy_data
&
1691 M88E1000_PSCR_POLARITY_REVERSAL
);
1693 ret_val
= e1000_check_polarity_m88(hw
);
1697 ret_val
= e1e_rphy(hw
, M88E1000_PHY_SPEC_STATUS
, &phy_data
);
1701 phy
->is_mdix
= (phy_data
& M88E1000_PSSR_MDIX
);
1703 if ((phy_data
& M88E1000_PSSR_SPEED
) == M88E1000_PSSR_1000MBS
) {
1704 ret_val
= e1000_get_cable_length(hw
);
1708 ret_val
= e1e_rphy(hw
, PHY_1000T_STATUS
, &phy_data
);
1712 phy
->local_rx
= (phy_data
& SR_1000T_LOCAL_RX_STATUS
)
1713 ? e1000_1000t_rx_status_ok
1714 : e1000_1000t_rx_status_not_ok
;
1716 phy
->remote_rx
= (phy_data
& SR_1000T_REMOTE_RX_STATUS
)
1717 ? e1000_1000t_rx_status_ok
1718 : e1000_1000t_rx_status_not_ok
;
1720 /* Set values to "undefined" */
1721 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
1722 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
1723 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
1730 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1731 * @hw: pointer to the HW structure
1733 * Read PHY status to determine if link is up. If link is up, then
1734 * set/determine 10base-T extended distance and polarity correction. Read
1735 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1736 * determine on the cable length, local and remote receiver.
1738 s32
e1000e_get_phy_info_igp(struct e1000_hw
*hw
)
1740 struct e1000_phy_info
*phy
= &hw
->phy
;
1745 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
1750 hw_dbg(hw
, "Phy info is only valid if link is up\n");
1751 return -E1000_ERR_CONFIG
;
1754 phy
->polarity_correction
= 1;
1756 ret_val
= e1000_check_polarity_igp(hw
);
1760 ret_val
= e1e_rphy(hw
, IGP01E1000_PHY_PORT_STATUS
, &data
);
1764 phy
->is_mdix
= (data
& IGP01E1000_PSSR_MDIX
);
1766 if ((data
& IGP01E1000_PSSR_SPEED_MASK
) ==
1767 IGP01E1000_PSSR_SPEED_1000MBPS
) {
1768 ret_val
= e1000_get_cable_length(hw
);
1772 ret_val
= e1e_rphy(hw
, PHY_1000T_STATUS
, &data
);
1776 phy
->local_rx
= (data
& SR_1000T_LOCAL_RX_STATUS
)
1777 ? e1000_1000t_rx_status_ok
1778 : e1000_1000t_rx_status_not_ok
;
1780 phy
->remote_rx
= (data
& SR_1000T_REMOTE_RX_STATUS
)
1781 ? e1000_1000t_rx_status_ok
1782 : e1000_1000t_rx_status_not_ok
;
1784 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
1785 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
1786 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
1793 * e1000e_phy_sw_reset - PHY software reset
1794 * @hw: pointer to the HW structure
1796 * Does a software reset of the PHY by reading the PHY control register and
1797 * setting/write the control register reset bit to the PHY.
1799 s32
e1000e_phy_sw_reset(struct e1000_hw
*hw
)
1804 ret_val
= e1e_rphy(hw
, PHY_CONTROL
, &phy_ctrl
);
1808 phy_ctrl
|= MII_CR_RESET
;
1809 ret_val
= e1e_wphy(hw
, PHY_CONTROL
, phy_ctrl
);
1819 * e1000e_phy_hw_reset_generic - PHY hardware reset
1820 * @hw: pointer to the HW structure
1822 * Verify the reset block is not blocking us from resetting. Acquire
1823 * semaphore (if necessary) and read/set/write the device control reset
1824 * bit in the PHY. Wait the appropriate delay time for the device to
1825 * reset and release the semaphore (if necessary).
1827 s32
e1000e_phy_hw_reset_generic(struct e1000_hw
*hw
)
1829 struct e1000_phy_info
*phy
= &hw
->phy
;
1833 ret_val
= e1000_check_reset_block(hw
);
1837 ret_val
= phy
->ops
.acquire_phy(hw
);
1842 ew32(CTRL
, ctrl
| E1000_CTRL_PHY_RST
);
1845 udelay(phy
->reset_delay_us
);
1852 phy
->ops
.release_phy(hw
);
1854 return e1000_get_phy_cfg_done(hw
);
1858 * e1000e_get_cfg_done - Generic configuration done
1859 * @hw: pointer to the HW structure
1861 * Generic function to wait 10 milli-seconds for configuration to complete
1862 * and return success.
1864 s32
e1000e_get_cfg_done(struct e1000_hw
*hw
)
1871 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
1872 * @hw: pointer to the HW structure
1874 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
1876 s32
e1000e_phy_init_script_igp3(struct e1000_hw
*hw
)
1878 hw_dbg(hw
, "Running IGP 3 PHY init script\n");
1880 /* PHY init IGP 3 */
1881 /* Enable rise/fall, 10-mode work in class-A */
1882 e1e_wphy(hw
, 0x2F5B, 0x9018);
1883 /* Remove all caps from Replica path filter */
1884 e1e_wphy(hw
, 0x2F52, 0x0000);
1885 /* Bias trimming for ADC, AFE and Driver (Default) */
1886 e1e_wphy(hw
, 0x2FB1, 0x8B24);
1887 /* Increase Hybrid poly bias */
1888 e1e_wphy(hw
, 0x2FB2, 0xF8F0);
1889 /* Add 4% to Tx amplitude in Gig mode */
1890 e1e_wphy(hw
, 0x2010, 0x10B0);
1891 /* Disable trimming (TTT) */
1892 e1e_wphy(hw
, 0x2011, 0x0000);
1893 /* Poly DC correction to 94.6% + 2% for all channels */
1894 e1e_wphy(hw
, 0x20DD, 0x249A);
1895 /* ABS DC correction to 95.9% */
1896 e1e_wphy(hw
, 0x20DE, 0x00D3);
1897 /* BG temp curve trim */
1898 e1e_wphy(hw
, 0x28B4, 0x04CE);
1899 /* Increasing ADC OPAMP stage 1 currents to max */
1900 e1e_wphy(hw
, 0x2F70, 0x29E4);
1901 /* Force 1000 ( required for enabling PHY regs configuration) */
1902 e1e_wphy(hw
, 0x0000, 0x0140);
1903 /* Set upd_freq to 6 */
1904 e1e_wphy(hw
, 0x1F30, 0x1606);
1906 e1e_wphy(hw
, 0x1F31, 0xB814);
1907 /* Disable adaptive fixed FFE (Default) */
1908 e1e_wphy(hw
, 0x1F35, 0x002A);
1909 /* Enable FFE hysteresis */
1910 e1e_wphy(hw
, 0x1F3E, 0x0067);
1911 /* Fixed FFE for short cable lengths */
1912 e1e_wphy(hw
, 0x1F54, 0x0065);
1913 /* Fixed FFE for medium cable lengths */
1914 e1e_wphy(hw
, 0x1F55, 0x002A);
1915 /* Fixed FFE for long cable lengths */
1916 e1e_wphy(hw
, 0x1F56, 0x002A);
1917 /* Enable Adaptive Clip Threshold */
1918 e1e_wphy(hw
, 0x1F72, 0x3FB0);
1919 /* AHT reset limit to 1 */
1920 e1e_wphy(hw
, 0x1F76, 0xC0FF);
1921 /* Set AHT master delay to 127 msec */
1922 e1e_wphy(hw
, 0x1F77, 0x1DEC);
1923 /* Set scan bits for AHT */
1924 e1e_wphy(hw
, 0x1F78, 0xF9EF);
1925 /* Set AHT Preset bits */
1926 e1e_wphy(hw
, 0x1F79, 0x0210);
1927 /* Change integ_factor of channel A to 3 */
1928 e1e_wphy(hw
, 0x1895, 0x0003);
1929 /* Change prop_factor of channels BCD to 8 */
1930 e1e_wphy(hw
, 0x1796, 0x0008);
1931 /* Change cg_icount + enable integbp for channels BCD */
1932 e1e_wphy(hw
, 0x1798, 0xD008);
1934 * Change cg_icount + enable integbp + change prop_factor_master
1935 * to 8 for channel A
1937 e1e_wphy(hw
, 0x1898, 0xD918);
1938 /* Disable AHT in Slave mode on channel A */
1939 e1e_wphy(hw
, 0x187A, 0x0800);
1941 * Enable LPLU and disable AN to 1000 in non-D0a states,
1944 e1e_wphy(hw
, 0x0019, 0x008D);
1945 /* Enable restart AN on an1000_dis change */
1946 e1e_wphy(hw
, 0x001B, 0x2080);
1947 /* Enable wh_fifo read clock in 10/100 modes */
1948 e1e_wphy(hw
, 0x0014, 0x0045);
1949 /* Restart AN, Speed selection is 1000 */
1950 e1e_wphy(hw
, 0x0000, 0x1340);
1955 /* Internal function pointers */
1958 * e1000_get_phy_cfg_done - Generic PHY configuration done
1959 * @hw: pointer to the HW structure
1961 * Return success if silicon family did not implement a family specific
1962 * get_cfg_done function.
1964 static s32
e1000_get_phy_cfg_done(struct e1000_hw
*hw
)
1966 if (hw
->phy
.ops
.get_cfg_done
)
1967 return hw
->phy
.ops
.get_cfg_done(hw
);
1973 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
1974 * @hw: pointer to the HW structure
1976 * When the silicon family has not implemented a forced speed/duplex
1977 * function for the PHY, simply return 0.
1979 static s32
e1000_phy_force_speed_duplex(struct e1000_hw
*hw
)
1981 if (hw
->phy
.ops
.force_speed_duplex
)
1982 return hw
->phy
.ops
.force_speed_duplex(hw
);
1988 * e1000e_get_phy_type_from_id - Get PHY type from id
1989 * @phy_id: phy_id read from the phy
1991 * Returns the phy type from the id.
1993 enum e1000_phy_type
e1000e_get_phy_type_from_id(u32 phy_id
)
1995 enum e1000_phy_type phy_type
= e1000_phy_unknown
;
1998 case M88E1000_I_PHY_ID
:
1999 case M88E1000_E_PHY_ID
:
2000 case M88E1111_I_PHY_ID
:
2001 case M88E1011_I_PHY_ID
:
2002 phy_type
= e1000_phy_m88
;
2004 case IGP01E1000_I_PHY_ID
: /* IGP 1 & 2 share this */
2005 phy_type
= e1000_phy_igp_2
;
2007 case GG82563_E_PHY_ID
:
2008 phy_type
= e1000_phy_gg82563
;
2010 case IGP03E1000_E_PHY_ID
:
2011 phy_type
= e1000_phy_igp_3
;
2014 case IFE_PLUS_E_PHY_ID
:
2015 case IFE_C_E_PHY_ID
:
2016 phy_type
= e1000_phy_ife
;
2018 case BME1000_E_PHY_ID
:
2019 case BME1000_E_PHY_ID_R2
:
2020 phy_type
= e1000_phy_bm
;
2022 case I82578_E_PHY_ID
:
2023 phy_type
= e1000_phy_82578
;
2025 case I82577_E_PHY_ID
:
2026 phy_type
= e1000_phy_82577
;
2029 phy_type
= e1000_phy_unknown
;
2036 * e1000e_determine_phy_address - Determines PHY address.
2037 * @hw: pointer to the HW structure
2039 * This uses a trial and error method to loop through possible PHY
2040 * addresses. It tests each by reading the PHY ID registers and
2041 * checking for a match.
2043 s32
e1000e_determine_phy_address(struct e1000_hw
*hw
)
2045 s32 ret_val
= -E1000_ERR_PHY_TYPE
;
2048 enum e1000_phy_type phy_type
= e1000_phy_unknown
;
2051 for (phy_addr
= 0; phy_addr
< 4; phy_addr
++) {
2052 hw
->phy
.addr
= phy_addr
;
2053 e1000e_get_phy_id(hw
);
2054 phy_type
= e1000e_get_phy_type_from_id(hw
->phy
.id
);
2057 * If phy_type is valid, break - we found our
2060 if (phy_type
!= e1000_phy_unknown
) {
2066 } while ((ret_val
!= 0) && (i
< 100));
2072 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2073 * @page: page to access
2075 * Returns the phy address for the page requested.
2077 static u32
e1000_get_phy_addr_for_bm_page(u32 page
, u32 reg
)
2081 if ((page
>= 768) || (page
== 0 && reg
== 25) || (reg
== 31))
2088 * e1000e_write_phy_reg_bm - Write BM PHY register
2089 * @hw: pointer to the HW structure
2090 * @offset: register offset to write to
2091 * @data: data to write at register offset
2093 * Acquires semaphore, if necessary, then writes the data to PHY register
2094 * at the offset. Release any acquired semaphores before exiting.
2096 s32
e1000e_write_phy_reg_bm(struct e1000_hw
*hw
, u32 offset
, u16 data
)
2099 u32 page_select
= 0;
2100 u32 page
= offset
>> IGP_PAGE_SHIFT
;
2103 /* Page 800 works differently than the rest so it has its own func */
2104 if (page
== BM_WUC_PAGE
) {
2105 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
, &data
,
2110 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
2114 hw
->phy
.addr
= e1000_get_phy_addr_for_bm_page(page
, offset
);
2116 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
2118 * Page select is register 31 for phy address 1 and 22 for
2119 * phy address 2 and 3. Page select is shifted only for
2122 if (hw
->phy
.addr
== 1) {
2123 page_shift
= IGP_PAGE_SHIFT
;
2124 page_select
= IGP01E1000_PHY_PAGE_SELECT
;
2127 page_select
= BM_PHY_PAGE_SELECT
;
2130 /* Page is shifted left, PHY expects (page x 32) */
2131 ret_val
= e1000e_write_phy_reg_mdic(hw
, page_select
,
2132 (page
<< page_shift
));
2134 hw
->phy
.ops
.release_phy(hw
);
2139 ret_val
= e1000e_write_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
2142 hw
->phy
.ops
.release_phy(hw
);
2149 * e1000e_read_phy_reg_bm - Read BM PHY register
2150 * @hw: pointer to the HW structure
2151 * @offset: register offset to be read
2152 * @data: pointer to the read data
2154 * Acquires semaphore, if necessary, then reads the PHY register at offset
2155 * and storing the retrieved information in data. Release any acquired
2156 * semaphores before exiting.
2158 s32
e1000e_read_phy_reg_bm(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
2161 u32 page_select
= 0;
2162 u32 page
= offset
>> IGP_PAGE_SHIFT
;
2165 /* Page 800 works differently than the rest so it has its own func */
2166 if (page
== BM_WUC_PAGE
) {
2167 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
, data
,
2172 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
2176 hw
->phy
.addr
= e1000_get_phy_addr_for_bm_page(page
, offset
);
2178 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
2180 * Page select is register 31 for phy address 1 and 22 for
2181 * phy address 2 and 3. Page select is shifted only for
2184 if (hw
->phy
.addr
== 1) {
2185 page_shift
= IGP_PAGE_SHIFT
;
2186 page_select
= IGP01E1000_PHY_PAGE_SELECT
;
2189 page_select
= BM_PHY_PAGE_SELECT
;
2192 /* Page is shifted left, PHY expects (page x 32) */
2193 ret_val
= e1000e_write_phy_reg_mdic(hw
, page_select
,
2194 (page
<< page_shift
));
2196 hw
->phy
.ops
.release_phy(hw
);
2201 ret_val
= e1000e_read_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
2203 hw
->phy
.ops
.release_phy(hw
);
2210 * e1000e_read_phy_reg_bm2 - Read BM PHY register
2211 * @hw: pointer to the HW structure
2212 * @offset: register offset to be read
2213 * @data: pointer to the read data
2215 * Acquires semaphore, if necessary, then reads the PHY register at offset
2216 * and storing the retrieved information in data. Release any acquired
2217 * semaphores before exiting.
2219 s32
e1000e_read_phy_reg_bm2(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
2222 u16 page
= (u16
)(offset
>> IGP_PAGE_SHIFT
);
2224 /* Page 800 works differently than the rest so it has its own func */
2225 if (page
== BM_WUC_PAGE
) {
2226 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
, data
,
2231 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
2237 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
2239 /* Page is shifted left, PHY expects (page x 32) */
2240 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_PHY_PAGE_SELECT
,
2244 hw
->phy
.ops
.release_phy(hw
);
2249 ret_val
= e1000e_read_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
2251 hw
->phy
.ops
.release_phy(hw
);
2257 * e1000e_write_phy_reg_bm2 - Write BM PHY register
2258 * @hw: pointer to the HW structure
2259 * @offset: register offset to write to
2260 * @data: data to write at register offset
2262 * Acquires semaphore, if necessary, then writes the data to PHY register
2263 * at the offset. Release any acquired semaphores before exiting.
2265 s32
e1000e_write_phy_reg_bm2(struct e1000_hw
*hw
, u32 offset
, u16 data
)
2268 u16 page
= (u16
)(offset
>> IGP_PAGE_SHIFT
);
2270 /* Page 800 works differently than the rest so it has its own func */
2271 if (page
== BM_WUC_PAGE
) {
2272 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
, &data
,
2277 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
2283 if (offset
> MAX_PHY_MULTI_PAGE_REG
) {
2284 /* Page is shifted left, PHY expects (page x 32) */
2285 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_PHY_PAGE_SELECT
,
2289 hw
->phy
.ops
.release_phy(hw
);
2294 ret_val
= e1000e_write_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& offset
,
2297 hw
->phy
.ops
.release_phy(hw
);
2303 * e1000_access_phy_wakeup_reg_bm - Read BM PHY wakeup register
2304 * @hw: pointer to the HW structure
2305 * @offset: register offset to be read or written
2306 * @data: pointer to the data to read or write
2307 * @read: determines if operation is read or write
2309 * Acquires semaphore, if necessary, then reads the PHY register at offset
2310 * and storing the retrieved information in data. Release any acquired
2311 * semaphores before exiting. Note that procedure to read the wakeup
2312 * registers are different. It works as such:
2313 * 1) Set page 769, register 17, bit 2 = 1
2314 * 2) Set page to 800 for host (801 if we were manageability)
2315 * 3) Write the address using the address opcode (0x11)
2316 * 4) Read or write the data using the data opcode (0x12)
2317 * 5) Restore 769_17.2 to its original value
2319 static s32
e1000_access_phy_wakeup_reg_bm(struct e1000_hw
*hw
, u32 offset
,
2320 u16
*data
, bool read
)
2323 u16 reg
= BM_PHY_REG_NUM(offset
);
2325 u8 phy_acquired
= 1;
2328 /* Gig must be disabled for MDIO accesses to page 800 */
2329 if ((hw
->mac
.type
== e1000_pchlan
) &&
2330 (!(er32(PHY_CTRL
) & E1000_PHY_CTRL_GBE_DISABLE
)))
2331 hw_dbg(hw
, "Attempting to access page 800 while gig enabled\n");
2333 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
2339 /* All operations in this function are phy address 1 */
2343 e1000e_write_phy_reg_mdic(hw
, IGP01E1000_PHY_PAGE_SELECT
,
2344 (BM_WUC_ENABLE_PAGE
<< IGP_PAGE_SHIFT
));
2346 ret_val
= e1000e_read_phy_reg_mdic(hw
, BM_WUC_ENABLE_REG
, &phy_reg
);
2350 /* First clear bit 4 to avoid a power state change */
2351 phy_reg
&= ~(BM_WUC_HOST_WU_BIT
);
2352 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_WUC_ENABLE_REG
, phy_reg
);
2356 /* Write bit 2 = 1, and clear bit 4 to 769_17 */
2357 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_WUC_ENABLE_REG
,
2358 phy_reg
| BM_WUC_ENABLE_BIT
);
2362 /* Select page 800 */
2363 ret_val
= e1000e_write_phy_reg_mdic(hw
, IGP01E1000_PHY_PAGE_SELECT
,
2364 (BM_WUC_PAGE
<< IGP_PAGE_SHIFT
));
2366 /* Write the page 800 offset value using opcode 0x11 */
2367 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_WUC_ADDRESS_OPCODE
, reg
);
2372 /* Read the page 800 value using opcode 0x12 */
2373 ret_val
= e1000e_read_phy_reg_mdic(hw
, BM_WUC_DATA_OPCODE
,
2376 /* Read the page 800 value using opcode 0x12 */
2377 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_WUC_DATA_OPCODE
,
2385 * Restore 769_17.2 to its original value
2388 e1000e_write_phy_reg_mdic(hw
, IGP01E1000_PHY_PAGE_SELECT
,
2389 (BM_WUC_ENABLE_PAGE
<< IGP_PAGE_SHIFT
));
2391 /* Clear 769_17.2 */
2392 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_WUC_ENABLE_REG
, phy_reg
);
2395 if (phy_acquired
== 1)
2396 hw
->phy
.ops
.release_phy(hw
);
2401 * e1000e_commit_phy - Soft PHY reset
2402 * @hw: pointer to the HW structure
2404 * Performs a soft PHY reset on those that apply. This is a function pointer
2405 * entry point called by drivers.
2407 s32
e1000e_commit_phy(struct e1000_hw
*hw
)
2409 if (hw
->phy
.ops
.commit_phy
)
2410 return hw
->phy
.ops
.commit_phy(hw
);
2416 * e1000_set_d0_lplu_state - Sets low power link up state for D0
2417 * @hw: pointer to the HW structure
2418 * @active: boolean used to enable/disable lplu
2420 * Success returns 0, Failure returns 1
2422 * The low power link up (lplu) state is set to the power management level D0
2423 * and SmartSpeed is disabled when active is true, else clear lplu for D0
2424 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2425 * is used during Dx states where the power conservation is most important.
2426 * During driver activity, SmartSpeed should be enabled so performance is
2427 * maintained. This is a function pointer entry point called by drivers.
2429 static s32
e1000_set_d0_lplu_state(struct e1000_hw
*hw
, bool active
)
2431 if (hw
->phy
.ops
.set_d0_lplu_state
)
2432 return hw
->phy
.ops
.set_d0_lplu_state(hw
, active
);
2437 s32
e1000_set_mdio_slow_mode_hv(struct e1000_hw
*hw
, bool slow
)
2442 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
2446 /* Set MDIO mode - page 769, register 16: 0x2580==slow, 0x2180==fast */
2448 ret_val
= e1000e_write_phy_reg_mdic(hw
, IGP01E1000_PHY_PAGE_SELECT
,
2449 (BM_PORT_CTRL_PAGE
<< IGP_PAGE_SHIFT
));
2451 hw
->phy
.ops
.release_phy(hw
);
2454 ret_val
= e1000e_write_phy_reg_mdic(hw
, BM_CS_CTRL1
,
2455 (0x2180 | (slow
<< 10)));
2457 /* dummy read when reverting to fast mode - throw away result */
2459 e1000e_read_phy_reg_mdic(hw
, BM_CS_CTRL1
, &data
);
2461 hw
->phy
.ops
.release_phy(hw
);
2467 * e1000_read_phy_reg_hv - Read HV PHY register
2468 * @hw: pointer to the HW structure
2469 * @offset: register offset to be read
2470 * @data: pointer to the read data
2472 * Acquires semaphore, if necessary, then reads the PHY register at offset
2473 * and storing the retrieved information in data. Release any acquired
2474 * semaphore before exiting.
2476 s32
e1000_read_phy_reg_hv(struct e1000_hw
*hw
, u32 offset
, u16
*data
)
2479 u16 page
= BM_PHY_REG_PAGE(offset
);
2480 u16 reg
= BM_PHY_REG_NUM(offset
);
2481 bool in_slow_mode
= false;
2483 /* Workaround failure in MDIO access while cable is disconnected */
2484 if ((hw
->phy
.type
== e1000_phy_82577
) &&
2485 !(er32(STATUS
) & E1000_STATUS_LU
)) {
2486 ret_val
= e1000_set_mdio_slow_mode_hv(hw
, true);
2490 in_slow_mode
= true;
2493 /* Page 800 works differently than the rest so it has its own func */
2494 if (page
== BM_WUC_PAGE
) {
2495 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
,
2500 if (page
> 0 && page
< HV_INTC_FC_PAGE_START
) {
2501 ret_val
= e1000_access_phy_debug_regs_hv(hw
, offset
,
2506 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
2510 hw
->phy
.addr
= e1000_get_phy_addr_for_hv_page(page
);
2512 if (page
== HV_INTC_FC_PAGE_START
)
2515 if (reg
> MAX_PHY_MULTI_PAGE_REG
) {
2516 if ((hw
->phy
.type
!= e1000_phy_82578
) ||
2517 ((reg
!= I82578_ADDR_REG
) &&
2518 (reg
!= I82578_ADDR_REG
+ 1))) {
2519 u32 phy_addr
= hw
->phy
.addr
;
2523 /* Page is shifted left, PHY expects (page x 32) */
2524 ret_val
= e1000e_write_phy_reg_mdic(hw
,
2525 IGP01E1000_PHY_PAGE_SELECT
,
2526 (page
<< IGP_PAGE_SHIFT
));
2528 hw
->phy
.ops
.release_phy(hw
);
2531 hw
->phy
.addr
= phy_addr
;
2535 ret_val
= e1000e_read_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& reg
,
2537 hw
->phy
.ops
.release_phy(hw
);
2540 /* Revert to MDIO fast mode, if applicable */
2541 if ((hw
->phy
.type
== e1000_phy_82577
) && in_slow_mode
)
2542 ret_val
= e1000_set_mdio_slow_mode_hv(hw
, false);
2548 * e1000_write_phy_reg_hv - Write HV PHY register
2549 * @hw: pointer to the HW structure
2550 * @offset: register offset to write to
2551 * @data: data to write at register offset
2553 * Acquires semaphore, if necessary, then writes the data to PHY register
2554 * at the offset. Release any acquired semaphores before exiting.
2556 s32
e1000_write_phy_reg_hv(struct e1000_hw
*hw
, u32 offset
, u16 data
)
2559 u16 page
= BM_PHY_REG_PAGE(offset
);
2560 u16 reg
= BM_PHY_REG_NUM(offset
);
2561 bool in_slow_mode
= false;
2563 /* Workaround failure in MDIO access while cable is disconnected */
2564 if ((hw
->phy
.type
== e1000_phy_82577
) &&
2565 !(er32(STATUS
) & E1000_STATUS_LU
)) {
2566 ret_val
= e1000_set_mdio_slow_mode_hv(hw
, true);
2570 in_slow_mode
= true;
2573 /* Page 800 works differently than the rest so it has its own func */
2574 if (page
== BM_WUC_PAGE
) {
2575 ret_val
= e1000_access_phy_wakeup_reg_bm(hw
, offset
,
2580 if (page
> 0 && page
< HV_INTC_FC_PAGE_START
) {
2581 ret_val
= e1000_access_phy_debug_regs_hv(hw
, offset
,
2586 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
2590 hw
->phy
.addr
= e1000_get_phy_addr_for_hv_page(page
);
2592 if (page
== HV_INTC_FC_PAGE_START
)
2596 * Workaround MDIO accesses being disabled after entering IEEE Power
2597 * Down (whenever bit 11 of the PHY Control register is set)
2599 if ((hw
->phy
.type
== e1000_phy_82578
) &&
2600 (hw
->phy
.revision
>= 1) &&
2601 (hw
->phy
.addr
== 2) &&
2602 ((MAX_PHY_REG_ADDRESS
& reg
) == 0) &&
2603 (data
& (1 << 11))) {
2605 hw
->phy
.ops
.release_phy(hw
);
2606 ret_val
= e1000_access_phy_debug_regs_hv(hw
, (1 << 6) | 0x3,
2611 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
2616 if (reg
> MAX_PHY_MULTI_PAGE_REG
) {
2617 if ((hw
->phy
.type
!= e1000_phy_82578
) ||
2618 ((reg
!= I82578_ADDR_REG
) &&
2619 (reg
!= I82578_ADDR_REG
+ 1))) {
2620 u32 phy_addr
= hw
->phy
.addr
;
2624 /* Page is shifted left, PHY expects (page x 32) */
2625 ret_val
= e1000e_write_phy_reg_mdic(hw
,
2626 IGP01E1000_PHY_PAGE_SELECT
,
2627 (page
<< IGP_PAGE_SHIFT
));
2629 hw
->phy
.ops
.release_phy(hw
);
2632 hw
->phy
.addr
= phy_addr
;
2636 ret_val
= e1000e_write_phy_reg_mdic(hw
, MAX_PHY_REG_ADDRESS
& reg
,
2638 hw
->phy
.ops
.release_phy(hw
);
2641 /* Revert to MDIO fast mode, if applicable */
2642 if ((hw
->phy
.type
== e1000_phy_82577
) && in_slow_mode
)
2643 ret_val
= e1000_set_mdio_slow_mode_hv(hw
, false);
2649 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page
2650 * @page: page to be accessed
2652 static u32
e1000_get_phy_addr_for_hv_page(u32 page
)
2656 if (page
>= HV_INTC_FC_PAGE_START
)
2663 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
2664 * @hw: pointer to the HW structure
2665 * @offset: register offset to be read or written
2666 * @data: pointer to the data to be read or written
2667 * @read: determines if operation is read or written
2669 * Acquires semaphore, if necessary, then reads the PHY register at offset
2670 * and storing the retreived information in data. Release any acquired
2671 * semaphores before exiting. Note that the procedure to read these regs
2672 * uses the address port and data port to read/write.
2674 static s32
e1000_access_phy_debug_regs_hv(struct e1000_hw
*hw
, u32 offset
,
2675 u16
*data
, bool read
)
2680 u8 phy_acquired
= 1;
2682 /* This takes care of the difference with desktop vs mobile phy */
2683 addr_reg
= (hw
->phy
.type
== e1000_phy_82578
) ?
2684 I82578_ADDR_REG
: I82577_ADDR_REG
;
2685 data_reg
= addr_reg
+ 1;
2687 ret_val
= hw
->phy
.ops
.acquire_phy(hw
);
2689 hw_dbg(hw
, "Could not acquire PHY\n");
2694 /* All operations in this function are phy address 2 */
2697 /* masking with 0x3F to remove the page from offset */
2698 ret_val
= e1000e_write_phy_reg_mdic(hw
, addr_reg
, (u16
)offset
& 0x3F);
2700 hw_dbg(hw
, "Could not write PHY the HV address register\n");
2704 /* Read or write the data value next */
2706 ret_val
= e1000e_read_phy_reg_mdic(hw
, data_reg
, data
);
2708 ret_val
= e1000e_write_phy_reg_mdic(hw
, data_reg
, *data
);
2711 hw_dbg(hw
, "Could not read data value from HV data register\n");
2716 if (phy_acquired
== 1)
2717 hw
->phy
.ops
.release_phy(hw
);
2722 * e1000_link_stall_workaround_hv - Si workaround
2723 * @hw: pointer to the HW structure
2725 * This function works around a Si bug where the link partner can get
2726 * a link up indication before the PHY does. If small packets are sent
2727 * by the link partner they can be placed in the packet buffer without
2728 * being properly accounted for by the PHY and will stall preventing
2729 * further packets from being received. The workaround is to clear the
2730 * packet buffer after the PHY detects link up.
2732 s32
e1000_link_stall_workaround_hv(struct e1000_hw
*hw
)
2737 if (hw
->phy
.type
!= e1000_phy_82578
)
2740 /* check if link is up and at 1Gbps */
2741 ret_val
= hw
->phy
.ops
.read_phy_reg(hw
, BM_CS_STATUS
, &data
);
2745 data
&= BM_CS_STATUS_LINK_UP
|
2746 BM_CS_STATUS_RESOLVED
|
2747 BM_CS_STATUS_SPEED_MASK
;
2749 if (data
!= (BM_CS_STATUS_LINK_UP
|
2750 BM_CS_STATUS_RESOLVED
|
2751 BM_CS_STATUS_SPEED_1000
))
2756 /* flush the packets in the fifo buffer */
2757 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
, HV_MUX_DATA_CTRL
,
2758 HV_MUX_DATA_CTRL_GEN_TO_MAC
|
2759 HV_MUX_DATA_CTRL_FORCE_SPEED
);
2763 ret_val
= hw
->phy
.ops
.write_phy_reg(hw
, HV_MUX_DATA_CTRL
,
2764 HV_MUX_DATA_CTRL_GEN_TO_MAC
);
2771 * e1000_check_polarity_82577 - Checks the polarity.
2772 * @hw: pointer to the HW structure
2774 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2776 * Polarity is determined based on the PHY specific status register.
2778 s32
e1000_check_polarity_82577(struct e1000_hw
*hw
)
2780 struct e1000_phy_info
*phy
= &hw
->phy
;
2784 ret_val
= phy
->ops
.read_phy_reg(hw
, I82577_PHY_STATUS_2
, &data
);
2787 phy
->cable_polarity
= (data
& I82577_PHY_STATUS2_REV_POLARITY
)
2788 ? e1000_rev_polarity_reversed
2789 : e1000_rev_polarity_normal
;
2795 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
2796 * @hw: pointer to the HW structure
2798 * Calls the PHY setup function to force speed and duplex. Clears the
2799 * auto-crossover to force MDI manually. Waits for link and returns
2800 * successful if link up is successful, else -E1000_ERR_PHY (-2).
2802 s32
e1000_phy_force_speed_duplex_82577(struct e1000_hw
*hw
)
2804 struct e1000_phy_info
*phy
= &hw
->phy
;
2809 ret_val
= phy
->ops
.read_phy_reg(hw
, PHY_CONTROL
, &phy_data
);
2813 e1000e_phy_force_speed_duplex_setup(hw
, &phy_data
);
2815 ret_val
= phy
->ops
.write_phy_reg(hw
, PHY_CONTROL
, phy_data
);
2820 * Clear Auto-Crossover to force MDI manually. 82577 requires MDI
2821 * forced whenever speed and duplex are forced.
2823 ret_val
= phy
->ops
.read_phy_reg(hw
, I82577_PHY_CTRL_2
, &phy_data
);
2827 phy_data
&= ~I82577_PHY_CTRL2_AUTO_MDIX
;
2828 phy_data
&= ~I82577_PHY_CTRL2_FORCE_MDI_MDIX
;
2830 ret_val
= phy
->ops
.write_phy_reg(hw
, I82577_PHY_CTRL_2
, phy_data
);
2834 hw_dbg(hw
, "I82577_PHY_CTRL_2: %X\n", phy_data
);
2838 if (phy
->autoneg_wait_to_complete
) {
2839 hw_dbg(hw
, "Waiting for forced speed/duplex link on 82577 phy\n");
2841 ret_val
= e1000e_phy_has_link_generic(hw
,
2849 hw_dbg(hw
, "Link taking longer than expected.\n");
2852 ret_val
= e1000e_phy_has_link_generic(hw
,
2865 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
2866 * @hw: pointer to the HW structure
2868 * Read PHY status to determine if link is up. If link is up, then
2869 * set/determine 10base-T extended distance and polarity correction. Read
2870 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2871 * determine on the cable length, local and remote receiver.
2873 s32
e1000_get_phy_info_82577(struct e1000_hw
*hw
)
2875 struct e1000_phy_info
*phy
= &hw
->phy
;
2880 ret_val
= e1000e_phy_has_link_generic(hw
, 1, 0, &link
);
2885 hw_dbg(hw
, "Phy info is only valid if link is up\n");
2886 ret_val
= -E1000_ERR_CONFIG
;
2890 phy
->polarity_correction
= true;
2892 ret_val
= e1000_check_polarity_82577(hw
);
2896 ret_val
= phy
->ops
.read_phy_reg(hw
, I82577_PHY_STATUS_2
, &data
);
2900 phy
->is_mdix
= (data
& I82577_PHY_STATUS2_MDIX
) ? true : false;
2902 if ((data
& I82577_PHY_STATUS2_SPEED_MASK
) ==
2903 I82577_PHY_STATUS2_SPEED_1000MBPS
) {
2904 ret_val
= hw
->phy
.ops
.get_cable_length(hw
);
2908 ret_val
= phy
->ops
.read_phy_reg(hw
, PHY_1000T_STATUS
, &data
);
2912 phy
->local_rx
= (data
& SR_1000T_LOCAL_RX_STATUS
)
2913 ? e1000_1000t_rx_status_ok
2914 : e1000_1000t_rx_status_not_ok
;
2916 phy
->remote_rx
= (data
& SR_1000T_REMOTE_RX_STATUS
)
2917 ? e1000_1000t_rx_status_ok
2918 : e1000_1000t_rx_status_not_ok
;
2920 phy
->cable_length
= E1000_CABLE_LENGTH_UNDEFINED
;
2921 phy
->local_rx
= e1000_1000t_rx_status_undefined
;
2922 phy
->remote_rx
= e1000_1000t_rx_status_undefined
;
2930 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
2931 * @hw: pointer to the HW structure
2933 * Reads the diagnostic status register and verifies result is valid before
2934 * placing it in the phy_cable_length field.
2936 s32
e1000_get_cable_length_82577(struct e1000_hw
*hw
)
2938 struct e1000_phy_info
*phy
= &hw
->phy
;
2940 u16 phy_data
, length
;
2942 ret_val
= phy
->ops
.read_phy_reg(hw
, I82577_PHY_DIAG_STATUS
, &phy_data
);
2946 length
= (phy_data
& I82577_DSTATUS_CABLE_LENGTH
) >>
2947 I82577_DSTATUS_CABLE_LENGTH_SHIFT
;
2949 if (length
== E1000_CABLE_LENGTH_UNDEFINED
)
2950 ret_val
= E1000_ERR_PHY
;
2952 phy
->cable_length
= length
;