1 #include <linux/errno.h>
2 #include <linux/kernel.h>
5 #include <linux/prctl.h>
6 #include <linux/slab.h>
7 #include <linux/sched.h>
8 #include <linux/module.h>
10 #include <linux/clockchips.h>
11 #include <linux/ftrace.h>
12 #include <asm/system.h>
15 #include <asm/uaccess.h>
18 unsigned long idle_halt
;
19 EXPORT_SYMBOL(idle_halt
);
20 unsigned long idle_nomwait
;
21 EXPORT_SYMBOL(idle_nomwait
);
23 struct kmem_cache
*task_xstate_cachep
;
25 int arch_dup_task_struct(struct task_struct
*dst
, struct task_struct
*src
)
28 if (src
->thread
.xstate
) {
29 dst
->thread
.xstate
= kmem_cache_alloc(task_xstate_cachep
,
31 if (!dst
->thread
.xstate
)
33 WARN_ON((unsigned long)dst
->thread
.xstate
& 15);
34 memcpy(dst
->thread
.xstate
, src
->thread
.xstate
, xstate_size
);
39 void free_thread_xstate(struct task_struct
*tsk
)
41 if (tsk
->thread
.xstate
) {
42 kmem_cache_free(task_xstate_cachep
, tsk
->thread
.xstate
);
43 tsk
->thread
.xstate
= NULL
;
47 void free_thread_info(struct thread_info
*ti
)
49 free_thread_xstate(ti
->task
);
50 free_pages((unsigned long)ti
, get_order(THREAD_SIZE
));
53 void arch_task_cache_init(void)
56 kmem_cache_create("task_xstate", xstate_size
,
57 __alignof__(union thread_xstate
),
62 * Free current thread data structures etc..
64 void exit_thread(void)
66 struct task_struct
*me
= current
;
67 struct thread_struct
*t
= &me
->thread
;
69 if (me
->thread
.io_bitmap_ptr
) {
70 struct tss_struct
*tss
= &per_cpu(init_tss
, get_cpu());
72 kfree(t
->io_bitmap_ptr
);
73 t
->io_bitmap_ptr
= NULL
;
74 clear_thread_flag(TIF_IO_BITMAP
);
76 * Careful, clear this in the TSS too:
78 memset(tss
->io_bitmap
, 0xff, t
->io_bitmap_max
);
83 ds_exit_thread(current
);
86 void flush_thread(void)
88 struct task_struct
*tsk
= current
;
91 if (test_tsk_thread_flag(tsk
, TIF_ABI_PENDING
)) {
92 clear_tsk_thread_flag(tsk
, TIF_ABI_PENDING
);
93 if (test_tsk_thread_flag(tsk
, TIF_IA32
)) {
94 clear_tsk_thread_flag(tsk
, TIF_IA32
);
96 set_tsk_thread_flag(tsk
, TIF_IA32
);
97 current_thread_info()->status
|= TS_COMPAT
;
102 clear_tsk_thread_flag(tsk
, TIF_DEBUG
);
104 tsk
->thread
.debugreg0
= 0;
105 tsk
->thread
.debugreg1
= 0;
106 tsk
->thread
.debugreg2
= 0;
107 tsk
->thread
.debugreg3
= 0;
108 tsk
->thread
.debugreg6
= 0;
109 tsk
->thread
.debugreg7
= 0;
110 memset(tsk
->thread
.tls_array
, 0, sizeof(tsk
->thread
.tls_array
));
112 * Forget coprocessor state..
114 tsk
->fpu_counter
= 0;
119 static void hard_disable_TSC(void)
121 write_cr4(read_cr4() | X86_CR4_TSD
);
124 void disable_TSC(void)
127 if (!test_and_set_thread_flag(TIF_NOTSC
))
129 * Must flip the CPU state synchronously with
130 * TIF_NOTSC in the current running context.
136 static void hard_enable_TSC(void)
138 write_cr4(read_cr4() & ~X86_CR4_TSD
);
141 static void enable_TSC(void)
144 if (test_and_clear_thread_flag(TIF_NOTSC
))
146 * Must flip the CPU state synchronously with
147 * TIF_NOTSC in the current running context.
153 int get_tsc_mode(unsigned long adr
)
157 if (test_thread_flag(TIF_NOTSC
))
158 val
= PR_TSC_SIGSEGV
;
162 return put_user(val
, (unsigned int __user
*)adr
);
165 int set_tsc_mode(unsigned int val
)
167 if (val
== PR_TSC_SIGSEGV
)
169 else if (val
== PR_TSC_ENABLE
)
177 void __switch_to_xtra(struct task_struct
*prev_p
, struct task_struct
*next_p
,
178 struct tss_struct
*tss
)
180 struct thread_struct
*prev
, *next
;
182 prev
= &prev_p
->thread
;
183 next
= &next_p
->thread
;
185 if (test_tsk_thread_flag(next_p
, TIF_DS_AREA_MSR
) ||
186 test_tsk_thread_flag(prev_p
, TIF_DS_AREA_MSR
))
187 ds_switch_to(prev_p
, next_p
);
188 else if (next
->debugctlmsr
!= prev
->debugctlmsr
)
189 update_debugctlmsr(next
->debugctlmsr
);
191 if (test_tsk_thread_flag(next_p
, TIF_DEBUG
)) {
192 set_debugreg(next
->debugreg0
, 0);
193 set_debugreg(next
->debugreg1
, 1);
194 set_debugreg(next
->debugreg2
, 2);
195 set_debugreg(next
->debugreg3
, 3);
197 set_debugreg(next
->debugreg6
, 6);
198 set_debugreg(next
->debugreg7
, 7);
201 if (test_tsk_thread_flag(prev_p
, TIF_NOTSC
) ^
202 test_tsk_thread_flag(next_p
, TIF_NOTSC
)) {
203 /* prev and next are different */
204 if (test_tsk_thread_flag(next_p
, TIF_NOTSC
))
210 if (test_tsk_thread_flag(next_p
, TIF_IO_BITMAP
)) {
212 * Copy the relevant range of the IO bitmap.
213 * Normally this is 128 bytes or less:
215 memcpy(tss
->io_bitmap
, next
->io_bitmap_ptr
,
216 max(prev
->io_bitmap_max
, next
->io_bitmap_max
));
217 } else if (test_tsk_thread_flag(prev_p
, TIF_IO_BITMAP
)) {
219 * Clear any possible leftover bits:
221 memset(tss
->io_bitmap
, 0xff, prev
->io_bitmap_max
);
225 int sys_fork(struct pt_regs
*regs
)
227 return do_fork(SIGCHLD
, regs
->sp
, regs
, 0, NULL
, NULL
);
231 * This is trivial, and on the face of it looks like it
232 * could equally well be done in user mode.
234 * Not so, for quite unobvious reasons - register pressure.
235 * In user mode vfork() cannot have a stack frame, and if
236 * done by calling the "clone()" system call directly, you
237 * do not have enough call-clobbered registers to hold all
238 * the information you need.
240 int sys_vfork(struct pt_regs
*regs
)
242 return do_fork(CLONE_VFORK
| CLONE_VM
| SIGCHLD
, regs
->sp
, regs
, 0,
248 * Idle related variables and functions
250 unsigned long boot_option_idle_override
= 0;
251 EXPORT_SYMBOL(boot_option_idle_override
);
254 * Powermanagement idle function, if any..
256 void (*pm_idle
)(void);
257 EXPORT_SYMBOL(pm_idle
);
261 * This halt magic was a workaround for ancient floppy DMA
262 * wreckage. It should be safe to remove.
264 static int hlt_counter
;
265 void disable_hlt(void)
269 EXPORT_SYMBOL(disable_hlt
);
271 void enable_hlt(void)
275 EXPORT_SYMBOL(enable_hlt
);
277 static inline int hlt_use_halt(void)
279 return (!hlt_counter
&& boot_cpu_data
.hlt_works_ok
);
282 static inline int hlt_use_halt(void)
289 * We use this if we don't have any better
292 void default_idle(void)
294 if (hlt_use_halt()) {
295 struct power_trace it
;
297 trace_power_start(&it
, POWER_CSTATE
, 1);
298 current_thread_info()->status
&= ~TS_POLLING
;
300 * TS_POLLING-cleared state must be visible before we
306 safe_halt(); /* enables interrupts racelessly */
309 current_thread_info()->status
|= TS_POLLING
;
310 trace_power_end(&it
);
313 /* loop is done by the caller */
317 #ifdef CONFIG_APM_MODULE
318 EXPORT_SYMBOL(default_idle
);
321 void stop_this_cpu(void *dummy
)
327 cpu_clear(smp_processor_id(), cpu_online_map
);
328 disable_local_APIC();
331 if (hlt_works(smp_processor_id()))
336 static void do_nothing(void *unused
)
341 * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
342 * pm_idle and update to new pm_idle value. Required while changing pm_idle
343 * handler on SMP systems.
345 * Caller must have changed pm_idle to the new value before the call. Old
346 * pm_idle value will not be used by any CPU after the return of this function.
348 void cpu_idle_wait(void)
351 /* kick all the CPUs so that they exit out of pm_idle */
352 smp_call_function(do_nothing
, NULL
, 1);
354 EXPORT_SYMBOL_GPL(cpu_idle_wait
);
357 * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
358 * which can obviate IPI to trigger checking of need_resched.
359 * We execute MONITOR against need_resched and enter optimized wait state
360 * through MWAIT. Whenever someone changes need_resched, we would be woken
361 * up from MWAIT (without an IPI).
363 * New with Core Duo processors, MWAIT can take some hints based on CPU
366 void mwait_idle_with_hints(unsigned long ax
, unsigned long cx
)
368 struct power_trace it
;
370 trace_power_start(&it
, POWER_CSTATE
, (ax
>>4)+1);
371 if (!need_resched()) {
372 if (cpu_has(¤t_cpu_data
, X86_FEATURE_CLFLUSH_MONITOR
))
373 clflush((void *)¤t_thread_info()->flags
);
375 __monitor((void *)¤t_thread_info()->flags
, 0, 0);
380 trace_power_end(&it
);
383 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
384 static void mwait_idle(void)
386 struct power_trace it
;
387 if (!need_resched()) {
388 trace_power_start(&it
, POWER_CSTATE
, 1);
389 if (cpu_has(¤t_cpu_data
, X86_FEATURE_CLFLUSH_MONITOR
))
390 clflush((void *)¤t_thread_info()->flags
);
392 __monitor((void *)¤t_thread_info()->flags
, 0, 0);
398 trace_power_end(&it
);
404 * On SMP it's slightly faster (but much more power-consuming!)
405 * to poll the ->work.need_resched flag instead of waiting for the
406 * cross-CPU IPI to arrive. Use this option with caution.
408 static void poll_idle(void)
410 struct power_trace it
;
412 trace_power_start(&it
, POWER_CSTATE
, 0);
414 while (!need_resched())
416 trace_power_end(&it
);
420 * mwait selection logic:
422 * It depends on the CPU. For AMD CPUs that support MWAIT this is
423 * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
424 * then depend on a clock divisor and current Pstate of the core. If
425 * all cores of a processor are in halt state (C1) the processor can
426 * enter the C1E (C1 enhanced) state. If mwait is used this will never
429 * idle=mwait overrides this decision and forces the usage of mwait.
431 static int __cpuinitdata force_mwait
;
433 #define MWAIT_INFO 0x05
434 #define MWAIT_ECX_EXTENDED_INFO 0x01
435 #define MWAIT_EDX_C1 0xf0
437 static int __cpuinit
mwait_usable(const struct cpuinfo_x86
*c
)
439 u32 eax
, ebx
, ecx
, edx
;
444 if (c
->cpuid_level
< MWAIT_INFO
)
447 cpuid(MWAIT_INFO
, &eax
, &ebx
, &ecx
, &edx
);
448 /* Check, whether EDX has extended info about MWAIT */
449 if (!(ecx
& MWAIT_ECX_EXTENDED_INFO
))
453 * edx enumeratios MONITOR/MWAIT extensions. Check, whether
456 return (edx
& MWAIT_EDX_C1
);
460 * Check for AMD CPUs, which have potentially C1E support
462 static int __cpuinit
check_c1e_idle(const struct cpuinfo_x86
*c
)
464 if (c
->x86_vendor
!= X86_VENDOR_AMD
)
470 /* Family 0x0f models < rev F do not have C1E */
471 if (c
->x86
== 0x0f && c
->x86_model
< 0x40)
477 static cpumask_t c1e_mask
= CPU_MASK_NONE
;
478 static int c1e_detected
;
480 void c1e_remove_cpu(int cpu
)
482 cpu_clear(cpu
, c1e_mask
);
486 * C1E aware idle routine. We check for C1E active in the interrupt
487 * pending message MSR. If we detect C1E, then we handle it the same
488 * way as C3 power states (local apic timer and TSC stop)
490 static void c1e_idle(void)
498 rdmsr(MSR_K8_INT_PENDING_MSG
, lo
, hi
);
499 if (lo
& K8_INTP_C1E_ACTIVE_MASK
) {
501 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC
))
502 mark_tsc_unstable("TSC halt in AMD C1E");
503 printk(KERN_INFO
"System has AMD C1E enabled\n");
504 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_AMDC1E
);
509 int cpu
= smp_processor_id();
511 if (!cpu_isset(cpu
, c1e_mask
)) {
512 cpu_set(cpu
, c1e_mask
);
514 * Force broadcast so ACPI can not interfere. Needs
515 * to run with interrupts enabled as it uses
519 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE
,
521 printk(KERN_INFO
"Switch to broadcast mode on CPU%d\n",
525 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER
, &cpu
);
530 * The switch back from broadcast mode needs to be
531 * called with interrupts disabled.
534 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT
, &cpu
);
540 void __cpuinit
select_idle_routine(const struct cpuinfo_x86
*c
)
543 if (pm_idle
== poll_idle
&& smp_num_siblings
> 1) {
544 printk(KERN_WARNING
"WARNING: polling idle and HT enabled,"
545 " performance may degrade.\n");
551 if (cpu_has(c
, X86_FEATURE_MWAIT
) && mwait_usable(c
)) {
553 * One CPU supports mwait => All CPUs supports mwait
555 printk(KERN_INFO
"using mwait in idle threads.\n");
556 pm_idle
= mwait_idle
;
557 } else if (check_c1e_idle(c
)) {
558 printk(KERN_INFO
"using C1E aware idle routine\n");
561 pm_idle
= default_idle
;
564 static int __init
idle_setup(char *str
)
569 if (!strcmp(str
, "poll")) {
570 printk("using polling idle threads.\n");
572 } else if (!strcmp(str
, "mwait"))
574 else if (!strcmp(str
, "halt")) {
576 * When the boot option of idle=halt is added, halt is
577 * forced to be used for CPU idle. In such case CPU C2/C3
578 * won't be used again.
579 * To continue to load the CPU idle driver, don't touch
580 * the boot_option_idle_override.
582 pm_idle
= default_idle
;
585 } else if (!strcmp(str
, "nomwait")) {
587 * If the boot option of "idle=nomwait" is added,
588 * it means that mwait will be disabled for CPU C2/C3
589 * states. In such case it won't touch the variable
590 * of boot_option_idle_override.
597 boot_option_idle_override
= 1;
600 early_param("idle", idle_setup
);