x86: add clflush before monitor for Intel 7400 series
[linux-2.6/mini2440.git] / arch / avr32 / mach-at32ap / hsmc.c
blob2875c11be95d5f232d2970e204695fbc83a526d3
1 /*
2 * Static Memory Controller for AT32 chips
4 * Copyright (C) 2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10 #include <linux/clk.h>
11 #include <linux/err.h>
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/platform_device.h>
16 #include <asm/io.h>
17 #include <mach/smc.h>
19 #include "hsmc.h"
21 #define NR_CHIP_SELECTS 6
23 struct hsmc {
24 void __iomem *regs;
25 struct clk *pclk;
26 struct clk *mck;
29 static struct hsmc *hsmc;
31 void smc_set_timing(struct smc_config *config,
32 const struct smc_timing *timing)
34 int recover;
35 int cycle;
37 unsigned long mul;
39 /* Reset all SMC timings */
40 config->ncs_read_setup = 0;
41 config->nrd_setup = 0;
42 config->ncs_write_setup = 0;
43 config->nwe_setup = 0;
44 config->ncs_read_pulse = 0;
45 config->nrd_pulse = 0;
46 config->ncs_write_pulse = 0;
47 config->nwe_pulse = 0;
48 config->read_cycle = 0;
49 config->write_cycle = 0;
52 * cycles = x / T = x * f
53 * = ((x * 1000000000) * ((f * 65536) / 1000000000)) / 65536
54 * = ((x * 1000000000) * (((f / 10000) * 65536) / 100000)) / 65536
56 mul = (clk_get_rate(hsmc->mck) / 10000) << 16;
57 mul /= 100000;
59 #define ns2cyc(x) ((((x) * mul) + 65535) >> 16)
61 if (timing->ncs_read_setup > 0)
62 config->ncs_read_setup = ns2cyc(timing->ncs_read_setup);
64 if (timing->nrd_setup > 0)
65 config->nrd_setup = ns2cyc(timing->nrd_setup);
67 if (timing->ncs_write_setup > 0)
68 config->ncs_write_setup = ns2cyc(timing->ncs_write_setup);
70 if (timing->nwe_setup > 0)
71 config->nwe_setup = ns2cyc(timing->nwe_setup);
73 if (timing->ncs_read_pulse > 0)
74 config->ncs_read_pulse = ns2cyc(timing->ncs_read_pulse);
76 if (timing->nrd_pulse > 0)
77 config->nrd_pulse = ns2cyc(timing->nrd_pulse);
79 if (timing->ncs_write_pulse > 0)
80 config->ncs_write_pulse = ns2cyc(timing->ncs_write_pulse);
82 if (timing->nwe_pulse > 0)
83 config->nwe_pulse = ns2cyc(timing->nwe_pulse);
85 if (timing->read_cycle > 0)
86 config->read_cycle = ns2cyc(timing->read_cycle);
88 if (timing->write_cycle > 0)
89 config->write_cycle = ns2cyc(timing->write_cycle);
91 /* Extend read cycle in needed */
92 if (timing->ncs_read_recover > 0)
93 recover = ns2cyc(timing->ncs_read_recover);
94 else
95 recover = 1;
97 cycle = config->ncs_read_setup + config->ncs_read_pulse + recover;
99 if (config->read_cycle < cycle)
100 config->read_cycle = cycle;
102 /* Extend read cycle in needed */
103 if (timing->nrd_recover > 0)
104 recover = ns2cyc(timing->nrd_recover);
105 else
106 recover = 1;
108 cycle = config->nrd_setup + config->nrd_pulse + recover;
110 if (config->read_cycle < cycle)
111 config->read_cycle = cycle;
113 /* Extend write cycle in needed */
114 if (timing->ncs_write_recover > 0)
115 recover = ns2cyc(timing->ncs_write_recover);
116 else
117 recover = 1;
119 cycle = config->ncs_write_setup + config->ncs_write_pulse + recover;
121 if (config->write_cycle < cycle)
122 config->write_cycle = cycle;
124 /* Extend write cycle in needed */
125 if (timing->nwe_recover > 0)
126 recover = ns2cyc(timing->nwe_recover);
127 else
128 recover = 1;
130 cycle = config->nwe_setup + config->nwe_pulse + recover;
132 if (config->write_cycle < cycle)
133 config->write_cycle = cycle;
135 EXPORT_SYMBOL(smc_set_timing);
137 int smc_set_configuration(int cs, const struct smc_config *config)
139 unsigned long offset;
140 u32 setup, pulse, cycle, mode;
142 if (!hsmc)
143 return -ENODEV;
144 if (cs >= NR_CHIP_SELECTS)
145 return -EINVAL;
147 setup = (HSMC_BF(NWE_SETUP, config->nwe_setup)
148 | HSMC_BF(NCS_WR_SETUP, config->ncs_write_setup)
149 | HSMC_BF(NRD_SETUP, config->nrd_setup)
150 | HSMC_BF(NCS_RD_SETUP, config->ncs_read_setup));
151 pulse = (HSMC_BF(NWE_PULSE, config->nwe_pulse)
152 | HSMC_BF(NCS_WR_PULSE, config->ncs_write_pulse)
153 | HSMC_BF(NRD_PULSE, config->nrd_pulse)
154 | HSMC_BF(NCS_RD_PULSE, config->ncs_read_pulse));
155 cycle = (HSMC_BF(NWE_CYCLE, config->write_cycle)
156 | HSMC_BF(NRD_CYCLE, config->read_cycle));
158 switch (config->bus_width) {
159 case 1:
160 mode = HSMC_BF(DBW, HSMC_DBW_8_BITS);
161 break;
162 case 2:
163 mode = HSMC_BF(DBW, HSMC_DBW_16_BITS);
164 break;
165 case 4:
166 mode = HSMC_BF(DBW, HSMC_DBW_32_BITS);
167 break;
168 default:
169 return -EINVAL;
172 switch (config->nwait_mode) {
173 case 0:
174 mode |= HSMC_BF(EXNW_MODE, HSMC_EXNW_MODE_DISABLED);
175 break;
176 case 1:
177 mode |= HSMC_BF(EXNW_MODE, HSMC_EXNW_MODE_RESERVED);
178 break;
179 case 2:
180 mode |= HSMC_BF(EXNW_MODE, HSMC_EXNW_MODE_FROZEN);
181 break;
182 case 3:
183 mode |= HSMC_BF(EXNW_MODE, HSMC_EXNW_MODE_READY);
184 break;
185 default:
186 return -EINVAL;
189 if (config->tdf_cycles) {
190 mode |= HSMC_BF(TDF_CYCLES, config->tdf_cycles);
193 if (config->nrd_controlled)
194 mode |= HSMC_BIT(READ_MODE);
195 if (config->nwe_controlled)
196 mode |= HSMC_BIT(WRITE_MODE);
197 if (config->byte_write)
198 mode |= HSMC_BIT(BAT);
199 if (config->tdf_mode)
200 mode |= HSMC_BIT(TDF_MODE);
202 pr_debug("smc cs%d: setup/%08x pulse/%08x cycle/%08x mode/%08x\n",
203 cs, setup, pulse, cycle, mode);
205 offset = cs * 0x10;
206 hsmc_writel(hsmc, SETUP0 + offset, setup);
207 hsmc_writel(hsmc, PULSE0 + offset, pulse);
208 hsmc_writel(hsmc, CYCLE0 + offset, cycle);
209 hsmc_writel(hsmc, MODE0 + offset, mode);
210 hsmc_readl(hsmc, MODE0); /* I/O barrier */
212 return 0;
214 EXPORT_SYMBOL(smc_set_configuration);
216 static int hsmc_probe(struct platform_device *pdev)
218 struct resource *regs;
219 struct clk *pclk, *mck;
220 int ret;
222 if (hsmc)
223 return -EBUSY;
225 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
226 if (!regs)
227 return -ENXIO;
228 pclk = clk_get(&pdev->dev, "pclk");
229 if (IS_ERR(pclk))
230 return PTR_ERR(pclk);
231 mck = clk_get(&pdev->dev, "mck");
232 if (IS_ERR(mck)) {
233 ret = PTR_ERR(mck);
234 goto out_put_pclk;
237 ret = -ENOMEM;
238 hsmc = kzalloc(sizeof(struct hsmc), GFP_KERNEL);
239 if (!hsmc)
240 goto out_put_clocks;
242 clk_enable(pclk);
243 clk_enable(mck);
245 hsmc->pclk = pclk;
246 hsmc->mck = mck;
247 hsmc->regs = ioremap(regs->start, regs->end - regs->start + 1);
248 if (!hsmc->regs)
249 goto out_disable_clocks;
251 dev_info(&pdev->dev, "Atmel Static Memory Controller at 0x%08lx\n",
252 (unsigned long)regs->start);
254 platform_set_drvdata(pdev, hsmc);
256 return 0;
258 out_disable_clocks:
259 clk_disable(mck);
260 clk_disable(pclk);
261 kfree(hsmc);
262 out_put_clocks:
263 clk_put(mck);
264 out_put_pclk:
265 clk_put(pclk);
266 hsmc = NULL;
267 return ret;
270 static struct platform_driver hsmc_driver = {
271 .probe = hsmc_probe,
272 .driver = {
273 .name = "smc",
277 static int __init hsmc_init(void)
279 return platform_driver_register(&hsmc_driver);
281 core_initcall(hsmc_init);