drivers/usb/musb/omap2430.c

   1 /*
   2  * Copyright (C) 2005-2007 by Texas Instruments
   3  * Some code has been taken from tusb6010.c
   4  * Copyrights for that are attributable to:
   5  * Copyright (C) 2006 Nokia Corporation
   6  * Jarkko Nikula <jarkko.nikula@nokia.com>
   7  * Tony Lindgren <tony@atomide.com>
   8  *
   9  * This file is part of the Inventra Controller Driver for Linux.
  10  *
  11  * The Inventra Controller Driver for Linux is free software; you
  12  * can redistribute it and/or modify it under the terms of the GNU
  13  * General Public License version 2 as published by the Free Software
  14  * Foundation.
  15  *
  16  * The Inventra Controller Driver for Linux is distributed in
  17  * the hope that it will be useful, but WITHOUT ANY WARRANTY;
  18  * without even the implied warranty of MERCHANTABILITY or
  19  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  20  * License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with The Inventra Controller Driver for Linux ; if not,
  24  * write to the Free Software Foundation, Inc., 59 Temple Place,
  25  * Suite 330, Boston, MA  02111-1307  USA
  26  *
  27  */
  28 #include <linux/module.h>
  29 #include <linux/kernel.h>
  30 #include <linux/sched.h>
  31 #include <linux/slab.h>
  32 #include <linux/init.h>
  33 #include <linux/list.h>
  34 #include <linux/clk.h>
  35 #include <linux/io.h>
  36
  37 #include <asm/mach-types.h>
  38 #include <mach/hardware.h>
  39 #include <mach/mux.h>
  40
  41 #include "musb_core.h"
  42 #include "omap2430.h"
  43
  44 #ifdef CONFIG_ARCH_OMAP3430
  45 #define get_cpu_rev()   2
  46 #endif
  47
  48 #define MUSB_TIMEOUT_A_WAIT_BCON        1100
  49
  50 static struct timer_list musb_idle_timer;
  51
  52 static void musb_do_idle(unsigned long _musb)
  53 {
  54         struct musb     *musb = (void *)_musb;
  55         unsigned long   flags;
  56 #ifdef CONFIG_USB_MUSB_HDRC_HCD
  57         u8      power;
  58 #endif
  59         u8      devctl;
  60
  61         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  62
  63         spin_lock_irqsave(&musb->lock, flags);
  64
  65         switch (musb->xceiv.state) {
  66         case OTG_STATE_A_WAIT_BCON:
  67                 devctl &= ~MUSB_DEVCTL_SESSION;
  68                 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
  69
  70                 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
  71                 if (devctl & MUSB_DEVCTL_BDEVICE) {
  72                         musb->xceiv.state = OTG_STATE_B_IDLE;
  73                         MUSB_DEV_MODE(musb);
  74                 } else {
  75                         musb->xceiv.state = OTG_STATE_A_IDLE;
  76                         MUSB_HST_MODE(musb);
  77                 }
  78                 break;
  79 #ifdef CONFIG_USB_MUSB_HDRC_HCD
  80         case OTG_STATE_A_SUSPEND:
  81                 /* finish RESUME signaling? */
  82                 if (musb->port1_status & MUSB_PORT_STAT_RESUME) {
  83                         power = musb_readb(musb->mregs, MUSB_POWER);
  84                         power &= ~MUSB_POWER_RESUME;
  85                         DBG(1, "root port resume stopped, power %02x\n", power);
  86                         musb_writeb(musb->mregs, MUSB_POWER, power);
  87                         musb->is_active = 1;
  88                         musb->port1_status &= ~(USB_PORT_STAT_SUSPEND
  89                                                 | MUSB_PORT_STAT_RESUME);
  90                         musb->port1_status |= USB_PORT_STAT_C_SUSPEND << 16;
  91                         usb_hcd_poll_rh_status(musb_to_hcd(musb));
  92                         /* NOTE: it might really be A_WAIT_BCON ... */
  93                         musb->xceiv.state = OTG_STATE_A_HOST;
  94                 }
  95                 break;
  96 #endif
  97 #ifdef CONFIG_USB_MUSB_HDRC_HCD
  98         case OTG_STATE_A_HOST:
  99                 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 100                 if (devctl &  MUSB_DEVCTL_BDEVICE)
 101                         musb->xceiv.state = OTG_STATE_B_IDLE;
 102                 else
 103                         musb->xceiv.state = OTG_STATE_A_WAIT_BCON;
 104 #endif
 105         default:
 106                 break;
 107         }
 108         spin_unlock_irqrestore(&musb->lock, flags);
 109 }
 110
 111
 112 void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
 113 {
 114         unsigned long           default_timeout = jiffies + msecs_to_jiffies(3);
 115         static unsigned long    last_timer;
 116
 117         if (timeout == 0)
 118                 timeout = default_timeout;
 119
 120         /* Never idle if active, or when VBUS timeout is not set as host */
 121         if (musb->is_active || ((musb->a_wait_bcon == 0)
 122                         && (musb->xceiv.state == OTG_STATE_A_WAIT_BCON))) {
 123                 DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
 124                 del_timer(&musb_idle_timer);
 125                 last_timer = jiffies;
 126                 return;
 127         }
 128
 129         if (time_after(last_timer, timeout)) {
 130                 if (!timer_pending(&musb_idle_timer))
 131                         last_timer = timeout;
 132                 else {
 133                         DBG(4, "Longer idle timer already pending, ignoring\n");
 134                         return;
 135                 }
 136         }
 137         last_timer = timeout;
 138
 139         DBG(4, "%s inactive, for idle timer for %lu ms\n",
 140                 otg_state_string(musb),
 141                 (unsigned long)jiffies_to_msecs(timeout - jiffies));
 142         mod_timer(&musb_idle_timer, timeout);
 143 }
 144
 145 void musb_platform_enable(struct musb *musb)
 146 {
 147 }
 148 void musb_platform_disable(struct musb *musb)
 149 {
 150 }
 151 static void omap_vbus_power(struct musb *musb, int is_on, int sleeping)
 152 {
 153 }
 154
 155 static void omap_set_vbus(struct musb *musb, int is_on)
 156 {
 157         u8              devctl;
 158         /* HDRC controls CPEN, but beware current surges during device
 159          * connect.  They can trigger transient overcurrent conditions
 160          * that must be ignored.
 161          */
 162
 163         devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 164
 165         if (is_on) {
 166                 musb->is_active = 1;
 167                 musb->xceiv.default_a = 1;
 168                 musb->xceiv.state = OTG_STATE_A_WAIT_VRISE;
 169                 devctl |= MUSB_DEVCTL_SESSION;
 170
 171                 MUSB_HST_MODE(musb);
 172         } else {
 173                 musb->is_active = 0;
 174
 175                 /* NOTE:  we're skipping A_WAIT_VFALL -> A_IDLE and
 176                  * jumping right to B_IDLE...
 177                  */
 178
 179                 musb->xceiv.default_a = 0;
 180                 musb->xceiv.state = OTG_STATE_B_IDLE;
 181                 devctl &= ~MUSB_DEVCTL_SESSION;
 182
 183                 MUSB_DEV_MODE(musb);
 184         }
 185         musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
 186
 187         DBG(1, "VBUS %s, devctl %02x "
 188                 /* otg %3x conf %08x prcm %08x */ "\n",
 189                 otg_state_string(musb),
 190                 musb_readb(musb->mregs, MUSB_DEVCTL));
 191 }
 192 static int omap_set_power(struct otg_transceiver *x, unsigned mA)
 193 {
 194         return 0;
 195 }
 196
 197 static int musb_platform_resume(struct musb *musb);
 198
 199 void musb_platform_set_mode(struct musb *musb, u8 musb_mode)
 200 {
 201         u8      devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 202
 203         devctl |= MUSB_DEVCTL_SESSION;
 204         musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
 205
 206         switch (musb_mode) {
 207         case MUSB_HOST:
 208                 otg_set_host(&musb->xceiv, musb->xceiv.host);
 209                 break;
 210         case MUSB_PERIPHERAL:
 211                 otg_set_peripheral(&musb->xceiv, musb->xceiv.gadget);
 212                 break;
 213         case MUSB_OTG:
 214                 break;
 215         }
 216 }
 217
 218 int __init musb_platform_init(struct musb *musb)
 219 {
 220         u32 l;
 221
 222 #if defined(CONFIG_ARCH_OMAP2430)
 223         omap_cfg_reg(AE5_2430_USB0HS_STP);
 224 #endif
 225
 226         musb_platform_resume(musb);
 227
 228         l = omap_readl(OTG_SYSCONFIG);
 229         l &= ~ENABLEWAKEUP;     /* disable wakeup */
 230         l &= ~NOSTDBY;          /* remove possible nostdby */
 231         l |= SMARTSTDBY;        /* enable smart standby */
 232         l &= ~AUTOIDLE;         /* disable auto idle */
 233         l &= ~NOIDLE;           /* remove possible noidle */
 234         l |= SMARTIDLE;         /* enable smart idle */
 235         l |= AUTOIDLE;          /* enable auto idle */
 236         omap_writel(l, OTG_SYSCONFIG);
 237
 238         l = omap_readl(OTG_INTERFSEL);
 239         l |= ULPI_12PIN;
 240         omap_writel(l, OTG_INTERFSEL);
 241
 242         pr_debug("HS USB OTG: revision 0x%x, sysconfig 0x%02x, "
 243                         "sysstatus 0x%x, intrfsel 0x%x, simenable  0x%x\n",
 244                         omap_readl(OTG_REVISION), omap_readl(OTG_SYSCONFIG),
 245                         omap_readl(OTG_SYSSTATUS), omap_readl(OTG_INTERFSEL),
 246                         omap_readl(OTG_SIMENABLE));
 247
 248         omap_vbus_power(musb, musb->board_mode == MUSB_HOST, 1);
 249
 250         if (is_host_enabled(musb))
 251                 musb->board_set_vbus = omap_set_vbus;
 252         if (is_peripheral_enabled(musb))
 253                 musb->xceiv.set_power = omap_set_power;
 254         musb->a_wait_bcon = MUSB_TIMEOUT_A_WAIT_BCON;
 255
 256         setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
 257
 258         return 0;
 259 }
 260
 261 int musb_platform_suspend(struct musb *musb)
 262 {
 263         u32 l;
 264
 265         if (!musb->clock)
 266                 return 0;
 267
 268         /* in any role */
 269         l = omap_readl(OTG_FORCESTDBY);
 270         l |= ENABLEFORCE;       /* enable MSTANDBY */
 271         omap_writel(l, OTG_FORCESTDBY);
 272
 273         l = omap_readl(OTG_SYSCONFIG);
 274         l |= ENABLEWAKEUP;      /* enable wakeup */
 275         omap_writel(l, OTG_SYSCONFIG);
 276
 277         if (musb->xceiv.set_suspend)
 278                 musb->xceiv.set_suspend(&musb->xceiv, 1);
 279
 280         if (musb->set_clock)
 281                 musb->set_clock(musb->clock, 0);
 282         else
 283                 clk_disable(musb->clock);
 284
 285         return 0;
 286 }
 287
 288 static int musb_platform_resume(struct musb *musb)
 289 {
 290         u32 l;
 291
 292         if (!musb->clock)
 293                 return 0;
 294
 295         if (musb->xceiv.set_suspend)
 296                 musb->xceiv.set_suspend(&musb->xceiv, 0);
 297
 298         if (musb->set_clock)
 299                 musb->set_clock(musb->clock, 1);
 300         else
 301                 clk_enable(musb->clock);
 302
 303         l = omap_readl(OTG_SYSCONFIG);
 304         l &= ~ENABLEWAKEUP;     /* disable wakeup */
 305         omap_writel(l, OTG_SYSCONFIG);
 306
 307         l = omap_readl(OTG_FORCESTDBY);
 308         l &= ~ENABLEFORCE;      /* disable MSTANDBY */
 309         omap_writel(l, OTG_FORCESTDBY);
 310
 311         return 0;
 312 }
 313
 314
 315 int musb_platform_exit(struct musb *musb)
 316 {
 317
 318         omap_vbus_power(musb, 0 /*off*/, 1);
 319
 320         musb_platform_suspend(musb);
 321
 322         clk_put(musb->clock);
 323         musb->clock = 0;
 324
 325         return 0;
 326 }