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firewire: Loop requests to the host controller back into the stack.
[linux-2.6/mini2440.git] / drivers / ide / pci / pdc202xx_new.c
blob6ceb25bc5a7bb1109e22ff804a997dde62d66cc9
1 /*
2 * Promise TX2/TX4/TX2000/133 IDE driver
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Split from:
10 * linux/drivers/ide/pdc202xx.c Version 0.35 Mar. 30, 2002
11 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
12 * Copyright (C) 2005-2006 MontaVista Software, Inc.
13 * Portions Copyright (C) 1999 Promise Technology, Inc.
14 * Author: Frank Tiernan (frankt@promise.com)
15 * Released under terms of General Public License
16 */
17
18 #include <linux/module.h>
19 #include <linux/types.h>
20 #include <linux/kernel.h>
21 #include <linux/delay.h>
22 #include <linux/timer.h>
23 #include <linux/mm.h>
24 #include <linux/ioport.h>
25 #include <linux/blkdev.h>
26 #include <linux/hdreg.h>
27 #include <linux/interrupt.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/ide.h>
31
32 #include <asm/io.h>
33 #include <asm/irq.h>
34
35 #ifdef CONFIG_PPC_PMAC
36 #include <asm/prom.h>
37 #include <asm/pci-bridge.h>
38 #endif
39
40 #define PDC202_DEBUG_CABLE 0
41
42 #undef DEBUG
43
44 #ifdef DEBUG
45 #define DBG(fmt, args...) printk("%s: " fmt, __FUNCTION__, ## args)
46 #else
47 #define DBG(fmt, args...)
48 #endif
49
50 static const char *pdc_quirk_drives[] = {
51 "QUANTUM FIREBALLlct08 08",
52 "QUANTUM FIREBALLP KA6.4",
53 "QUANTUM FIREBALLP KA9.1",
54 "QUANTUM FIREBALLP LM20.4",
55 "QUANTUM FIREBALLP KX13.6",
56 "QUANTUM FIREBALLP KX20.5",
57 "QUANTUM FIREBALLP KX27.3",
58 "QUANTUM FIREBALLP LM20.5",
59 NULL
60 };
61
62 static u8 max_dma_rate(struct pci_dev *pdev)
63 {
64 u8 mode;
65
66 switch(pdev->device) {
67 case PCI_DEVICE_ID_PROMISE_20277:
68 case PCI_DEVICE_ID_PROMISE_20276:
69 case PCI_DEVICE_ID_PROMISE_20275:
70 case PCI_DEVICE_ID_PROMISE_20271:
71 case PCI_DEVICE_ID_PROMISE_20269:
72 mode = 4;
73 break;
74 case PCI_DEVICE_ID_PROMISE_20270:
75 case PCI_DEVICE_ID_PROMISE_20268:
76 mode = 3;
77 break;
78 default:
79 return 0;
80 }
81
82 return mode;
83 }
84
85 static u8 pdcnew_ratemask(ide_drive_t *drive)
86 {
87 u8 mode = max_dma_rate(HWIF(drive)->pci_dev);
88
89 if (!eighty_ninty_three(drive))
90 mode = min_t(u8, mode, 1);
91
92 return mode;
93 }
94
95 /**
96 * get_indexed_reg - Get indexed register
97 * @hwif: for the port address
98 * @index: index of the indexed register
99 */
100 static u8 get_indexed_reg(ide_hwif_t *hwif, u8 index)
101 {
102 u8 value;
103
104 outb(index, hwif->dma_vendor1);
105 value = inb(hwif->dma_vendor3);
106
107 DBG("index[%02X] value[%02X]\n", index, value);
108 return value;
109 }
110
111 /**
112 * set_indexed_reg - Set indexed register
113 * @hwif: for the port address
114 * @index: index of the indexed register
115 */
116 static void set_indexed_reg(ide_hwif_t *hwif, u8 index, u8 value)
117 {
118 outb(index, hwif->dma_vendor1);
119 outb(value, hwif->dma_vendor3);
120 DBG("index[%02X] value[%02X]\n", index, value);
121 }
122
123 /*
124 * ATA Timing Tables based on 133 MHz PLL output clock.
125 *
126 * If the PLL outputs 100 MHz clock, the ASIC hardware will set
127 * the timing registers automatically when "set features" command is
128 * issued to the device. However, if the PLL output clock is 133 MHz,
129 * the following tables must be used.
130 */
131 static struct pio_timing {
132 u8 reg0c, reg0d, reg13;
133 } pio_timings [] = {
134 { 0xfb, 0x2b, 0xac }, /* PIO mode 0, IORDY off, Prefetch off */
135 { 0x46, 0x29, 0xa4 }, /* PIO mode 1, IORDY off, Prefetch off */
136 { 0x23, 0x26, 0x64 }, /* PIO mode 2, IORDY off, Prefetch off */
137 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
138 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
139 };
140
141 static struct mwdma_timing {
142 u8 reg0e, reg0f;
143 } mwdma_timings [] = {
144 { 0xdf, 0x5f }, /* MWDMA mode 0 */
145 { 0x6b, 0x27 }, /* MWDMA mode 1 */
146 { 0x69, 0x25 }, /* MWDMA mode 2 */
147 };
148
149 static struct udma_timing {
150 u8 reg10, reg11, reg12;
151 } udma_timings [] = {
152 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
153 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
154 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
155 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
156 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
157 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
158 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
159 };
160
161 static int pdcnew_tune_chipset(ide_drive_t *drive, u8 speed)
162 {
163 ide_hwif_t *hwif = HWIF(drive);
164 u8 adj = (drive->dn & 1) ? 0x08 : 0x00;
165 int err;
166
167 speed = ide_rate_filter(pdcnew_ratemask(drive), speed);
168
169 /*
170 * Issue SETFEATURES_XFER to the drive first. PDC202xx hardware will
171 * automatically set the timing registers based on 100 MHz PLL output.
172 */
173 err = ide_config_drive_speed(drive, speed);
174
175 /*
176 * As we set up the PLL to output 133 MHz for UltraDMA/133 capable
177 * chips, we must override the default register settings...
178 */
179 if (max_dma_rate(hwif->pci_dev) == 4) {
180 u8 mode = speed & 0x07;
181
182 switch (speed) {
183 case XFER_UDMA_6:
184 case XFER_UDMA_5:
185 case XFER_UDMA_4:
186 case XFER_UDMA_3:
187 case XFER_UDMA_2:
188 case XFER_UDMA_1:
189 case XFER_UDMA_0:
190 set_indexed_reg(hwif, 0x10 + adj,
191 udma_timings[mode].reg10);
192 set_indexed_reg(hwif, 0x11 + adj,
193 udma_timings[mode].reg11);
194 set_indexed_reg(hwif, 0x12 + adj,
195 udma_timings[mode].reg12);
196 break;
197
198 case XFER_MW_DMA_2:
199 case XFER_MW_DMA_1:
200 case XFER_MW_DMA_0:
201 set_indexed_reg(hwif, 0x0e + adj,
202 mwdma_timings[mode].reg0e);
203 set_indexed_reg(hwif, 0x0f + adj,
204 mwdma_timings[mode].reg0f);
205 break;
206 case XFER_PIO_4:
207 case XFER_PIO_3:
208 case XFER_PIO_2:
209 case XFER_PIO_1:
210 case XFER_PIO_0:
211 set_indexed_reg(hwif, 0x0c + adj,
212 pio_timings[mode].reg0c);
213 set_indexed_reg(hwif, 0x0d + adj,
214 pio_timings[mode].reg0d);
215 set_indexed_reg(hwif, 0x13 + adj,
216 pio_timings[mode].reg13);
217 break;
218 default:
219 printk(KERN_ERR "pdc202xx_new: "
220 "Unknown speed %d ignored\n", speed);
221 }
222 } else if (speed == XFER_UDMA_2) {
223 /* Set tHOLD bit to 0 if using UDMA mode 2 */
224 u8 tmp = get_indexed_reg(hwif, 0x10 + adj);
225
226 set_indexed_reg(hwif, 0x10 + adj, tmp & 0x7f);
227 }
228
229 return err;
230 }
231
232 static void pdcnew_tune_drive(ide_drive_t *drive, u8 pio)
233 {
234 pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
235 (void)pdcnew_tune_chipset(drive, XFER_PIO_0 + pio);
236 }
237
238 static u8 pdcnew_cable_detect(ide_hwif_t *hwif)
239 {
240 return get_indexed_reg(hwif, 0x0b) & 0x04;
241 }
242
243 static int config_chipset_for_dma(ide_drive_t *drive)
244 {
245 struct hd_driveid *id = drive->id;
246 ide_hwif_t *hwif = HWIF(drive);
247 u8 ultra_66 = (id->dma_ultra & 0x0078) ? 1 : 0;
248 u8 cable = pdcnew_cable_detect(hwif);
249 u8 speed;
250
251 if (ultra_66 && cable) {
252 printk(KERN_WARNING "Warning: %s channel "
253 "requires an 80-pin cable for operation.\n",
254 hwif->channel ? "Secondary" : "Primary");
255 printk(KERN_WARNING "%s reduced to Ultra33 mode.\n", drive->name);
256 }
257
258 if (drive->media != ide_disk)
259 return 0;
260
261 if (id->capability & 4) {
262 /*
263 * Set IORDY_EN & PREFETCH_EN (this seems to have
264 * NO real effect since this register is reloaded
265 * by hardware when the transfer mode is selected)
266 */
267 u8 tmp, adj = (drive->dn & 1) ? 0x08 : 0x00;
268
269 tmp = get_indexed_reg(hwif, 0x13 + adj);
270 set_indexed_reg(hwif, 0x13 + adj, tmp | 0x03);
271 }
272
273 speed = ide_dma_speed(drive, pdcnew_ratemask(drive));
274
275 if (!speed)
276 return 0;
277
278 (void) hwif->speedproc(drive, speed);
279 return ide_dma_enable(drive);
280 }
281
282 static int pdcnew_config_drive_xfer_rate(ide_drive_t *drive)
283 {
284 drive->init_speed = 0;
285
286 if (ide_use_dma(drive) && config_chipset_for_dma(drive))
287 return 0;
288
289 if (ide_use_fast_pio(drive))
290 pdcnew_tune_drive(drive, 255);
291
292 return -1;
293 }
294
295 static int pdcnew_quirkproc(ide_drive_t *drive)
296 {
297 const char **list, *model = drive->id->model;
298
299 for (list = pdc_quirk_drives; *list != NULL; list++)
300 if (strstr(model, *list) != NULL)
301 return 2;
302 return 0;
303 }
304
305 static void pdcnew_reset(ide_drive_t *drive)
306 {
307 /*
308 * Deleted this because it is redundant from the caller.
309 */
310 printk(KERN_WARNING "pdc202xx_new: %s channel reset.\n",
311 HWIF(drive)->channel ? "Secondary" : "Primary");
312 }
313
314 /**
315 * read_counter - Read the byte count registers
316 * @dma_base: for the port address
317 */
318 static long __devinit read_counter(u32 dma_base)
319 {
320 u32 pri_dma_base = dma_base, sec_dma_base = dma_base + 0x08;
321 u8 cnt0, cnt1, cnt2, cnt3;
322 long count = 0, last;
323 int retry = 3;
324
325 do {
326 last = count;
327
328 /* Read the current count */
329 outb(0x20, pri_dma_base + 0x01);
330 cnt0 = inb(pri_dma_base + 0x03);
331 outb(0x21, pri_dma_base + 0x01);
332 cnt1 = inb(pri_dma_base + 0x03);
333 outb(0x20, sec_dma_base + 0x01);
334 cnt2 = inb(sec_dma_base + 0x03);
335 outb(0x21, sec_dma_base + 0x01);
336 cnt3 = inb(sec_dma_base + 0x03);
337
338 count = (cnt3 << 23) | (cnt2 << 15) | (cnt1 << 8) | cnt0;
339
340 /*
341 * The 30-bit decrementing counter is read in 4 pieces.
342 * Incorrect value may be read when the most significant bytes
343 * are changing...
344 */
345 } while (retry-- && (((last ^ count) & 0x3fff8000) || last < count));
346
347 DBG("cnt0[%02X] cnt1[%02X] cnt2[%02X] cnt3[%02X]\n",
348 cnt0, cnt1, cnt2, cnt3);
349
350 return count;
351 }
352
353 /**
354 * detect_pll_input_clock - Detect the PLL input clock in Hz.
355 * @dma_base: for the port address
356 * E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
357 */
358 static long __devinit detect_pll_input_clock(unsigned long dma_base)
359 {
360 long start_count, end_count;
361 long pll_input;
362 u8 scr1;
363
364 start_count = read_counter(dma_base);
365
366 /* Start the test mode */
367 outb(0x01, dma_base + 0x01);
368 scr1 = inb(dma_base + 0x03);
369 DBG("scr1[%02X]\n", scr1);
370 outb(scr1 | 0x40, dma_base + 0x03);
371
372 /* Let the counter run for 10 ms. */
373 mdelay(10);
374
375 end_count = read_counter(dma_base);
376
377 /* Stop the test mode */
378 outb(0x01, dma_base + 0x01);
379 scr1 = inb(dma_base + 0x03);
380 DBG("scr1[%02X]\n", scr1);
381 outb(scr1 & ~0x40, dma_base + 0x03);
382
383 /*
384 * Calculate the input clock in Hz
385 * (the clock counter is 30 bit wide and counts down)
386 */
387 pll_input = ((start_count - end_count) & 0x3ffffff) * 100;
388
389 DBG("start[%ld] end[%ld]\n", start_count, end_count);
390
391 return pll_input;
392 }
393
394 #ifdef CONFIG_PPC_PMAC
395 static void __devinit apple_kiwi_init(struct pci_dev *pdev)
396 {
397 struct device_node *np = pci_device_to_OF_node(pdev);
398 unsigned int class_rev = 0;
399 u8 conf;
400
401 if (np == NULL || !device_is_compatible(np, "kiwi-root"))
402 return;
403
404 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
405 class_rev &= 0xff;
406
407 if (class_rev >= 0x03) {
408 /* Setup chip magic config stuff (from darwin) */
409 pci_read_config_byte (pdev, 0x40, &conf);
410 pci_write_config_byte(pdev, 0x40, (conf | 0x01));
411 }
412 }
413 #endif /* CONFIG_PPC_PMAC */
414
415 static unsigned int __devinit init_chipset_pdcnew(struct pci_dev *dev, const char *name)
416 {
417 unsigned long dma_base = pci_resource_start(dev, 4);
418 unsigned long sec_dma_base = dma_base + 0x08;
419 long pll_input, pll_output, ratio;
420 int f, r;
421 u8 pll_ctl0, pll_ctl1;
422
423 if (dev->resource[PCI_ROM_RESOURCE].start) {
424 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
425 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
426 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
427 (unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
428 }
429
430 #ifdef CONFIG_PPC_PMAC
431 apple_kiwi_init(dev);
432 #endif
433
434 /* Calculate the required PLL output frequency */
435 switch(max_dma_rate(dev)) {
436 case 4: /* it's 133 MHz for Ultra133 chips */
437 pll_output = 133333333;
438 break;
439 case 3: /* and 100 MHz for Ultra100 chips */
440 default:
441 pll_output = 100000000;
442 break;
443 }
444
445 /*
446 * Detect PLL input clock.
447 * On some systems, where PCI bus is running at non-standard clock rate
448 * (e.g. 25 or 40 MHz), we have to adjust the cycle time.
449 * PDC20268 and newer chips employ PLL circuit to help correct timing
450 * registers setting.
451 */
452 pll_input = detect_pll_input_clock(dma_base);
453 printk("%s: PLL input clock is %ld kHz\n", name, pll_input / 1000);
454
455 /* Sanity check */
456 if (unlikely(pll_input < 5000000L || pll_input > 70000000L)) {
457 printk(KERN_ERR "%s: Bad PLL input clock %ld Hz, giving up!\n",
458 name, pll_input);
459 goto out;
460 }
461
462 #ifdef DEBUG
463 DBG("pll_output is %ld Hz\n", pll_output);
464
465 /* Show the current clock value of PLL control register
466 * (maybe already configured by the BIOS)
467 */
468 outb(0x02, sec_dma_base + 0x01);
469 pll_ctl0 = inb(sec_dma_base + 0x03);
470 outb(0x03, sec_dma_base + 0x01);
471 pll_ctl1 = inb(sec_dma_base + 0x03);
472
473 DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
474 #endif
475
476 /*
477 * Calculate the ratio of F, R and NO
478 * POUT = (F + 2) / (( R + 2) * NO)
479 */
480 ratio = pll_output / (pll_input / 1000);
481 if (ratio < 8600L) { /* 8.6x */
482 /* Using NO = 0x01, R = 0x0d */
483 r = 0x0d;
484 } else if (ratio < 12900L) { /* 12.9x */
485 /* Using NO = 0x01, R = 0x08 */
486 r = 0x08;
487 } else if (ratio < 16100L) { /* 16.1x */
488 /* Using NO = 0x01, R = 0x06 */
489 r = 0x06;
490 } else if (ratio < 64000L) { /* 64x */
491 r = 0x00;
492 } else {
493 /* Invalid ratio */
494 printk(KERN_ERR "%s: Bad ratio %ld, giving up!\n", name, ratio);
495 goto out;
496 }
497
498 f = (ratio * (r + 2)) / 1000 - 2;
499
500 DBG("F[%d] R[%d] ratio*1000[%ld]\n", f, r, ratio);
501
502 if (unlikely(f < 0 || f > 127)) {
503 /* Invalid F */
504 printk(KERN_ERR "%s: F[%d] invalid!\n", name, f);
505 goto out;
506 }
507
508 pll_ctl0 = (u8) f;
509 pll_ctl1 = (u8) r;
510
511 DBG("Writing pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
512
513 outb(0x02, sec_dma_base + 0x01);
514 outb(pll_ctl0, sec_dma_base + 0x03);
515 outb(0x03, sec_dma_base + 0x01);
516 outb(pll_ctl1, sec_dma_base + 0x03);
517
518 /* Wait the PLL circuit to be stable */
519 mdelay(30);
520
521 #ifdef DEBUG
522 /*
523 * Show the current clock value of PLL control register
524 */
525 outb(0x02, sec_dma_base + 0x01);
526 pll_ctl0 = inb(sec_dma_base + 0x03);
527 outb(0x03, sec_dma_base + 0x01);
528 pll_ctl1 = inb(sec_dma_base + 0x03);
529
530 DBG("pll_ctl[%02X][%02X]\n", pll_ctl0, pll_ctl1);
531 #endif
532
533 out:
534 return dev->irq;
535 }
536
537 static void __devinit init_hwif_pdc202new(ide_hwif_t *hwif)
538 {
539 hwif->autodma = 0;
540
541 hwif->tuneproc = &pdcnew_tune_drive;
542 hwif->quirkproc = &pdcnew_quirkproc;
543 hwif->speedproc = &pdcnew_tune_chipset;
544 hwif->resetproc = &pdcnew_reset;
545
546 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
547
548 hwif->ultra_mask = 0x7f;
549 hwif->mwdma_mask = 0x07;
550
551 hwif->err_stops_fifo = 1;
552
553 hwif->ide_dma_check = &pdcnew_config_drive_xfer_rate;
554
555 if (!hwif->udma_four)
556 hwif->udma_four = pdcnew_cable_detect(hwif) ? 0 : 1;
557
558 if (!noautodma)
559 hwif->autodma = 1;
560 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
561
562 #if PDC202_DEBUG_CABLE
563 printk(KERN_DEBUG "%s: %s-pin cable\n",
564 hwif->name, hwif->udma_four ? "80" : "40");
565 #endif /* PDC202_DEBUG_CABLE */
566 }
567
568 static int __devinit init_setup_pdcnew(struct pci_dev *dev, ide_pci_device_t *d)
569 {
570 return ide_setup_pci_device(dev, d);
571 }
572
573 static int __devinit init_setup_pdc20270(struct pci_dev *dev,
574 ide_pci_device_t *d)
575 {
576 struct pci_dev *findev = NULL;
577 int ret;
578
579 if ((dev->bus->self &&
580 dev->bus->self->vendor == PCI_VENDOR_ID_DEC) &&
581 (dev->bus->self->device == PCI_DEVICE_ID_DEC_21150)) {
582 if (PCI_SLOT(dev->devfn) & 2)
583 return -ENODEV;
584 d->extra = 0;
585 while ((findev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
586 if ((findev->vendor == dev->vendor) &&
587 (findev->device == dev->device) &&
588 (PCI_SLOT(findev->devfn) & 2)) {
589 if (findev->irq != dev->irq) {
590 findev->irq = dev->irq;
591 }
592 ret = ide_setup_pci_devices(dev, findev, d);
593 pci_dev_put(findev);
594 return ret;
595 }
596 }
597 }
598 return ide_setup_pci_device(dev, d);
599 }
600
601 static int __devinit init_setup_pdc20276(struct pci_dev *dev,
602 ide_pci_device_t *d)
603 {
604 if ((dev->bus->self) &&
605 (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
606 ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
607 (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
608 printk(KERN_INFO "ide: Skipping Promise PDC20276 "
609 "attached to I2O RAID controller.\n");
610 return -ENODEV;
611 }
612 return ide_setup_pci_device(dev, d);
613 }
614
615 static ide_pci_device_t pdcnew_chipsets[] __devinitdata = {
616 { /* 0 */
617 .name = "PDC20268",
618 .init_setup = init_setup_pdcnew,
619 .init_chipset = init_chipset_pdcnew,
620 .init_hwif = init_hwif_pdc202new,
621 .channels = 2,
622 .autodma = AUTODMA,
623 .bootable = OFF_BOARD,
624 },{ /* 1 */
625 .name = "PDC20269",
626 .init_setup = init_setup_pdcnew,
627 .init_chipset = init_chipset_pdcnew,
628 .init_hwif = init_hwif_pdc202new,
629 .channels = 2,
630 .autodma = AUTODMA,
631 .bootable = OFF_BOARD,
632 },{ /* 2 */
633 .name = "PDC20270",
634 .init_setup = init_setup_pdc20270,
635 .init_chipset = init_chipset_pdcnew,
636 .init_hwif = init_hwif_pdc202new,
637 .channels = 2,
638 .autodma = AUTODMA,
639 .bootable = OFF_BOARD,
640 },{ /* 3 */
641 .name = "PDC20271",
642 .init_setup = init_setup_pdcnew,
643 .init_chipset = init_chipset_pdcnew,
644 .init_hwif = init_hwif_pdc202new,
645 .channels = 2,
646 .autodma = AUTODMA,
647 .bootable = OFF_BOARD,
648 },{ /* 4 */
649 .name = "PDC20275",
650 .init_setup = init_setup_pdcnew,
651 .init_chipset = init_chipset_pdcnew,
652 .init_hwif = init_hwif_pdc202new,
653 .channels = 2,
654 .autodma = AUTODMA,
655 .bootable = OFF_BOARD,
656 },{ /* 5 */
657 .name = "PDC20276",
658 .init_setup = init_setup_pdc20276,
659 .init_chipset = init_chipset_pdcnew,
660 .init_hwif = init_hwif_pdc202new,
661 .channels = 2,
662 .autodma = AUTODMA,
663 .bootable = OFF_BOARD,
664 },{ /* 6 */
665 .name = "PDC20277",
666 .init_setup = init_setup_pdcnew,
667 .init_chipset = init_chipset_pdcnew,
668 .init_hwif = init_hwif_pdc202new,
669 .channels = 2,
670 .autodma = AUTODMA,
671 .bootable = OFF_BOARD,
672 }
673 };
674
675 /**
676 * pdc202new_init_one - called when a pdc202xx is found
677 * @dev: the pdc202new device
678 * @id: the matching pci id
679 *
680 * Called when the PCI registration layer (or the IDE initialization)
681 * finds a device matching our IDE device tables.
682 */
683
684 static int __devinit pdc202new_init_one(struct pci_dev *dev, const struct pci_device_id *id)
685 {
686 ide_pci_device_t *d = &pdcnew_chipsets[id->driver_data];
687
688 return d->init_setup(dev, d);
689 }
690
691 static struct pci_device_id pdc202new_pci_tbl[] = {
692 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20268, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
693 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20269, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
694 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20270, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
695 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20271, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
696 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20275, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
697 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20276, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
698 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20277, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6},
699 { 0, },
700 };
701 MODULE_DEVICE_TABLE(pci, pdc202new_pci_tbl);
702
703 static struct pci_driver driver = {
704 .name = "Promise_IDE",
705 .id_table = pdc202new_pci_tbl,
706 .probe = pdc202new_init_one,
707 };
708
709 static int __init pdc202new_ide_init(void)
710 {
711 return ide_pci_register_driver(&driver);
712 }
713
714 module_init(pdc202new_ide_init);
715
716 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
717 MODULE_DESCRIPTION("PCI driver module for Promise PDC20268 and higher");
718 MODULE_LICENSE("GPL");
Support for the Chinese Samsung S3C2440 based development boards