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x86: put irq_2_pin pointer into irq_cfg
[linux-2.6/mini2440.git] / arch / x86 / kernel / io_apic_64.c
blob51ef7eb75f2ed45e637df1aa89845a4c70ba5953
1 /*
2 * Intel IO-APIC support for multi-Pentium hosts.
3 *
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5 *
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
8 *
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
14 *
15 * Fixes
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
18 * and Rolf G. Tews
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
21 */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
36 #ifdef CONFIG_ACPI
37 #include <acpi/acpi_bus.h>
38 #endif
39 #include <linux/bootmem.h>
40 #include <linux/dmar.h>
41
42 #include <asm/idle.h>
43 #include <asm/io.h>
44 #include <asm/smp.h>
45 #include <asm/desc.h>
46 #include <asm/proto.h>
47 #include <asm/acpi.h>
48 #include <asm/dma.h>
49 #include <asm/i8259.h>
50 #include <asm/nmi.h>
51 #include <asm/msidef.h>
52 #include <asm/hypertransport.h>
53 #include <asm/irq_remapping.h>
54
55 #include <mach_ipi.h>
56 #include <mach_apic.h>
57
58 #define __apicdebuginit(type) static type __init
59
60 struct irq_cfg;
61 struct irq_pin_list;
62 struct irq_cfg {
63 unsigned int irq;
64 struct irq_cfg *next;
65 struct irq_pin_list *irq_2_pin;
66 cpumask_t domain;
67 cpumask_t old_domain;
68 unsigned move_cleanup_count;
69 u8 vector;
70 u8 move_in_progress : 1;
71 };
72
73 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
74 static struct irq_cfg irq_cfg_legacy[] __initdata = {
75 [0] = { .irq = 0, .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
76 [1] = { .irq = 1, .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
77 [2] = { .irq = 2, .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
78 [3] = { .irq = 3, .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
79 [4] = { .irq = 4, .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
80 [5] = { .irq = 5, .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
81 [6] = { .irq = 6, .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
82 [7] = { .irq = 7, .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
83 [8] = { .irq = 8, .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
84 [9] = { .irq = 9, .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
85 [10] = { .irq = 10, .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
86 [11] = { .irq = 11, .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
87 [12] = { .irq = 12, .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
88 [13] = { .irq = 13, .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
89 [14] = { .irq = 14, .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
90 [15] = { .irq = 15, .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
91 };
92
93 static struct irq_cfg irq_cfg_init = { .irq = -1U, };
94 /* need to be biger than size of irq_cfg_legacy */
95 static int nr_irq_cfg = 32;
96
97 static int __init parse_nr_irq_cfg(char *arg)
98 {
99 if (arg) {
100 nr_irq_cfg = simple_strtoul(arg, NULL, 0);
101 if (nr_irq_cfg < 32)
102 nr_irq_cfg = 32;
103 }
104 return 0;
105 }
106
107 early_param("nr_irq_cfg", parse_nr_irq_cfg);
108
109 static void init_one_irq_cfg(struct irq_cfg *cfg)
110 {
111 memcpy(cfg, &irq_cfg_init, sizeof(struct irq_cfg));
112 }
113
114 static void __init init_work(void *data)
115 {
116 struct dyn_array *da = data;
117 struct irq_cfg *cfg;
118 int i;
119
120 cfg = *da->name;
121
122 memcpy(cfg, irq_cfg_legacy, sizeof(irq_cfg_legacy));
123
124 i = sizeof(irq_cfg_legacy)/sizeof(irq_cfg_legacy[0]);
125 for (; i < *da->nr; i++)
126 init_one_irq_cfg(&cfg[i]);
127
128 for (i = 1; i < *da->nr; i++)
129 cfg[i-1].next = &cfg[i];
130 }
131
132 static struct irq_cfg *irq_cfgx;
133 DEFINE_DYN_ARRAY(irq_cfgx, sizeof(struct irq_cfg), nr_irq_cfg, PAGE_SIZE, init_work);
134
135 static struct irq_cfg *irq_cfg(unsigned int irq)
136 {
137 struct irq_cfg *cfg;
138
139 BUG_ON(irq == -1U);
140
141 cfg = &irq_cfgx[0];
142 while (cfg) {
143 if (cfg->irq == irq)
144 return cfg;
145
146 if (cfg->irq == -1U)
147 return NULL;
148
149 cfg = cfg->next;
150 }
151
152 return NULL;
153 }
154
155 static struct irq_cfg *irq_cfg_alloc(unsigned int irq)
156 {
157 struct irq_cfg *cfg, *cfg_pri;
158 int i;
159 int count = 0;
160
161 BUG_ON(irq == -1U);
162
163 cfg_pri = cfg = &irq_cfgx[0];
164 while (cfg) {
165 if (cfg->irq == irq)
166 return cfg;
167
168 if (cfg->irq == -1U) {
169 cfg->irq = irq;
170 return cfg;
171 }
172 cfg_pri = cfg;
173 cfg = cfg->next;
174 count++;
175 }
176
177 /*
178 * we run out of pre-allocate ones, allocate more
179 */
180 printk(KERN_DEBUG "try to get more irq_cfg %d\n", nr_irq_cfg);
181
182 if (after_bootmem)
183 cfg = kzalloc(sizeof(struct irq_cfg)*nr_irq_cfg, GFP_ATOMIC);
184 else
185 cfg = __alloc_bootmem_nopanic(sizeof(struct irq_cfg)*nr_irq_cfg, PAGE_SIZE, 0);
186
187 if (!cfg)
188 panic("please boot with nr_irq_cfg= %d\n", count * 2);
189
190 for (i = 0; i < nr_irq_cfg; i++)
191 init_one_irq_cfg(&cfg[i]);
192
193 for (i = 1; i < nr_irq_cfg; i++)
194 cfg[i-1].next = &cfg[i];
195
196 cfg->irq = irq;
197 cfg_pri->next = cfg;
198
199 return cfg;
200 }
201
202 static int assign_irq_vector(int irq, cpumask_t mask);
203
204 int first_system_vector = 0xfe;
205
206 char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
207
208 int sis_apic_bug; /* not actually supported, dummy for compile */
209
210 static int no_timer_check;
211
212 static int disable_timer_pin_1 __initdata;
213
214 int timer_through_8259 __initdata;
215
216 /* Where if anywhere is the i8259 connect in external int mode */
217 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
218
219 static DEFINE_SPINLOCK(ioapic_lock);
220 static DEFINE_SPINLOCK(vector_lock);
221
222 /*
223 * # of IRQ routing registers
224 */
225 int nr_ioapic_registers[MAX_IO_APICS];
226
227 /* I/O APIC RTE contents at the OS boot up */
228 struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
229
230 /* I/O APIC entries */
231 struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
232 int nr_ioapics;
233
234 /* MP IRQ source entries */
235 struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
236
237 /* # of MP IRQ source entries */
238 int mp_irq_entries;
239
240 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
241
242 /*
243 * Rough estimation of how many shared IRQs there are, can
244 * be changed anytime.
245 */
246
247 int pin_map_size;
248
249 /*
250 * This is performance-critical, we want to do it O(1)
251 *
252 * the indexing order of this array favors 1:1 mappings
253 * between pins and IRQs.
254 */
255
256 struct irq_pin_list {
257 int apic, pin;
258 struct irq_pin_list *next;
259 };
260
261 static struct irq_pin_list *irq_2_pin_head;
262 /* fill one page ? */
263 static int nr_irq_2_pin = 0x100;
264 static struct irq_pin_list *irq_2_pin_ptr;
265 static void __init irq_2_pin_init_work(void *data)
266 {
267 struct dyn_array *da = data;
268 struct irq_pin_list *pin;
269 int i;
270
271 pin = *da->name;
272
273 for (i = 1; i < *da->nr; i++)
274 pin[i-1].next = &pin[i];
275
276 irq_2_pin_ptr = &pin[0];
277 }
278 DEFINE_DYN_ARRAY(irq_2_pin_head, sizeof(struct irq_pin_list), nr_irq_2_pin, PAGE_SIZE, irq_2_pin_init_work);
279
280 static struct irq_pin_list *get_one_free_irq_2_pin(void)
281 {
282 struct irq_pin_list *pin;
283 int i;
284
285 pin = irq_2_pin_ptr;
286
287 if (pin) {
288 irq_2_pin_ptr = pin->next;
289 pin->next = NULL;
290 return pin;
291 }
292
293 /*
294 * we run out of pre-allocate ones, allocate more
295 */
296 printk(KERN_DEBUG "try to get more irq_2_pin %d\n", nr_irq_2_pin);
297
298 if (after_bootmem)
299 pin = kzalloc(sizeof(struct irq_pin_list)*nr_irq_2_pin,
300 GFP_ATOMIC);
301 else
302 pin = __alloc_bootmem_nopanic(sizeof(struct irq_pin_list) *
303 nr_irq_2_pin, PAGE_SIZE, 0);
304
305 if (!pin)
306 panic("can not get more irq_2_pin\n");
307
308 for (i = 1; i < nr_irq_2_pin; i++)
309 pin[i-1].next = &pin[i];
310
311 irq_2_pin_ptr = pin->next;
312 pin->next = NULL;
313
314 return pin;
315 }
316
317 struct io_apic {
318 unsigned int index;
319 unsigned int unused[3];
320 unsigned int data;
321 };
322
323 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
324 {
325 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
326 + (mp_ioapics[idx].mp_apicaddr & ~PAGE_MASK);
327 }
328
329 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
330 {
331 struct io_apic __iomem *io_apic = io_apic_base(apic);
332 writel(reg, &io_apic->index);
333 return readl(&io_apic->data);
334 }
335
336 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
337 {
338 struct io_apic __iomem *io_apic = io_apic_base(apic);
339 writel(reg, &io_apic->index);
340 writel(value, &io_apic->data);
341 }
342
343 /*
344 * Re-write a value: to be used for read-modify-write
345 * cycles where the read already set up the index register.
346 */
347 static inline void io_apic_modify(unsigned int apic, unsigned int value)
348 {
349 struct io_apic __iomem *io_apic = io_apic_base(apic);
350 writel(value, &io_apic->data);
351 }
352
353 static bool io_apic_level_ack_pending(unsigned int irq)
354 {
355 struct irq_pin_list *entry;
356 unsigned long flags;
357 struct irq_cfg *cfg = irq_cfg(irq);
358
359 spin_lock_irqsave(&ioapic_lock, flags);
360 entry = cfg->irq_2_pin;
361 for (;;) {
362 unsigned int reg;
363 int pin;
364
365 if (!entry)
366 break;
367 pin = entry->pin;
368 reg = io_apic_read(entry->apic, 0x10 + pin*2);
369 /* Is the remote IRR bit set? */
370 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
371 spin_unlock_irqrestore(&ioapic_lock, flags);
372 return true;
373 }
374 if (!entry->next)
375 break;
376 entry = entry->next;
377 }
378 spin_unlock_irqrestore(&ioapic_lock, flags);
379
380 return false;
381 }
382
383 /*
384 * Synchronize the IO-APIC and the CPU by doing
385 * a dummy read from the IO-APIC
386 */
387 static inline void io_apic_sync(unsigned int apic)
388 {
389 struct io_apic __iomem *io_apic = io_apic_base(apic);
390 readl(&io_apic->data);
391 }
392
393 #define __DO_ACTION(R, ACTION, FINAL) \
394 \
395 { \
396 int pin; \
397 struct irq_cfg *cfg; \
398 struct irq_pin_list *entry; \
399 \
400 BUG_ON(irq >= nr_irqs); \
401 cfg = irq_cfg(irq); \
402 entry = cfg->irq_2_pin; \
403 for (;;) { \
404 unsigned int reg; \
405 if (!entry) \
406 break; \
407 pin = entry->pin; \
408 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
409 reg ACTION; \
410 io_apic_modify(entry->apic, reg); \
411 FINAL; \
412 if (!entry->next) \
413 break; \
414 entry = entry->next; \
415 } \
416 }
417
418 union entry_union {
419 struct { u32 w1, w2; };
420 struct IO_APIC_route_entry entry;
421 };
422
423 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
424 {
425 union entry_union eu;
426 unsigned long flags;
427 spin_lock_irqsave(&ioapic_lock, flags);
428 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
429 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
430 spin_unlock_irqrestore(&ioapic_lock, flags);
431 return eu.entry;
432 }
433
434 /*
435 * When we write a new IO APIC routing entry, we need to write the high
436 * word first! If the mask bit in the low word is clear, we will enable
437 * the interrupt, and we need to make sure the entry is fully populated
438 * before that happens.
439 */
440 static void
441 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
442 {
443 union entry_union eu;
444 eu.entry = e;
445 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
446 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
447 }
448
449 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
450 {
451 unsigned long flags;
452 spin_lock_irqsave(&ioapic_lock, flags);
453 __ioapic_write_entry(apic, pin, e);
454 spin_unlock_irqrestore(&ioapic_lock, flags);
455 }
456
457 /*
458 * When we mask an IO APIC routing entry, we need to write the low
459 * word first, in order to set the mask bit before we change the
460 * high bits!
461 */
462 static void ioapic_mask_entry(int apic, int pin)
463 {
464 unsigned long flags;
465 union entry_union eu = { .entry.mask = 1 };
466
467 spin_lock_irqsave(&ioapic_lock, flags);
468 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
469 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
470 spin_unlock_irqrestore(&ioapic_lock, flags);
471 }
472
473 #ifdef CONFIG_SMP
474 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
475 {
476 int apic, pin;
477 struct irq_cfg *cfg;
478 struct irq_pin_list *entry;
479
480 BUG_ON(irq >= nr_irqs);
481 cfg = irq_cfg(irq);
482 entry = cfg->irq_2_pin;
483 for (;;) {
484 unsigned int reg;
485
486 if (!entry)
487 break;
488
489 apic = entry->apic;
490 pin = entry->pin;
491 /*
492 * With interrupt-remapping, destination information comes
493 * from interrupt-remapping table entry.
494 */
495 if (!irq_remapped(irq))
496 io_apic_write(apic, 0x11 + pin*2, dest);
497 reg = io_apic_read(apic, 0x10 + pin*2);
498 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
499 reg |= vector;
500 io_apic_modify(apic, reg);
501 if (!entry->next)
502 break;
503 entry = entry->next;
504 }
505 }
506
507 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
508 {
509 struct irq_cfg *cfg = irq_cfg(irq);
510 unsigned long flags;
511 unsigned int dest;
512 cpumask_t tmp;
513 struct irq_desc *desc;
514
515 cpus_and(tmp, mask, cpu_online_map);
516 if (cpus_empty(tmp))
517 return;
518
519 if (assign_irq_vector(irq, mask))
520 return;
521
522 cpus_and(tmp, cfg->domain, mask);
523 dest = cpu_mask_to_apicid(tmp);
524
525 /*
526 * Only the high 8 bits are valid.
527 */
528 dest = SET_APIC_LOGICAL_ID(dest);
529
530 desc = irq_to_desc(irq);
531 spin_lock_irqsave(&ioapic_lock, flags);
532 __target_IO_APIC_irq(irq, dest, cfg->vector);
533 desc->affinity = mask;
534 spin_unlock_irqrestore(&ioapic_lock, flags);
535 }
536 #endif
537
538 /*
539 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
540 * shared ISA-space IRQs, so we have to support them. We are super
541 * fast in the common case, and fast for shared ISA-space IRQs.
542 */
543 int first_free_entry;
544 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
545 {
546 struct irq_cfg *cfg;
547 struct irq_pin_list *entry;
548
549 BUG_ON(irq >= nr_irqs);
550 /* first time to refer irq_cfg, so with new */
551 cfg = irq_cfg_alloc(irq);
552 entry = cfg->irq_2_pin;
553 if (!entry) {
554 entry = get_one_free_irq_2_pin();
555 cfg->irq_2_pin = entry;
556 entry->apic = apic;
557 entry->pin = pin;
558 printk(KERN_DEBUG " 0 add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
559 return;
560 }
561
562 while (entry->next) {
563 /* not again, please */
564 if (entry->apic == apic && entry->pin == pin)
565 return;
566
567 entry = entry->next;
568 }
569
570 entry->next = get_one_free_irq_2_pin();
571 entry = entry->next;
572 entry->apic = apic;
573 entry->pin = pin;
574 printk(KERN_DEBUG " x add_pin_to_irq: irq %d --> apic %d pin %d\n", irq, apic, pin);
575 }
576
577 /*
578 * Reroute an IRQ to a different pin.
579 */
580 static void __init replace_pin_at_irq(unsigned int irq,
581 int oldapic, int oldpin,
582 int newapic, int newpin)
583 {
584 struct irq_cfg *cfg = irq_cfg(irq);
585 struct irq_pin_list *entry = cfg->irq_2_pin;
586 int replaced = 0;
587
588 while (entry) {
589 if (entry->apic == oldapic && entry->pin == oldpin) {
590 entry->apic = newapic;
591 entry->pin = newpin;
592 replaced = 1;
593 /* every one is different, right? */
594 break;
595 }
596 entry = entry->next;
597 }
598
599 /* why? call replace before add? */
600 if (!replaced)
601 add_pin_to_irq(irq, newapic, newpin);
602 }
603
604
605 #define DO_ACTION(name,R,ACTION, FINAL) \
606 \
607 static void name##_IO_APIC_irq (unsigned int irq) \
608 __DO_ACTION(R, ACTION, FINAL)
609
610 /* mask = 1 */
611 DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, io_apic_sync(entry->apic))
612
613 /* mask = 0 */
614 DO_ACTION(__unmask, 0, &= ~IO_APIC_REDIR_MASKED, )
615
616 static void mask_IO_APIC_irq (unsigned int irq)
617 {
618 unsigned long flags;
619
620 spin_lock_irqsave(&ioapic_lock, flags);
621 __mask_IO_APIC_irq(irq);
622 spin_unlock_irqrestore(&ioapic_lock, flags);
623 }
624
625 static void unmask_IO_APIC_irq (unsigned int irq)
626 {
627 unsigned long flags;
628
629 spin_lock_irqsave(&ioapic_lock, flags);
630 __unmask_IO_APIC_irq(irq);
631 spin_unlock_irqrestore(&ioapic_lock, flags);
632 }
633
634 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
635 {
636 struct IO_APIC_route_entry entry;
637
638 /* Check delivery_mode to be sure we're not clearing an SMI pin */
639 entry = ioapic_read_entry(apic, pin);
640 if (entry.delivery_mode == dest_SMI)
641 return;
642 /*
643 * Disable it in the IO-APIC irq-routing table:
644 */
645 ioapic_mask_entry(apic, pin);
646 }
647
648 static void clear_IO_APIC (void)
649 {
650 int apic, pin;
651
652 for (apic = 0; apic < nr_ioapics; apic++)
653 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
654 clear_IO_APIC_pin(apic, pin);
655 }
656
657 /*
658 * Saves and masks all the unmasked IO-APIC RTE's
659 */
660 int save_mask_IO_APIC_setup(void)
661 {
662 union IO_APIC_reg_01 reg_01;
663 unsigned long flags;
664 int apic, pin;
665
666 /*
667 * The number of IO-APIC IRQ registers (== #pins):
668 */
669 for (apic = 0; apic < nr_ioapics; apic++) {
670 spin_lock_irqsave(&ioapic_lock, flags);
671 reg_01.raw = io_apic_read(apic, 1);
672 spin_unlock_irqrestore(&ioapic_lock, flags);
673 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
674 }
675
676 for (apic = 0; apic < nr_ioapics; apic++) {
677 early_ioapic_entries[apic] =
678 kzalloc(sizeof(struct IO_APIC_route_entry) *
679 nr_ioapic_registers[apic], GFP_KERNEL);
680 if (!early_ioapic_entries[apic])
681 return -ENOMEM;
682 }
683
684 for (apic = 0; apic < nr_ioapics; apic++)
685 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
686 struct IO_APIC_route_entry entry;
687
688 entry = early_ioapic_entries[apic][pin] =
689 ioapic_read_entry(apic, pin);
690 if (!entry.mask) {
691 entry.mask = 1;
692 ioapic_write_entry(apic, pin, entry);
693 }
694 }
695 return 0;
696 }
697
698 void restore_IO_APIC_setup(void)
699 {
700 int apic, pin;
701
702 for (apic = 0; apic < nr_ioapics; apic++)
703 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
704 ioapic_write_entry(apic, pin,
705 early_ioapic_entries[apic][pin]);
706 }
707
708 void reinit_intr_remapped_IO_APIC(int intr_remapping)
709 {
710 /*
711 * for now plain restore of previous settings.
712 * TBD: In the case of OS enabling interrupt-remapping,
713 * IO-APIC RTE's need to be setup to point to interrupt-remapping
714 * table entries. for now, do a plain restore, and wait for
715 * the setup_IO_APIC_irqs() to do proper initialization.
716 */
717 restore_IO_APIC_setup();
718 }
719
720 int skip_ioapic_setup;
721 int ioapic_force;
722
723 static int __init parse_noapic(char *str)
724 {
725 disable_ioapic_setup();
726 return 0;
727 }
728 early_param("noapic", parse_noapic);
729
730 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
731 static int __init disable_timer_pin_setup(char *arg)
732 {
733 disable_timer_pin_1 = 1;
734 return 1;
735 }
736 __setup("disable_timer_pin_1", disable_timer_pin_setup);
737
738
739 /*
740 * Find the IRQ entry number of a certain pin.
741 */
742 static int find_irq_entry(int apic, int pin, int type)
743 {
744 int i;
745
746 for (i = 0; i < mp_irq_entries; i++)
747 if (mp_irqs[i].mp_irqtype == type &&
748 (mp_irqs[i].mp_dstapic == mp_ioapics[apic].mp_apicid ||
749 mp_irqs[i].mp_dstapic == MP_APIC_ALL) &&
750 mp_irqs[i].mp_dstirq == pin)
751 return i;
752
753 return -1;
754 }
755
756 /*
757 * Find the pin to which IRQ[irq] (ISA) is connected
758 */
759 static int __init find_isa_irq_pin(int irq, int type)
760 {
761 int i;
762
763 for (i = 0; i < mp_irq_entries; i++) {
764 int lbus = mp_irqs[i].mp_srcbus;
765
766 if (test_bit(lbus, mp_bus_not_pci) &&
767 (mp_irqs[i].mp_irqtype == type) &&
768 (mp_irqs[i].mp_srcbusirq == irq))
769
770 return mp_irqs[i].mp_dstirq;
771 }
772 return -1;
773 }
774
775 static int __init find_isa_irq_apic(int irq, int type)
776 {
777 int i;
778
779 for (i = 0; i < mp_irq_entries; i++) {
780 int lbus = mp_irqs[i].mp_srcbus;
781
782 if (test_bit(lbus, mp_bus_not_pci) &&
783 (mp_irqs[i].mp_irqtype == type) &&
784 (mp_irqs[i].mp_srcbusirq == irq))
785 break;
786 }
787 if (i < mp_irq_entries) {
788 int apic;
789 for(apic = 0; apic < nr_ioapics; apic++) {
790 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic)
791 return apic;
792 }
793 }
794
795 return -1;
796 }
797
798 /*
799 * Find a specific PCI IRQ entry.
800 * Not an __init, possibly needed by modules
801 */
802 static int pin_2_irq(int idx, int apic, int pin);
803
804 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
805 {
806 int apic, i, best_guess = -1;
807
808 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
809 bus, slot, pin);
810 if (test_bit(bus, mp_bus_not_pci)) {
811 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
812 return -1;
813 }
814 for (i = 0; i < mp_irq_entries; i++) {
815 int lbus = mp_irqs[i].mp_srcbus;
816
817 for (apic = 0; apic < nr_ioapics; apic++)
818 if (mp_ioapics[apic].mp_apicid == mp_irqs[i].mp_dstapic ||
819 mp_irqs[i].mp_dstapic == MP_APIC_ALL)
820 break;
821
822 if (!test_bit(lbus, mp_bus_not_pci) &&
823 !mp_irqs[i].mp_irqtype &&
824 (bus == lbus) &&
825 (slot == ((mp_irqs[i].mp_srcbusirq >> 2) & 0x1f))) {
826 int irq = pin_2_irq(i,apic,mp_irqs[i].mp_dstirq);
827
828 if (!(apic || IO_APIC_IRQ(irq)))
829 continue;
830
831 if (pin == (mp_irqs[i].mp_srcbusirq & 3))
832 return irq;
833 /*
834 * Use the first all-but-pin matching entry as a
835 * best-guess fuzzy result for broken mptables.
836 */
837 if (best_guess < 0)
838 best_guess = irq;
839 }
840 }
841 BUG_ON(best_guess >= nr_irqs);
842 return best_guess;
843 }
844
845 /* ISA interrupts are always polarity zero edge triggered,
846 * when listed as conforming in the MP table. */
847
848 #define default_ISA_trigger(idx) (0)
849 #define default_ISA_polarity(idx) (0)
850
851 /* PCI interrupts are always polarity one level triggered,
852 * when listed as conforming in the MP table. */
853
854 #define default_PCI_trigger(idx) (1)
855 #define default_PCI_polarity(idx) (1)
856
857 static int MPBIOS_polarity(int idx)
858 {
859 int bus = mp_irqs[idx].mp_srcbus;
860 int polarity;
861
862 /*
863 * Determine IRQ line polarity (high active or low active):
864 */
865 switch (mp_irqs[idx].mp_irqflag & 3)
866 {
867 case 0: /* conforms, ie. bus-type dependent polarity */
868 if (test_bit(bus, mp_bus_not_pci))
869 polarity = default_ISA_polarity(idx);
870 else
871 polarity = default_PCI_polarity(idx);
872 break;
873 case 1: /* high active */
874 {
875 polarity = 0;
876 break;
877 }
878 case 2: /* reserved */
879 {
880 printk(KERN_WARNING "broken BIOS!!\n");
881 polarity = 1;
882 break;
883 }
884 case 3: /* low active */
885 {
886 polarity = 1;
887 break;
888 }
889 default: /* invalid */
890 {
891 printk(KERN_WARNING "broken BIOS!!\n");
892 polarity = 1;
893 break;
894 }
895 }
896 return polarity;
897 }
898
899 static int MPBIOS_trigger(int idx)
900 {
901 int bus = mp_irqs[idx].mp_srcbus;
902 int trigger;
903
904 /*
905 * Determine IRQ trigger mode (edge or level sensitive):
906 */
907 switch ((mp_irqs[idx].mp_irqflag>>2) & 3)
908 {
909 case 0: /* conforms, ie. bus-type dependent */
910 if (test_bit(bus, mp_bus_not_pci))
911 trigger = default_ISA_trigger(idx);
912 else
913 trigger = default_PCI_trigger(idx);
914 break;
915 case 1: /* edge */
916 {
917 trigger = 0;
918 break;
919 }
920 case 2: /* reserved */
921 {
922 printk(KERN_WARNING "broken BIOS!!\n");
923 trigger = 1;
924 break;
925 }
926 case 3: /* level */
927 {
928 trigger = 1;
929 break;
930 }
931 default: /* invalid */
932 {
933 printk(KERN_WARNING "broken BIOS!!\n");
934 trigger = 0;
935 break;
936 }
937 }
938 return trigger;
939 }
940
941 static inline int irq_polarity(int idx)
942 {
943 return MPBIOS_polarity(idx);
944 }
945
946 static inline int irq_trigger(int idx)
947 {
948 return MPBIOS_trigger(idx);
949 }
950
951 static int pin_2_irq(int idx, int apic, int pin)
952 {
953 int irq, i;
954 int bus = mp_irqs[idx].mp_srcbus;
955
956 /*
957 * Debugging check, we are in big trouble if this message pops up!
958 */
959 if (mp_irqs[idx].mp_dstirq != pin)
960 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
961
962 if (test_bit(bus, mp_bus_not_pci)) {
963 irq = mp_irqs[idx].mp_srcbusirq;
964 } else {
965 /*
966 * PCI IRQs are mapped in order
967 */
968 i = irq = 0;
969 while (i < apic)
970 irq += nr_ioapic_registers[i++];
971 irq += pin;
972 }
973 BUG_ON(irq >= nr_irqs);
974 return irq;
975 }
976
977 void lock_vector_lock(void)
978 {
979 /* Used to the online set of cpus does not change
980 * during assign_irq_vector.
981 */
982 spin_lock(&vector_lock);
983 }
984
985 void unlock_vector_lock(void)
986 {
987 spin_unlock(&vector_lock);
988 }
989
990 static int __assign_irq_vector(int irq, cpumask_t mask)
991 {
992 /*
993 * NOTE! The local APIC isn't very good at handling
994 * multiple interrupts at the same interrupt level.
995 * As the interrupt level is determined by taking the
996 * vector number and shifting that right by 4, we
997 * want to spread these out a bit so that they don't
998 * all fall in the same interrupt level.
999 *
1000 * Also, we've got to be careful not to trash gate
1001 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1002 */
1003 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1004 unsigned int old_vector;
1005 int cpu;
1006 struct irq_cfg *cfg;
1007
1008 BUG_ON((unsigned)irq >= nr_irqs);
1009 cfg = irq_cfg(irq);
1010
1011 /* Only try and allocate irqs on cpus that are present */
1012 cpus_and(mask, mask, cpu_online_map);
1013
1014 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1015 return -EBUSY;
1016
1017 old_vector = cfg->vector;
1018 if (old_vector) {
1019 cpumask_t tmp;
1020 cpus_and(tmp, cfg->domain, mask);
1021 if (!cpus_empty(tmp))
1022 return 0;
1023 }
1024
1025 for_each_cpu_mask_nr(cpu, mask) {
1026 cpumask_t domain, new_mask;
1027 int new_cpu;
1028 int vector, offset;
1029
1030 domain = vector_allocation_domain(cpu);
1031 cpus_and(new_mask, domain, cpu_online_map);
1032
1033 vector = current_vector;
1034 offset = current_offset;
1035 next:
1036 vector += 8;
1037 if (vector >= first_system_vector) {
1038 /* If we run out of vectors on large boxen, must share them. */
1039 offset = (offset + 1) % 8;
1040 vector = FIRST_DEVICE_VECTOR + offset;
1041 }
1042 if (unlikely(current_vector == vector))
1043 continue;
1044 if (vector == IA32_SYSCALL_VECTOR)
1045 goto next;
1046 for_each_cpu_mask_nr(new_cpu, new_mask)
1047 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1048 goto next;
1049 /* Found one! */
1050 current_vector = vector;
1051 current_offset = offset;
1052 if (old_vector) {
1053 cfg->move_in_progress = 1;
1054 cfg->old_domain = cfg->domain;
1055 }
1056 for_each_cpu_mask_nr(new_cpu, new_mask)
1057 per_cpu(vector_irq, new_cpu)[vector] = irq;
1058 cfg->vector = vector;
1059 cfg->domain = domain;
1060 return 0;
1061 }
1062 return -ENOSPC;
1063 }
1064
1065 static int assign_irq_vector(int irq, cpumask_t mask)
1066 {
1067 int err;
1068 unsigned long flags;
1069
1070 spin_lock_irqsave(&vector_lock, flags);
1071 err = __assign_irq_vector(irq, mask);
1072 spin_unlock_irqrestore(&vector_lock, flags);
1073 return err;
1074 }
1075
1076 static void __clear_irq_vector(int irq)
1077 {
1078 struct irq_cfg *cfg;
1079 cpumask_t mask;
1080 int cpu, vector;
1081
1082 BUG_ON((unsigned)irq >= nr_irqs);
1083 cfg = irq_cfg(irq);
1084 BUG_ON(!cfg->vector);
1085
1086 vector = cfg->vector;
1087 cpus_and(mask, cfg->domain, cpu_online_map);
1088 for_each_cpu_mask_nr(cpu, mask)
1089 per_cpu(vector_irq, cpu)[vector] = -1;
1090
1091 cfg->vector = 0;
1092 cpus_clear(cfg->domain);
1093 }
1094
1095 void __setup_vector_irq(int cpu)
1096 {
1097 /* Initialize vector_irq on a new cpu */
1098 /* This function must be called with vector_lock held */
1099 int irq, vector;
1100
1101 /* Mark the inuse vectors */
1102 for (irq = 0; irq < nr_irqs; ++irq) {
1103 struct irq_cfg *cfg = irq_cfg(irq);
1104
1105 if (!cpu_isset(cpu, cfg->domain))
1106 continue;
1107 vector = cfg->vector;
1108 per_cpu(vector_irq, cpu)[vector] = irq;
1109 }
1110 /* Mark the free vectors */
1111 for (vector = 0; vector < NR_VECTORS; ++vector) {
1112 struct irq_cfg *cfg;
1113
1114 irq = per_cpu(vector_irq, cpu)[vector];
1115 if (irq < 0)
1116 continue;
1117
1118 cfg = irq_cfg(irq);
1119 if (!cpu_isset(cpu, cfg->domain))
1120 per_cpu(vector_irq, cpu)[vector] = -1;
1121 }
1122 }
1123
1124 static struct irq_chip ioapic_chip;
1125 #ifdef CONFIG_INTR_REMAP
1126 static struct irq_chip ir_ioapic_chip;
1127 #endif
1128
1129 static void ioapic_register_intr(int irq, unsigned long trigger)
1130 {
1131 struct irq_desc *desc;
1132
1133 desc = irq_to_desc(irq);
1134 if (trigger)
1135 desc->status |= IRQ_LEVEL;
1136 else
1137 desc->status &= ~IRQ_LEVEL;
1138
1139 #ifdef CONFIG_INTR_REMAP
1140 if (irq_remapped(irq)) {
1141 desc->status |= IRQ_MOVE_PCNTXT;
1142 if (trigger)
1143 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1144 handle_fasteoi_irq,
1145 "fasteoi");
1146 else
1147 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1148 handle_edge_irq, "edge");
1149 return;
1150 }
1151 #endif
1152 if (trigger)
1153 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1154 handle_fasteoi_irq,
1155 "fasteoi");
1156 else
1157 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1158 handle_edge_irq, "edge");
1159 }
1160
1161 static int setup_ioapic_entry(int apic, int irq,
1162 struct IO_APIC_route_entry *entry,
1163 unsigned int destination, int trigger,
1164 int polarity, int vector)
1165 {
1166 /*
1167 * add it to the IO-APIC irq-routing table:
1168 */
1169 memset(entry,0,sizeof(*entry));
1170
1171 #ifdef CONFIG_INTR_REMAP
1172 if (intr_remapping_enabled) {
1173 struct intel_iommu *iommu = map_ioapic_to_ir(apic);
1174 struct irte irte;
1175 struct IR_IO_APIC_route_entry *ir_entry =
1176 (struct IR_IO_APIC_route_entry *) entry;
1177 int index;
1178
1179 if (!iommu)
1180 panic("No mapping iommu for ioapic %d\n", apic);
1181
1182 index = alloc_irte(iommu, irq, 1);
1183 if (index < 0)
1184 panic("Failed to allocate IRTE for ioapic %d\n", apic);
1185
1186 memset(&irte, 0, sizeof(irte));
1187
1188 irte.present = 1;
1189 irte.dst_mode = INT_DEST_MODE;
1190 irte.trigger_mode = trigger;
1191 irte.dlvry_mode = INT_DELIVERY_MODE;
1192 irte.vector = vector;
1193 irte.dest_id = IRTE_DEST(destination);
1194
1195 modify_irte(irq, &irte);
1196
1197 ir_entry->index2 = (index >> 15) & 0x1;
1198 ir_entry->zero = 0;
1199 ir_entry->format = 1;
1200 ir_entry->index = (index & 0x7fff);
1201 } else
1202 #endif
1203 {
1204 entry->delivery_mode = INT_DELIVERY_MODE;
1205 entry->dest_mode = INT_DEST_MODE;
1206 entry->dest = destination;
1207 }
1208
1209 entry->mask = 0; /* enable IRQ */
1210 entry->trigger = trigger;
1211 entry->polarity = polarity;
1212 entry->vector = vector;
1213
1214 /* Mask level triggered irqs.
1215 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1216 */
1217 if (trigger)
1218 entry->mask = 1;
1219 return 0;
1220 }
1221
1222 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
1223 int trigger, int polarity)
1224 {
1225 struct irq_cfg *cfg;
1226 struct IO_APIC_route_entry entry;
1227 cpumask_t mask;
1228
1229 if (!IO_APIC_IRQ(irq))
1230 return;
1231
1232 cfg = irq_cfg(irq);
1233
1234 mask = TARGET_CPUS;
1235 if (assign_irq_vector(irq, mask))
1236 return;
1237
1238 cpus_and(mask, cfg->domain, mask);
1239
1240 apic_printk(APIC_VERBOSE,KERN_DEBUG
1241 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1242 "IRQ %d Mode:%i Active:%i)\n",
1243 apic, mp_ioapics[apic].mp_apicid, pin, cfg->vector,
1244 irq, trigger, polarity);
1245
1246
1247 if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
1248 cpu_mask_to_apicid(mask), trigger, polarity,
1249 cfg->vector)) {
1250 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1251 mp_ioapics[apic].mp_apicid, pin);
1252 __clear_irq_vector(irq);
1253 return;
1254 }
1255
1256 ioapic_register_intr(irq, trigger);
1257 if (irq < 16)
1258 disable_8259A_irq(irq);
1259
1260 ioapic_write_entry(apic, pin, entry);
1261 }
1262
1263 static void __init setup_IO_APIC_irqs(void)
1264 {
1265 int apic, pin, idx, irq, first_notcon = 1;
1266
1267 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1268
1269 for (apic = 0; apic < nr_ioapics; apic++) {
1270 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1271
1272 idx = find_irq_entry(apic,pin,mp_INT);
1273 if (idx == -1) {
1274 if (first_notcon) {
1275 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mp_apicid, pin);
1276 first_notcon = 0;
1277 } else
1278 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mp_apicid, pin);
1279 continue;
1280 }
1281 if (!first_notcon) {
1282 apic_printk(APIC_VERBOSE, " not connected.\n");
1283 first_notcon = 1;
1284 }
1285
1286 irq = pin_2_irq(idx, apic, pin);
1287 add_pin_to_irq(irq, apic, pin);
1288
1289 setup_IO_APIC_irq(apic, pin, irq,
1290 irq_trigger(idx), irq_polarity(idx));
1291 }
1292 }
1293
1294 if (!first_notcon)
1295 apic_printk(APIC_VERBOSE, " not connected.\n");
1296 }
1297
1298 /*
1299 * Set up the timer pin, possibly with the 8259A-master behind.
1300 */
1301 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
1302 int vector)
1303 {
1304 struct IO_APIC_route_entry entry;
1305
1306 if (intr_remapping_enabled)
1307 return;
1308
1309 memset(&entry, 0, sizeof(entry));
1310
1311 /*
1312 * We use logical delivery to get the timer IRQ
1313 * to the first CPU.
1314 */
1315 entry.dest_mode = INT_DEST_MODE;
1316 entry.mask = 1; /* mask IRQ now */
1317 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
1318 entry.delivery_mode = INT_DELIVERY_MODE;
1319 entry.polarity = 0;
1320 entry.trigger = 0;
1321 entry.vector = vector;
1322
1323 /*
1324 * The timer IRQ doesn't have to know that behind the
1325 * scene we may have a 8259A-master in AEOI mode ...
1326 */
1327 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1328
1329 /*
1330 * Add it to the IO-APIC irq-routing table:
1331 */
1332 ioapic_write_entry(apic, pin, entry);
1333 }
1334
1335
1336 __apicdebuginit(void) print_IO_APIC(void)
1337 {
1338 int apic, i;
1339 union IO_APIC_reg_00 reg_00;
1340 union IO_APIC_reg_01 reg_01;
1341 union IO_APIC_reg_02 reg_02;
1342 unsigned long flags;
1343
1344 if (apic_verbosity == APIC_QUIET)
1345 return;
1346
1347 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1348 for (i = 0; i < nr_ioapics; i++)
1349 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1350 mp_ioapics[i].mp_apicid, nr_ioapic_registers[i]);
1351
1352 /*
1353 * We are a bit conservative about what we expect. We have to
1354 * know about every hardware change ASAP.
1355 */
1356 printk(KERN_INFO "testing the IO APIC.......................\n");
1357
1358 for (apic = 0; apic < nr_ioapics; apic++) {
1359
1360 spin_lock_irqsave(&ioapic_lock, flags);
1361 reg_00.raw = io_apic_read(apic, 0);
1362 reg_01.raw = io_apic_read(apic, 1);
1363 if (reg_01.bits.version >= 0x10)
1364 reg_02.raw = io_apic_read(apic, 2);
1365 spin_unlock_irqrestore(&ioapic_lock, flags);
1366
1367 printk("\n");
1368 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mp_apicid);
1369 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1370 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1371
1372 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1373 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1374
1375 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1376 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1377
1378 if (reg_01.bits.version >= 0x10) {
1379 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1380 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1381 }
1382
1383 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1384
1385 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1386 " Stat Dmod Deli Vect: \n");
1387
1388 for (i = 0; i <= reg_01.bits.entries; i++) {
1389 struct IO_APIC_route_entry entry;
1390
1391 entry = ioapic_read_entry(apic, i);
1392
1393 printk(KERN_DEBUG " %02x %03X ",
1394 i,
1395 entry.dest
1396 );
1397
1398 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1399 entry.mask,
1400 entry.trigger,
1401 entry.irr,
1402 entry.polarity,
1403 entry.delivery_status,
1404 entry.dest_mode,
1405 entry.delivery_mode,
1406 entry.vector
1407 );
1408 }
1409 }
1410 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1411 for (i = 0; i < nr_irqs; i++) {
1412 struct irq_cfg *cfg = irq_cfg(i);
1413 struct irq_pin_list *entry = cfg->irq_2_pin;
1414 if (!entry)
1415 continue;
1416 printk(KERN_DEBUG "IRQ%d ", i);
1417 for (;;) {
1418 printk("-> %d:%d", entry->apic, entry->pin);
1419 if (!entry->next)
1420 break;
1421 entry = entry->next;
1422 }
1423 printk("\n");
1424 }
1425
1426 printk(KERN_INFO ".................................... done.\n");
1427
1428 return;
1429 }
1430
1431 __apicdebuginit(void) print_APIC_bitfield(int base)
1432 {
1433 unsigned int v;
1434 int i, j;
1435
1436 if (apic_verbosity == APIC_QUIET)
1437 return;
1438
1439 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1440 for (i = 0; i < 8; i++) {
1441 v = apic_read(base + i*0x10);
1442 for (j = 0; j < 32; j++) {
1443 if (v & (1<<j))
1444 printk("1");
1445 else
1446 printk("0");
1447 }
1448 printk("\n");
1449 }
1450 }
1451
1452 __apicdebuginit(void) print_local_APIC(void *dummy)
1453 {
1454 unsigned int v, ver, maxlvt;
1455 unsigned long icr;
1456
1457 if (apic_verbosity == APIC_QUIET)
1458 return;
1459
1460 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1461 smp_processor_id(), hard_smp_processor_id());
1462 v = apic_read(APIC_ID);
1463 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1464 v = apic_read(APIC_LVR);
1465 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1466 ver = GET_APIC_VERSION(v);
1467 maxlvt = lapic_get_maxlvt();
1468
1469 v = apic_read(APIC_TASKPRI);
1470 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1471
1472 v = apic_read(APIC_ARBPRI);
1473 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1474 v & APIC_ARBPRI_MASK);
1475 v = apic_read(APIC_PROCPRI);
1476 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1477
1478 v = apic_read(APIC_EOI);
1479 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1480 v = apic_read(APIC_RRR);
1481 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1482 v = apic_read(APIC_LDR);
1483 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1484 v = apic_read(APIC_DFR);
1485 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1486 v = apic_read(APIC_SPIV);
1487 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1488
1489 printk(KERN_DEBUG "... APIC ISR field:\n");
1490 print_APIC_bitfield(APIC_ISR);
1491 printk(KERN_DEBUG "... APIC TMR field:\n");
1492 print_APIC_bitfield(APIC_TMR);
1493 printk(KERN_DEBUG "... APIC IRR field:\n");
1494 print_APIC_bitfield(APIC_IRR);
1495
1496 v = apic_read(APIC_ESR);
1497 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1498
1499 icr = apic_icr_read();
1500 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1501 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1502
1503 v = apic_read(APIC_LVTT);
1504 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1505
1506 if (maxlvt > 3) { /* PC is LVT#4. */
1507 v = apic_read(APIC_LVTPC);
1508 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1509 }
1510 v = apic_read(APIC_LVT0);
1511 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1512 v = apic_read(APIC_LVT1);
1513 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1514
1515 if (maxlvt > 2) { /* ERR is LVT#3. */
1516 v = apic_read(APIC_LVTERR);
1517 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1518 }
1519
1520 v = apic_read(APIC_TMICT);
1521 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1522 v = apic_read(APIC_TMCCT);
1523 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1524 v = apic_read(APIC_TDCR);
1525 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1526 printk("\n");
1527 }
1528
1529 __apicdebuginit(void) print_all_local_APICs(void)
1530 {
1531 on_each_cpu(print_local_APIC, NULL, 1);
1532 }
1533
1534 __apicdebuginit(void) print_PIC(void)
1535 {
1536 unsigned int v;
1537 unsigned long flags;
1538
1539 if (apic_verbosity == APIC_QUIET)
1540 return;
1541
1542 printk(KERN_DEBUG "\nprinting PIC contents\n");
1543
1544 spin_lock_irqsave(&i8259A_lock, flags);
1545
1546 v = inb(0xa1) << 8 | inb(0x21);
1547 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1548
1549 v = inb(0xa0) << 8 | inb(0x20);
1550 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1551
1552 outb(0x0b,0xa0);
1553 outb(0x0b,0x20);
1554 v = inb(0xa0) << 8 | inb(0x20);
1555 outb(0x0a,0xa0);
1556 outb(0x0a,0x20);
1557
1558 spin_unlock_irqrestore(&i8259A_lock, flags);
1559
1560 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1561
1562 v = inb(0x4d1) << 8 | inb(0x4d0);
1563 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1564 }
1565
1566 __apicdebuginit(int) print_all_ICs(void)
1567 {
1568 print_PIC();
1569 print_all_local_APICs();
1570 print_IO_APIC();
1571
1572 return 0;
1573 }
1574
1575 fs_initcall(print_all_ICs);
1576
1577
1578 void __init enable_IO_APIC(void)
1579 {
1580 union IO_APIC_reg_01 reg_01;
1581 int i8259_apic, i8259_pin;
1582 int apic;
1583 unsigned long flags;
1584
1585 /*
1586 * The number of IO-APIC IRQ registers (== #pins):
1587 */
1588 for (apic = 0; apic < nr_ioapics; apic++) {
1589 spin_lock_irqsave(&ioapic_lock, flags);
1590 reg_01.raw = io_apic_read(apic, 1);
1591 spin_unlock_irqrestore(&ioapic_lock, flags);
1592 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1593 }
1594 for(apic = 0; apic < nr_ioapics; apic++) {
1595 int pin;
1596 /* See if any of the pins is in ExtINT mode */
1597 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1598 struct IO_APIC_route_entry entry;
1599 entry = ioapic_read_entry(apic, pin);
1600
1601 /* If the interrupt line is enabled and in ExtInt mode
1602 * I have found the pin where the i8259 is connected.
1603 */
1604 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1605 ioapic_i8259.apic = apic;
1606 ioapic_i8259.pin = pin;
1607 goto found_i8259;
1608 }
1609 }
1610 }
1611 found_i8259:
1612 /* Look to see what if the MP table has reported the ExtINT */
1613 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1614 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1615 /* Trust the MP table if nothing is setup in the hardware */
1616 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1617 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1618 ioapic_i8259.pin = i8259_pin;
1619 ioapic_i8259.apic = i8259_apic;
1620 }
1621 /* Complain if the MP table and the hardware disagree */
1622 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1623 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1624 {
1625 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1626 }
1627
1628 /*
1629 * Do not trust the IO-APIC being empty at bootup
1630 */
1631 clear_IO_APIC();
1632 }
1633
1634 /*
1635 * Not an __init, needed by the reboot code
1636 */
1637 void disable_IO_APIC(void)
1638 {
1639 /*
1640 * Clear the IO-APIC before rebooting:
1641 */
1642 clear_IO_APIC();
1643
1644 /*
1645 * If the i8259 is routed through an IOAPIC
1646 * Put that IOAPIC in virtual wire mode
1647 * so legacy interrupts can be delivered.
1648 */
1649 if (ioapic_i8259.pin != -1) {
1650 struct IO_APIC_route_entry entry;
1651
1652 memset(&entry, 0, sizeof(entry));
1653 entry.mask = 0; /* Enabled */
1654 entry.trigger = 0; /* Edge */
1655 entry.irr = 0;
1656 entry.polarity = 0; /* High */
1657 entry.delivery_status = 0;
1658 entry.dest_mode = 0; /* Physical */
1659 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1660 entry.vector = 0;
1661 entry.dest = read_apic_id();
1662
1663 /*
1664 * Add it to the IO-APIC irq-routing table:
1665 */
1666 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1667 }
1668
1669 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1670 }
1671
1672 /*
1673 * There is a nasty bug in some older SMP boards, their mptable lies
1674 * about the timer IRQ. We do the following to work around the situation:
1675 *
1676 * - timer IRQ defaults to IO-APIC IRQ
1677 * - if this function detects that timer IRQs are defunct, then we fall
1678 * back to ISA timer IRQs
1679 */
1680 static int __init timer_irq_works(void)
1681 {
1682 unsigned long t1 = jiffies;
1683 unsigned long flags;
1684
1685 local_save_flags(flags);
1686 local_irq_enable();
1687 /* Let ten ticks pass... */
1688 mdelay((10 * 1000) / HZ);
1689 local_irq_restore(flags);
1690
1691 /*
1692 * Expect a few ticks at least, to be sure some possible
1693 * glue logic does not lock up after one or two first
1694 * ticks in a non-ExtINT mode. Also the local APIC
1695 * might have cached one ExtINT interrupt. Finally, at
1696 * least one tick may be lost due to delays.
1697 */
1698
1699 /* jiffies wrap? */
1700 if (time_after(jiffies, t1 + 4))
1701 return 1;
1702 return 0;
1703 }
1704
1705 /*
1706 * In the SMP+IOAPIC case it might happen that there are an unspecified
1707 * number of pending IRQ events unhandled. These cases are very rare,
1708 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1709 * better to do it this way as thus we do not have to be aware of
1710 * 'pending' interrupts in the IRQ path, except at this point.
1711 */
1712 /*
1713 * Edge triggered needs to resend any interrupt
1714 * that was delayed but this is now handled in the device
1715 * independent code.
1716 */
1717
1718 /*
1719 * Starting up a edge-triggered IO-APIC interrupt is
1720 * nasty - we need to make sure that we get the edge.
1721 * If it is already asserted for some reason, we need
1722 * return 1 to indicate that is was pending.
1723 *
1724 * This is not complete - we should be able to fake
1725 * an edge even if it isn't on the 8259A...
1726 */
1727
1728 static unsigned int startup_ioapic_irq(unsigned int irq)
1729 {
1730 int was_pending = 0;
1731 unsigned long flags;
1732
1733 spin_lock_irqsave(&ioapic_lock, flags);
1734 if (irq < 16) {
1735 disable_8259A_irq(irq);
1736 if (i8259A_irq_pending(irq))
1737 was_pending = 1;
1738 }
1739 __unmask_IO_APIC_irq(irq);
1740 spin_unlock_irqrestore(&ioapic_lock, flags);
1741
1742 return was_pending;
1743 }
1744
1745 static int ioapic_retrigger_irq(unsigned int irq)
1746 {
1747 struct irq_cfg *cfg = irq_cfg(irq);
1748 unsigned long flags;
1749
1750 spin_lock_irqsave(&vector_lock, flags);
1751 send_IPI_mask(cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector);
1752 spin_unlock_irqrestore(&vector_lock, flags);
1753
1754 return 1;
1755 }
1756
1757 /*
1758 * Level and edge triggered IO-APIC interrupts need different handling,
1759 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1760 * handled with the level-triggered descriptor, but that one has slightly
1761 * more overhead. Level-triggered interrupts cannot be handled with the
1762 * edge-triggered handler, without risking IRQ storms and other ugly
1763 * races.
1764 */
1765
1766 #ifdef CONFIG_SMP
1767
1768 #ifdef CONFIG_INTR_REMAP
1769 static void ir_irq_migration(struct work_struct *work);
1770
1771 static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
1772
1773 /*
1774 * Migrate the IO-APIC irq in the presence of intr-remapping.
1775 *
1776 * For edge triggered, irq migration is a simple atomic update(of vector
1777 * and cpu destination) of IRTE and flush the hardware cache.
1778 *
1779 * For level triggered, we need to modify the io-apic RTE aswell with the update
1780 * vector information, along with modifying IRTE with vector and destination.
1781 * So irq migration for level triggered is little bit more complex compared to
1782 * edge triggered migration. But the good news is, we use the same algorithm
1783 * for level triggered migration as we have today, only difference being,
1784 * we now initiate the irq migration from process context instead of the
1785 * interrupt context.
1786 *
1787 * In future, when we do a directed EOI (combined with cpu EOI broadcast
1788 * suppression) to the IO-APIC, level triggered irq migration will also be
1789 * as simple as edge triggered migration and we can do the irq migration
1790 * with a simple atomic update to IO-APIC RTE.
1791 */
1792 static void migrate_ioapic_irq(int irq, cpumask_t mask)
1793 {
1794 struct irq_cfg *cfg;
1795 struct irq_desc *desc;
1796 cpumask_t tmp, cleanup_mask;
1797 struct irte irte;
1798 int modify_ioapic_rte;
1799 unsigned int dest;
1800 unsigned long flags;
1801
1802 cpus_and(tmp, mask, cpu_online_map);
1803 if (cpus_empty(tmp))
1804 return;
1805
1806 if (get_irte(irq, &irte))
1807 return;
1808
1809 if (assign_irq_vector(irq, mask))
1810 return;
1811
1812 cfg = irq_cfg(irq);
1813 cpus_and(tmp, cfg->domain, mask);
1814 dest = cpu_mask_to_apicid(tmp);
1815
1816 desc = irq_to_desc(irq);
1817 modify_ioapic_rte = desc->status & IRQ_LEVEL;
1818 if (modify_ioapic_rte) {
1819 spin_lock_irqsave(&ioapic_lock, flags);
1820 __target_IO_APIC_irq(irq, dest, cfg->vector);
1821 spin_unlock_irqrestore(&ioapic_lock, flags);
1822 }
1823
1824 irte.vector = cfg->vector;
1825 irte.dest_id = IRTE_DEST(dest);
1826
1827 /*
1828 * Modified the IRTE and flushes the Interrupt entry cache.
1829 */
1830 modify_irte(irq, &irte);
1831
1832 if (cfg->move_in_progress) {
1833 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1834 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1835 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1836 cfg->move_in_progress = 0;
1837 }
1838
1839 desc->affinity = mask;
1840 }
1841
1842 static int migrate_irq_remapped_level(int irq)
1843 {
1844 int ret = -1;
1845 struct irq_desc *desc = irq_to_desc(irq);
1846
1847 mask_IO_APIC_irq(irq);
1848
1849 if (io_apic_level_ack_pending(irq)) {
1850 /*
1851 * Interrupt in progress. Migrating irq now will change the
1852 * vector information in the IO-APIC RTE and that will confuse
1853 * the EOI broadcast performed by cpu.
1854 * So, delay the irq migration to the next instance.
1855 */
1856 schedule_delayed_work(&ir_migration_work, 1);
1857 goto unmask;
1858 }
1859
1860 /* everthing is clear. we have right of way */
1861 migrate_ioapic_irq(irq, desc->pending_mask);
1862
1863 ret = 0;
1864 desc->status &= ~IRQ_MOVE_PENDING;
1865 cpus_clear(desc->pending_mask);
1866
1867 unmask:
1868 unmask_IO_APIC_irq(irq);
1869 return ret;
1870 }
1871
1872 static void ir_irq_migration(struct work_struct *work)
1873 {
1874 int irq;
1875
1876 for (irq = 0; irq < nr_irqs; irq++) {
1877 struct irq_desc *desc = irq_to_desc(irq);
1878 if (desc->status & IRQ_MOVE_PENDING) {
1879 unsigned long flags;
1880
1881 spin_lock_irqsave(&desc->lock, flags);
1882 if (!desc->chip->set_affinity ||
1883 !(desc->status & IRQ_MOVE_PENDING)) {
1884 desc->status &= ~IRQ_MOVE_PENDING;
1885 spin_unlock_irqrestore(&desc->lock, flags);
1886 continue;
1887 }
1888
1889 desc->chip->set_affinity(irq, desc->pending_mask);
1890 spin_unlock_irqrestore(&desc->lock, flags);
1891 }
1892 }
1893 }
1894
1895 /*
1896 * Migrates the IRQ destination in the process context.
1897 */
1898 static void set_ir_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
1899 {
1900 struct irq_desc *desc = irq_to_desc(irq);
1901
1902 if (desc->status & IRQ_LEVEL) {
1903 desc->status |= IRQ_MOVE_PENDING;
1904 desc->pending_mask = mask;
1905 migrate_irq_remapped_level(irq);
1906 return;
1907 }
1908
1909 migrate_ioapic_irq(irq, mask);
1910 }
1911 #endif
1912
1913 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1914 {
1915 unsigned vector, me;
1916 ack_APIC_irq();
1917 exit_idle();
1918 irq_enter();
1919
1920 me = smp_processor_id();
1921 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1922 unsigned int irq;
1923 struct irq_desc *desc;
1924 struct irq_cfg *cfg;
1925 irq = __get_cpu_var(vector_irq)[vector];
1926 if (irq >= nr_irqs)
1927 continue;
1928
1929 desc = irq_to_desc(irq);
1930 cfg = irq_cfg(irq);
1931 spin_lock(&desc->lock);
1932 if (!cfg->move_cleanup_count)
1933 goto unlock;
1934
1935 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1936 goto unlock;
1937
1938 __get_cpu_var(vector_irq)[vector] = -1;
1939 cfg->move_cleanup_count--;
1940 unlock:
1941 spin_unlock(&desc->lock);
1942 }
1943
1944 irq_exit();
1945 }
1946
1947 static void irq_complete_move(unsigned int irq)
1948 {
1949 struct irq_cfg *cfg = irq_cfg(irq);
1950 unsigned vector, me;
1951
1952 if (likely(!cfg->move_in_progress))
1953 return;
1954
1955 vector = ~get_irq_regs()->orig_ax;
1956 me = smp_processor_id();
1957 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1958 cpumask_t cleanup_mask;
1959
1960 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1961 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1962 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1963 cfg->move_in_progress = 0;
1964 }
1965 }
1966 #else
1967 static inline void irq_complete_move(unsigned int irq) {}
1968 #endif
1969 #ifdef CONFIG_INTR_REMAP
1970 static void ack_x2apic_level(unsigned int irq)
1971 {
1972 ack_x2APIC_irq();
1973 }
1974
1975 static void ack_x2apic_edge(unsigned int irq)
1976 {
1977 ack_x2APIC_irq();
1978 }
1979 #endif
1980
1981 static void ack_apic_edge(unsigned int irq)
1982 {
1983 irq_complete_move(irq);
1984 move_native_irq(irq);
1985 ack_APIC_irq();
1986 }
1987
1988 static void ack_apic_level(unsigned int irq)
1989 {
1990 int do_unmask_irq = 0;
1991
1992 irq_complete_move(irq);
1993 #ifdef CONFIG_GENERIC_PENDING_IRQ
1994 /* If we are moving the irq we need to mask it */
1995 if (unlikely(irq_to_desc(irq)->status & IRQ_MOVE_PENDING)) {
1996 do_unmask_irq = 1;
1997 mask_IO_APIC_irq(irq);
1998 }
1999 #endif
2000
2001 /*
2002 * We must acknowledge the irq before we move it or the acknowledge will
2003 * not propagate properly.
2004 */
2005 ack_APIC_irq();
2006
2007 /* Now we can move and renable the irq */
2008 if (unlikely(do_unmask_irq)) {
2009 /* Only migrate the irq if the ack has been received.
2010 *
2011 * On rare occasions the broadcast level triggered ack gets
2012 * delayed going to ioapics, and if we reprogram the
2013 * vector while Remote IRR is still set the irq will never
2014 * fire again.
2015 *
2016 * To prevent this scenario we read the Remote IRR bit
2017 * of the ioapic. This has two effects.
2018 * - On any sane system the read of the ioapic will
2019 * flush writes (and acks) going to the ioapic from
2020 * this cpu.
2021 * - We get to see if the ACK has actually been delivered.
2022 *
2023 * Based on failed experiments of reprogramming the
2024 * ioapic entry from outside of irq context starting
2025 * with masking the ioapic entry and then polling until
2026 * Remote IRR was clear before reprogramming the
2027 * ioapic I don't trust the Remote IRR bit to be
2028 * completey accurate.
2029 *
2030 * However there appears to be no other way to plug
2031 * this race, so if the Remote IRR bit is not
2032 * accurate and is causing problems then it is a hardware bug
2033 * and you can go talk to the chipset vendor about it.
2034 */
2035 if (!io_apic_level_ack_pending(irq))
2036 move_masked_irq(irq);
2037 unmask_IO_APIC_irq(irq);
2038 }
2039 }
2040
2041 static struct irq_chip ioapic_chip __read_mostly = {
2042 .name = "IO-APIC",
2043 .startup = startup_ioapic_irq,
2044 .mask = mask_IO_APIC_irq,
2045 .unmask = unmask_IO_APIC_irq,
2046 .ack = ack_apic_edge,
2047 .eoi = ack_apic_level,
2048 #ifdef CONFIG_SMP
2049 .set_affinity = set_ioapic_affinity_irq,
2050 #endif
2051 .retrigger = ioapic_retrigger_irq,
2052 };
2053
2054 #ifdef CONFIG_INTR_REMAP
2055 static struct irq_chip ir_ioapic_chip __read_mostly = {
2056 .name = "IR-IO-APIC",
2057 .startup = startup_ioapic_irq,
2058 .mask = mask_IO_APIC_irq,
2059 .unmask = unmask_IO_APIC_irq,
2060 .ack = ack_x2apic_edge,
2061 .eoi = ack_x2apic_level,
2062 #ifdef CONFIG_SMP
2063 .set_affinity = set_ir_ioapic_affinity_irq,
2064 #endif
2065 .retrigger = ioapic_retrigger_irq,
2066 };
2067 #endif
2068
2069 static inline void init_IO_APIC_traps(void)
2070 {
2071 int irq;
2072 struct irq_desc *desc;
2073
2074 /*
2075 * NOTE! The local APIC isn't very good at handling
2076 * multiple interrupts at the same interrupt level.
2077 * As the interrupt level is determined by taking the
2078 * vector number and shifting that right by 4, we
2079 * want to spread these out a bit so that they don't
2080 * all fall in the same interrupt level.
2081 *
2082 * Also, we've got to be careful not to trash gate
2083 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2084 */
2085 for (irq = 0; irq < nr_irqs ; irq++) {
2086 struct irq_cfg *cfg;
2087
2088 cfg = irq_cfg(irq);
2089 if (IO_APIC_IRQ(irq) && !cfg->vector) {
2090 /*
2091 * Hmm.. We don't have an entry for this,
2092 * so default to an old-fashioned 8259
2093 * interrupt if we can..
2094 */
2095 if (irq < 16)
2096 make_8259A_irq(irq);
2097 else {
2098 desc = irq_to_desc(irq);
2099 /* Strange. Oh, well.. */
2100 desc->chip = &no_irq_chip;
2101 }
2102 }
2103 }
2104 }
2105
2106 static void unmask_lapic_irq(unsigned int irq)
2107 {
2108 unsigned long v;
2109
2110 v = apic_read(APIC_LVT0);
2111 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2112 }
2113
2114 static void mask_lapic_irq(unsigned int irq)
2115 {
2116 unsigned long v;
2117
2118 v = apic_read(APIC_LVT0);
2119 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2120 }
2121
2122 static void ack_lapic_irq (unsigned int irq)
2123 {
2124 ack_APIC_irq();
2125 }
2126
2127 static struct irq_chip lapic_chip __read_mostly = {
2128 .name = "local-APIC",
2129 .mask = mask_lapic_irq,
2130 .unmask = unmask_lapic_irq,
2131 .ack = ack_lapic_irq,
2132 };
2133
2134 static void lapic_register_intr(int irq)
2135 {
2136 struct irq_desc *desc;
2137
2138 desc = irq_to_desc(irq);
2139 desc->status &= ~IRQ_LEVEL;
2140 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2141 "edge");
2142 }
2143
2144 static void __init setup_nmi(void)
2145 {
2146 /*
2147 * Dirty trick to enable the NMI watchdog ...
2148 * We put the 8259A master into AEOI mode and
2149 * unmask on all local APICs LVT0 as NMI.
2150 *
2151 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2152 * is from Maciej W. Rozycki - so we do not have to EOI from
2153 * the NMI handler or the timer interrupt.
2154 */
2155 printk(KERN_INFO "activating NMI Watchdog ...");
2156
2157 enable_NMI_through_LVT0();
2158
2159 printk(" done.\n");
2160 }
2161
2162 /*
2163 * This looks a bit hackish but it's about the only one way of sending
2164 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2165 * not support the ExtINT mode, unfortunately. We need to send these
2166 * cycles as some i82489DX-based boards have glue logic that keeps the
2167 * 8259A interrupt line asserted until INTA. --macro
2168 */
2169 static inline void __init unlock_ExtINT_logic(void)
2170 {
2171 int apic, pin, i;
2172 struct IO_APIC_route_entry entry0, entry1;
2173 unsigned char save_control, save_freq_select;
2174
2175 pin = find_isa_irq_pin(8, mp_INT);
2176 apic = find_isa_irq_apic(8, mp_INT);
2177 if (pin == -1)
2178 return;
2179
2180 entry0 = ioapic_read_entry(apic, pin);
2181
2182 clear_IO_APIC_pin(apic, pin);
2183
2184 memset(&entry1, 0, sizeof(entry1));
2185
2186 entry1.dest_mode = 0; /* physical delivery */
2187 entry1.mask = 0; /* unmask IRQ now */
2188 entry1.dest = hard_smp_processor_id();
2189 entry1.delivery_mode = dest_ExtINT;
2190 entry1.polarity = entry0.polarity;
2191 entry1.trigger = 0;
2192 entry1.vector = 0;
2193
2194 ioapic_write_entry(apic, pin, entry1);
2195
2196 save_control = CMOS_READ(RTC_CONTROL);
2197 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2198 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2199 RTC_FREQ_SELECT);
2200 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2201
2202 i = 100;
2203 while (i-- > 0) {
2204 mdelay(10);
2205 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2206 i -= 10;
2207 }
2208
2209 CMOS_WRITE(save_control, RTC_CONTROL);
2210 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2211 clear_IO_APIC_pin(apic, pin);
2212
2213 ioapic_write_entry(apic, pin, entry0);
2214 }
2215
2216 /*
2217 * This code may look a bit paranoid, but it's supposed to cooperate with
2218 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2219 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2220 * fanatically on his truly buggy board.
2221 *
2222 * FIXME: really need to revamp this for modern platforms only.
2223 */
2224 static inline void __init check_timer(void)
2225 {
2226 struct irq_cfg *cfg = irq_cfg(0);
2227 int apic1, pin1, apic2, pin2;
2228 unsigned long flags;
2229 int no_pin1 = 0;
2230
2231 local_irq_save(flags);
2232
2233 /*
2234 * get/set the timer IRQ vector:
2235 */
2236 disable_8259A_irq(0);
2237 assign_irq_vector(0, TARGET_CPUS);
2238
2239 /*
2240 * As IRQ0 is to be enabled in the 8259A, the virtual
2241 * wire has to be disabled in the local APIC.
2242 */
2243 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2244 init_8259A(1);
2245
2246 pin1 = find_isa_irq_pin(0, mp_INT);
2247 apic1 = find_isa_irq_apic(0, mp_INT);
2248 pin2 = ioapic_i8259.pin;
2249 apic2 = ioapic_i8259.apic;
2250
2251 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2252 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2253 cfg->vector, apic1, pin1, apic2, pin2);
2254
2255 /*
2256 * Some BIOS writers are clueless and report the ExtINTA
2257 * I/O APIC input from the cascaded 8259A as the timer
2258 * interrupt input. So just in case, if only one pin
2259 * was found above, try it both directly and through the
2260 * 8259A.
2261 */
2262 if (pin1 == -1) {
2263 if (intr_remapping_enabled)
2264 panic("BIOS bug: timer not connected to IO-APIC");
2265 pin1 = pin2;
2266 apic1 = apic2;
2267 no_pin1 = 1;
2268 } else if (pin2 == -1) {
2269 pin2 = pin1;
2270 apic2 = apic1;
2271 }
2272
2273 if (pin1 != -1) {
2274 /*
2275 * Ok, does IRQ0 through the IOAPIC work?
2276 */
2277 if (no_pin1) {
2278 add_pin_to_irq(0, apic1, pin1);
2279 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2280 }
2281 unmask_IO_APIC_irq(0);
2282 if (!no_timer_check && timer_irq_works()) {
2283 if (nmi_watchdog == NMI_IO_APIC) {
2284 setup_nmi();
2285 enable_8259A_irq(0);
2286 }
2287 if (disable_timer_pin_1 > 0)
2288 clear_IO_APIC_pin(0, pin1);
2289 goto out;
2290 }
2291 if (intr_remapping_enabled)
2292 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2293 clear_IO_APIC_pin(apic1, pin1);
2294 if (!no_pin1)
2295 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2296 "8254 timer not connected to IO-APIC\n");
2297
2298 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2299 "(IRQ0) through the 8259A ...\n");
2300 apic_printk(APIC_QUIET, KERN_INFO
2301 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2302 /*
2303 * legacy devices should be connected to IO APIC #0
2304 */
2305 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2306 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2307 unmask_IO_APIC_irq(0);
2308 enable_8259A_irq(0);
2309 if (timer_irq_works()) {
2310 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2311 timer_through_8259 = 1;
2312 if (nmi_watchdog == NMI_IO_APIC) {
2313 disable_8259A_irq(0);
2314 setup_nmi();
2315 enable_8259A_irq(0);
2316 }
2317 goto out;
2318 }
2319 /*
2320 * Cleanup, just in case ...
2321 */
2322 disable_8259A_irq(0);
2323 clear_IO_APIC_pin(apic2, pin2);
2324 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2325 }
2326
2327 if (nmi_watchdog == NMI_IO_APIC) {
2328 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2329 "through the IO-APIC - disabling NMI Watchdog!\n");
2330 nmi_watchdog = NMI_NONE;
2331 }
2332
2333 apic_printk(APIC_QUIET, KERN_INFO
2334 "...trying to set up timer as Virtual Wire IRQ...\n");
2335
2336 lapic_register_intr(0);
2337 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2338 enable_8259A_irq(0);
2339
2340 if (timer_irq_works()) {
2341 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2342 goto out;
2343 }
2344 disable_8259A_irq(0);
2345 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2346 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2347
2348 apic_printk(APIC_QUIET, KERN_INFO
2349 "...trying to set up timer as ExtINT IRQ...\n");
2350
2351 init_8259A(0);
2352 make_8259A_irq(0);
2353 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2354
2355 unlock_ExtINT_logic();
2356
2357 if (timer_irq_works()) {
2358 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2359 goto out;
2360 }
2361 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2362 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2363 "report. Then try booting with the 'noapic' option.\n");
2364 out:
2365 local_irq_restore(flags);
2366 }
2367
2368 static int __init notimercheck(char *s)
2369 {
2370 no_timer_check = 1;
2371 return 1;
2372 }
2373 __setup("no_timer_check", notimercheck);
2374
2375 /*
2376 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2377 * to devices. However there may be an I/O APIC pin available for
2378 * this interrupt regardless. The pin may be left unconnected, but
2379 * typically it will be reused as an ExtINT cascade interrupt for
2380 * the master 8259A. In the MPS case such a pin will normally be
2381 * reported as an ExtINT interrupt in the MP table. With ACPI
2382 * there is no provision for ExtINT interrupts, and in the absence
2383 * of an override it would be treated as an ordinary ISA I/O APIC
2384 * interrupt, that is edge-triggered and unmasked by default. We
2385 * used to do this, but it caused problems on some systems because
2386 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2387 * the same ExtINT cascade interrupt to drive the local APIC of the
2388 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2389 * the I/O APIC in all cases now. No actual device should request
2390 * it anyway. --macro
2391 */
2392 #define PIC_IRQS (1<<2)
2393
2394 void __init setup_IO_APIC(void)
2395 {
2396
2397 /*
2398 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2399 */
2400
2401 io_apic_irqs = ~PIC_IRQS;
2402
2403 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2404
2405 sync_Arb_IDs();
2406 setup_IO_APIC_irqs();
2407 init_IO_APIC_traps();
2408 check_timer();
2409 }
2410
2411 struct sysfs_ioapic_data {
2412 struct sys_device dev;
2413 struct IO_APIC_route_entry entry[0];
2414 };
2415 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2416
2417 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2418 {
2419 struct IO_APIC_route_entry *entry;
2420 struct sysfs_ioapic_data *data;
2421 int i;
2422
2423 data = container_of(dev, struct sysfs_ioapic_data, dev);
2424 entry = data->entry;
2425 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
2426 *entry = ioapic_read_entry(dev->id, i);
2427
2428 return 0;
2429 }
2430
2431 static int ioapic_resume(struct sys_device *dev)
2432 {
2433 struct IO_APIC_route_entry *entry;
2434 struct sysfs_ioapic_data *data;
2435 unsigned long flags;
2436 union IO_APIC_reg_00 reg_00;
2437 int i;
2438
2439 data = container_of(dev, struct sysfs_ioapic_data, dev);
2440 entry = data->entry;
2441
2442 spin_lock_irqsave(&ioapic_lock, flags);
2443 reg_00.raw = io_apic_read(dev->id, 0);
2444 if (reg_00.bits.ID != mp_ioapics[dev->id].mp_apicid) {
2445 reg_00.bits.ID = mp_ioapics[dev->id].mp_apicid;
2446 io_apic_write(dev->id, 0, reg_00.raw);
2447 }
2448 spin_unlock_irqrestore(&ioapic_lock, flags);
2449 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
2450 ioapic_write_entry(dev->id, i, entry[i]);
2451
2452 return 0;
2453 }
2454
2455 static struct sysdev_class ioapic_sysdev_class = {
2456 .name = "ioapic",
2457 .suspend = ioapic_suspend,
2458 .resume = ioapic_resume,
2459 };
2460
2461 static int __init ioapic_init_sysfs(void)
2462 {
2463 struct sys_device * dev;
2464 int i, size, error;
2465
2466 error = sysdev_class_register(&ioapic_sysdev_class);
2467 if (error)
2468 return error;
2469
2470 for (i = 0; i < nr_ioapics; i++ ) {
2471 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2472 * sizeof(struct IO_APIC_route_entry);
2473 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
2474 if (!mp_ioapic_data[i]) {
2475 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2476 continue;
2477 }
2478 dev = &mp_ioapic_data[i]->dev;
2479 dev->id = i;
2480 dev->cls = &ioapic_sysdev_class;
2481 error = sysdev_register(dev);
2482 if (error) {
2483 kfree(mp_ioapic_data[i]);
2484 mp_ioapic_data[i] = NULL;
2485 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2486 continue;
2487 }
2488 }
2489
2490 return 0;
2491 }
2492
2493 device_initcall(ioapic_init_sysfs);
2494
2495 /*
2496 * Dynamic irq allocate and deallocation
2497 */
2498 int create_irq(void)
2499 {
2500 /* Allocate an unused irq */
2501 int irq;
2502 int new;
2503 unsigned long flags;
2504 struct irq_cfg *cfg_new;
2505
2506 irq = -ENOSPC;
2507 spin_lock_irqsave(&vector_lock, flags);
2508 for (new = (nr_irqs - 1); new >= 0; new--) {
2509 if (platform_legacy_irq(new))
2510 continue;
2511 cfg_new = irq_cfg(new);
2512 if (cfg_new && cfg_new->vector != 0)
2513 continue;
2514 /* check if need to create one */
2515 if (!cfg_new)
2516 cfg_new = irq_cfg_alloc(new);
2517 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
2518 irq = new;
2519 break;
2520 }
2521 spin_unlock_irqrestore(&vector_lock, flags);
2522
2523 if (irq >= 0) {
2524 dynamic_irq_init(irq);
2525 }
2526 return irq;
2527 }
2528
2529 void destroy_irq(unsigned int irq)
2530 {
2531 unsigned long flags;
2532
2533 dynamic_irq_cleanup(irq);
2534
2535 #ifdef CONFIG_INTR_REMAP
2536 free_irte(irq);
2537 #endif
2538 spin_lock_irqsave(&vector_lock, flags);
2539 __clear_irq_vector(irq);
2540 spin_unlock_irqrestore(&vector_lock, flags);
2541 }
2542
2543 /*
2544 * MSI message composition
2545 */
2546 #ifdef CONFIG_PCI_MSI
2547 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2548 {
2549 struct irq_cfg *cfg;
2550 int err;
2551 unsigned dest;
2552 cpumask_t tmp;
2553
2554 tmp = TARGET_CPUS;
2555 err = assign_irq_vector(irq, tmp);
2556 if (err)
2557 return err;
2558
2559 cfg = irq_cfg(irq);
2560 cpus_and(tmp, cfg->domain, tmp);
2561 dest = cpu_mask_to_apicid(tmp);
2562
2563 #ifdef CONFIG_INTR_REMAP
2564 if (irq_remapped(irq)) {
2565 struct irte irte;
2566 int ir_index;
2567 u16 sub_handle;
2568
2569 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
2570 BUG_ON(ir_index == -1);
2571
2572 memset (&irte, 0, sizeof(irte));
2573
2574 irte.present = 1;
2575 irte.dst_mode = INT_DEST_MODE;
2576 irte.trigger_mode = 0; /* edge */
2577 irte.dlvry_mode = INT_DELIVERY_MODE;
2578 irte.vector = cfg->vector;
2579 irte.dest_id = IRTE_DEST(dest);
2580
2581 modify_irte(irq, &irte);
2582
2583 msg->address_hi = MSI_ADDR_BASE_HI;
2584 msg->data = sub_handle;
2585 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
2586 MSI_ADDR_IR_SHV |
2587 MSI_ADDR_IR_INDEX1(ir_index) |
2588 MSI_ADDR_IR_INDEX2(ir_index);
2589 } else
2590 #endif
2591 {
2592 msg->address_hi = MSI_ADDR_BASE_HI;
2593 msg->address_lo =
2594 MSI_ADDR_BASE_LO |
2595 ((INT_DEST_MODE == 0) ?
2596 MSI_ADDR_DEST_MODE_PHYSICAL:
2597 MSI_ADDR_DEST_MODE_LOGICAL) |
2598 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2599 MSI_ADDR_REDIRECTION_CPU:
2600 MSI_ADDR_REDIRECTION_LOWPRI) |
2601 MSI_ADDR_DEST_ID(dest);
2602
2603 msg->data =
2604 MSI_DATA_TRIGGER_EDGE |
2605 MSI_DATA_LEVEL_ASSERT |
2606 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2607 MSI_DATA_DELIVERY_FIXED:
2608 MSI_DATA_DELIVERY_LOWPRI) |
2609 MSI_DATA_VECTOR(cfg->vector);
2610 }
2611 return err;
2612 }
2613
2614 #ifdef CONFIG_SMP
2615 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2616 {
2617 struct irq_cfg *cfg;
2618 struct msi_msg msg;
2619 unsigned int dest;
2620 cpumask_t tmp;
2621 struct irq_desc *desc;
2622
2623 cpus_and(tmp, mask, cpu_online_map);
2624 if (cpus_empty(tmp))
2625 return;
2626
2627 if (assign_irq_vector(irq, mask))
2628 return;
2629
2630 cfg = irq_cfg(irq);
2631 cpus_and(tmp, cfg->domain, mask);
2632 dest = cpu_mask_to_apicid(tmp);
2633
2634 read_msi_msg(irq, &msg);
2635
2636 msg.data &= ~MSI_DATA_VECTOR_MASK;
2637 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2638 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2639 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2640
2641 write_msi_msg(irq, &msg);
2642 desc = irq_to_desc(irq);
2643 desc->affinity = mask;
2644 }
2645
2646 #ifdef CONFIG_INTR_REMAP
2647 /*
2648 * Migrate the MSI irq to another cpumask. This migration is
2649 * done in the process context using interrupt-remapping hardware.
2650 */
2651 static void ir_set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2652 {
2653 struct irq_cfg *cfg;
2654 unsigned int dest;
2655 cpumask_t tmp, cleanup_mask;
2656 struct irte irte;
2657 struct irq_desc *desc;
2658
2659 cpus_and(tmp, mask, cpu_online_map);
2660 if (cpus_empty(tmp))
2661 return;
2662
2663 if (get_irte(irq, &irte))
2664 return;
2665
2666 if (assign_irq_vector(irq, mask))
2667 return;
2668
2669 cfg = irq_cfg(irq);
2670 cpus_and(tmp, cfg->domain, mask);
2671 dest = cpu_mask_to_apicid(tmp);
2672
2673 irte.vector = cfg->vector;
2674 irte.dest_id = IRTE_DEST(dest);
2675
2676 /*
2677 * atomically update the IRTE with the new destination and vector.
2678 */
2679 modify_irte(irq, &irte);
2680
2681 /*
2682 * After this point, all the interrupts will start arriving
2683 * at the new destination. So, time to cleanup the previous
2684 * vector allocation.
2685 */
2686 if (cfg->move_in_progress) {
2687 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
2688 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
2689 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2690 cfg->move_in_progress = 0;
2691 }
2692
2693 desc = irq_to_desc(irq);
2694 desc->affinity = mask;
2695 }
2696 #endif
2697 #endif /* CONFIG_SMP */
2698
2699 /*
2700 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2701 * which implement the MSI or MSI-X Capability Structure.
2702 */
2703 static struct irq_chip msi_chip = {
2704 .name = "PCI-MSI",
2705 .unmask = unmask_msi_irq,
2706 .mask = mask_msi_irq,
2707 .ack = ack_apic_edge,
2708 #ifdef CONFIG_SMP
2709 .set_affinity = set_msi_irq_affinity,
2710 #endif
2711 .retrigger = ioapic_retrigger_irq,
2712 };
2713
2714 #ifdef CONFIG_INTR_REMAP
2715 static struct irq_chip msi_ir_chip = {
2716 .name = "IR-PCI-MSI",
2717 .unmask = unmask_msi_irq,
2718 .mask = mask_msi_irq,
2719 .ack = ack_x2apic_edge,
2720 #ifdef CONFIG_SMP
2721 .set_affinity = ir_set_msi_irq_affinity,
2722 #endif
2723 .retrigger = ioapic_retrigger_irq,
2724 };
2725
2726 /*
2727 * Map the PCI dev to the corresponding remapping hardware unit
2728 * and allocate 'nvec' consecutive interrupt-remapping table entries
2729 * in it.
2730 */
2731 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
2732 {
2733 struct intel_iommu *iommu;
2734 int index;
2735
2736 iommu = map_dev_to_ir(dev);
2737 if (!iommu) {
2738 printk(KERN_ERR
2739 "Unable to map PCI %s to iommu\n", pci_name(dev));
2740 return -ENOENT;
2741 }
2742
2743 index = alloc_irte(iommu, irq, nvec);
2744 if (index < 0) {
2745 printk(KERN_ERR
2746 "Unable to allocate %d IRTE for PCI %s\n", nvec,
2747 pci_name(dev));
2748 return -ENOSPC;
2749 }
2750 return index;
2751 }
2752 #endif
2753
2754 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc, int irq)
2755 {
2756 int ret;
2757 struct msi_msg msg;
2758
2759 ret = msi_compose_msg(dev, irq, &msg);
2760 if (ret < 0)
2761 return ret;
2762
2763 set_irq_msi(irq, desc);
2764 write_msi_msg(irq, &msg);
2765
2766 #ifdef CONFIG_INTR_REMAP
2767 if (irq_remapped(irq)) {
2768 struct irq_desc *desc = irq_to_desc(irq);
2769 /*
2770 * irq migration in process context
2771 */
2772 desc->status |= IRQ_MOVE_PCNTXT;
2773 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
2774 } else
2775 #endif
2776 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2777
2778 return 0;
2779 }
2780
2781 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2782 {
2783 int irq, ret;
2784
2785 irq = create_irq();
2786 if (irq < 0)
2787 return irq;
2788
2789 #ifdef CONFIG_INTR_REMAP
2790 if (!intr_remapping_enabled)
2791 goto no_ir;
2792
2793 ret = msi_alloc_irte(dev, irq, 1);
2794 if (ret < 0)
2795 goto error;
2796 no_ir:
2797 #endif
2798 ret = setup_msi_irq(dev, desc, irq);
2799 if (ret < 0) {
2800 destroy_irq(irq);
2801 return ret;
2802 }
2803 return 0;
2804
2805 #ifdef CONFIG_INTR_REMAP
2806 error:
2807 destroy_irq(irq);
2808 return ret;
2809 #endif
2810 }
2811
2812 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
2813 {
2814 int irq, ret, sub_handle;
2815 struct msi_desc *desc;
2816 #ifdef CONFIG_INTR_REMAP
2817 struct intel_iommu *iommu = 0;
2818 int index = 0;
2819 #endif
2820
2821 sub_handle = 0;
2822 list_for_each_entry(desc, &dev->msi_list, list) {
2823 irq = create_irq();
2824 if (irq < 0)
2825 return irq;
2826 #ifdef CONFIG_INTR_REMAP
2827 if (!intr_remapping_enabled)
2828 goto no_ir;
2829
2830 if (!sub_handle) {
2831 /*
2832 * allocate the consecutive block of IRTE's
2833 * for 'nvec'
2834 */
2835 index = msi_alloc_irte(dev, irq, nvec);
2836 if (index < 0) {
2837 ret = index;
2838 goto error;
2839 }
2840 } else {
2841 iommu = map_dev_to_ir(dev);
2842 if (!iommu) {
2843 ret = -ENOENT;
2844 goto error;
2845 }
2846 /*
2847 * setup the mapping between the irq and the IRTE
2848 * base index, the sub_handle pointing to the
2849 * appropriate interrupt remap table entry.
2850 */
2851 set_irte_irq(irq, iommu, index, sub_handle);
2852 }
2853 no_ir:
2854 #endif
2855 ret = setup_msi_irq(dev, desc, irq);
2856 if (ret < 0)
2857 goto error;
2858 sub_handle++;
2859 }
2860 return 0;
2861
2862 error:
2863 destroy_irq(irq);
2864 return ret;
2865 }
2866
2867 void arch_teardown_msi_irq(unsigned int irq)
2868 {
2869 destroy_irq(irq);
2870 }
2871
2872 #ifdef CONFIG_DMAR
2873 #ifdef CONFIG_SMP
2874 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2875 {
2876 struct irq_cfg *cfg;
2877 struct msi_msg msg;
2878 unsigned int dest;
2879 cpumask_t tmp;
2880 struct irq_desc *desc;
2881
2882 cpus_and(tmp, mask, cpu_online_map);
2883 if (cpus_empty(tmp))
2884 return;
2885
2886 if (assign_irq_vector(irq, mask))
2887 return;
2888
2889 cfg = irq_cfg(irq);
2890 cpus_and(tmp, cfg->domain, mask);
2891 dest = cpu_mask_to_apicid(tmp);
2892
2893 dmar_msi_read(irq, &msg);
2894
2895 msg.data &= ~MSI_DATA_VECTOR_MASK;
2896 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2897 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2898 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2899
2900 dmar_msi_write(irq, &msg);
2901 desc = irq_to_desc(irq);
2902 desc->affinity = mask;
2903 }
2904 #endif /* CONFIG_SMP */
2905
2906 struct irq_chip dmar_msi_type = {
2907 .name = "DMAR_MSI",
2908 .unmask = dmar_msi_unmask,
2909 .mask = dmar_msi_mask,
2910 .ack = ack_apic_edge,
2911 #ifdef CONFIG_SMP
2912 .set_affinity = dmar_msi_set_affinity,
2913 #endif
2914 .retrigger = ioapic_retrigger_irq,
2915 };
2916
2917 int arch_setup_dmar_msi(unsigned int irq)
2918 {
2919 int ret;
2920 struct msi_msg msg;
2921
2922 ret = msi_compose_msg(NULL, irq, &msg);
2923 if (ret < 0)
2924 return ret;
2925 dmar_msi_write(irq, &msg);
2926 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
2927 "edge");
2928 return 0;
2929 }
2930 #endif
2931
2932 #endif /* CONFIG_PCI_MSI */
2933 /*
2934 * Hypertransport interrupt support
2935 */
2936 #ifdef CONFIG_HT_IRQ
2937
2938 #ifdef CONFIG_SMP
2939
2940 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2941 {
2942 struct ht_irq_msg msg;
2943 fetch_ht_irq_msg(irq, &msg);
2944
2945 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2946 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2947
2948 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2949 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2950
2951 write_ht_irq_msg(irq, &msg);
2952 }
2953
2954 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2955 {
2956 struct irq_cfg *cfg;
2957 unsigned int dest;
2958 cpumask_t tmp;
2959 struct irq_desc *desc;
2960
2961 cpus_and(tmp, mask, cpu_online_map);
2962 if (cpus_empty(tmp))
2963 return;
2964
2965 if (assign_irq_vector(irq, mask))
2966 return;
2967
2968 cfg = irq_cfg(irq);
2969 cpus_and(tmp, cfg->domain, mask);
2970 dest = cpu_mask_to_apicid(tmp);
2971
2972 target_ht_irq(irq, dest, cfg->vector);
2973 desc = irq_to_desc(irq);
2974 desc->affinity = mask;
2975 }
2976 #endif
2977
2978 static struct irq_chip ht_irq_chip = {
2979 .name = "PCI-HT",
2980 .mask = mask_ht_irq,
2981 .unmask = unmask_ht_irq,
2982 .ack = ack_apic_edge,
2983 #ifdef CONFIG_SMP
2984 .set_affinity = set_ht_irq_affinity,
2985 #endif
2986 .retrigger = ioapic_retrigger_irq,
2987 };
2988
2989 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2990 {
2991 struct irq_cfg *cfg;
2992 int err;
2993 cpumask_t tmp;
2994
2995 tmp = TARGET_CPUS;
2996 err = assign_irq_vector(irq, tmp);
2997 if (!err) {
2998 struct ht_irq_msg msg;
2999 unsigned dest;
3000
3001 cfg = irq_cfg(irq);
3002 cpus_and(tmp, cfg->domain, tmp);
3003 dest = cpu_mask_to_apicid(tmp);
3004
3005 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3006
3007 msg.address_lo =
3008 HT_IRQ_LOW_BASE |
3009 HT_IRQ_LOW_DEST_ID(dest) |
3010 HT_IRQ_LOW_VECTOR(cfg->vector) |
3011 ((INT_DEST_MODE == 0) ?
3012 HT_IRQ_LOW_DM_PHYSICAL :
3013 HT_IRQ_LOW_DM_LOGICAL) |
3014 HT_IRQ_LOW_RQEOI_EDGE |
3015 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
3016 HT_IRQ_LOW_MT_FIXED :
3017 HT_IRQ_LOW_MT_ARBITRATED) |
3018 HT_IRQ_LOW_IRQ_MASKED;
3019
3020 write_ht_irq_msg(irq, &msg);
3021
3022 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3023 handle_edge_irq, "edge");
3024 }
3025 return err;
3026 }
3027 #endif /* CONFIG_HT_IRQ */
3028
3029 /* --------------------------------------------------------------------------
3030 ACPI-based IOAPIC Configuration
3031 -------------------------------------------------------------------------- */
3032
3033 #ifdef CONFIG_ACPI
3034
3035 #define IO_APIC_MAX_ID 0xFE
3036
3037 int __init io_apic_get_redir_entries (int ioapic)
3038 {
3039 union IO_APIC_reg_01 reg_01;
3040 unsigned long flags;
3041
3042 spin_lock_irqsave(&ioapic_lock, flags);
3043 reg_01.raw = io_apic_read(ioapic, 1);
3044 spin_unlock_irqrestore(&ioapic_lock, flags);
3045
3046 return reg_01.bits.entries;
3047 }
3048
3049
3050 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3051 {
3052 if (!IO_APIC_IRQ(irq)) {
3053 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3054 ioapic);
3055 return -EINVAL;
3056 }
3057
3058 /*
3059 * IRQs < 16 are already in the irq_2_pin[] map
3060 */
3061 if (irq >= 16)
3062 add_pin_to_irq(irq, ioapic, pin);
3063
3064 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
3065
3066 return 0;
3067 }
3068
3069
3070 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3071 {
3072 int i;
3073
3074 if (skip_ioapic_setup)
3075 return -1;
3076
3077 for (i = 0; i < mp_irq_entries; i++)
3078 if (mp_irqs[i].mp_irqtype == mp_INT &&
3079 mp_irqs[i].mp_srcbusirq == bus_irq)
3080 break;
3081 if (i >= mp_irq_entries)
3082 return -1;
3083
3084 *trigger = irq_trigger(i);
3085 *polarity = irq_polarity(i);
3086 return 0;
3087 }
3088
3089 #endif /* CONFIG_ACPI */
3090
3091 /*
3092 * This function currently is only a helper for the i386 smp boot process where
3093 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3094 * so mask in all cases should simply be TARGET_CPUS
3095 */
3096 #ifdef CONFIG_SMP
3097 void __init setup_ioapic_dest(void)
3098 {
3099 int pin, ioapic, irq, irq_entry;
3100 struct irq_cfg *cfg;
3101
3102 if (skip_ioapic_setup == 1)
3103 return;
3104
3105 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
3106 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
3107 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3108 if (irq_entry == -1)
3109 continue;
3110 irq = pin_2_irq(irq_entry, ioapic, pin);
3111
3112 /* setup_IO_APIC_irqs could fail to get vector for some device
3113 * when you have too many devices, because at that time only boot
3114 * cpu is online.
3115 */
3116 cfg = irq_cfg(irq);
3117 if (!cfg->vector)
3118 setup_IO_APIC_irq(ioapic, pin, irq,
3119 irq_trigger(irq_entry),
3120 irq_polarity(irq_entry));
3121 #ifdef CONFIG_INTR_REMAP
3122 else if (intr_remapping_enabled)
3123 set_ir_ioapic_affinity_irq(irq, TARGET_CPUS);
3124 #endif
3125 else
3126 set_ioapic_affinity_irq(irq, TARGET_CPUS);
3127 }
3128
3129 }
3130 }
3131 #endif
3132
3133 #define IOAPIC_RESOURCE_NAME_SIZE 11
3134
3135 static struct resource *ioapic_resources;
3136
3137 static struct resource * __init ioapic_setup_resources(void)
3138 {
3139 unsigned long n;
3140 struct resource *res;
3141 char *mem;
3142 int i;
3143
3144 if (nr_ioapics <= 0)
3145 return NULL;
3146
3147 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3148 n *= nr_ioapics;
3149
3150 mem = alloc_bootmem(n);
3151 res = (void *)mem;
3152
3153 if (mem != NULL) {
3154 mem += sizeof(struct resource) * nr_ioapics;
3155
3156 for (i = 0; i < nr_ioapics; i++) {
3157 res[i].name = mem;
3158 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3159 sprintf(mem, "IOAPIC %u", i);
3160 mem += IOAPIC_RESOURCE_NAME_SIZE;
3161 }
3162 }
3163
3164 ioapic_resources = res;
3165
3166 return res;
3167 }
3168
3169 void __init ioapic_init_mappings(void)
3170 {
3171 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3172 struct resource *ioapic_res;
3173 int i;
3174
3175 ioapic_res = ioapic_setup_resources();
3176 for (i = 0; i < nr_ioapics; i++) {
3177 if (smp_found_config) {
3178 ioapic_phys = mp_ioapics[i].mp_apicaddr;
3179 } else {
3180 ioapic_phys = (unsigned long)
3181 alloc_bootmem_pages(PAGE_SIZE);
3182 ioapic_phys = __pa(ioapic_phys);
3183 }
3184 set_fixmap_nocache(idx, ioapic_phys);
3185 apic_printk(APIC_VERBOSE,
3186 "mapped IOAPIC to %016lx (%016lx)\n",
3187 __fix_to_virt(idx), ioapic_phys);
3188 idx++;
3189
3190 if (ioapic_res != NULL) {
3191 ioapic_res->start = ioapic_phys;
3192 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
3193 ioapic_res++;
3194 }
3195 }
3196 }
3197
3198 static int __init ioapic_insert_resources(void)
3199 {
3200 int i;
3201 struct resource *r = ioapic_resources;
3202
3203 if (!r) {
3204 printk(KERN_ERR
3205 "IO APIC resources could be not be allocated.\n");
3206 return -1;
3207 }
3208
3209 for (i = 0; i < nr_ioapics; i++) {
3210 insert_resource(&iomem_resource, r);
3211 r++;
3212 }
3213
3214 return 0;
3215 }
3216
3217 /* Insert the IO APIC resources after PCI initialization has occured to handle
3218 * IO APICS that are mapped in on a BAR in PCI space. */
3219 late_initcall(ioapic_insert_resources);
3220
Support for the Chinese Samsung S3C2440 based development boards