2 * mmc_spi.c - Access SD/MMC cards through SPI master controllers
4 * (C) Copyright 2005, Intec Automation,
5 * Mike Lavender (mike@steroidmicros)
6 * (C) Copyright 2006-2007, David Brownell
7 * (C) Copyright 2007, Axis Communications,
8 * Hans-Peter Nilsson (hp@axis.com)
9 * (C) Copyright 2007, ATRON electronic GmbH,
10 * Jan Nikitenko <jan.nikitenko@gmail.com>
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
27 #include <linux/hrtimer.h>
28 #include <linux/delay.h>
29 #include <linux/bio.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/crc7.h>
32 #include <linux/crc-itu-t.h>
33 #include <linux/scatterlist.h>
35 #include <linux/mmc/host.h>
36 #include <linux/mmc/mmc.h> /* for R1_SPI_* bit values */
38 #include <linux/spi/spi.h>
39 #include <linux/spi/mmc_spi.h>
41 #include <asm/unaligned.h>
46 * - For now, we won't try to interoperate with a real mmc/sd/sdio
47 * controller, although some of them do have hardware support for
48 * SPI protocol. The main reason for such configs would be mmc-ish
49 * cards like DataFlash, which don't support that "native" protocol.
51 * We don't have a "DataFlash/MMC/SD/SDIO card slot" abstraction to
52 * switch between driver stacks, and in any case if "native" mode
53 * is available, it will be faster and hence preferable.
55 * - MMC depends on a different chipselect management policy than the
56 * SPI interface currently supports for shared bus segments: it needs
57 * to issue multiple spi_message requests with the chipselect active,
58 * using the results of one message to decide the next one to issue.
60 * Pending updates to the programming interface, this driver expects
61 * that it not share the bus with other drivers (precluding conflicts).
63 * - We tell the controller to keep the chipselect active from the
64 * beginning of an mmc_host_ops.request until the end. So beware
65 * of SPI controller drivers that mis-handle the cs_change flag!
67 * However, many cards seem OK with chipselect flapping up/down
68 * during that time ... at least on unshared bus segments.
73 * Local protocol constants, internal to data block protocols.
76 /* Response tokens used to ack each block written: */
77 #define SPI_MMC_RESPONSE_CODE(x) ((x) & 0x1f)
78 #define SPI_RESPONSE_ACCEPTED ((2 << 1)|1)
79 #define SPI_RESPONSE_CRC_ERR ((5 << 1)|1)
80 #define SPI_RESPONSE_WRITE_ERR ((6 << 1)|1)
82 /* Read and write blocks start with these tokens and end with crc;
83 * on error, read tokens act like a subset of R2_SPI_* values.
85 #define SPI_TOKEN_SINGLE 0xfe /* single block r/w, multiblock read */
86 #define SPI_TOKEN_MULTI_WRITE 0xfc /* multiblock write */
87 #define SPI_TOKEN_STOP_TRAN 0xfd /* terminate multiblock write */
89 #define MMC_SPI_BLOCKSIZE 512
92 /* These fixed timeouts come from the latest SD specs, which say to ignore
93 * the CSD values. The R1B value is for card erase (e.g. the "I forgot the
94 * card's password" scenario); it's mostly applied to STOP_TRANSMISSION after
95 * reads which takes nowhere near that long. Older cards may be able to use
96 * shorter timeouts ... but why bother?
98 #define readblock_timeout ktime_set(0, 100 * 1000 * 1000)
99 #define writeblock_timeout ktime_set(0, 250 * 1000 * 1000)
100 #define r1b_timeout ktime_set(3, 0)
103 /****************************************************************************/
106 * Local Data Structures
109 /* "scratch" is per-{command,block} data exchanged with the card */
116 struct mmc_spi_host
{
117 struct mmc_host
*mmc
;
118 struct spi_device
*spi
;
120 unsigned char power_mode
;
123 struct mmc_spi_platform_data
*pdata
;
125 /* for bulk data transfers */
126 struct spi_transfer token
, t
, crc
, early_status
;
127 struct spi_message m
;
129 /* for status readback */
130 struct spi_transfer status
;
131 struct spi_message readback
;
133 /* underlying DMA-aware controller, or null */
134 struct device
*dma_dev
;
136 /* buffer used for commands and for message "overhead" */
137 struct scratch
*data
;
140 /* Specs say to write ones most of the time, even when the card
141 * has no need to read its input data; and many cards won't care.
142 * This is our source of those ones.
149 /****************************************************************************/
152 * MMC-over-SPI protocol glue, used by the MMC stack interface
155 static inline int mmc_cs_off(struct mmc_spi_host
*host
)
157 /* chipselect will always be inactive after setup() */
158 return spi_setup(host
->spi
);
162 mmc_spi_readbytes(struct mmc_spi_host
*host
, unsigned len
)
166 if (len
> sizeof(*host
->data
)) {
171 host
->status
.len
= len
;
174 dma_sync_single_for_device(host
->dma_dev
,
175 host
->data_dma
, sizeof(*host
->data
),
178 status
= spi_sync(host
->spi
, &host
->readback
);
180 status
= host
->readback
.status
;
183 dma_sync_single_for_cpu(host
->dma_dev
,
184 host
->data_dma
, sizeof(*host
->data
),
191 mmc_spi_skip(struct mmc_spi_host
*host
, ktime_t timeout
, unsigned n
, u8 byte
)
193 u8
*cp
= host
->data
->status
;
195 timeout
= ktime_add(timeout
, ktime_get());
201 status
= mmc_spi_readbytes(host
, n
);
205 for (i
= 0; i
< n
; i
++) {
210 /* REVISIT investigate msleep() to avoid busy-wait I/O
211 * in at least some cases.
213 if (ktime_to_ns(ktime_sub(ktime_get(), timeout
)) > 0)
220 mmc_spi_wait_unbusy(struct mmc_spi_host
*host
, ktime_t timeout
)
222 return mmc_spi_skip(host
, timeout
, sizeof(host
->data
->status
), 0);
225 static int mmc_spi_readtoken(struct mmc_spi_host
*host
)
227 return mmc_spi_skip(host
, readblock_timeout
, 1, 0xff);
232 * Note that for SPI, cmd->resp[0] is not the same data as "native" protocol
233 * hosts return! The low byte holds R1_SPI bits. The next byte may hold
234 * R2_SPI bits ... for SEND_STATUS, or after data read errors.
236 * cmd->resp[1] holds any four-byte response, for R3 (READ_OCR) and on
237 * newer cards R7 (IF_COND).
240 static char *maptype(struct mmc_command
*cmd
)
242 switch (mmc_spi_resp_type(cmd
)) {
243 case MMC_RSP_SPI_R1
: return "R1";
244 case MMC_RSP_SPI_R1B
: return "R1B";
245 case MMC_RSP_SPI_R2
: return "R2/R5";
246 case MMC_RSP_SPI_R3
: return "R3/R4/R7";
251 /* return zero, else negative errno after setting cmd->error */
252 static int mmc_spi_response_get(struct mmc_spi_host
*host
,
253 struct mmc_command
*cmd
, int cs_on
)
255 u8
*cp
= host
->data
->status
;
256 u8
*end
= cp
+ host
->t
.len
;
260 snprintf(tag
, sizeof(tag
), " ... CMD%d response SPI_%s",
261 cmd
->opcode
, maptype(cmd
));
263 /* Except for data block reads, the whole response will already
264 * be stored in the scratch buffer. It's somewhere after the
265 * command and the first byte we read after it. We ignore that
266 * first byte. After STOP_TRANSMISSION command it may include
267 * two data bits, but otherwise it's all ones.
270 while (cp
< end
&& *cp
== 0xff)
273 /* Data block reads (R1 response types) may need more data... */
277 cp
= host
->data
->status
;
279 /* Card sends N(CR) (== 1..8) bytes of all-ones then one
280 * status byte ... and we already scanned 2 bytes.
282 * REVISIT block read paths use nasty byte-at-a-time I/O
283 * so it can always DMA directly into the target buffer.
284 * It'd probably be better to memcpy() the first chunk and
285 * avoid extra i/o calls...
287 for (i
= 2; i
< 9; i
++) {
288 value
= mmc_spi_readbytes(host
, 1);
300 dev_dbg(&host
->spi
->dev
, "%s: INVALID RESPONSE, %02x\n",
306 cmd
->resp
[0] = *cp
++;
309 /* Status byte: the entire seven-bit R1 response. */
310 if (cmd
->resp
[0] != 0) {
311 if ((R1_SPI_PARAMETER
| R1_SPI_ADDRESS
312 | R1_SPI_ILLEGAL_COMMAND
)
315 else if (R1_SPI_COM_CRC
& cmd
->resp
[0])
317 else if ((R1_SPI_ERASE_SEQ
| R1_SPI_ERASE_RESET
)
320 /* else R1_SPI_IDLE, "it's resetting" */
323 switch (mmc_spi_resp_type(cmd
)) {
325 /* SPI R1B == R1 + busy; STOP_TRANSMISSION (for multiblock reads)
326 * and less-common stuff like various erase operations.
328 case MMC_RSP_SPI_R1B
:
329 /* maybe we read all the busy tokens already */
330 while (cp
< end
&& *cp
== 0)
333 mmc_spi_wait_unbusy(host
, r1b_timeout
);
336 /* SPI R2 == R1 + second status byte; SEND_STATUS
337 * SPI R5 == R1 + data byte; IO_RW_DIRECT
340 cmd
->resp
[0] |= *cp
<< 8;
343 /* SPI R3, R4, or R7 == R1 + 4 bytes */
345 cmd
->resp
[1] = be32_to_cpu(get_unaligned((u32
*)cp
));
348 /* SPI R1 == just one status byte */
353 dev_dbg(&host
->spi
->dev
, "bad response type %04x\n",
354 mmc_spi_resp_type(cmd
));
361 dev_dbg(&host
->spi
->dev
, "%s: resp %04x %08x\n",
362 tag
, cmd
->resp
[0], cmd
->resp
[1]);
364 /* disable chipselect on errors and some success cases */
365 if (value
>= 0 && cs_on
)
374 /* Issue command and read its response.
375 * Returns zero on success, negative for error.
377 * On error, caller must cope with mmc core retry mechanism. That
378 * means immediate low-level resubmit, which affects the bus lock...
381 mmc_spi_command_send(struct mmc_spi_host
*host
,
382 struct mmc_request
*mrq
,
383 struct mmc_command
*cmd
, int cs_on
)
385 struct scratch
*data
= host
->data
;
386 u8
*cp
= data
->status
;
389 struct spi_transfer
*t
;
391 /* We can handle most commands (except block reads) in one full
392 * duplex I/O operation before either starting the next transfer
393 * (data block or command) or else deselecting the card.
395 * First, write 7 bytes:
396 * - an all-ones byte to ensure the card is ready
397 * - opcode byte (plus start and transmission bits)
398 * - four bytes of big-endian argument
399 * - crc7 (plus end bit) ... always computed, it's cheap
401 * We init the whole buffer to all-ones, which is what we need
402 * to write while we're reading (later) response data.
404 memset(cp
++, 0xff, sizeof(data
->status
));
406 *cp
++ = 0x40 | cmd
->opcode
;
407 *cp
++ = (u8
)(arg
>> 24);
408 *cp
++ = (u8
)(arg
>> 16);
409 *cp
++ = (u8
)(arg
>> 8);
411 *cp
++ = (crc7(0, &data
->status
[1], 5) << 1) | 0x01;
413 /* Then, read up to 13 bytes (while writing all-ones):
414 * - N(CR) (== 1..8) bytes of all-ones
415 * - status byte (for all response types)
416 * - the rest of the response, either:
417 * + nothing, for R1 or R1B responses
418 * + second status byte, for R2 responses
419 * + four data bytes, for R3 and R7 responses
421 * Finally, read some more bytes ... in the nice cases we know in
422 * advance how many, and reading 1 more is always OK:
423 * - N(EC) (== 0..N) bytes of all-ones, before deselect/finish
424 * - N(RC) (== 1..N) bytes of all-ones, before next command
425 * - N(WR) (== 1..N) bytes of all-ones, before data write
427 * So in those cases one full duplex I/O of at most 21 bytes will
428 * handle the whole command, leaving the card ready to receive a
429 * data block or new command. We do that whenever we can, shaving
430 * CPU and IRQ costs (especially when using DMA or FIFOs).
432 * There are two other cases, where it's not generally practical
433 * to rely on a single I/O:
435 * - R1B responses need at least N(EC) bytes of all-zeroes.
437 * In this case we can *try* to fit it into one I/O, then
438 * maybe read more data later.
440 * - Data block reads are more troublesome, since a variable
441 * number of padding bytes precede the token and data.
442 * + N(CX) (== 0..8) bytes of all-ones, before CSD or CID
443 * + N(AC) (== 1..many) bytes of all-ones
445 * In this case we currently only have minimal speedups here:
446 * when N(CR) == 1 we can avoid I/O in response_get().
448 if (cs_on
&& (mrq
->data
->flags
& MMC_DATA_READ
)) {
449 cp
+= 2; /* min(N(CR)) + status */
452 cp
+= 10; /* max(N(CR)) + status + min(N(RC),N(WR)) */
453 if (cmd
->flags
& MMC_RSP_SPI_S2
) /* R2/R5 */
455 else if (cmd
->flags
& MMC_RSP_SPI_B4
) /* R3/R4/R7 */
457 else if (cmd
->flags
& MMC_RSP_BUSY
) /* R1B */
458 cp
= data
->status
+ sizeof(data
->status
);
459 /* else: R1 (most commands) */
462 dev_dbg(&host
->spi
->dev
, " mmc_spi: CMD%d, resp %s\n",
463 cmd
->opcode
, maptype(cmd
));
465 /* send command, leaving chipselect active */
466 spi_message_init(&host
->m
);
469 memset(t
, 0, sizeof(*t
));
470 t
->tx_buf
= t
->rx_buf
= data
->status
;
471 t
->tx_dma
= t
->rx_dma
= host
->data_dma
;
472 t
->len
= cp
- data
->status
;
474 spi_message_add_tail(t
, &host
->m
);
477 host
->m
.is_dma_mapped
= 1;
478 dma_sync_single_for_device(host
->dma_dev
,
479 host
->data_dma
, sizeof(*host
->data
),
482 status
= spi_sync(host
->spi
, &host
->m
);
484 status
= host
->m
.status
;
487 dma_sync_single_for_cpu(host
->dma_dev
,
488 host
->data_dma
, sizeof(*host
->data
),
491 dev_dbg(&host
->spi
->dev
, " ... write returned %d\n", status
);
496 /* after no-data commands and STOP_TRANSMISSION, chipselect off */
497 return mmc_spi_response_get(host
, cmd
, cs_on
);
500 /* Build data message with up to four separate transfers. For TX, we
501 * start by writing the data token. And in most cases, we finish with
504 * We always provide TX data for data and CRC. The MMC/SD protocol
505 * requires us to write ones; but Linux defaults to writing zeroes;
506 * so we explicitly initialize it to all ones on RX paths.
508 * We also handle DMA mapping, so the underlying SPI controller does
509 * not need to (re)do it for each message.
512 mmc_spi_setup_data_message(
513 struct mmc_spi_host
*host
,
515 enum dma_data_direction direction
)
517 struct spi_transfer
*t
;
518 struct scratch
*scratch
= host
->data
;
519 dma_addr_t dma
= host
->data_dma
;
521 spi_message_init(&host
->m
);
523 host
->m
.is_dma_mapped
= 1;
525 /* for reads, readblock() skips 0xff bytes before finding
526 * the token; for writes, this transfer issues that token.
528 if (direction
== DMA_TO_DEVICE
) {
530 memset(t
, 0, sizeof(*t
));
533 scratch
->data_token
= SPI_TOKEN_MULTI_WRITE
;
535 scratch
->data_token
= SPI_TOKEN_SINGLE
;
536 t
->tx_buf
= &scratch
->data_token
;
538 t
->tx_dma
= dma
+ offsetof(struct scratch
, data_token
);
539 spi_message_add_tail(t
, &host
->m
);
542 /* Body of transfer is buffer, then CRC ...
543 * either TX-only, or RX with TX-ones.
546 memset(t
, 0, sizeof(*t
));
547 t
->tx_buf
= host
->ones
;
548 t
->tx_dma
= host
->ones_dma
;
549 /* length and actual buffer info are written later */
550 spi_message_add_tail(t
, &host
->m
);
553 memset(t
, 0, sizeof(*t
));
555 if (direction
== DMA_TO_DEVICE
) {
556 /* the actual CRC may get written later */
557 t
->tx_buf
= &scratch
->crc_val
;
559 t
->tx_dma
= dma
+ offsetof(struct scratch
, crc_val
);
561 t
->tx_buf
= host
->ones
;
562 t
->tx_dma
= host
->ones_dma
;
563 t
->rx_buf
= &scratch
->crc_val
;
565 t
->rx_dma
= dma
+ offsetof(struct scratch
, crc_val
);
567 spi_message_add_tail(t
, &host
->m
);
570 * A single block read is followed by N(EC) [0+] all-ones bytes
571 * before deselect ... don't bother.
573 * Multiblock reads are followed by N(AC) [1+] all-ones bytes before
574 * the next block is read, or a STOP_TRANSMISSION is issued. We'll
575 * collect that single byte, so readblock() doesn't need to.
577 * For a write, the one-byte data response follows immediately, then
578 * come zero or more busy bytes, then N(WR) [1+] all-ones bytes.
579 * Then single block reads may deselect, and multiblock ones issue
580 * the next token (next data block, or STOP_TRAN). We can try to
581 * minimize I/O ops by using a single read to collect end-of-busy.
583 if (multiple
|| direction
== DMA_TO_DEVICE
) {
584 t
= &host
->early_status
;
585 memset(t
, 0, sizeof(*t
));
586 t
->len
= (direction
== DMA_TO_DEVICE
)
587 ? sizeof(scratch
->status
)
589 t
->tx_buf
= host
->ones
;
590 t
->tx_dma
= host
->ones_dma
;
591 t
->rx_buf
= scratch
->status
;
593 t
->rx_dma
= dma
+ offsetof(struct scratch
, status
);
595 spi_message_add_tail(t
, &host
->m
);
601 * - caller handled preceding N(WR) [1+] all-ones bytes
606 * - an all-ones byte ... card writes a data-response byte
607 * - followed by N(EC) [0+] all-ones bytes, card writes zero/'busy'
609 * Return negative errno, else success.
612 mmc_spi_writeblock(struct mmc_spi_host
*host
, struct spi_transfer
*t
)
614 struct spi_device
*spi
= host
->spi
;
616 struct scratch
*scratch
= host
->data
;
618 if (host
->mmc
->use_spi_crc
)
619 scratch
->crc_val
= cpu_to_be16(
620 crc_itu_t(0, t
->tx_buf
, t
->len
));
622 dma_sync_single_for_device(host
->dma_dev
,
623 host
->data_dma
, sizeof(*scratch
),
626 status
= spi_sync(spi
, &host
->m
);
628 status
= host
->m
.status
;
631 dev_dbg(&spi
->dev
, "write error (%d)\n", status
);
636 dma_sync_single_for_cpu(host
->dma_dev
,
637 host
->data_dma
, sizeof(*scratch
),
641 * Get the transmission data-response reply. It must follow
642 * immediately after the data block we transferred. This reply
643 * doesn't necessarily tell whether the write operation succeeded;
644 * it just says if the transmission was ok and whether *earlier*
645 * writes succeeded; see the standard.
647 switch (SPI_MMC_RESPONSE_CODE(scratch
->status
[0])) {
648 case SPI_RESPONSE_ACCEPTED
:
651 case SPI_RESPONSE_CRC_ERR
:
652 /* host shall then issue MMC_STOP_TRANSMISSION */
655 case SPI_RESPONSE_WRITE_ERR
:
656 /* host shall then issue MMC_STOP_TRANSMISSION,
657 * and should MMC_SEND_STATUS to sort it out
666 dev_dbg(&spi
->dev
, "write error %02x (%d)\n",
667 scratch
->status
[0], status
);
675 /* Return when not busy. If we didn't collect that status yet,
676 * we'll need some more I/O.
678 for (i
= 1; i
< sizeof(scratch
->status
); i
++) {
679 if (scratch
->status
[i
] != 0)
682 return mmc_spi_wait_unbusy(host
, writeblock_timeout
);
687 * - skip leading all-ones bytes ... either
688 * + N(AC) [1..f(clock,CSD)] usually, else
689 * + N(CX) [0..8] when reading CSD or CID
691 * + token ... if error token, no data or crc
695 * After single block reads, we're done; N(EC) [0+] all-ones bytes follow
696 * before dropping chipselect.
698 * For multiblock reads, caller either reads the next block or issues a
699 * STOP_TRANSMISSION command.
702 mmc_spi_readblock(struct mmc_spi_host
*host
, struct spi_transfer
*t
)
704 struct spi_device
*spi
= host
->spi
;
706 struct scratch
*scratch
= host
->data
;
708 /* At least one SD card sends an all-zeroes byte when N(CX)
709 * applies, before the all-ones bytes ... just cope with that.
711 status
= mmc_spi_readbytes(host
, 1);
714 status
= scratch
->status
[0];
715 if (status
== 0xff || status
== 0)
716 status
= mmc_spi_readtoken(host
);
718 if (status
== SPI_TOKEN_SINGLE
) {
720 dma_sync_single_for_device(host
->dma_dev
,
721 host
->data_dma
, sizeof(*scratch
),
723 dma_sync_single_for_device(host
->dma_dev
,
728 status
= spi_sync(spi
, &host
->m
);
730 status
= host
->m
.status
;
733 dma_sync_single_for_cpu(host
->dma_dev
,
734 host
->data_dma
, sizeof(*scratch
),
736 dma_sync_single_for_cpu(host
->dma_dev
,
742 dev_dbg(&spi
->dev
, "read error %02x (%d)\n", status
, status
);
744 /* we've read extra garbage, timed out, etc */
748 /* low four bits are an R2 subset, fifth seems to be
749 * vendor specific ... map them all to generic error..
754 if (host
->mmc
->use_spi_crc
) {
755 u16 crc
= crc_itu_t(0, t
->rx_buf
, t
->len
);
757 be16_to_cpus(&scratch
->crc_val
);
758 if (scratch
->crc_val
!= crc
) {
759 dev_dbg(&spi
->dev
, "read - crc error: crc_val=0x%04x, "
760 "computed=0x%04x len=%d\n",
761 scratch
->crc_val
, crc
, t
->len
);
774 * An MMC/SD data stage includes one or more blocks, optional CRCs,
775 * and inline handshaking. That handhaking makes it unlike most
776 * other SPI protocol stacks.
779 mmc_spi_data_do(struct mmc_spi_host
*host
, struct mmc_command
*cmd
,
780 struct mmc_data
*data
, u32 blk_size
)
782 struct spi_device
*spi
= host
->spi
;
783 struct device
*dma_dev
= host
->dma_dev
;
784 struct spi_transfer
*t
;
785 enum dma_data_direction direction
;
786 struct scatterlist
*sg
;
788 int multiple
= (data
->blocks
> 1);
790 if (data
->flags
& MMC_DATA_READ
)
791 direction
= DMA_FROM_DEVICE
;
793 direction
= DMA_TO_DEVICE
;
794 mmc_spi_setup_data_message(host
, multiple
, direction
);
797 /* Handle scatterlist segments one at a time, with synch for
798 * each 512-byte block
800 for (sg
= data
->sg
, n_sg
= data
->sg_len
; n_sg
; n_sg
--, sg
++) {
802 dma_addr_t dma_addr
= 0;
804 unsigned length
= sg
->length
;
805 enum dma_data_direction dir
= direction
;
807 /* set up dma mapping for controller drivers that might
808 * use DMA ... though they may fall back to PIO
811 /* never invalidate whole *shared* pages ... */
812 if ((sg
->offset
!= 0 || length
!= PAGE_SIZE
)
813 && dir
== DMA_FROM_DEVICE
)
814 dir
= DMA_BIDIRECTIONAL
;
816 dma_addr
= dma_map_page(dma_dev
, sg
->page
, 0,
818 if (direction
== DMA_TO_DEVICE
)
819 t
->tx_dma
= dma_addr
+ sg
->offset
;
821 t
->rx_dma
= dma_addr
+ sg
->offset
;
824 /* allow pio too; we don't allow highmem */
825 kmap_addr
= kmap(sg
->page
);
826 if (direction
== DMA_TO_DEVICE
)
827 t
->tx_buf
= kmap_addr
+ sg
->offset
;
829 t
->rx_buf
= kmap_addr
+ sg
->offset
;
831 /* transfer each block, and update request status */
833 t
->len
= min(length
, blk_size
);
835 dev_dbg(&host
->spi
->dev
,
836 " mmc_spi: %s block, %d bytes\n",
837 (direction
== DMA_TO_DEVICE
)
842 if (direction
== DMA_TO_DEVICE
)
843 status
= mmc_spi_writeblock(host
, t
);
845 status
= mmc_spi_readblock(host
, t
);
849 data
->bytes_xfered
+= t
->len
;
856 /* discard mappings */
857 if (direction
== DMA_FROM_DEVICE
)
858 flush_kernel_dcache_page(sg
->page
);
861 dma_unmap_page(dma_dev
, dma_addr
, PAGE_SIZE
, dir
);
864 data
->error
= status
;
865 dev_dbg(&spi
->dev
, "%s status %d\n",
866 (direction
== DMA_TO_DEVICE
)
873 /* NOTE some docs describe an MMC-only SET_BLOCK_COUNT (CMD23) that
874 * can be issued before multiblock writes. Unlike its more widely
875 * documented analogue for SD cards (SET_WR_BLK_ERASE_COUNT, ACMD23),
876 * that can affect the STOP_TRAN logic. Complete (and current)
877 * MMC specs should sort that out before Linux starts using CMD23.
879 if (direction
== DMA_TO_DEVICE
&& multiple
) {
880 struct scratch
*scratch
= host
->data
;
882 const unsigned statlen
= sizeof(scratch
->status
);
884 dev_dbg(&spi
->dev
, " mmc_spi: STOP_TRAN\n");
886 /* Tweak the per-block message we set up earlier by morphing
887 * it to hold single buffer with the token followed by some
888 * all-ones bytes ... skip N(BR) (0..1), scan the rest for
889 * "not busy any longer" status, and leave chip selected.
891 INIT_LIST_HEAD(&host
->m
.transfers
);
892 list_add(&host
->early_status
.transfer_list
,
895 memset(scratch
->status
, 0xff, statlen
);
896 scratch
->status
[0] = SPI_TOKEN_STOP_TRAN
;
898 host
->early_status
.tx_buf
= host
->early_status
.rx_buf
;
899 host
->early_status
.tx_dma
= host
->early_status
.rx_dma
;
900 host
->early_status
.len
= statlen
;
903 dma_sync_single_for_device(host
->dma_dev
,
904 host
->data_dma
, sizeof(*scratch
),
907 tmp
= spi_sync(spi
, &host
->m
);
909 tmp
= host
->m
.status
;
912 dma_sync_single_for_cpu(host
->dma_dev
,
913 host
->data_dma
, sizeof(*scratch
),
922 /* Ideally we collected "not busy" status with one I/O,
923 * avoiding wasteful byte-at-a-time scanning... but more
924 * I/O is often needed.
926 for (tmp
= 2; tmp
< statlen
; tmp
++) {
927 if (scratch
->status
[tmp
] != 0)
930 tmp
= mmc_spi_wait_unbusy(host
, writeblock_timeout
);
931 if (tmp
< 0 && !data
->error
)
936 /****************************************************************************/
939 * MMC driver implementation -- the interface to the MMC stack
942 static void mmc_spi_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
944 struct mmc_spi_host
*host
= mmc_priv(mmc
);
945 int status
= -EINVAL
;
948 /* MMC core and layered drivers *MUST* issue SPI-aware commands */
950 struct mmc_command
*cmd
;
954 if (!mmc_spi_resp_type(cmd
)) {
955 dev_dbg(&host
->spi
->dev
, "bogus command\n");
956 cmd
->error
= -EINVAL
;
961 if (cmd
&& !mmc_spi_resp_type(cmd
)) {
962 dev_dbg(&host
->spi
->dev
, "bogus STOP command\n");
963 cmd
->error
= -EINVAL
;
969 mmc_request_done(host
->mmc
, mrq
);
975 /* issue command; then optionally data and stop */
976 status
= mmc_spi_command_send(host
, mrq
, mrq
->cmd
, mrq
->data
!= NULL
);
977 if (status
== 0 && mrq
->data
) {
978 mmc_spi_data_do(host
, mrq
->cmd
, mrq
->data
, mrq
->data
->blksz
);
980 status
= mmc_spi_command_send(host
, mrq
, mrq
->stop
, 0);
985 mmc_request_done(host
->mmc
, mrq
);
988 /* See Section 6.4.1, in SD "Simplified Physical Layer Specification 2.0"
990 * NOTE that here we can't know that the card has just been powered up;
991 * not all MMC/SD sockets support power switching.
993 * FIXME when the card is still in SPI mode, e.g. from a previous kernel,
994 * this doesn't seem to do the right thing at all...
996 static void mmc_spi_initsequence(struct mmc_spi_host
*host
)
998 /* Try to be very sure any previous command has completed;
999 * wait till not-busy, skip debris from any old commands.
1001 mmc_spi_wait_unbusy(host
, r1b_timeout
);
1002 mmc_spi_readbytes(host
, 10);
1005 * Do a burst with chipselect active-high. We need to do this to
1006 * meet the requirement of 74 clock cycles with both chipselect
1007 * and CMD (MOSI) high before CMD0 ... after the card has been
1008 * powered up to Vdd(min), and so is ready to take commands.
1010 * Some cards are particularly needy of this (e.g. Viking "SD256")
1011 * while most others don't seem to care.
1013 * Note that this is one of the places MMC/SD plays games with the
1014 * SPI protocol. Another is that when chipselect is released while
1015 * the card returns BUSY status, the clock must issue several cycles
1016 * with chipselect high before the card will stop driving its output.
1018 host
->spi
->mode
|= SPI_CS_HIGH
;
1019 if (spi_setup(host
->spi
) != 0) {
1020 /* Just warn; most cards work without it. */
1021 dev_warn(&host
->spi
->dev
,
1022 "can't change chip-select polarity\n");
1023 host
->spi
->mode
&= ~SPI_CS_HIGH
;
1025 mmc_spi_readbytes(host
, 18);
1027 host
->spi
->mode
&= ~SPI_CS_HIGH
;
1028 if (spi_setup(host
->spi
) != 0) {
1029 /* Wot, we can't get the same setup we had before? */
1030 dev_err(&host
->spi
->dev
,
1031 "can't restore chip-select polarity\n");
1036 static char *mmc_powerstring(u8 power_mode
)
1038 switch (power_mode
) {
1039 case MMC_POWER_OFF
: return "off";
1040 case MMC_POWER_UP
: return "up";
1041 case MMC_POWER_ON
: return "on";
1046 static void mmc_spi_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1048 struct mmc_spi_host
*host
= mmc_priv(mmc
);
1050 if (host
->power_mode
!= ios
->power_mode
) {
1053 canpower
= host
->pdata
&& host
->pdata
->setpower
;
1055 dev_dbg(&host
->spi
->dev
, "mmc_spi: power %s (%d)%s\n",
1056 mmc_powerstring(ios
->power_mode
),
1058 canpower
? ", can switch" : "");
1060 /* switch power on/off if possible, accounting for
1061 * max 250msec powerup time if needed.
1064 switch (ios
->power_mode
) {
1067 host
->pdata
->setpower(&host
->spi
->dev
,
1069 if (ios
->power_mode
== MMC_POWER_UP
)
1070 msleep(host
->powerup_msecs
);
1074 /* See 6.4.1 in the simplified SD card physical spec 2.0 */
1075 if (ios
->power_mode
== MMC_POWER_ON
)
1076 mmc_spi_initsequence(host
);
1078 /* If powering down, ground all card inputs to avoid power
1079 * delivery from data lines! On a shared SPI bus, this
1080 * will probably be temporary; 6.4.2 of the simplified SD
1081 * spec says this must last at least 1msec.
1083 * - Clock low means CPOL 0, e.g. mode 0
1084 * - MOSI low comes from writing zero
1085 * - Chipselect is usually active low...
1087 if (canpower
&& ios
->power_mode
== MMC_POWER_OFF
) {
1090 host
->spi
->mode
&= ~(SPI_CPOL
|SPI_CPHA
);
1091 mres
= spi_setup(host
->spi
);
1093 dev_dbg(&host
->spi
->dev
,
1094 "switch to SPI mode 0 failed\n");
1096 if (spi_w8r8(host
->spi
, 0x00) < 0)
1097 dev_dbg(&host
->spi
->dev
,
1098 "put spi signals to low failed\n");
1101 * Now clock should be low due to spi mode 0;
1102 * MOSI should be low because of written 0x00;
1103 * chipselect should be low (it is active low)
1104 * power supply is off, so now MMC is off too!
1106 * FIXME no, chipselect can be high since the
1107 * device is inactive and SPI_CS_HIGH is clear...
1111 host
->spi
->mode
|= (SPI_CPOL
|SPI_CPHA
);
1112 mres
= spi_setup(host
->spi
);
1114 dev_dbg(&host
->spi
->dev
,
1115 "switch back to SPI mode 3"
1120 host
->power_mode
= ios
->power_mode
;
1123 if (host
->spi
->max_speed_hz
!= ios
->clock
&& ios
->clock
!= 0) {
1126 host
->spi
->max_speed_hz
= ios
->clock
;
1127 status
= spi_setup(host
->spi
);
1128 dev_dbg(&host
->spi
->dev
,
1129 "mmc_spi: clock to %d Hz, %d\n",
1130 host
->spi
->max_speed_hz
, status
);
1134 static int mmc_spi_get_ro(struct mmc_host
*mmc
)
1136 struct mmc_spi_host
*host
= mmc_priv(mmc
);
1138 if (host
->pdata
&& host
->pdata
->get_ro
)
1139 return host
->pdata
->get_ro(mmc
->parent
);
1140 /* board doesn't support read only detection; assume writeable */
1145 static const struct mmc_host_ops mmc_spi_ops
= {
1146 .request
= mmc_spi_request
,
1147 .set_ios
= mmc_spi_set_ios
,
1148 .get_ro
= mmc_spi_get_ro
,
1152 /****************************************************************************/
1155 * SPI driver implementation
1159 mmc_spi_detect_irq(int irq
, void *mmc
)
1161 struct mmc_spi_host
*host
= mmc_priv(mmc
);
1162 u16 delay_msec
= max(host
->pdata
->detect_delay
, (u16
)100);
1164 mmc_detect_change(mmc
, msecs_to_jiffies(delay_msec
));
1168 static int mmc_spi_probe(struct spi_device
*spi
)
1171 struct mmc_host
*mmc
;
1172 struct mmc_spi_host
*host
;
1175 /* MMC and SD specs only seem to care that sampling is on the
1176 * rising edge ... meaning SPI modes 0 or 3. So either SPI mode
1177 * should be legit. We'll use mode 0 since it seems to be a
1178 * bit less troublesome on some hardware ... unclear why.
1180 spi
->mode
= SPI_MODE_0
;
1181 spi
->bits_per_word
= 8;
1183 status
= spi_setup(spi
);
1185 dev_dbg(&spi
->dev
, "needs SPI mode %02x, %d KHz; %d\n",
1186 spi
->mode
, spi
->max_speed_hz
/ 1000,
1191 /* We can use the bus safely iff nobody else will interfere with
1192 * us. That is, either we have the experimental exclusive access
1193 * primitives ... or else there's nobody to share it with.
1195 if (spi
->master
->num_chipselect
> 1) {
1196 struct device
*parent
= spi
->dev
.parent
;
1198 /* If there are multiple devices on this bus, we
1201 spin_lock(&parent
->klist_children
.k_lock
);
1202 if (parent
->klist_children
.k_list
.next
1203 != parent
->klist_children
.k_list
.prev
)
1207 spin_unlock(&parent
->klist_children
.k_lock
);
1209 dev_err(&spi
->dev
, "can't share SPI bus\n");
1213 /* REVISIT we can't guarantee another device won't
1214 * be added later. It's uncommon though ... for now,
1215 * work as if this is safe.
1217 dev_warn(&spi
->dev
, "ASSUMING unshared SPI bus!\n");
1220 /* We need a supply of ones to transmit. This is the only time
1221 * the CPU touches these, so cache coherency isn't a concern.
1223 * NOTE if many systems use more than one MMC-over-SPI connector
1224 * it'd save some memory to share this. That's evidently rare.
1227 ones
= kmalloc(MMC_SPI_BLOCKSIZE
, GFP_KERNEL
);
1230 memset(ones
, 0xff, MMC_SPI_BLOCKSIZE
);
1232 mmc
= mmc_alloc_host(sizeof(*host
), &spi
->dev
);
1236 mmc
->ops
= &mmc_spi_ops
;
1237 mmc
->max_blk_size
= MMC_SPI_BLOCKSIZE
;
1239 /* As long as we keep track of the number of successfully
1240 * transmitted blocks, we're good for multiwrite.
1242 mmc
->caps
= MMC_CAP_SPI
| MMC_CAP_MULTIWRITE
;
1244 /* SPI doesn't need the lowspeed device identification thing for
1245 * MMC or SD cards, since it never comes up in open drain mode.
1246 * That's good; some SPI masters can't handle very low speeds!
1248 * However, low speed SDIO cards need not handle over 400 KHz;
1249 * that's the only reason not to use a few MHz for f_min (until
1250 * the upper layer reads the target frequency from the CSD).
1252 mmc
->f_min
= 400000;
1253 mmc
->f_max
= spi
->max_speed_hz
;
1255 host
= mmc_priv(mmc
);
1261 /* Platform data is used to hook up things like card sensing
1262 * and power switching gpios.
1264 host
->pdata
= spi
->dev
.platform_data
;
1266 mmc
->ocr_avail
= host
->pdata
->ocr_mask
;
1267 if (!mmc
->ocr_avail
) {
1268 dev_warn(&spi
->dev
, "ASSUMING 3.2-3.4 V slot power\n");
1269 mmc
->ocr_avail
= MMC_VDD_32_33
|MMC_VDD_33_34
;
1271 if (host
->pdata
&& host
->pdata
->setpower
) {
1272 host
->powerup_msecs
= host
->pdata
->powerup_msecs
;
1273 if (!host
->powerup_msecs
|| host
->powerup_msecs
> 250)
1274 host
->powerup_msecs
= 250;
1277 dev_set_drvdata(&spi
->dev
, mmc
);
1279 /* preallocate dma buffers */
1280 host
->data
= kmalloc(sizeof(*host
->data
), GFP_KERNEL
);
1284 if (spi
->master
->dev
.parent
->dma_mask
) {
1285 struct device
*dev
= spi
->master
->dev
.parent
;
1287 host
->dma_dev
= dev
;
1288 host
->ones_dma
= dma_map_single(dev
, ones
,
1289 MMC_SPI_BLOCKSIZE
, DMA_TO_DEVICE
);
1290 host
->data_dma
= dma_map_single(dev
, host
->data
,
1291 sizeof(*host
->data
), DMA_BIDIRECTIONAL
);
1293 /* REVISIT in theory those map operations can fail... */
1295 dma_sync_single_for_cpu(host
->dma_dev
,
1296 host
->data_dma
, sizeof(*host
->data
),
1300 /* setup message for status/busy readback */
1301 spi_message_init(&host
->readback
);
1302 host
->readback
.is_dma_mapped
= (host
->dma_dev
!= NULL
);
1304 spi_message_add_tail(&host
->status
, &host
->readback
);
1305 host
->status
.tx_buf
= host
->ones
;
1306 host
->status
.tx_dma
= host
->ones_dma
;
1307 host
->status
.rx_buf
= &host
->data
->status
;
1308 host
->status
.rx_dma
= host
->data_dma
+ offsetof(struct scratch
, status
);
1309 host
->status
.cs_change
= 1;
1311 /* register card detect irq */
1312 if (host
->pdata
&& host
->pdata
->init
) {
1313 status
= host
->pdata
->init(&spi
->dev
, mmc_spi_detect_irq
, mmc
);
1315 goto fail_glue_init
;
1318 status
= mmc_add_host(mmc
);
1322 dev_info(&spi
->dev
, "SD/MMC host %s%s%s%s\n",
1323 mmc
->class_dev
.bus_id
,
1324 host
->dma_dev
? "" : ", no DMA",
1325 (host
->pdata
&& host
->pdata
->get_ro
)
1327 (host
->pdata
&& host
->pdata
->setpower
)
1328 ? "" : ", no poweroff");
1332 mmc_remove_host (mmc
);
1335 dma_unmap_single(host
->dma_dev
, host
->data_dma
,
1336 sizeof(*host
->data
), DMA_BIDIRECTIONAL
);
1341 dev_set_drvdata(&spi
->dev
, NULL
);
1349 static int __devexit
mmc_spi_remove(struct spi_device
*spi
)
1351 struct mmc_host
*mmc
= dev_get_drvdata(&spi
->dev
);
1352 struct mmc_spi_host
*host
;
1355 host
= mmc_priv(mmc
);
1357 /* prevent new mmc_detect_change() calls */
1358 if (host
->pdata
&& host
->pdata
->exit
)
1359 host
->pdata
->exit(&spi
->dev
, mmc
);
1361 mmc_remove_host(mmc
);
1363 if (host
->dma_dev
) {
1364 dma_unmap_single(host
->dma_dev
, host
->ones_dma
,
1365 MMC_SPI_BLOCKSIZE
, DMA_TO_DEVICE
);
1366 dma_unmap_single(host
->dma_dev
, host
->data_dma
,
1367 sizeof(*host
->data
), DMA_BIDIRECTIONAL
);
1373 spi
->max_speed_hz
= mmc
->f_max
;
1375 dev_set_drvdata(&spi
->dev
, NULL
);
1381 static struct spi_driver mmc_spi_driver
= {
1384 .bus
= &spi_bus_type
,
1385 .owner
= THIS_MODULE
,
1387 .probe
= mmc_spi_probe
,
1388 .remove
= __devexit_p(mmc_spi_remove
),
1392 static int __init
mmc_spi_init(void)
1394 return spi_register_driver(&mmc_spi_driver
);
1396 module_init(mmc_spi_init
);
1399 static void __exit
mmc_spi_exit(void)
1401 spi_unregister_driver(&mmc_spi_driver
);
1403 module_exit(mmc_spi_exit
);
1406 MODULE_AUTHOR("Mike Lavender, David Brownell, "
1407 "Hans-Peter Nilsson, Jan Nikitenko");
1408 MODULE_DESCRIPTION("SPI SD/MMC host driver");
1409 MODULE_LICENSE("GPL");